JP2009033073A - Production process of semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide end point detection technology in a remote plasma cleaning which is suited for manufacturing process of mass production of semiconductor integrated circuit device. <P>SOLUTION: A production process of semiconductor integrated circuit device comprises applying plasma to excite reaction gas to deposit a desired film in a reaction chamber 52, supplying a cleaning gas excited in a remote plasma excitation chamber to the reaction chamber to perform a remote plasma cleaning of the reaction chamber under non-plasma excitation atmosphere, and repeating these steps. A slight emission of light from the film-forming chamber under the non-plasma excitation atmosphere is monitored to detect an end point of the remote plasma cleaning. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technique effective when applied to a CVD technique in a method of manufacturing a semiconductor integrated circuit device (or a semiconductor device).

  In Japanese Unexamined Patent Publication No. 2006-086325 (Patent Document 1), in remote plasma cleaning of a plasma CVD apparatus, plasma for end point detection is excited using a film-forming electrode in a CVD chamber, It is disclosed that the end point of cleaning is detected by monitoring light emission from plasma.

  In Japanese Patent Laid-Open No. 2002-057149 (Patent Document 2) or US Pat. No. 7,201,174 (Patent Document 3), in the remote plasma cleaning of a plasma CVD apparatus, what is an electrode for film formation in a CVD chamber? It is disclosed to excite a local plasma using another plasma excitation means and monitor the light emission from the plasma to detect the end point of cleaning.

  Japanese Patent Application Laid-Open No. 2006-287228 (Patent Document 4) or US Patent Publication No. 2006-0228473 (Patent Document 5) discloses that a monochromatic laser beam is placed on a wall surface in a CVD chamber in remote plasma cleaning of a plasma CVD apparatus. In other words, the end point of cleaning is detected by optically monitoring the reflected light.

  Japanese Laid-Open Patent Publication No. 9-097785 (Patent Document 6) discloses that in plasma cleaning of a plasma CVD apparatus, the end point of cleaning is detected by monitoring light emission from a specific location in the CVD chamber. .

  Japanese Laid-Open Patent Publication No. 11-176815 (Patent Document 7) or US Pat. No. 6,207,008 (Patent Document 8) monitors light emission from a portion separated from plasma in a chamber when detecting an etching end point of a plasma etching apparatus. Thus, it is disclosed to detect the end point of etching.

  Japanese Patent Application Laid-Open No. 2004-281673 (Patent Document 9) or US Patent Publication No. 2006-0207630 (Patent Document 10) discloses an in-situ plasma cleaning of a plasma CVD apparatus by emission spectroscopic analysis in a CVD chamber. It is disclosed to detect the end point of cleaning.

  Japanese Patent Laid-Open No. 2005-033173 (Patent Document 11) or US Patent Publication No. 2004-0253828 (Patent Document 12) discloses an electrode for film formation in a CVD chamber in remote plasma cleaning of a plasma CVD apparatus. Is used to excite a weak plasma and electrically monitor the plasma to detect the end point of cleaning.

JP 2006-086325 A JP 2002-057149 A US Pat. No. 7,201,174 JP 2006-287228 A US Patent Publication No. 2006-0228473 Japanese Patent Laid-Open No. 9-097785 JP-A-11-176815 US Pat. No. 6,207,008 JP 2004-281673 A US Patent Publication No. 2006-0207630 JP 2005-033173 A US Patent Publication No. 2004-0253828

In general, in a plasma CVD process in the manufacturing process of a semiconductor integrated circuit device or a semiconductor device, a processing chamber is provided each time a unit wafer (one wafer type) is processed in order to reduce foreign matter and ensure good film forming characteristics. By performing the cleaning process (with no wafer to be processed in the processing chamber), the deposited film formed in the processing chamber at the time of film formation on the preceding wafer is removed. In this cleaning process, in order not to damage the electrodes and other precision parts in the processing chamber, usually, fluorine radicals and the like generated by plasma excitation of a cleaning gas such as NF ₃ outside the processing chamber are guided to the processing chamber ( This is generally performed by removing the deposited film deposited by a gas phase reaction. At the time of this cleaning, since the high frequency power for film formation is not supplied to the processing chamber, in order to see the end point of the cleaning, the cleaning atmosphere is excited locally and the light emission is observed or locally. It is conceivable to electrically measure the excited plasma.

  However, it has been clarified by the present inventors that there are the following problems when actually applied to a mass production process. That is, unlike the film formation, the conditions are not suitable for plasma excitation, and it is difficult to excite plasma locally.

  An object of the present invention is to provide an end point detection technique in remote plasma cleaning suitable for mass production of a semiconductor integrated circuit device manufacturing process.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, in the present invention, the step of depositing a desired film by exciting the reaction gas using plasma in the reaction chamber introduces the cleaning gas excited in the remote plasma excitation chamber into the reaction chamber and the same in a non-plasma excitation atmosphere. In the method of manufacturing a semiconductor integrated circuit device (or semiconductor device) that repeats the step of remote plasma cleaning of the reaction chamber, the end point of the remote plasma cleaning is determined by monitoring the light emission of the wafer processing chamber that is not plasma-excited. It is to detect.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  In other words, the end point of the remote plasma cleaning can be detected by monitoring the weak light emission in the wafer processing chamber which has not been plasma-excited, which has been considered difficult in the past.

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) introducing a first wafer into a wafer processing chamber of a plasma CVD apparatus having a first plasma excitation system;
(B) performing a plasma CVD process on the first wafer introduced into the wafer processing chamber by performing plasma excitation with the first plasma excitation system;
(C) after the step (b), a step of discharging the first wafer from the wafer processing chamber to the outside;
(D) after the step (c), performing a remote plasma cleaning on the wafer processing chamber;
(E) introducing a second wafer into the wafer processing chamber where the remote plasma cleaning has been performed;
(F) performing the plasma CVD process by performing plasma excitation on the second wafer introduced into the wafer processing chamber by the first plasma excitation system;
Here, the step (d) includes the following substeps:
(D1) a step of plasma-exciting a cleaning gas by a second plasma excitation system in a remote plasma generation chamber provided outside the wafer processing chamber, and transferring the excited cleaning gas into the wafer processing chamber ;
(D2) detecting an end point of the remote plasma cleaning by monitoring light emission in the wafer processing chamber with a light detector in a state where the plasma is not excited in the wafer processing chamber;
(D3) A step of terminating the remote plasma cleaning based on the result of the substep (d2).

  2. In the method of manufacturing a semiconductor integrated circuit device according to the item 1, the light detector is directed in a direction not substantially detecting light emitted from the remote plasma generation chamber.

  3. In the method for manufacturing a semiconductor integrated circuit device according to item 1 or 2, the photodetector is directed downward from the horizontal.

  4). In the method of manufacturing a semiconductor integrated circuit device according to any one of items 1 to 3, the photodetector is directed downward by 10 degrees or more from the horizontal.

  5). 4. In the method of manufacturing a semiconductor integrated circuit device according to any one of items 1 to 3, the photodetector is directed downward by 15 degrees or more from the horizontal.

  6). 4. In the method of manufacturing a semiconductor integrated circuit device according to any one of items 1 to 3, the photodetector is directed downward by 20 degrees or more from the horizontal.

  7. 7. In the method of manufacturing a semiconductor integrated circuit device according to any one of 1 to 6, the connecting pipe that connects the wafer processing chamber and the remote plasma generation chamber is bent.

  8). 8. The method of manufacturing a semiconductor integrated circuit device that connects the wafer processing chamber and the remote plasma generation chamber according to any one of 1 to 7, wherein the connection pipe connects the wafer processing chamber and the remote plasma generation chamber. An antireflection film is provided on the inner surface.

  9. 9. The method of manufacturing a semiconductor integrated circuit device according to any one of 1 to 8, wherein light is emitted from the remote plasma generation chamber so that the light from the remote plasma generation chamber does not substantially enter the photodetector. A shielding plate is provided.

  10. 10. In the method for manufacturing a semiconductor integrated circuit device according to any one of items 1 to 9, light emission monitoring by the photodetector is performed based on light emission in a state where cleaning of the wafer processing chamber is completed.

  11. 11. In the method of manufacturing a semiconductor integrated circuit device according to any one of items 1 to 10, the cleaning gas is supplied from above the wafer processing chamber through a connection pipe from the remote plasma generation chamber.

  12 11. In the method for manufacturing a semiconductor integrated circuit device according to any one of items 1 to 10, the cleaning gas is supplied from a side of the wafer processing chamber through a connection pipe from the remote plasma generation chamber.

  13. 13. In the method of manufacturing a semiconductor integrated circuit device according to any one of items 1 to 12, the cleaning gas is directly supplied to the wafer processing chamber without passing through a gas shielding member.

  14 In the method for manufacturing a semiconductor integrated circuit device according to the item 11 or 12, the length of the connection pipe is 50 centimeters or less.

15. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) introducing the first wafer into the wafer processing chamber of the thermal CVD apparatus;
(B) performing a thermal CVD process on the first wafer introduced into the wafer processing chamber;
(C) after the step (b), a step of discharging the first wafer from the wafer processing chamber to the outside;
(D) after the step (c), performing a remote plasma cleaning on the wafer processing chamber;
(E) introducing a second wafer into the wafer processing chamber where the remote plasma cleaning has been performed;
(F) performing the thermal CVD process on the second wafer introduced into the wafer processing chamber;
Here, the step (d) includes the following substeps:
(D1) A step of plasma-exciting a cleaning gas by a second plasma excitation system in a remote plasma generation chamber provided outside the wafer processing chamber and transferring the excited cleaning gas into the wafer processing chamber ;
(D2) detecting an end point of the remote plasma cleaning by monitoring light emission in the wafer processing chamber with a photodetector in a state where the wafer processing chamber is not plasma-excited;
(D3) A step of terminating the remote plasma cleaning based on the result of the substep (d2).

  16. 16. The method for manufacturing a semiconductor integrated circuit device according to the item 15, wherein the photodetector is directed in a direction that does not substantially detect light emitted from the remote plasma generation chamber.

  17. In the method of manufacturing a semiconductor integrated circuit device according to the item 15 or 16, the photodetector is directed downward from the horizontal.

  18. 18. In the method of manufacturing a semiconductor integrated circuit device according to any one of 15 to 17, the photodetector is directed downward by 10 degrees or more from the horizontal.

  19. 18. In the method for manufacturing a semiconductor integrated circuit device according to any one of items 15 to 17, the photodetector is directed downward by 15 degrees or more from the horizontal.

  20. 18. In the method of manufacturing a semiconductor integrated circuit device according to any one of 15 to 17, the photodetector is directed downward by 20 degrees or more from the horizontal.

  21. 21. In the method for manufacturing a semiconductor integrated circuit device according to any one of 15 to 20, the connecting pipe that connects the wafer processing chamber and the remote plasma generation chamber is bent.

  22. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 15 to 21, an antireflection film is provided on an inner surface of a connection pipe that connects the wafer processing chamber and the remote plasma generation chamber.

  23. 23. In the method of manufacturing a semiconductor integrated circuit device according to any one of 15 to 22, the light is emitted from the remote plasma generation chamber so that the light from the remote plasma generation chamber does not substantially enter the photodetector. A shielding plate is provided.

  24. 24. In the method for manufacturing a semiconductor integrated circuit device according to any one of items 15 to 23, the light emission monitoring by the photodetector is performed based on light emission in a state where the cleaning of the wafer processing chamber is completed.

  25. 25. In the method for manufacturing a semiconductor integrated circuit device according to any one of 15 to 24, the cleaning gas is supplied from above the wafer processing chamber through a connection pipe from the remote plasma generation chamber.

  26. 26. In the method for manufacturing a semiconductor integrated circuit device according to any one of items 15 to 25, the cleaning gas is supplied from the side of the wafer processing chamber through a connection pipe from the remote plasma generation chamber.

  27. 27. In the method for manufacturing a semiconductor integrated circuit device according to any one of 15 to 26, the cleaning gas is directly supplied to the wafer processing chamber without passing through a gas shielding member.

  28. 27. In the method for manufacturing a semiconductor integrated circuit device according to the item 25 or 26, the length of the connection pipe is 50 centimeters or less.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of parts for convenience, if necessary, but these are not independent from each other unless otherwise specified. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  2. Similarly, in the description of the embodiment, etc., regarding the material, composition, etc., “X consisting of A” etc. is an element other than A unless specifically stated otherwise and clearly not in context. It is not excluded that one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say. Similarly, the term “silicon oxide film” refers to not only relatively pure undoped silicon oxide (Undoped Silicon Dioxide or Non-Doped Silicate Glass), but also FSG (Fluorosilicate Glass), TEOS-based silicon oxide (TEOS-based silicon oxide), SiOC (Silicon Oxicarbide) or Carbon-doped Silicon oxide (OSG) (Organosilicate glass), PSG (Phosphorus Silicate Glass), BPSG (Borophosphosilicate Glass) and other thermal oxide films, CVD oxide films, SOG (Spin ON Glass), nano-clustering silica (Nano-Clustering Silica: NSC), etc., coating system silicon oxide, silica-based low-k insulating film (porous insulating film) with pores introduced in the same material ), And a composite film with other silicon-based insulating films having these as main constituent elements.

  3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  5). “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor integrated circuit device (same as a semiconductor device or an electronic device) is formed, but also an epitaxial wafer, a composite wafer such as an insulating substrate and a semiconductor layer, etc. Needless to say.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

1. Explanation of detection of weak light emission by adjusting the orientation of the photodetector (mainly FIGS. 1 to 3)
Before remote plasma cleaning was widely performed, the end point of cleaning was detected in the film formation chamber, that is, the reaction chamber, by looking at the emission of cleaning plasma (by a plasma excitation mechanism for film formation, etc.). In such a case, if the film formation chamber is observed with a high-sensitivity light detector, light emission from a very powerful reaction gas (cleaning gas) and heat radiation from the reaction chamber wall (other wafer stage) In order to avoid such a result, it was usually observed with relatively low sensitivity. In remote plasma cleaning, since plasma excitation is not performed in the film forming chamber, it was thought that it was meaningless to observe light emission from the reaction chamber with a photodetector. For this reason, even after remote plasma cleaning has become widely performed, optically observing a reaction chamber that is not directly plasma-excited during cleaning has not been performed.

  However, according to the careful observations by the present inventors, when a light detector having directivity is directed to an appropriate position in the reaction chamber during cleaning, light emission from the reactive species related to the cleaning reaction is weak. It became clear that it could be observed. In addition, it was found that the concentration of F radicals and so on would be easier to observe if the gas diffuser plate (trapping radicals, etc.) used for cleaning and gas introduction was removed. . In other words, the signal obtained is at the same level as the heat radiation and the leak signal from the remote plasma source, but if the gas introduction method and observation method are devised, it can be used for end point detection.

  Hereinafter, detection of light emission from a non-plasma excitation space during a cleaning process such as remote plasma cleaning according to the present embodiment will be described with reference to FIGS.

  FIG. 1 is a schematic front sectional view of a plasma CVD apparatus used in the method for manufacturing a semiconductor integrated circuit device of the present embodiment. According to FIG. 1, an inductively coupled plasma CVD apparatus 55 (which is classified as a so-called high density plasma furnace) having a remote plasma cleaning mechanism (including a plasma excitation system 65 for remote plasma cleaning) used in the present embodiment, The configuration of the inductively coupled film-forming plasma excitation system 53 will be described. Needless to say, the present invention can be applied to a device using a thermal CVD apparatus.

  In FIG. 1, first, the operation and function of each part during film formation will be described. A wafer to be processed 1 (first wafer) such as a 300φ single crystal silicon wafer is provided in a film forming chamber 52 (for example, a cylindrical shape having a height of about 550 mm and a lower portion of 600 mm diameter, and an upper portion having a half dome shape). An electrostatic chuck 56 (also a wafer susceptor) on the lower electrode 66 is placed. The lower electrode 66 is connected to a bias power source. A reactive gas (usually including other additive gases) is supplied from a film formation reaction gas supply port 60 at a predetermined degree of vacuum, and RF power is excited from the RF power source of the film formation plasma excitation system 53 via a matching box. When supplied to the coil, plasma is generated by inductive coupling, thereby causing a film formation reaction. When the film formation is finished, the processed wafer 1 is taken out of the furnace. If the next wafer 1 (second wafer) is introduced and processed as it is, it is generally difficult to form a film having the same quality as the previous wafer. That is, it is necessary to return the conditions in the furnace similar to those in which the previous wafer was processed, that is, the state of the in-furnace deposited film to the same state (initial state) as in the previous wafer processing. This is called cleaning. However, in the example shown in FIG. 6 below, it seems that the process is more stable when the degree of vacuum is relatively high, or when the initial deposit is slightly attached before the first film forming process. Applies more accurately to the second and subsequent wafers in the lot.

To perform cleaning, first, the film forming atmosphere is evacuated by a vacuum exhaust system for a wafer processing chamber (generally having a dry pump or a turbo molecular pump as a main pump in the vicinity of the processing chamber 52). Thereafter, in the remote plasma generation chamber 51 of the remote plasma excitation system, radicals of a cleaning gas (for example, a gas containing a fluorine-containing inorganic gas such as NF ₃ or a fluorine-containing organic gas) may be generated by plasma excitation. Through the connecting pipe 61 (the connecting pipe needs to be as short as possible to prevent trapping of radicals. For example, 50 centimeters or less), it is transferred to the wafer processing chamber 52 (no wafer is accommodated). Then, the cleaning reaction proceeds and the wafer processing chamber 52 returns to the initial state. During this cleaning, the cleaning time for accurately returning the wafer processing chamber 52 to the initial state varies from time to time. Therefore, it is necessary to detect the end point of the time when the product adhered to the wafer processing chamber is almost removed each time as the end point, and to end the cleaning (not necessarily required as will be described later). This is the end point detection of cleaning.

  Next, a method for detecting the end point of cleaning will be described. First, a method for adjusting the photodetector 57 will be described with reference to FIGS. 1 and 2. FIG. 2 shows the observed emission spectrum during remote plasma cleaning. If the orientation of the photodetector 57 is not appropriate, it will be buried in noise such as background radiation and leaked light, and no effective peak will be observed, so that the spectrum mode of FIG. Adjust orientation and sensitivity. In this type of plasma furnace, since the remote plasma generation chamber 51 is above the reaction chamber 52, it is effective to make the direction of the photodetector 57 slightly downward. The downward inclination angle is 10 degrees or more, preferably 15 degrees or more. Further, when the wafer stage 56 is not heated to a relatively high temperature, 20 degrees or more is desirable.

  FIG. 3 is a measurement diagram showing the principle of detection of the cleaning end point by light emission from the plasma CVD apparatus of FIG. The principle of end point detection will be described with reference to FIG. The end point of cleaning is performed by monitoring light emission from the cleaning gas component 54 that has passed through the observation window 63 with the light detector 57, the spectroscope 58, and the light emission monitor 59. As shown in FIG. 3, the spectral intensity of a specific wavelength has converged to a constant value around 118 seconds. This is considered the end point.

  When the cleaning is completed, the next wafer 1 (second wafer) is introduced into the wafer processing chamber 52, and a film forming process equivalent to the previous wafer is performed. In this manner, the film formation / cleaning process is repeated until all the wafers in the lot unit are processed, that is, the film formation / cleaning circulation process is executed. When the lot processing is completed, lot pre-processing is executed to adjust the state of the apparatus (see FIG. 6 or FIG. 15).

  Further, in the monitor system 59, it is preferable to store the spectrum intensity in a state where there is no deposited film in the reaction chamber 52 (cleaning completed state) and to evaluate the observation value based on this (in the following example). the same).

2. Explanation of detection of weak light emission by connecting pipe bending (mainly Fig. 4)
FIG. 4 is a schematic front sectional view of another plasma CVD apparatus used in the method for manufacturing a semiconductor integrated circuit device of the present embodiment. This example is characterized in that there is a connection pipe 61 to the remote plasma generation chamber 51 on the lower side of the reaction chamber 52, and the connection pipe 61 is bent. When the remote plasma generation chamber 51 is located on the lower side of the reaction chamber 52, unlike the section 1, it is difficult to avoid light leaking from the remote plasma generation chamber 51 by turning the photodetector 57 obliquely downward. It is. Therefore, in this case, it is effective to bend the connecting pipe 61 so that the leaked light does not enter the photodetector 57 directly. In this case, it is necessary to find a place where the spectral mode as shown in FIG. 2 is obtained in another direction not directing the photodetector 57 directly toward the outlet of the connection pipe 61.

  Further, it is effective to form an antireflection film or a light absorbing material layer on the inner wall of the connecting pipe 61. As the antireflection film or the light absorbing material layer, for example, fluorine coating, thermoplastic polyimide or the like can be used.

3. Explanation of detection of weak light emission by a shielding plate (mainly FIG. 5)
FIG. 5 is a schematic front sectional view of still another plasma CVD apparatus used in the method of manufacturing a semiconductor integrated circuit device according to the present embodiment. This example is characterized in that a shielding plate 62 (for example, alumina ceramics) that blocks leakage light from above the reaction chamber 52 is provided. This is effective when it is not possible to find a place where the spectral mode as shown in FIG.

4). Explanation of the process applied to the element isolation process (mainly FIGS. 6 to 10)
A process applied to the element isolation trench filling process of the STI (Shallow Trench Isolation) type element isolation process will be described with reference to FIGS. This element isolation groove filling step is performed by an HDP-CVD method (High Density Plasma CVD). As the plasma furnace, the single wafer ICP type high density plasma CVD furnace described in FIG. 1 is used. In this method, a vacuum region of about 0.27 Pa to 1.3 Pa is generally used. The reaction gas is generally monosilane.

  The operation procedure of the HDP-CVD apparatus will be described with reference to FIG. First, in order to raise the cleanliness of the apparatus to a predetermined level, a pre-cleaning step 31 (with no wafer to be processed) is executed. Next, a pre-coating process 32 (with no wafer to be processed) for depositing an oxide film on the inner surface of the processing chamber 52 and other parts is performed. Subsequently, the film forming process 33 is performed in a state where the wafer 1 (first wafer) is set on the wafer stage 54 of the processing chamber 52. When the film formation is completed, the wafer 1 is discharged out of the processing chamber 52. Thereafter, the remote plasma cleaning process 34 is performed in a state where there is no wafer to be processed in the processing chamber 52. Thereafter, the same film forming process 33 as before is performed in a state where the wafer 1 (second wafer) is set on the wafer stage 54 of the processing chamber 52 as in the previous case. Thereafter, the remote plasma cleaning process 34 and the film forming process 33 are repeated until the processing of the entire wafer belonging to the predetermined lot is completed (film forming / cleaning circulation process). When the processing of the entire wafer belonging to a predetermined lot is completed, the pre-cleaning step 31 and the pre-coating step 32 are executed before the next lot is processed, and the film forming / cleaning circulation step is started. Depending on the conditions, the execution order of the pre-cleaning step 31 and the pre-coating step 32 may be reversed (see FIG. 15).

  6 will be described in detail with reference to FIGS. FIG. 7 is a device cross-sectional view of the element isolation groove forming step. An element isolation trench 3 is formed in a silicon wafer (substrate) 1 using the silicon nitride film 2 as a dry etching mask.

  FIG. 8 shows an element isolation trench filling step. The previous element isolation trench 3 is filled with a CVD silicon oxide film 4 (CVD process 1; HDP-CVD-1).

  FIG. 9 is a device cross-sectional view when the CMP process is completed. Here, the CVD silicon oxide film 4 outside the element isolation trench 3 is removed.

  FIG. 10 shows the silicon nitride film removing step. Here, the silicon nitride film 2 is removed by wet etching.

5). Explanation of the process applied to the aluminum wiring process (mainly FIGS. 11 to 14)
The cleaning end point detection method and HDP-CVD apparatus operation procedure described in section 4 (FIG. 6) can be applied to HDP-CVD for forming an ILD film (Inter-Layer Dielectric) in an aluminum wiring process in a similar manner.

  The ILD film forming process will be described with reference to FIGS. FIG. 11 is a device sectional view of the aluminum wiring patterning step. The aluminum wiring formed on the lower ILD film 19 includes an intermediate aluminum alloy layer 5 and upper and lower barrier metal layers 6 such as TiN. Generally, aluminum wiring patterning is performed by dry etching using a resist film as an etching mask.

FIG. 12 shows a completed state of the HDP-CVD film 14 (CVD process 2; HDP-CVD-2). Further, as shown in FIG. 13, a plasma CVD silicon oxide film using TEOS (Tetraethyl-orthosilicate), that is, a P-TEOS SIO ₂ film 7 is formed (CVD process 3; P-TEOS-1). Thereafter, a planarization process by CMP is performed. Furthermore, a thin P-TEOS SIO ₂ film of about 50 to 100 nm may be formed after the CMP process (CVD process 4; P-TEOS-2). Note that the same cleaning end point detection method and apparatus operation procedure (FIG. 6) can also be applied to these CVD processes. FIG. 14 is a device cross-sectional view when the interlayer CMP process is completed.

  The P-TEOS process is generally performed using a single wafer plasma furnace (not a high density type) that is similar to the furnace shown in FIG. The pressure range used is generally 67 Pa to 2000 Pa.

6). Explanation of the process applied to the pre-metal process (mainly FIGS. 15 to 19)
15 to 19, an NSG film (Non-Doped silicate glass film), that is, a non-doped silicon oxide film in the pre-metal insulating film forming process is formed at atmospheric pressure, that is, about 1.0 × 10 ⁵ Pa, or An explanation will be given of a case where the process is performed by thermal CVD using ozone and TEOS (Tetraethyl-orthosilicate) under sub-atmospheric (about 2,700 Pa to 80,000 Pa) (so-called ozone TEOS silicon). Oxide film). In this case, the evacuation system generally has a single pump configuration and a mechanical dry pump as a main pump. In general, those under atmospheric pressure are called AP-CVD (Atmospheric CVD), and those under sub-atmospheric pressure are called SA-CVD (Sub-Atmospheric CVD). A batch furnace is generally used for the former, and a single-wafer furnace similar to that described in FIG. 1 (but not a plasma furnace) is used for the latter. The following description specifically explains the case of a single-wafer furnace.

  FIG. 15 shows an example of an apparatus operation procedure similar to that of FIG. The order of the precoat 41 and the precleaning 42 is opposite to the previous figure, but the film forming process 43 and the cleaning process 44 are substantially the same except for the detailed conditions. The order of pre-processing and the like may be changed as appropriate depending on the characteristics of the process and the apparatus, and thus the description is not repeated. Details of the process will be described below with reference to FIGS.

  FIG. 16 is a schematic cross-sectional view of a device related to a gate electrode pattern. A source or drain region 8 is formed on the gate electrode portion 9 and the first main surface (device surface) of the substrate 1 around it.

Figure 17 is a cross-sectional structure after forming the NSG-CVD film 10 (CVD process _{5; O 3 -TEOS-1)} . FIG. 18 is a device cross section when a BPSG film 11 (Borophosphosilicate Glass Film) is formed thereon by similar thermal CVD (CVD process 6; O ₃ -TEOS-2). In this case, TMP (Trimethylphosphite), TEPO (Triethylphosphate), TMB (trimethylborate), TEB (Triethylborate) or the like is generally used as the process gas. FIG. 19 shows a device cross section when the CMP for the pre-metal insulating film 13 is completed after the same P-TEOS SIO ₂ film 12 (CVD process 7; P-TEOS-3) is formed thereon.

7). Description of exemplary cross-sectional structure of target device (mainly FIG. 20)
FIG. 20 is a cross-sectional view showing an example of a MOS or MIS type semiconductor integrated circuit device having a four-layer aluminum wiring manufactured by applying the processes and techniques described in sections 4 to 6. The aluminum wirings are connected by a tungsten plug 15 surrounded by a barrier metal layer 16 made of TiN or the like. The uppermost film 17 is a final passivation film (CVD process 8; P-SiN-1) made of plasma, silicon, nitride or the like.

8). Application of end point detection for each CVD process The cleaning end point detection procedure described in section 1 can be applied to CVD processes 1-8. In this case, the pretreatment of the apparatus is equivalent to that described in FIG. 6 in section 4 for the CVD processes 1 and 2, and the process described in FIG. 15 in section 6 for the CVD processes 3 to 8. It will be equivalent. This device pre-processing is performed for each lot (for example, 25 sheets or 12 sheets, etc.), but is performed for each appropriate number of sheets (including the number of fluctuations and an infinite number) regardless of the lot unit for mass production. You may do it.

  Further, when the stability of the process can be ensured, it is not always essential to perform normal reaction chamber cleaning for each wafer process. Based on the stability of the process, the single wafer processing may be performed for each sheet, for every two sheets, for every three sheets, for every four to twelve sheets, or for every lot.

9. Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, in the above-described embodiment, the description is mainly made on the CVD process of the silicon oxide film. However, the present invention is not limited to this, and SiN and other insulating films, tungsten and other metal films, titanium nitride, and other metals. Needless to say, the present invention can also be applied to a CVD process such as a nitride film, ruthenium oxide or other metal oxide film.

  The plasma furnace type has been described in detail by taking an ICP type (Inductively Coupled Plasma furnace) single wafer processing furnace as an example. Needless to say, the present invention can be applied to a flat plate type. Needless to say, the present invention can also be applied to a thermal CVD furnace and a batch-type CVD furnace that perform film formation by non-plasma.

It is a front schematic cross section of the plasma CVD apparatus used in the manufacturing method of the semiconductor integrated circuit device of this Embodiment. It is a measurement figure which shows an example of distribution of the light emission from the plasma CVD apparatus used in the manufacturing method of the semiconductor integrated circuit device of this Embodiment. It is a measurement figure which shows the principle of the cleaning end point detection by light emission from the plasma CVD apparatus used in the manufacturing method of the semiconductor integrated circuit device of this Embodiment. It is a front schematic cross section of the other plasma CVD apparatus used in the manufacturing method of the semiconductor integrated circuit device of this Embodiment. FIG. 6 is a schematic front sectional view of still another plasma CVD apparatus used in the method for manufacturing a semiconductor integrated circuit device of the present embodiment. It is an apparatus processing flowchart which shows an example of the plasma CVD process used for the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is device sectional drawing showing the element isolation groove | channel formation process in the element isolation process which is an example of the plasma CVD process used for the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is device sectional drawing showing the element isolation groove embedding process in the element isolation process which is an example of the plasma CVD process used for the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is device sectional drawing showing the element isolation | separation CMP process in the element isolation process which is an example of the plasma CVD process used for the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is device sectional drawing showing the silicon nitride element isolation | separation patterning film removal process in the element isolation process which is an example of the plasma CVD process used for the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is device sectional drawing showing the wiring pattern formation process in the aluminum wiring process which is an example of the plasma CVD process used for the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is device sectional drawing showing the wiring pattern embedding process 1 in the aluminum wiring process which is an example of the plasma CVD process used for the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is device sectional drawing showing the wiring pattern embedding process 2 in the aluminum wiring process which is an example of the plasma CVD process used for the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is device sectional drawing showing the wiring interlayer insulation film CMP process in the aluminum wiring process which is an example of the plasma CVD process used for the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is an apparatus processing flowchart which shows an example of the thermal CVD process used for the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is device sectional drawing showing the gate formation process in the gate formation and premetal process which is an example of the thermal CVD process used for the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is device sectional drawing showing the NSG film formation process on a gate in the gate formation and premetal process which is an example of the thermal CVD process used for the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is device sectional drawing showing the BPSG film formation process on a gate in the gate formation and premetal process which is an example of the thermal CVD process used for the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is device sectional drawing showing the CMP process of the gate formation and premetal process which is an example of the thermal CVD process used for the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is device sectional drawing which shows an example of the device manufactured by the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Wafer 51 Remote plasma generation chamber 52 Wafer processing chamber 53 1st plasma excitation system 55 Plasma CVD apparatus 57 Photo detector 65 2nd plasma excitation system

Claims (20)

A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) introducing a first wafer into a wafer processing chamber of a plasma CVD apparatus having a first plasma excitation system;
(B) performing a plasma CVD process on the first wafer introduced into the wafer processing chamber by performing plasma excitation with the first plasma excitation system;
(C) after the step (b), a step of discharging the first wafer from the wafer processing chamber to the outside;
(D) after the step (c), performing a remote plasma cleaning on the wafer processing chamber;
(E) introducing a second wafer into the wafer processing chamber where the remote plasma cleaning has been performed;
(F) performing the plasma CVD process by performing plasma excitation on the second wafer introduced into the wafer processing chamber by the first plasma excitation system;
Here, the step (d) includes the following substeps:
(D1) a step of plasma-exciting a cleaning gas by a second plasma excitation system in a remote plasma generation chamber provided outside the wafer processing chamber, and transferring the excited cleaning gas into the wafer processing chamber ;
(D2) detecting an end point of the remote plasma cleaning by monitoring light emission in the wafer processing chamber with a light detector in a state where the plasma is not excited in the wafer processing chamber;
(D3) A step of terminating the remote plasma cleaning based on the result of the substep (d2).   In the method of manufacturing a semiconductor integrated circuit device according to the item 1, the light detector is directed in a direction not substantially detecting light emitted from the remote plasma generation chamber.   In the method of manufacturing a semiconductor integrated circuit device according to the item 2, the photodetector is directed downward from the horizontal.   In the method for manufacturing a semiconductor integrated circuit device according to the item 2, the photodetector is directed downward by 10 degrees or more from the horizontal.   In the method of manufacturing a semiconductor integrated circuit device according to the item 2, the light detector faces downward by 15 degrees or more from the horizontal.   In the method of manufacturing a semiconductor integrated circuit device according to the item 2, the photodetector is directed downward by 20 degrees or more from the horizontal.   In the method of manufacturing a semiconductor integrated circuit device according to the item 1, the connecting pipe connecting the wafer processing chamber and the remote plasma generating chamber is bent.   In the method for manufacturing a semiconductor integrated circuit device according to the item 7, an antireflection film is provided on an inner surface of the connection pipe.   In the method for manufacturing a semiconductor integrated circuit device according to the item 1, a light shielding plate is provided in the wafer processing chamber so that light emitted from the remote plasma generation chamber does not substantially enter the photodetector. Yes.   In the method of manufacturing a semiconductor integrated circuit device according to the item 1, the light emission monitoring by the photodetector is performed with reference to light emission in a state where the cleaning of the wafer processing chamber is completed. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) introducing the first wafer into the wafer processing chamber of the thermal CVD apparatus;
(B) performing a thermal CVD process on the first wafer introduced into the wafer processing chamber;
(C) after the step (b), a step of discharging the first wafer from the wafer processing chamber to the outside;
(D) after the step (c), performing a remote plasma cleaning on the wafer processing chamber;
(E) introducing a second wafer into the wafer processing chamber where the remote plasma cleaning has been performed;
(F) performing the thermal CVD process on the second wafer introduced into the wafer processing chamber;
Here, the step (d) includes the following substeps:
(D1) a step of plasma-exciting a cleaning gas by a second plasma excitation system in a remote plasma generation chamber provided outside the wafer processing chamber, and transferring the excited cleaning gas into the wafer processing chamber ;
(D2) detecting an end point of the remote plasma cleaning by monitoring light emission in the wafer processing chamber with a light detector in a state where the plasma is not excited in the wafer processing chamber;
(D3) A step of terminating the remote plasma cleaning based on the result of the substep (d2).   12. In the method for manufacturing a semiconductor integrated circuit device according to the item 11, the light detector is directed in a direction that does not substantially detect light emission from the remote plasma generation chamber.   In the method of manufacturing a semiconductor integrated circuit device according to the item 12, the light detector faces downward from the horizontal.   In the method of manufacturing a semiconductor integrated circuit device according to the item 12, the light detector faces downward by 10 degrees or more from the horizontal.   In the method of manufacturing a semiconductor integrated circuit device according to the item 12, the light detector faces downward by 15 degrees or more from the horizontal.   In the method of manufacturing a semiconductor integrated circuit device according to the item 12, the photodetector is directed downward by 20 degrees or more from the horizontal.   12. In the method for manufacturing a semiconductor integrated circuit device according to the item 11, the connection pipe connecting the wafer processing chamber and the remote plasma generation chamber is bent.   In the method for manufacturing a semiconductor integrated circuit device according to the item 17, an antireflection film is provided on an inner surface of the connection pipe.   12. In the method of manufacturing a semiconductor integrated circuit device according to the item 11, a light shielding plate is provided in the wafer processing chamber so that light emitted from the remote plasma generation chamber does not substantially enter the photodetector. Yes.   In the method of manufacturing a semiconductor integrated circuit device according to the item 11, the light emission monitoring by the photodetector is performed with reference to light emission in a state where the cleaning of the wafer processing chamber is completed.

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