JP2009031987A - Bias generation circuit and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bias generation circuit and a semiconductor device, which can respond to the request of maintaining current of the whole circuit constant or the request of maintaining the resistance value of a transistor which receives bias voltage at a constant value. <P>SOLUTION: The bias generation circuit includes: the first and second resistances serially connected between a power supply voltage and ground and having the same resistance value; the third resistance serially connected between the power supply voltage and the ground and having the resistance value, and a MOS transistor; and a differential amplifier circuit having an inverted input terminal and a non-inverted input terminal, one of the inverted input terminal and the non-inverted input terminal being connected to a first node connecting the first and second resistances, and the other of the inverted input terminal and the non-inverted input terminal being connected to a second node connecting the third resistance to the MOS transistor, and an output terminal connected to a gate of the MOS transistor. A bias current controlled to be constant by the resistance value is outputted from a third node connecting the gate of the MOS transistor to the output terminal of the differential circuit without depending on a parameter for determining characteristics of the MOS transistor. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a bias generation circuit and a semiconductor device, and more particularly to a bias generation circuit and a semiconductor device configured to generate a constant bias current.

  In a bias generation circuit built in a semiconductor device or the like, there is a case where a bias current needs to be kept constant. 1 and 2 are circuit diagrams showing a conventional bias generation circuit configured to satisfy such a requirement.

  FIG. 1 shows an example of a conventional bias circuit. The bias generation circuit has a resistor R and an NMOS transistor M1 connected as shown in FIG. In FIG. 1 and FIGS. 2 to 5 described later, VDD indicates a power supply voltage, and GND indicates a ground voltage.

図２は従来のバイアス回路の他の例を示し、バイアス発生回路は同図に示す如く接続された抵抗R、NMOSトランジスタM11, M12及びPMOSトランジスタM13,M14を有する。 Here, when the current flowing through the resistor R and the NMOS transistor M1 is denoted by Ib, and the threshold voltage of the NMOS transistor M1 is denoted by Vth, the potential VB of the node VB connecting the gate and the source of the current Ib and the NMOS transistor M1 is 1) and (2). Note that β is a parameter that determines the current of each NMOS transistor M1 and is a value determined by transistor dimensions or the like, and is a symbol used in a drain current equation of a general MOS transistor.

FIG. 2 shows another example of a conventional bias circuit, which has a resistor R, NMOS transistors M11 and M12, and PMOS transistors M13 and M14 connected as shown in FIG.

通常、図１のバイアス発生回路で発生されたノードVBからの電圧や、図２のバイアス発生回路で発生されたノードVBN又はVBPからの電圧は、カレントミラー回路を構成する他のトランジスタに供給することで、カレントミラー回路を流れる電流を制御する。 Here, the resistor R, the current flowing through the NMOS transistors M11 and M12 and the PMOS transistors M13 and M14 are Ib, the threshold voltage of the NMOS transistor M11 is Vth1, the threshold voltage of the PMOS transistor M14 is Vth4, and the parameters that determine the current of the NMOS transistor M11 are β1, a parameter that determines the current of the PMOS transistor M14 is denoted by β4, and assuming that the channel width of the NMOS transistor M12 is m times that of the NMOS transistor M11, the current Ib and the potential of the node VBN connecting the gates of the NMOS transistors M11 and M12 The potential VBP of the node VBP connecting the VBN and the gates of the PMOS transistors M13 and M14 is expressed by the following equations (3), (4), and (5), respectively.

Normally, the voltage from the node VB generated by the bias generation circuit of FIG. 1 and the voltage from the node VBN or VBP generated by the bias generation circuit of FIG. 2 are supplied to other transistors constituting the current mirror circuit. Thus, the current flowing through the current mirror circuit is controlled.

  In the bias generation circuit of FIG. 1, by inputting the output of the bias generation circuit obtained from the node VB to the gate of the NMOS transistor M2 constituting the NMOS transistor M1 and the current mirror circuit, the current Io flowing through the NMOS transistor M2 is NMOS transistor. It can be kept constant regardless of the source potential Vo of M2.

  In the bias generation circuit of FIG. 2, the output of the bias generation circuit obtained from the node VBN is input to the gate of the NMOS transistor M15 that constitutes the current mirror circuit together with the NMOS transistor M12, so that the current Ion flowing through the NMOS transistor M15 It can be kept constant regardless of the source potential Von of M15, and the output of the bias generation circuit obtained from the node VBP is input to the PMOS transistor M14 and the gate of the PMOS transistor M16 constituting the current mirror circuit, so that the PMOS The current Iop flowing through the transistor M16 can be kept constant regardless of the source potential Vop of the PMOS transistor M16.

  The above equations (1) to (5) are based on the premise that the operation region of each transistor is a saturation region, but the same equation is also obtained when the operation region of each transistor is a weak inversion region. The description thereof is omitted.

For example, Patent Document 1 proposes a bias generation circuit having a transistor that suppresses the influence of variations in manufacturing processes and a transistor that suppresses the influence of fluctuations in power supply voltage.
JP 2003-150258 A

  The current Ib and bias output voltage VBN flowing in the bias generation circuit of FIG. 1 and the current Ib and bias output voltages VBN and VBP flowing in the bias generation circuit of FIG. 2 are calculated from the above equations (1) to (5). In these formulas (1) to (5), there are parameters Vth, Vth1, Vth4, β, β1, β4 that determine the characteristics of the transistor. As is well known, the values of these parameters Vth, Vth1, Vth4, β, β1, β4 vary from about half of the design value to about twice due to variations in temperature and semiconductor device manufacturing processes. . For this reason, the current Ib flowing through the bias generation circuit and the bias output current also change greatly.

  When designing a semiconductor device, the circuit is designed so that it can respond to changes in these parameters Vth, Vth1, Vth4, β, β1, β4 in normal circuit operation, so there is no problem, but the entire circuit 1 or 2 is not applicable to the case where it is desired to maintain a constant current or to maintain a constant resistance value of a transistor receiving a bias voltage. there were.

  Therefore, the present invention provides a bias generation circuit and a semiconductor device that can be used even when it is desired to keep the current of the entire circuit constant or when the resistance value of a transistor receiving a bias voltage is kept constant. For the purpose.

  The above-described problem has the first and second resistors having the same resistance value connected in series between the power supply voltage and the ground, and the resistance value connected in series between the power supply voltage and the ground. One of an inverting input terminal and a non-inverting input terminal is connected to a first node connecting the third resistor, the first MOS transistor, and the first and second resistors, and the third resistor and the first MOS transistor are connected to each other. A differential amplification circuit in which the other of the inverting input terminal and the non-inverting input terminal is connected to a second node connecting one MOS transistor, and an output terminal is connected to the gate of the first MOS transistor; From the third node that connects the gate of the first MOS transistor and the output terminal of the differential amplifier circuit, the resistance value is controlled to be constant without depending on the parameter that determines the characteristics of the first MOS transistor. Output bias current It can be achieved by a bias generator circuit according to claim.

  The above object can be achieved by a semiconductor device including the bias generation circuit. In this case, the semiconductor device further includes a third MOS transistor that has a gate, a source, or a drain connected in common to the first MOS transistor, and that forms a current mirror circuit with the first MOS transistor. A configuration in which the first current flowing through the first and second resistors, the current flowing through the third resistor and the first MOS transistor, and the current flowing through the third MOS transistor are controlled to be equal. It is also good.

  According to the present invention, it is possible to realize a bias generation circuit and a semiconductor device that can be used even when it is desired to keep the current of the entire circuit constant or when the resistance value of a transistor that receives a bias voltage is kept constant. be able to.

  In the present invention, the bias generation circuit includes a resistance bridge circuit having a plurality of resistance elements, and has a configuration in which at least one of the plurality of resistance elements is replaced with a MOS transistor. The bias generation circuit also includes a circuit unit for controlling the gate potential of the MOS transistor so that the on-resistance value of the MOS transistor becomes equal to the resistance value of the resistance element before replacement. Thereby, a constant current source whose current value is determined only by the resistance element can be configured.

  In a semiconductor device having such a bias generation circuit, another MOS transistor constituting a current mirror circuit formed on the same substrate having a gate and a source or drain connected in common is connected to the MOS transistor. Thus, the current value flowing through the other MOS transistor may be determined by a resistance element.

  That is, there is provided a bias generation circuit that can be used even when it is desired to keep the current of the entire circuit constant or when the resistance value of the transistor receiving the bias voltage is kept constant, and such a bias generation circuit. A semiconductor device can be configured.

  Hereinafter, embodiments of the bias generation circuit and the semiconductor device according to the present invention will be described with reference to FIG.

  In the first embodiment of the present invention, the semiconductor device (or semiconductor chip) has a configuration in which various integrated circuits are formed on a substrate (not shown). In this embodiment, the bias generation circuit is an integrated circuit that is formed on the substrate of such a semiconductor device and supplies a bias current (or bias voltage) to various integrated circuits formed on the same substrate. .

  FIG. 3 is a circuit diagram showing a bias generation circuit according to the first embodiment of the present invention. The bias generation circuit includes a resistance bridge circuit 20 and a differential amplifier circuit (or operational amplifier) 21 connected as shown in FIG. The resistance bridge circuit 20 has a configuration in which at least one of a plurality of resistors R having the same resistance value R is replaced with an NMOS transistor M21. The differential amplifier circuit 21 controls the gate potential of the NMOS transistor M1 so that the on-resistance value of the NMOS transistor M21 becomes equal to the resistance value R of the resistor R before replacement. Thereby, a constant current source whose current value is determined only by the resistance R of the NMOS transistor M1 can be configured. The node A connects the resistors R and R on the left side in FIG. 3 in series. The node B connects the resistor R on the right side in FIG. 3 and the NMOS transistor M21 in series. Node A is connected to the inverting input terminal of the differential amplifier circuit 21, and node B is connected to the non-inverting input terminal of the differential amplifier circuit 21. The node VB1 connects the output terminal of the differential amplifier circuit 21 and the gate of the NMOS transistor M21.

NMOSトランジスタM22が飽和領域、若しくは、弱反転領域で動作する場合、NMOSトランジスタM22は、NMOSトランジスタM22を流れる電流Ioがそのゲート電圧（VB1）のみで決定される定電流源として動作するため、電源電圧VDDが一定であれば抵抗値のみで電流が決定される定電流源となる。図１及び図２に示す従来例の場合、式（１）〜（５）中にトランジスタの特性を決定するパラメータVth,Vth1,Vth4,β, β1, β4が存在するが、上記式（６）中にはそのようなトランジスタの特性を決定するパラメータが存在しないので、本実施例のバイアス発生回路は従来例に比べて安定した定電流源を実現できる。 Next, the operation of the bias generation circuit of FIG. 3 will be described. In the resistance bridge circuit 20, the potential of the node A and the potential of the node B become the same potential by the operation of the differential amplifier circuit 21. In order for the node A and the node B to have the same potential, the on-resistance value of the NMOS transistor M21 needs to be the same as the resistance value R of the resistor R. For this reason, the on-resistance value of the NMOS transistor M21 is kept at the resistance value R equal to the resistance R. In this case, since the resistance value of the node A through which the current Ia flows is equal to the resistance value of the node B through which the current Ib flows, Ia = Ib. Further, since the NMOS transistor M22 provided in the same semiconductor device as the NMOS transistor M21 (that is, on the same substrate) is a current mirror circuit having a common gate and source or drain, the current flowing through the NMOS transistor M22 The current value of Io is equal to the current Ib. From the above, the value of Ia (= Ib = Io) is obtained from the following equation (6).

When the NMOS transistor M22 operates in the saturation region or the weak inversion region, the NMOS transistor M22 operates as a constant current source in which the current Io flowing through the NMOS transistor M22 is determined only by its gate voltage (VB1). If the voltage VDD is constant, the current is determined by only the resistance value. In the case of the conventional example shown in FIGS. 1 and 2, parameters Vth, Vth1, Vth4, β, β1, β4 that determine the characteristics of the transistor are present in the equations (1) to (5). Since there is no parameter for determining the characteristics of such a transistor, the bias generation circuit of this embodiment can realize a constant current source that is more stable than the conventional example.

  In the second embodiment of the present invention, the semiconductor device has a configuration in which various integrated circuits are formed on a substrate (not shown). In this embodiment, the bias generation circuit is an integrated circuit that is formed on the substrate of such a semiconductor device and supplies a bias current (or bias voltage) to various integrated circuits formed on the same substrate. .

  FIG. 4 is a circuit diagram showing a bias generation circuit according to the second embodiment of the present invention. The bias generation circuit includes a resistance bridge circuit 30 and a differential amplifier circuit (or operational amplifier) 31 connected as shown in FIG. The resistance bridge circuit 30 has a configuration in which at least one of the plurality of resistors R is replaced with a PMOS transistor M31. The differential amplifier circuit 31 controls the gate potential of the MOS transistor M31 so that the on-resistance value of the PMOS transistor M31 is equal to the resistance value R of the resistor R before replacement. As a result, a constant current source whose current value is determined only by the resistance R of the PMOS transistor M31 can be configured. The node A connects the resistors R and R on the left side in FIG. 4 in series. The node B connects the resistor R on the right side in FIG. 4 and the PMOS transistor M31 in series. Node A is connected to the inverting input terminal of the differential amplifier circuit 31, and node B is connected to the non-inverting input terminal of the differential amplifier circuit 31. The node VB1 connects the output terminal of the differential amplifier circuit 31 and the gate of the PMOS transistor M31.

  4, only the NMOS transistors M12 and M22 shown in FIG. 3 are replaced with PMOS transistors M31 and M32, and the operation of the bias generation circuit shown in FIG. 4 is substantially the same as that in FIG. The description is omitted.

  When the PMOS transistor M32 operates in the saturation region or the weak inversion region, the PMOS transistor M32 operates as a constant current source in which the current Io flowing through the PMOS transistor M32 is determined only by its gate voltage (VB1). If the voltage VDD is constant, the current is determined by only the resistance value. In the case of the conventional example shown in FIGS. 1 and 2, parameters Vth, Vth1, Vth4, β, β1, β4 that determine the characteristics of the transistor are present in the equations (1) to (5). Since there are no parameters that determine the characteristics of such transistors, the bias generation circuit of this embodiment realizes a constant current source that is more stable than the conventional example, as in the case of the first embodiment. it can.

  FIG. 5 is a circuit diagram showing a bias generating circuit according to the third embodiment of the present invention. 5 that are the same as those in FIG. 3 are given the same reference numerals, and descriptions thereof are omitted. In this embodiment, a configuration in which transistors are cascode coupled is adopted.

  The resistance bridge circuit 20-1 illustrated in FIG. 5 further includes an NMOS transistor M23 connected between the node B and the NMOS transistor M21. The gate of the NMOS transistor M23 is connected to the node B. Further, an NMOS transistor M24 is further connected to the NMOS transistor M22 that forms a current mirror circuit having a common gate and source or drain together with the NMOS transistor M21. The NMOS transistor M24 is connected between the potential Vo and the NMOS transistor M22, and the gate of the NMOS transistor M24 is connected to the node B. Therefore, in this embodiment, the NMOS transistors M21 and M23 and the NMOS transistors M22 and M24 constitute a current mirror circuit.

  When such a cascode-coupled configuration is employed, a constant current source with higher accuracy than that of the first embodiment can be realized.

  The bias generation circuit of the fourth embodiment of the present invention is obtained by applying the configuration of the third embodiment having cascode coupling as shown in FIG. 5 to the configuration of the second embodiment shown in FIG. That is, in this embodiment, the NMOS transistors M21 to M24 in FIG. 5 are simply replaced with PMOS transistors, and illustration and description thereof are omitted.

In addition, this invention also includes the invention attached to the following.
(Appendix 1)
First and second resistors having the same resistance value connected in series between a power supply voltage and ground;
A third resistor having a resistance value and a first MOS transistor connected in series between the power supply voltage and the ground;
One of an inverting input terminal and a non-inverting input terminal is connected to a first node that connects the first and second resistors, and a second node that connects the third resistor and the first MOS transistor. A differential amplifier circuit in which the other of the inverting input terminal and the non-inverting input terminal is connected, and an output terminal is connected to the gate of the first MOS transistor;
From the third node that connects the gate of the first MOS transistor and the output terminal of the differential amplifier circuit, the resistance value is controlled to be constant without depending on the parameter that determines the characteristics of the first MOS transistor. A bias generation circuit that outputs a bias current.
(Appendix 2)
2. The supplementary note 1, further comprising a second MOS transistor that is cascode-coupled between the second node and the first MOS transistor and has a gate connected to the second node. Bias generator circuit.
(Appendix 3)
The first MOS transistor is an NMOS transistor connected to the ground, the inverting input terminal is connected to the first node, and the non-inverting input terminal is connected to the second node. The bias generator circuit according to appendix 1 or 2.
(Appendix 4)
The first MOS transistor is a PMOS transistor connected to the power supply voltage, the inverting input terminal is connected to the first node, and the non-inverting input terminal is connected to the second node. The bias generator circuit according to appendix 1 or 2.
(Appendix 5)
A semiconductor device comprising the bias generation circuit according to any one of appendices 1 to 4.
(Appendix 6)
A first MOS transistor, a gate and a source or drain are connected in common, and the first MOS transistor further comprises a third MOS transistor constituting a current mirror circuit;
The first current flowing through the first and second resistors, the current flowing through the third resistor and the first MOS transistor, and the current flowing through the third MOS transistor are controlled to be equal. The semiconductor device according to appendix 5, characterized in that:
(Appendix 7)
The semiconductor device according to appendix 6, wherein the bias generation circuit and the third MOS transistor are formed on the same substrate.

  While the present invention has been described with reference to the embodiments, it is needless to say that the present invention is not limited to the above-described embodiments, and various modifications and improvements can be made within the scope of the present invention.

It is a circuit diagram which shows an example of the conventional bias generation circuit. It is a circuit diagram which shows the other example of the conventional bias generation circuit. 1 is a circuit diagram illustrating a bias generation circuit according to a first embodiment of the present invention. FIG. It is a circuit diagram which shows the bias generation circuit of 2nd Example of this invention. It is a circuit diagram which shows the bias generation circuit of 3rd Example of this invention.

Explanation of symbols

20, 20-1, 30 Resistive bridge circuit 21, 31 Differential amplifier circuit
M21, M22, M23, M24 NMOS transistors
M31, M32 PMOS transistor
R resistance
VDD supply voltage
GND Ground voltage

Claims (5)

First and second resistors having the same resistance value connected in series between a power supply voltage and ground;
A third resistor having a resistance value and a first MOS transistor connected in series between the power supply voltage and the ground;
One of an inverting input terminal and a non-inverting input terminal is connected to a first node that connects the first and second resistors, and a second node that connects the third resistor and the first MOS transistor. A differential amplifier circuit in which the other of the inverting input terminal and the non-inverting input terminal is connected, and an output terminal is connected to the gate of the first MOS transistor;
From the third node that connects the gate of the first MOS transistor and the output terminal of the differential amplifier circuit, the resistance value is controlled to be constant without depending on the parameter that determines the characteristics of the first MOS transistor. A bias generation circuit that outputs a bias current.   2. The semiconductor device according to claim 1, further comprising a second MOS transistor cascode-coupled between the second node and the first MOS transistor and having a gate connected to the second node. The bias generation circuit described.   The first MOS transistor is an NMOS transistor connected to the ground, the inverting input terminal is connected to the first node, and the non-inverting input terminal is connected to the second node. The bias generation circuit according to claim 1 or 2.   The first MOS transistor is a PMOS transistor connected to the power supply voltage, the inverting input terminal is connected to the first node, and the non-inverting input terminal is connected to the second node. The bias generation circuit according to claim 1 or 2. A bias generation circuit according to any one of claims 1 to 4,
A first MOS transistor, a gate and a source or drain connected in common, and the first MOS transistor and a third MOS transistor constituting a current mirror circuit;
The first current flowing through the first and second resistors, the current flowing through the third resistor and the first MOS transistor, and the current flowing through the third MOS transistor are controlled to be equal. A semiconductor device.

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