JP2009027632A - Level shift circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a level shift circuit which cuts off a path of a through current surely regardless of the supply state of each power source to a plurality of circuit portions to be operated by different power sources. <P>SOLUTION: The level shift circuit comprises an input circuit portion 8 operated by a power source voltage VDD1 and an output circuit portion 9 operated by a power source voltage VDD2. The input circuit portion 8 is provided with an inverter circuit 13 which operates at the power source voltage VDD1 and converts a control signal input from the output circuit portion 9, and an output of the inverter circuit 13 is used as the control signal of the input circuit portion 8 together with an output of an inverter circuit 14 operating at the VDD2 of the output circuit portion 9. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a level shift circuit that includes a plurality of circuit units that operate with different power sources and that transmits signals between the circuit units.

  Conventionally, in a control chip or the like configured to operate a circuit using a plurality of power supplies with different power supply voltages, a level shift circuit is used to transmit signals between circuits operated with different power supply voltages.

  This type of level shift circuit operates normally when power of each power supply voltage is supplied. However, if any power supply is cut off, a through current may flow and the output may become unstable. is there. This through current reduces the life of the battery when used in applications that operate on batteries.

  Therefore, for example, in Patent Document 1, as shown in FIG. 4, in a level shift circuit 100 including an input circuit 101 that operates with a power supply voltage VDD1 and an output circuit 102 that operates with a power supply voltage VDD2, A control signal PD input from a control circuit (not shown) is inverted and input by the inverter circuit 106, the NAND gate circuit 105 that fixes the output level of the output circuit 102, and the inverted signal of the control signal PD is further converted to an inverter circuit. And NOR gate circuits 103 and 104 which are input after being inverted by 107 and which fix the output level of the input circuit 101.

  In the level shift circuit 100 configured as described above, when the power supply voltage VDD1 of the input circuit 101 is cut off, the control circuit that operates the output circuit 102 inputs an H level signal as the control signal PD.

  Thereby, on the output circuit 102 side, a signal obtained by inverting the control signal PD by the inverter circuit 106 is input to the NAND gate circuit 105 of the output circuit 102, and the output level of the output circuit 102 is fixed.

  On the other hand, on the input circuit 1 side, a signal obtained by further inverting the control signal inverted by the inverter circuit 106 by the inverter circuit 107 is input to the NOR gate circuits 103 and 104 of the input circuit 101, and the output level of the input circuit 101 is L Fixed to level. As a result, N1 and N2 of the output circuit 102 are turned off.

Therefore, by controlling in this way, the path of the through current can be blocked.
JP 2006-173889 A

  However, in the level shift circuit of Patent Document 1, if the supply of the power supply voltage VDD2 is cut off while the power supply voltage VDD1 is supplied, the output of the inverter circuit 107 in the output circuit 102 becomes indefinite and the input circuit Since the control signal PD is not transmitted to the terminal 101, there is a problem that a through current flows in the NOR gate circuits 103 and 104 of the input circuit unit 101.

  Here, it is conceivable to prevent the through current from flowing by starting up the power supply voltage VDD2 first when the power supply is turned on and lowering the power supply voltage VDD2 later when the power supply is turned off. In an IC that has multiple circuit units that operate with a power supply and that exchanges signals between each circuit unit, the control of the startup and shutdown sequence is complicated because no through current path is created. End up.

  The present invention has been made to solve the above-described problem, and is a level shift circuit that can reliably cut off a through current path regardless of the supply state of power to a plurality of circuit units operating with different power supplies. The purpose is to provide.

  In order to achieve the above object, the invention according to claim 1 is characterized in that an input circuit unit that operates by being supplied with power of a first power supply voltage, and is electrically connected to the input circuit unit, the first power supply voltage. An output circuit portion that operates by being supplied with electric power of a second power supply voltage different from the above, and an N-channel first transistor and a second transistor that are provided in the output circuit portion and have a source grounded, A P-channel third transistor connected to the power supply line of the second power supply voltage and having a drain connected to the drain of the first transistor and a gate connected to the drain of the second transistor; The source is connected to the power supply line of the second power supply voltage, the drain is connected to the drain of the second transistor, and the gate is connected to the drain of the first transistor. A level conversion circuit composed of the fourth transistor, and the second power supply voltage is supplied to operate to convert the power cutoff control signal input from the outside to the output circuit unit. A first conversion circuit that outputs the first power supply voltage, a second conversion circuit that operates by being supplied with power of the second power supply voltage, converts a signal input from the first conversion circuit, and outputs the signal; A third converter circuit that operates by being supplied with power of the first power supply voltage, converts a signal input from the first converter circuit, and outputs the signal; and the level converter circuit provided in the output circuit unit. And a fixing circuit for fixing a signal level output from the output circuit unit based on the output from the second conversion circuit and the control signal output from the second conversion circuit, and the input circuit unit Input from the outside to the circuit section First generation circuit for generating a control signal to be output to the gate of the first transistor based on an input signal, a signal output from the second conversion circuit, and a signal output from the third conversion circuit And based on the signal generated in the first generation circuit, the signal output from the second conversion circuit, and the signal output from the third conversion circuit, provided in the input circuit unit. And a second generation circuit that generates a control signal to be output to the gates of the two transistors.

  The present invention further includes connecting the output terminal of the third conversion circuit to the input terminal of the fixing circuit, and in the fixing circuit, the output from the level conversion circuit, the output from the second conversion circuit, and the The signal level output from the output circuit unit may be fixed based on the output from the third conversion circuit.

  The present invention further includes an N-channel fifth transistor having a drain connected to a subsequent stage of the fixing circuit, a source grounded, and a gate connected to an output terminal of the third conversion circuit. It is good also as a structure.

  On the other hand, in order to achieve the above object, the invention according to claim 4 includes a first power supply region having a plurality of circuit portions that operate by being supplied with power of the first power supply voltage, and the first power supply region. A second power supply region which has a circuit portion electrically connected to the provided circuit portion and operates by being supplied with power of a second power supply voltage different from the first power supply voltage; The first conversion circuit unit is provided in the power supply region, and performs a predetermined conversion on the power-off control signal input from the outside, and outputs the control signal. The first conversion circuit is provided in the second power supply region. A first conversion circuit provided in the first power supply region, a second conversion circuit unit that performs a reverse conversion to the first conversion circuit unit and outputs the signal output from the first conversion circuit unit; The signal output from the unit is subjected to conversion opposite to that of the first conversion circuit unit and output. A third conversion circuit unit, a level conversion circuit unit provided in the second power supply region and performing level conversion in accordance with a signal input via the first power supply region, and the first power supply A signal that is provided in the area and is input to the level conversion circuit unit based on the signal output from the second conversion circuit unit and the signal output from the third conversion circuit unit. And a fixing circuit unit provided in the second power supply region and fixing an output from the level conversion circuit unit based on a signal output from the second conversion circuit. I have.

  The present invention may further include a sub-fixing circuit unit that further fixes the output from the fixing circuit unit based on a signal output from the third conversion circuit unit.

  As described above, the present invention has an excellent effect that the path of the through current can be reliably cut off regardless of the supply state of power to a plurality of circuit units operating with different power supplies.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 shows a level shift circuit 1 according to the first embodiment.

  As shown in the figure, the level shift circuit 1 according to the first embodiment includes an input circuit unit 8 that operates at the power supply voltage VDD1 and an output circuit unit 9 that operates at the power supply voltage VDD2. ing.

  The input circuit unit 8 includes two NOR circuits 10 and 11, and an inverter circuit 13 that receives a power cutoff control signal output from an inverter circuit 15 of the output circuit unit 9 described later is provided. ing.

  The input terminal IN of the input circuit unit 8 is connected to a first control circuit (not shown) that operates at the power supply voltage VDD1, and the control signal IN is input from the first control circuit. On the other hand, the output terminal of the input circuit unit 8 is connected to the output circuit unit 9.

  The control signal IN is input to the input terminal of the NOR gate circuit 10, and the output terminal of the inverter circuit 13 and the output terminal of the inverter circuit 14 of the output circuit unit 9 are connected to the input terminal of the NOR gate circuit 11. The output terminal of the NOR gate circuit 10, the output terminal of the inverter circuit 13, and the output terminal of the inverter circuit 14 of the output circuit unit 9 are connected to the ends.

  On the other hand, the output circuit unit 9 includes NMOS transistors N3 and N4, PMOS transistors P3 and P4, two inverter circuits 14 and 15, and a NOR gate circuit 12.

  The control terminal PD of the output circuit unit 9 is a power source different from the power source that supplies the power source voltages VDD1 and VDD2, and is a power source that does not shut off the power (however, the input circuit unit 8 and the output circuit unit 9 If the circuits are on the same LSI, they are connected to a second control circuit (not shown) that operates at the power supply voltage VDD3), and a control signal PD is input from the second control circuit.

  A control terminal PD is connected to the input terminal of the inverter circuit 15, and the power cutoff control signal PD input from the second control circuit is input, and the input control signal PD is inverted and output.

  Further, the output terminal of the inverter circuit 15 is connected to the input terminal of the inverter circuit 14, and the control signal PD inverted by the inverter circuit 15 is further inverted and output.

  The sources of the NMOS transistors N3 and N4 are grounded, the output terminal of the NOR gate circuit 10 of the input circuit unit 8 is connected to the gate of the NMOS transistor N3, and the NOR gate circuit of the input circuit unit 8 is connected to the gate of the NMOS transistor N4. 11 output terminals are connected to each other.

  The PMOS transistors P3 and P4 have VDD2 as a source, the drain of the NMOS transistor N4 is connected to the gate of the PMOS transistor P3, and the drain of the NMOS transistor N3 is connected to the gate of the PMOS transistor P4.

  Further, the drain of the PMOS transistor P4 and the drain of the NMOS transistor N4 are connected, and the source of the NMOS transistor N3 and the drain of the PMOS transistor P3 are connected.

  The NOR gate circuit 12 is connected to the drain of the PMOS transistor P3 and the output terminal of the inverter circuit 14, and the output terminal is connected to the output terminal OUT.

  Hereinafter, the operation of the first embodiment will be described.

  First, a case will be described in which both the power supply voltage VDD1 and the power supply voltage VDD2 are on, and H level signals are input to the control terminals PD and IN, respectively.

  The signal input to the control terminal PD is inverted by the inverter circuit 15 of the output circuit unit 9, further inverted by the inverter circuit 14, and becomes the same H level as the control terminal PD. Further, the output of the inverter circuit 15 becomes the same H level as that of the control terminal PD by the inverter circuit 13 of the input circuit unit 8.

  Therefore, since the H level is input from the inverter circuit 13 to the NOR gate circuits 10 and 11 of the input circuit unit 8, the output signals of these NOR gate circuits 10 and 11 are independent of the input signal level of the input terminal IN. L level. By this L level output signal, the NMOS transistors N3 and N4 of the output circuit section 9 are turned off, and the through current path is cut off.

  Further, since an H level signal is input to the NOR gate circuit 12 of the output circuit unit 9 by the inverter circuit 14, the output signal of the NOR gate circuit 12 is at the L level regardless of the signal level of the other input terminal. It becomes.

  As a result, when both power supplies are on and the control terminal PD is at the H level, all the through current paths in the level shift circuit 1 are cut off.

  Here, when the power supply of the power supply voltage VDD1 is cut off, since the signal from the output circuit unit 9 is input, the NOR gate circuits 10 and 11 of the input circuit unit 8 are held at the L level.

  As a result, even when the power supply of the power supply voltage VDD1 is cut off, all the through current paths in the level shift circuit 1 are kept cut off.

  Further, when the power supply of the power supply voltage VDD2 is cut off from the state where both power supplies of the power supply voltages VDD1 and VDD2 are supplied, the output of the inverter circuit 15 of the output circuit unit 9 maintains the L level. At this time, since the output of the inverter circuit 13 of the input circuit unit 8 is held at the H level, the outputs of the NOR gate circuits 10 and 11 of the input circuit unit 8 are held at the L level.

  As a result, even when the power supply of the power supply voltage VDD2 is cut off, all the through current paths in the level shift circuit 1 are kept cut off.

  Note that, here, a case where an H level signal is input to the control terminals PD and IN has been described, but as described above, the output signal levels of the NOR gate circuits 10, 11, and 12 are the signals of the input terminal IN. Since the operation does not depend on the level, the operation is the same when the control terminal PD is at the H level and the input terminal IN is at the L level.

  Next, a case will be described in which the power supply voltages VDD1 and VDD2 are on, and an L level signal is input to the control terminal PD and an H level signal is input to the input terminal IN.

  In this case, the output signal of the inverter circuit 15 of the output circuit unit 9 becomes H level and is input to the inverter circuit 13 of the input circuit unit 8. Therefore, the output signal of inverter circuit 13 is at L level.

  As a result, the NOR gate circuits 10 and 11 of the input circuit unit 8 perform an inverting operation because two of the three inputs become L level. The H level signal input to the input terminal IN becomes L level at the output of the NOR gate circuit 10 of the input circuit unit 8 and H level at the output of the NOR gate circuit 11.

  Thus, on the output circuit unit 9 side, the NMOS transistor N4 is turned off and N3 is turned on, so that the PMOS transistor P3 is turned off and P4 is turned on, and one input terminal of the NOR gate circuit 12 has L level is input.

  Further, since the L-level output signal is input from the inverter circuit 14 to the other input terminal of the NOR gate circuit 12, an inversion operation is performed in the same manner as the NOR gate circuits 10 and 11 of the input circuit unit 8 described above. Accordingly, the H level is output to the output terminal OUT.

  On the other hand, when the L level is input to the input terminal IN, the outputs of the NOR gate circuits 10 and 11 of the input circuit unit 8 become the H level and the L level, respectively. N3 is off and N4 is on. As a result, the PMOS transistor P4 is turned off and P3 is turned on, so that the H level is input to one input terminal of the NOR gate circuit 12, and the L level is output to the output terminal OUT.

  That is, when the H level is input to the control terminal PD, the output terminal OUT becomes the L level regardless of the input level of the input terminal IN. Further, when the L level is input to the control terminal PD, the signal having the signal amplitude VDD1 input to the input terminal IN is output to the output terminal OUT as the same logic of the signal amplitude VDD2.

  As described above, according to the first embodiment, the input circuit unit 8 that operates at the power supply voltage VDD1 and the output circuit unit 9 that operates at the power supply voltage VDD2 are provided. An inverter circuit 13 that operates at VDD1 and converts a control signal input from the output circuit unit 9 is provided. The output of the inverter circuit 13 is used as a control signal together with the output of the inverter circuit 14 that operates at VDD2 of the output circuit unit 9. By using this, when the H level is input to the control terminal PD, there is an effect that no through current path is formed regardless of the power supply of either VDD1 or VDD2.

(Second Embodiment)
In the first embodiment, the inverter circuit is provided in the input circuit unit 8 to prevent the through current path. However, in the second embodiment, the power supply of any power supply voltage is further cut off. A mode in which the output from the output terminal OUT in this case is fixed to the L level will be described.

  FIG. 2 shows a level shift circuit 2 according to the second embodiment. In the figure, the same components as those of the level shift circuit 1 according to the first embodiment are denoted by the same reference numerals, and the description thereof is omitted here.

  As shown in the figure, in the second embodiment, the output circuit unit 17 is further provided with an NMOS transistor N7. The NMOS transistor N7 has a drain connected to the output terminal OUT of the output circuit unit 17, a gate connected to the output terminal of the inverter circuit 13 of the input circuit 16 operating at the power supply voltage VDD1, and a source grounded.

  According to the level shift circuit 17 configured as described above, when an H level signal is input to the control terminal PD and the power supply of VDD2 is shut off from the state where the power supply voltages VDD1 and VDD2 are supplied, the output circuit Since both inputs of the NOR gate circuit 12 of the unit 17 are indefinite, the output is also indefinite.

  At this time, since the H level is output from the inverter circuit 13 of the input circuit unit 16 operating at VDD1, the NMOS transistor N7 is turned on, and the L level is output to the output terminal OUT.

  As described above, according to the second embodiment, by adding the NMOS transistor N7, the output terminal OUT can be fixed at the L level regardless of the power supply of VDD1 or VDD2. The effect that it can be obtained.

  In the second embodiment, the circuit connected to the output terminal OUT has been described using the two-input NOR gate circuit 12 and the NMOS transistor N7. However, the present invention is not limited to this. Instead, the two can be combined into a three-input NOR gate circuit.

  In each of the embodiments described above, the inverter gate circuit is used for signal transmission from the control terminal PD. However, the present invention is not limited to this, as long as the same logic as that of each of the above embodiments can be configured. . For example, the same logic can be configured by appropriately combining gate circuits such as a NAND gate circuit and a NOR gate circuit.

  For example, FIG. 4 is a functional block diagram functionally showing the configuration of the level shift circuit (see FIGS. 1 and 2) of each embodiment. As shown in the figure, the level shift unit 50 includes a first power supply region 52 driven by the first power supply voltage VDD1, a second power supply region 54 driven by the second power supply voltage VDD2, It is comprised including. The first power supply region 52 and the second power supply region 54 are electrically connected, the first power supply region 52 is connected to the first control unit, and the second power supply region 54 is The second control unit and the load (both not shown) are connected.

  Further, the control signal IN is input to the first power supply region 52 from the first control unit, and the control signal PD is input to the second power supply region 54 from the second control unit. That is, the first power supply region 52 and the second power supply region 54 are controlled in operating states (including a power supply state) by different control units.

  The first power supply region 52 includes an input circuit unit 56 and receives a control signal IN. The input circuit unit 56 generates signals S 1 and S 1 ′ and outputs them to the second power supply region 54. The input circuit section 56 corresponds to the generation circuit section of the invention of claim 4.

  The second power supply region 54 includes a level conversion circuit unit 58, a fixed circuit unit 60, a first conversion circuit unit 62, and a second conversion circuit unit 63. The level conversion circuit unit 58 outputs a conversion signal S2 corresponding to the signal S1 and the signal S1 'output from the first power supply region 52.

  The control signal PD input to the second power supply area 54 is a control signal indicating a supply state of power supply to the second power supply area 54. The control signal PD is converted through the first conversion circuit unit 62 and is output to the second conversion circuit unit 63 as the conversion signal S3. In the second conversion circuit unit 63, a signal S 3 ′ (= control signal PD) obtained by performing a conversion opposite to that of the first conversion circuit unit 62 is converted into the fixed circuit unit 60 and the first conversion signal S 3. Is output to the input circuit 56 in the power source region.

  In the immobilization circuit unit 60, when a signal indicating power supply is input as the control signal PD so that the second power supply region 54 operates in response to the control signal PD, a signal corresponding to the conversion signal S2 is output. On the other hand, when the signal indicating the interruption of the power supply is input as the control signal PD while the signal is output to the load, the output signal to the load is fixed.

  Here, the first power supply region 52 includes the third conversion circuit unit 64. The third conversion circuit unit 64 receives the conversion signal S3 from the first conversion circuit unit 62 in the second power supply region 54. The third conversion circuit unit 64 performs conversion opposite to that of the first conversion circuit 62 on the conversion signal S3 and outputs the converted signal S4 to the input circuit unit 56.

  With this configuration, the input circuit unit 56 generates and outputs a signal S1 and a signal S1 'based on the control signal IN, the signal S3', and the signal S4.

  Hereinafter, the operation of the function shown in FIG.

  First, when power is supplied to at least the second power supply region 54, the conversion signal S4 and the signal S3 'input to the input circuit unit 56 are the same signal. Therefore, as long as power is supplied to the second power supply region 54, the first power supply region 52 and the second power supply region 54 regardless of the power supply state (supply or cutoff) to the first power supply region 52. The through current path can be cut off.

  On the other hand, when power supply to the second power supply region 54 is interrupted and power is supplied to the first power supply region 52, the second power supply region 54 supplies the first power supply region. The voltage level of the line outputting the signal to 52 is the same, and the same signal is input as the conversion signal S3 and the signal S3 ′. However, since the conversion signal S3 is converted by the third conversion circuit unit 64, the signal S4 output from the third conversion circuit unit 64 is a signal opposite to the signal S3 '. As a result, one of the signal S4 and the signal S3 'input to the input circuit unit 56 is an output when the control signal PD indicates power-off. Therefore, when the power supply to the second power supply region 54 is interrupted and the power supply is supplied to the first power supply region 52, the first power supply is irrespective of the value of the control signal IN. The through current path in the region 52 and the second power supply region 54 can be cut off.

  A sub-fixed circuit unit corresponding to the NMOS transistor N7 described in the second embodiment is further connected to the output terminal of the fixed circuit unit 60 having the configuration shown in FIG. The output terminal can also be connected to the input terminal of the sub-fixing circuit unit.

  Thereby, even when the power supply to the first power supply region 52 is interrupted, the effect that the output terminal OUT can be fixed at the L level is obtained.

It is a block diagram of the level shift circuit which concerns on 1st Embodiment. It is a block diagram of the level shift circuit which concerns on 2nd Embodiment. It is a functional block diagram which shows the structure of the level shift circuit of each embodiment functionally. It is a block diagram which shows an example of the conventional level shift circuit.

Explanation of symbols

1 level shift circuit 8 input circuit section 9 output circuit section 10 NOR gate circuit (first generation circuit)
11 NOR gate circuit (second generation circuit)
12 NOR gate circuit (fixed circuit)
13 Inverter circuit (third conversion circuit)
14 Inverter circuit (second conversion circuit)
15 Inverter circuit (first conversion circuit)
N3 NMOS transistor (first transistor)
N4 NMOS transistor (second transistor)
P3 PMOS transistor (third transistor)
P4 PMOS transistor (fourth transistor)
N7 NMOS transistor (fifth transistor)

Claims (5)

An input circuit unit that operates by being supplied with power of a first power supply voltage;
An output circuit unit that is electrically connected to the input circuit unit and operates by being supplied with power of a second power supply voltage different from the first power supply voltage;
N-channel first and second transistors provided in the output circuit section, the source of which is grounded, the source is connected to the power supply line of the second power supply voltage, and the drain is the first transistor A P-channel third transistor connected to the drain of the transistor, having a gate connected to the drain of the second transistor, a source connected to a power supply line of the second power supply voltage, and a drain connected to the first transistor A level conversion circuit comprising: a fourth transistor having a gate connected to the drain of the second transistor and a gate connected to the drain of the first transistor;
A first conversion circuit that operates by being supplied with power of the second power supply voltage, converts a power-off control signal input from the outside to the output circuit unit, and outputs the control signal;
A second conversion circuit that operates by being supplied with power of the second power supply voltage, converts a signal input from the first conversion circuit, and outputs the converted signal;
A third conversion circuit that operates by being supplied with power of the first power supply voltage, converts a signal input from the first conversion circuit, and outputs the converted signal;
A fixing circuit that is provided in the output circuit unit and fixes a signal level output from the output circuit unit based on an output from the level conversion circuit and a control signal output from the second conversion circuit. When,
Based on an input signal that is provided in the input circuit unit and is input from the outside to the input circuit unit, a signal output from the second conversion circuit, and a signal output from the third conversion circuit, A first generation circuit for generating a control signal to be output to the gate of the first transistor;
Based on the signal generated in the first generation circuit, the signal output from the second conversion circuit, and the signal output from the third conversion circuit, provided in the input circuit unit. A second generation circuit for generating a control signal to be output to the gate of the transistor;
Level shift circuit with Further connecting the output terminal of the third conversion circuit to the input terminal of the fixed circuit;
In the fixing circuit, the signal level output from the output circuit unit is fixed based on the output from the level conversion circuit, the output from the second conversion circuit, and the output from the third conversion circuit. The level shift circuit according to claim 1.   2. The N-channel fifth transistor according to claim 1, further comprising an N-channel fifth transistor having a drain connected to a subsequent stage of the fixing circuit, a source grounded, and a gate connected to an output terminal of the third conversion circuit. Level shift circuit. A first power supply region having a plurality of circuit units that operate by being supplied with power of a first power supply voltage;
A circuit unit electrically connected to a circuit unit provided in the first power supply region, and operates by being supplied with power of a second power supply voltage different from the first power supply voltage; A power area;
A first conversion circuit unit that is provided in the second power supply region and performs predetermined conversion on a power-off control signal input from outside;
A second conversion circuit unit that is provided in the second power supply region and outputs a signal output from the first conversion circuit unit by performing a reverse conversion to the first conversion circuit unit;
A third conversion circuit unit that is provided in the first power supply region and outputs a signal output from the first conversion circuit unit by performing a reverse conversion to the first conversion circuit unit;
A level conversion circuit unit that is provided in the second power supply region and performs level conversion according to a signal input via the first power supply region;
A level conversion circuit that is provided in the first power supply region and that receives an externally input signal based on a signal output from the second conversion circuit unit and a signal output from the third conversion circuit unit. A generation circuit unit that generates a signal to be output to the unit;
An immobilization circuit unit that is provided in the second power supply region and immobilizes an output from the level conversion circuit unit based on a signal output from the second conversion circuit;
Level shift circuit with   5. The level shift circuit according to claim 4, further comprising a sub-fixing circuit unit that further fixes an output from the fixing circuit unit based on a signal output from the third conversion circuit unit.

Images