JP2009027455A - Insulated transmission circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an insulated transmission circuit which performs signal transmission and power source voltage generation which achieves cost reduction by reducing a space which a transformer occupies, and miniaturizing circuits. <P>SOLUTION: The insulated transmission circuit, which transmits a transmission signal from a transmission source to a transmission destination, is provided with: a frequency modulation unit which carries out frequency modulation of the transmission signal based on a clock signal; an insulation unit which transmits the output signal of the frequency modulation unit by the transformer; a rectifying unit which rectifies the output of the transformer; and a frequency demodulation unit which carries out frequency demodulation of the output of the transformer. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an isolated transmission circuit, and more particularly to an isolated transmission circuit that generates signal transmission and power supply voltage.

  Some circuits that transmit electrical signals have an insulating portion in order to reduce malfunction due to a common mode voltage or because the reference voltage of a circuit that sends a signal is different from a circuit that receives the signal. Further, an isolated power supply voltage generation circuit is required to supply a power supply voltage to a circuit that receives the transmitted signal. The insulated transmission circuit and power supply voltage generation circuit will be described with reference to FIG.

  In FIG. 3, the successive approximation AD converter 4 receives a signal for starting AD conversion, and AD-converts the analog input signal S2 (analog signal-digital signal conversion). The AD conversion start signal is transmitted from the CPU 1 to the AD converter 4.

  The CPU 1 is a signal transmission source, and the AD converter 4 is a transmission destination. The transmission signal S1 output from the CPU 1 is transmitted to the AD converter 4 via the insulated transmission circuit 2 as an AD conversion start signal.

  The insulated transmission circuit 2 includes a transformer 3 and the like. The transformer 3 electrically insulates the CPU 1 and the AD converter 4 connected to the insulated transmission circuit 2, and transmits the transmission signal S 1 from the CPU 1 to the AD converter 4. Transmit to.

  The power supply terminal and the reference voltage terminal of the CPU 1 are connected to the positive terminal (+) and the negative terminal (−) of the DC power supply 20, respectively. When the voltage of the positive terminal (+) of the DC power supply 20 is the first power supply voltage V1, and the voltage of the negative terminal (−) of the DC power supply 20 is the first common voltage V2, the CPU 1 starts from the first power supply voltage V1. Supplied with power supply voltage.

The DC-DC conversion circuit 10 is an inverter type insulation type DC voltage conversion circuit. The SW control circuit 11 is connected to the first power supply voltage V1 and the first common voltage V2. The DC-DC conversion circuit 10 converts the DC voltage of the first power supply voltage V1 into an AC voltage by the SW control circuit 11, boosts or steps down the AC voltage with the transformer 12, and converts the boosted or stepped down voltage into a diode. Rectified by D1 and capacitor C1, and converted to a DC voltage of the second power supply voltage V3.

One end of the capacitor C1 is connected to the second power supply voltage V3, and the other end of the capacitor C1 is connected to the second common voltage V4.

The power supply terminal and the reference voltage terminal of the AD converter 4 are connected to the second power supply voltage V3 and the second common voltage V4, respectively, and the AD converter 4 is supplied with the power supply voltage from the second power supply voltage V3. .

The CPU 1 and the AD converter 4 are electrically insulated by the transformer 3 of the insulated transmission circuit 2 and the transformer 12 of the DC-DC conversion circuit 10.

JP 2002-340638 A

  The configuration of FIG. 3 is disclosed in a part of FIG.

  In FIG. 3, electrical insulation requires two transformers (transformer 3 of insulated transmission circuit 2 and transformer 12 of DC-DC conversion circuit 10).

  Since each of the transformers 3 and 12 includes a plurality of windings, a core (magnetic material), a bobbin that winds the windings, and the like, the component shape is large. For this reason, the transformer occupies a wide space, and it is difficult to reduce the size of the circuit. In addition, a printed circuit board on which components such as a transformer are mounted increases, and the cost of the printed circuit board increases.

  An object of the present invention is to provide an insulated transmission circuit that performs signal transmission and power supply voltage generation that reduce the space occupied by a transformer, reduce the circuit size, and reduce the cost of a printed circuit board or the like.

In order to achieve such an object, the invention of claim 1
In an isolated transmission circuit that transmits a transmission signal from a transmission source to a transmission destination,
A frequency modulation unit for frequency modulating the transmission signal based on a clock signal;
An insulating unit for transmitting an output signal of the frequency modulation unit by a transformer;
A rectifying unit for rectifying the output of the transformer;
A frequency demodulator that demodulates the output of the transformer;
It is characterized by having.

The invention of claim 2 is the invention of claim 1,
The frequency modulation unit is
A first frequency modulation unit that frequency-modulates the transmission signal according to a voltage value of the transmission signal into a first divided signal or a DC signal obtained by dividing the clock signal;
According to the frequency value of the output signal of the first frequency modulation unit, the output signal of the first frequency modulation unit is divided by the second frequency-divided signal obtained by dividing the first frequency-divided signal or the clock signal. A second frequency modulation unit for frequency-modulating the signal divided by 3;
It is characterized by having.

The invention of claim 3 is the invention of claim 2,
The frequency demodulator
A digital signal converter for converting the output of the transformer into a digital signal;
A monostable multivibrator section that outputs a pulse signal having a duration longer than the period of the third divided signal and shorter than the period of the second divided signal based on the change in the output voltage of the digital signal converter;
A first flip-flop unit that holds an output signal of the monostable multivibrator unit based on an output voltage change of the digital signal converter unit;
It is characterized by having.

The invention of claim 4 is the invention according to claim 2 or 3,
The first frequency modulation unit includes:
A second flip-flop unit that holds the transmission signal based on a voltage change of the clock signal;
A frequency divider that divides the clock signal and outputs a fourth frequency-divided signal;
A first logic circuit unit that outputs a logical sum signal of the fourth frequency-divided signal and the output signal of the second flip-flop unit;
The second frequency modulator is
A second logic circuit unit that outputs an exclusive OR signal between the output signal of the first logic circuit unit and the output signal of the second frequency modulation unit;
A third flip-flop unit that holds an output signal of the second logic circuit unit based on a voltage change of the clock signal;
And the output of the third flip-flop unit is the output of the second frequency modulation unit.
It is characterized by that.

The invention according to claim 5 is the invention according to any one of claims 1 to 4,
The insulating part is
A drive unit for causing a current to flow in the first winding of the transformer based on an output signal of the frequency modulation unit;
A second winding of the transformer magnetically coupled to the first winding;
It is characterized by having.

According to the present invention, an insulated transmission circuit that performs signal transmission and power supply voltage generation with a reduced number of transformers reduces the space occupied by the transformer, reduces the circuit size, and reduces the cost of printed circuit boards and the like. realizable.

An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a circuit block diagram of an isolated transmission circuit to which the present invention is applied.

FIG. 2 shows signal waveforms in FIG. 1, where the horizontal axis represents time (msec) and the vertical axis represents voltage (V). Each signal waveform except S60 in FIG. 2 (h) is a digital waveform, and the low voltage is substantially the modulation side common voltage V11 or the demodulation side common voltage V21 (hereinafter referred to as “L voltage”). The voltage is substantially the modulation-side power supply voltage V10 or the demodulation-side power supply voltage V20 (hereinafter referred to as “H voltage”). For example, the H voltage is about 5V. The broken line on the vertical axis represents the same time axis in each signal waveform, and is used for explaining the operation.

In this embodiment, signal transmission and power supply voltage generation are performed by insulation with a single transformer.

  Returning to FIG. 1, the insulated transmission circuit 100 includes a frequency modulation unit 30, an insulation unit 60, a rectification unit 70, a frequency demodulation unit 80, and the like.

  The frequency modulation unit 30 frequency modulates the transmission signal S31 output from the CPU 200 based on the clock signal S30. The frequency modulation unit output signal S51 is transmitted by the transformer 62 of the insulating unit 60, and the frequency demodulation unit 80 demodulates the transformer output S60. The frequency demodulator output signal S82 is input to, for example, an AD converter or a communication controller (both not shown).

  For example, when the transmission signal S31 is a signal for starting AD conversion, the transmission signal S31 output from the CPU 200 that is the signal transmission source is transmitted to the AD converter that is the transmission destination, and AD conversion is started. .

  Further, the rectifier 70 rectifies the transformer output S60 in order to generate power supply voltages such as the frequency demodulator 80 and the AD converter (not shown). The rectifier output V20 supplies a power supply voltage to the frequency demodulator 80, the AD converter, and the like.

  Next, the frequency modulation unit 30 will be described in detail. The frequency modulation unit 30 includes a first frequency modulation unit 40 and a second frequency modulation unit 50.

  The first frequency modulation unit 40 frequency-modulates the transmission signal S31 based on the clock signal S30, and outputs a first frequency modulation unit output signal S42. In FIG. 2 (e), in the first frequency modulation unit output signal S42, the L voltage is maintained for the time T20. (B) The transmission signal S31 is (a) a first divided signal obtained by dividing the clock signal S30. (B) The transmission signal S31 is frequency-modulated to a DC signal (frequency is 0 Hz).

  The second frequency modulation unit 50 frequency-modulates the first frequency modulation unit output signal S42 based on the clock signal S30, and outputs a second frequency modulation unit output S51. In FIG. 2 (g), in the frequency modulation unit output S51, S51 having the frequency value of the first divided signal is frequency-modulated to a second divided signal obtained by dividing the first divided signal during time T40. S51 which is 0 Hz (DC signal) during time T41 is (a) frequency-modulated to a third frequency-divided signal obtained by frequency-dividing the clock signal S30.

  Next, the first frequency modulation unit 40 will be described in detail. The first frequency modulation unit 40 includes a second flip-flop unit 41, a frequency dividing unit 42, a first logic circuit unit 43, and the like.

  The second flip-flop unit 41 is a D-type flip-flop. The D terminal is connected to the CPU 200 and receives the transmission signal S31. The clock input terminal of the second flip-flop unit 41 is connected to the clock generation unit 201 to receive the clock signal S30, and the output terminal Q is connected to one of the input terminals of the first logic circuit unit 43. The first logic circuit unit 43 is an OR circuit.

  The input of the frequency divider 42 is connected to the clock generator 201 and receives the clock signal S30. The output of the frequency divider 42 is connected to the other input terminal of the first logic circuit unit 43.

  The output terminal of the first logic circuit unit 43 outputs a first frequency modulation unit output signal (first logic circuit unit output signal) S42.

  Next, the second frequency modulation unit 50 will be described in detail. The second frequency modulation unit 50 includes a second logic circuit unit 51, a third flip-flop unit 52, and the like.

  One input terminal of the second logic circuit unit 51 is connected to the output terminal of the first logic circuit unit 43, and the other input terminal is connected to the output terminal Q of the third flip-flop unit 52. The second logic circuit unit 51 is an exclusive OR circuit.

  The third flip-flop unit 52 is a D-type flip-flop. The D terminal is connected to the output terminal of the second logic circuit unit 51 and receives the second logic circuit unit output signal S50. The clock input terminal of the third flip-flop unit 52 is connected to the clock generation unit 201 to receive the clock signal S30, and the output terminal Q outputs a frequency modulation unit output signal (second frequency modulation unit output) S51.

  The power supply terminal and the reference voltage terminal of each part of the first frequency modulation unit 40 and the second frequency modulation unit 50 are connected to the modulation side power supply voltage V10 and the modulation side common voltage V11, respectively. From the power supply voltage. The same applies to the CPU 200 and the clock generator 201.

The modulation-side power supply voltage V10 is connected to a positive terminal (+) of a DC power supply (not shown), and the modulation-side common voltage V11 is connected to a negative terminal (−).

  Next, based on the above-described configuration, each signal waveform of the first frequency modulation unit 40 and the second frequency modulation unit 50 will be described in detail with reference to FIG.

  2A, when the voltage of the clock signal S30 changes from the L voltage to the H voltage, the second flip-flop unit 41 holds the transmission signal S31 and outputs it from the output terminal Q. This output signal is referred to as (c) second flip-flop unit output signal S40.

Therefore, the signal waveform of (a) clock signal S30 and (b) transmission signal S31 causes the second flip-flop section output signal S40 to have the signal waveform of FIG.

  The frequency divider 42 outputs a fourth frequency-divided signal S41 obtained by dividing the input clock signal S30 by 2 (frequency is halved). For this reason, the fourth frequency-divided signal S41 has the signal waveform of FIG.

  The first logic circuit unit 43 outputs a logical sum signal of (c) the second flip-flop unit output signal S40 and (d) the fourth divided signal S41. This output signal is referred to as (e) first frequency modulation unit output signal (first logic circuit unit output signal) S42.

Therefore, the first frequency modulation unit output signal S42 has the signal waveform shown in FIG. 2E due to the signal waveforms of (c) the second flip-flop unit output signal S40 and (d) the fourth divided signal S41. (E) The first frequency modulation unit output signal S42 outputs the signal of the (d) fourth divided signal S41 during the time T20 (first divided signal). (E) The first frequency modulation unit output signal S42 outputs an H voltage (frequency is 0 Hz) as a DC signal during T21.

  The second logic circuit unit 51 outputs (f) the second logic circuit unit output S50 as an exclusive OR signal of (e) the first frequency modulation unit output signal S42 and (g) the frequency modulation unit output S51. . (A) When the voltage of the clock signal S30 changes from the L voltage to the H voltage, the third flip-flop unit 52 holds (f) the second logic circuit unit output S50 and outputs it from the output terminal Q. To do.

  Therefore, during the time T1 to T2 in FIG. 2, since (e) the first frequency modulation unit output signal S42 is L voltage and (g) the frequency modulation unit output S51 is H voltage, (f) the second logic circuit The partial output S50 is an H voltage. At T2, (f) the second logic circuit unit output S50 is an H voltage, and (g) the frequency modulation unit output S51 holds the H voltage and outputs it.

  Between times T2 and T3, (e) the first frequency modulation unit output signal S42 is an H voltage, and (g) the frequency modulation unit output S51 is an H voltage, so (f) the second logic circuit unit output S50 is an L voltage. It becomes. At T3, (f) the second logic circuit unit output S50 is an L voltage, and (g) the frequency modulation unit output S51 holds and outputs the L voltage.

  Between times T3 and T4, (e) the first frequency modulation unit output signal S42 is an L voltage, and (g) the frequency modulation unit output S51 is an L voltage, so (f) the second logic circuit unit output S50 is an L voltage. It becomes. At T4, (f) the second logic circuit unit output S50 is the L voltage, and (g) the frequency modulation unit output S51 holds the L voltage and outputs it.

  Between times T4 and T5, since (e) the first frequency modulation unit output signal S42 is an H voltage and (g) the frequency modulation unit output S51 is an L voltage, (f) the second logic circuit unit output S50 is an H voltage. It becomes. At T5, (f) the second logic circuit unit output S50 is the H voltage, and (g) the frequency modulation unit output S51 holds and outputs the H voltage.

  Thereafter, during time T40 in FIG. 2G, (e) the first frequency modulation unit output signal S42, (f) the second logic circuit unit output S50, and (g) the frequency modulation unit output S51 have the signal waveforms described above. repeat. (G) The frequency modulation unit output S51 outputs a signal (second divided signal) obtained by dividing the frequency of the first frequency modulation unit output signal S42 by 2 during T40.

  2, since (e) the first frequency modulation unit output signal S42 is an H voltage and (g) the frequency modulation unit output S51 is an L voltage, (f) the second logic circuit unit. The output S50 is an H voltage. At T7, (f) the second logic circuit unit output S50 is the H voltage, and (g) the frequency modulation unit output S51 holds the H voltage and outputs it.

  Between times T7 and T8, (e) the first frequency modulation unit output signal S42 is an H voltage, and (g) the frequency modulation unit output S51 is an H voltage, so (f) the second logic circuit unit output S50 is an L voltage. It becomes. At time T8, (f) the second logic circuit unit output S50 is an L voltage, and (g) the frequency modulation unit output S51 holds and outputs the L voltage.

  Between times T8 and T9, (e) the first frequency modulation unit output signal S42 is an H voltage and (g) the frequency modulation unit output S51 is an L voltage, so (f) the second logic circuit unit output S50 is an H voltage. It becomes. At T9, (f) the second logic circuit unit output S50 is the H voltage, and (g) the frequency modulation unit output S51 holds and outputs the H voltage.

  Thereafter, during time T41, (e) the first frequency modulation unit output signal S42, (f) the second logic circuit unit output S50, and (g) the frequency modulation unit output S51 repeat the above-described signal waveforms. (G) The frequency modulation unit output S51 outputs a signal (third frequency division signal) obtained by dividing (a) the clock signal S30 by 2 during T41.

  Next, the insulating unit 60 will be described in detail. The insulating unit 60 includes a driving unit 61 and a transformer 62, and the driving unit 61 uses, for example, an FET (field effect transistor).

The transformer 62 includes a first winding (coil) 63 and a second winding (coil) 64 that is magnetically coupled to the first winding, and a direction in which the first winding 63 and the second winding 64 are wound. Is the forward type.

  The gate terminal of the FET of the drive unit 61 is connected to the output terminal Q of the second flip-flop unit 52 and receives the frequency modulation unit output signal S51. The drain terminal of the FET is connected to one end of the first winding 63, and the source terminal is connected to the modulation side common voltage V11.

  The other end of the first winding 63 is connected to the modulation-side power supply voltage V10. The second winding 64 is connected to the rectification unit 70, and one end of the second winding 64 is connected to the frequency demodulation unit 80. One end of the second winding 64 is a transformer output S60.

  Based on this configuration, each signal waveform of the insulating unit 60 will be described in detail with reference to FIG.

  At time T1 in FIG. 2, the H voltage of the frequency modulation unit output S51 in FIG. 2G is applied between the gate and source of the FET of the drive unit 61. Then, the resistance decreases between the drain and source of the FET and is turned on, so that the FET passes a current through the first winding 63. For this reason, the current flows from the modulation side power supply voltage V10 to the modulation side common voltage V11 via the first winding 63, the drain and source of the FET.

  (H) In the transformer output S60, a voltage based on the time change of the current is generated by electromagnetic induction. Therefore, during time T50, (h) a voltage exceeding the rectifier output voltage V20 is generated in the transformer output S60. For example, the voltage exceeding V20 is about 1V.

  At time T3, (g) the L voltage of the frequency modulation unit output S51 is applied between the gate and source of the FET of the drive unit 61. Since the resistance increases between the drain and source of the FET and is turned OFF, the FET does not pass a current through the first winding 63. Since the current does not flow through the first winding 63, (h) the transformer output S60 does not generate a voltage due to electromagnetic induction, and becomes the L voltage. Thereafter, (h) the transformer output S60 repeats the signal waveform described above.

  Next, the frequency demodulator 80 will be described in detail. The frequency demodulation unit 80 includes a digital signal conversion unit 81, a monostable multivibrator unit 82, a first flip-flop unit 83, and the like.

  The transformer output S60, which is one end of the second winding 64, is connected to the rectifier output V20 via resistors R21 and R20 connected in series. Capacitor C20 is connected in parallel to resistor R21 to reduce noise superimposed on the signal at the connection point of resistors R21 and R20.

The connection point between the resistors R21 and R20 is connected to the input terminal of the digital signal conversion unit 81, and the output terminal of the digital signal conversion unit 81 is connected to the clock input terminal of the monostable multivibrator unit 82.

The digital signal converter 81 is, for example, an inverter (logic inversion circuit). In order to prevent chattering due to noise superimposed on the signal at the connection point of the resistors R21 and R20, this inverter may have a threshold value (Schmitt trigger type).

  The monostable multivibrator unit 82 is connected to the rectifier unit output V20 via the resistor R22 and the capacitor C21. The output terminal Q of the monostable multivibrator unit 82 is connected to the D terminal of the first flip-flop unit 83. The first flip-flop unit 83 is a D-type flip-flop.

  When the voltage of the output signal S80 of the digital signal converter 81 changes, the monostable multivibrator unit 82 outputs a pulse signal having a time width related to the resistance value of the resistor R22 and the capacitance value of the capacitor C21 from the output terminal Q. Output.

  The clock input terminal of the first flip-flop unit 83 is connected to the output signal S80 of the digital signal converter 81, and the output signal S82 of the first flip-flop unit 83 is the output of the frequency demodulator 80.

  The power supply terminal and the reference voltage terminal of each part such as the digital signal conversion part 81 and the first flip-flop part 83 are connected to the rectification part output (demodulation side power supply voltage) V20 and the demodulation side common voltage V21, respectively. A power supply voltage 80 is supplied from the rectifier output V20.

  Based on this configuration, each signal waveform of the frequency demodulator 80 will be described in detail with reference to FIG.

  In FIG. 2 (h), a voltage exceeding the rectifier output voltage V20 is generated in the transformer output S60 for a time T50, and a voltage obtained by dividing this voltage by the resistors R21 and R20 is input to the digital signal converter 81. Is done.

  For this reason, since the divided voltage exceeds the threshold value of the digital signal converter 81 during time T50, (i) the output S80 of the digital signal converter becomes H voltage during time T50. Thereafter, (i) the digital signal converter output S80 becomes the H voltage when (h) the transformer output S60 exceeds the rectifier output voltage V20.

  (J) The monostable multivibrator unit output S81 outputs a pulse signal whose time width of the H voltage is T60 when the voltage of the digital signal converter unit output S80 changes from the L voltage to the H voltage.

  T60 is a time related to the resistance value of the resistor R22 and the capacitance value of the capacitor C21, and the time width of T60 is longer than the period T31 of the third divided signal in (g), and the period T30 of the second divided signal. Shorter.

  Time T55 from time T11 to T12 is longer than T30. Therefore, at T11, (i) when the voltage of the digital signal conversion unit output S80 changes from L voltage to H voltage, (j) the monostable multivibrator unit output S81 changes from L voltage to H voltage, Thereafter, the voltage H is maintained for T60, and then becomes the voltage L. (I) The same operation is performed at time T12 when the voltage of the digital signal converter output S80 changes from the L voltage to the H voltage.

  On the other hand, time T56 from time T13 to T14 is shorter than T31. Therefore, at T13, (i) when the voltage of the digital signal converter output S80 changes from L voltage to H voltage, (j) the monostable multivibrator output S81 changes from L voltage to H voltage. (J) The monostable multivibrator unit output S81 maintains the H voltage, and before the time T60 elapses, at T14, (i) the voltage of the digital signal conversion unit output S80 changes from the L voltage to the H voltage. Therefore, (j) the monostable multivibrator output S81 does not become the L voltage but maintains the H voltage.

  Since the same state continues, (j) the monostable multivibrator unit output S81 maintains the H voltage and becomes the L voltage after the time T60 has elapsed from the time T15.

  (I) When the voltage of the digital signal conversion unit output S80 changes from the L voltage to the H voltage, the first flip-flop unit 83 holds (j) the monostable multivibrator unit output S81, and from the output terminal Q Output.

  At time T11, (j) the monostable multivibrator output S81 is L voltage, and (k) the frequency demodulator output S82 changes from H voltage to L voltage. Also at times T12 and T13, (j) monostable multivibrator unit output S81 is at L voltage, so during time T70, (k) frequency demodulator unit output S82 maintains L voltage.

  At time T14, (j) monostable multivibrator unit output S81 is at H voltage, and (k) frequency demodulator unit output S82 changes from L voltage to H voltage. Also at time T15 and T16, (j) monostable multivibrator output S81 is at H voltage, so during time T71, (k) frequency demodulator output S82 maintains H voltage, and after T16, L voltage.

  (K) The frequency demodulator output S82 becomes a signal obtained by demodulating the transmission signal S31 (b), and the insulated transmission circuit 100 can perform signal transmission. For example, T70 and T71 are about 1 msec.

  Next, the rectification unit 70 will be described in detail. The rectifier 70 includes diodes D10 and D11, a capacitor C10, a coil L10, and the like, and performs a forward operation.

  The transformer output S60, which is one end of the second winding 64, is connected to the anode of the diode D10, and the cathode of the diode D10 is connected to one end of the capacitor C10 and the rectifier output (demodulation side power supply voltage) V20.

  The other end of the second winding 64 is connected to the anode of the diode D11 and one end of the coil L10, and the cathode of the diode D11 is connected to the other end of the coil L10, the other end of the capacitor C10, and the demodulation side common voltage V21. The

  Based on this configuration, each signal waveform of the rectifying unit 70 will be described in detail with reference to FIG.

  During time T51 in FIG. 2 (h), current flows from the transformer output S60, which is one end of the second winding 64, to the other end of the second winding 64 via the diode D10, the capacitor C10, and the coil L10. Flowing.

  During T51, electric energy is stored in the coil L10 by the flowing current. Due to this electrical energy, a current flows from one end of the coil L10 to the other end of the coil L10 via the second winding 64, the diode D10, and the capacitor C10 during the time T52.

  Due to the operation at times T51 and T52, (h) a voltage obtained by rectifying the transformer output S60 is generated at both ends of the capacitor C10, and this voltage becomes the rectifier output (demodulation side power supply voltage) V20. Supply the power supply voltage. Note that the diode D11 absorbs an electromotive force that is suddenly changed in voltage generated in the coil L10.

With this embodiment, the isolated transmission circuit that performs signal transmission and power supply voltage generation with a single transformer reduces the space occupied by the transformer, reduces the size of the circuit, and reduces the cost of printed circuit boards. it can.

It is an example of the circuit block diagram of the insulated transmission circuit to which this invention is applied. It is each signal waveform in FIG. It is a circuit block diagram of the insulated transmission circuit in background art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 30 Frequency modulation part 40 1st frequency modulation part 41 2nd flip-flop part 42 Frequency division part 43 1st logic circuit part 50 2nd frequency modulation part 51 2nd logic circuit part 52 3rd flip-flop part 60 Insulation part 61 Drive unit 62 Transformer 63 First winding 64 Second winding 70 Rectification unit 80 Frequency demodulation unit 81 Digital signal conversion unit 82 Monostable multivibrator unit 83 First flip-flop unit 100 Insulated transmission circuit 200 CPU
201 Clock generator

Claims (5)

In an isolated transmission circuit that transmits a transmission signal from a transmission source to a transmission destination,
A frequency modulation unit for frequency modulating the transmission signal based on a clock signal;
An insulating unit for transmitting an output signal of the frequency modulation unit by a transformer;
A rectifying unit for rectifying the output of the transformer;
A frequency demodulator that demodulates the output of the transformer;
An insulated transmission circuit comprising: The frequency modulation unit is
A first frequency modulation unit that frequency-modulates the transmission signal according to a voltage value of the transmission signal into a first divided signal or a DC signal obtained by dividing the clock signal;
According to the frequency value of the output signal of the first frequency modulation unit, the output signal of the first frequency modulation unit is divided by the second frequency-divided signal obtained by dividing the first frequency-divided signal or the clock signal. A second frequency modulation unit for frequency-modulating the signal divided by 3;
The insulated transmission circuit according to claim 1, further comprising: The frequency demodulator
A digital signal converter for converting the output of the transformer into a digital signal;
A monostable multivibrator section that outputs a pulse signal having a duration longer than the period of the third divided signal and shorter than the period of the second divided signal based on the change in the output voltage of the digital signal converter;
A first flip-flop unit that holds an output signal of the monostable multivibrator unit based on an output voltage change of the digital signal converter unit;
The insulated transmission circuit according to claim 2, further comprising: The first frequency modulation unit includes:
A second flip-flop unit that holds the transmission signal based on a voltage change of the clock signal;
A frequency divider that divides the clock signal and outputs a fourth frequency-divided signal;
A first logic circuit unit that outputs a logical sum signal of the fourth frequency-divided signal and the output signal of the second flip-flop unit;
The second frequency modulator is
A second logic circuit unit that outputs an exclusive OR signal between the output signal of the first logic circuit unit and the output signal of the second frequency modulation unit;
A third flip-flop unit that holds an output signal of the second logic circuit unit based on a voltage change of the clock signal;
And the output of the third flip-flop unit is the output of the second frequency modulation unit.
The insulated transmission circuit according to claim 2 or 3, wherein The insulating part is
A drive unit for causing a current to flow in the first winding of the transformer based on an output signal of the frequency modulation unit;
A second winding of the transformer magnetically coupled to the first winding;
5. The insulated transmission circuit according to claim 1, further comprising:

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