JP2009027013A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that is equipped with a differential transmission channel having no constraint on design flexibility. <P>SOLUTION: The semiconductor device 1 includes a semiconductor integrated circuit, arranged at least on a surface layer or inside; a plurality of external connection pads 2 for electrically connecting the semiconductor integrated circuit to the outside; and a differential signal transmission line 3, which is connected to two external connection pads that are used for differential signal transmission out of the external connection pads. A resistor is provided between the external connection pads which are used for differential signal transmission. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly, to a semiconductor device compatible with high-speed signal transmission and a manufacturing method thereof.

  In recent years, with the progress of digitalization of electronic devices and the necessity of increasing the capacity and speed of signal transmission, high-speed data transmission between a plurality of semiconductor packages mounted on a printed wiring board is required.

  On the other hand, open-drain interface specifications and small-amplitude interface specifications such as LVDS (Low Voltage Differential Signaling) are known as clock synchronous high-speed input / output interface specifications.

  However, each of these conventional input / output interface specifications is a “single transmission method” in which a plurality of data bits are transmitted through a single data line, and has a problem of being easily affected by external noise.

  Therefore, as a high-speed input / output interface specification, there has been proposed a method using “differential transmission” in which common mode noise removal performance is improved by transmitting one data bit using two data lines. (For example, refer to Patent Document 1).

  One of the necessary items for properly functioning this differential transmission method is a technique of “termination” for differential wiring.

  In addition to the high-speed transmission of electronic devices described above, there is a strong demand for “lightening, thinning, and shortening of devices”, which is a basic concept of modern technology, and appropriate and highly integrated termination technology for differential wiring is eagerly desired.

  Termination is considered as “resistance value”, and in the case of the differential transmission method, generally 100Ω is often used.

  For example, if the termination resistance is designed to be 100Ω, the differential mode noise is theoretically perfectly matched and terminated by inserting a 100Ω chip resistor between two lines of the differential transmission path.

  However, in fact, in a high-speed transmission circuit that requires differential transmission, the distance between two lines of the differential transmission path is narrower than the width of the chip resistor, and therefore it is not possible to arrange a chip resistor between the lines. Can not.

  Therefore, a method is generally used in which a chip resistor connected to GND is provided around the outside of the pair of differential two lines, and the chip resistor is connected by connection wiring branched from each differential two line.

  Here, an actual termination method using a conventional general differential transmission system will be described with reference to FIG.

  In FIG. 2, reference numeral 20 denotes a semiconductor device that uses a differential signal 2A in a circuit on a substrate, and a region 21 where a differential transmission IC is mounted and a plurality of ball grid array type package ICs existing in the region. Solder ball receiving pads (hereinafter referred to as “receiving pads”) 22 and differential signal transmission lines (hereinafter referred to as “differential transmission lines”) connected to the receiving pads 22 of the receiving pads 22 used for differential transmission. 23) and a terminating resistor 2C branched from the receiving pad 22 of the receiving pad 22 used for differential transmission and connected to each branch line of the pair of differential transmission paths 23.

  As shown in FIG. 2, the pair of differential transmission lines 23 branches from the receiving pad 22 in the region 24, each branch line is connected to the termination resistor 2C, and each termination resistor 2C is connected to GND (2B If the termination resistors 2C are 50Ω chip resistors, the differential transmission line 23 is ± 50Ω with GND (2B) as the center, that is, between the differential transmission lines. A 100Ω differential termination resistor is provided.

  However, in practice, a commercially available chip resistor that is generally used is normally 51Ω, and the termination resistance value between the differential transmission lines is also 102Ω, which is different from the desired resistance value of 100Ω.

  In addition, although it varies depending on the product standard of the chip resistor to be used, there is always variation. For example, when a product with a standard that guarantees an accuracy of ± 5% is used, the termination resistance value between the differential transmissions is There is a possibility of changing in the range of 92Ω (equivalent to −10%) to 112Ω (equivalent to + 10%) with 102Ω as the center, and it is difficult to obtain a stable termination. Therefore, there is a possibility that stable differential transmission cannot be maintained. there were.

  Further, in the case of using the method of connecting to the chip resistor by the branched connection wiring, it is difficult to completely equalize the line from each of the pair of differential two lines to the terminating chip resistor. The balance between the two wires is lost, and there is a problem in that common mode noise occurs in addition to differential mode noise.

  Further, the connection wiring itself from each differential two line to the terminating chip resistor hinders the linearity of the differential line and causes the balance of the differential two lines to be lost, and also requires a differential transmission line. Such a high-speed transmission circuit is a factor that adversely affects delay and loss.

  Thus, a method of terminating the differential transmission path using a circuit called a center tap method has been proposed (for example, see Patent Document 2).

  Here, the termination method of the differential transmission line by the center tap method will be described with reference to FIG.

  In FIG. 3, reference numeral 30 denotes a semiconductor device that uses a differential signal 3A in a circuit in a substrate, and includes an area 31 on which a differential transmission IC is mounted, a plurality of receiving pads 32 existing in the area, and the receiving pads. 32, a differential transmission path 33 connected to a receiving pad 32 used for differential transmission, and a branch of the pair of differential transmission paths 33 branched from the receiving pad 32 used for differential transmission. A termination resistor 3C connected to each line and a capacitor 3D connected to the termination resistor 3C are provided.

  As shown in FIG. 3, the pair of differential transmission lines 33 branches from the receiving pad in the region 34, each branch line is connected to the termination resistor 3C, and each termination resistor 3C is connected in series. Since the capacitor 3D is connected to the connection portion of the two termination resistors and is connected to the GND (3B) via the capacitor 3D, the center of the two termination resistors becomes a virtual GND, and the differential 2 It is the structure which suppresses that the balance of a line is lost.

  With such a configuration, common mode noise is consumed by the impedance of each termination resistor 3C and capacitor 3D, and as a result, common mode noise is suppressed.

  However, as shown in FIG. 3, the center tap termination circuit requires at least two resistors and one capacitor in total, which is a total of three chip parts, and has high design flexibility for high-speed transmission that requires high integration and high-density wiring. There was a problem of binding.

Further, it is necessary to connect at least one terminal of the capacitor 3D to the GND, and there is a problem that the constraint on the degree of freedom of design is further increased.
JP-A-10-303521 JP 2001-053192 A

  The present invention has been made in view of the above problems and actual circumstances, and an object of the present invention is to provide a semiconductor device including a differential transmission path that is free from constraints on design freedom.

  That is, the present invention according to claim 1 is a differential signal transmission line in which a semiconductor integrated circuit is arranged at least on the surface layer or inside, and a plurality of pads for external connection for electrically connecting the semiconductor integrated circuit and the outside are arranged. In the semiconductor device including the above, the above problem is solved by a semiconductor device characterized in that a resistor is provided on a surface on which a plurality of pads for external connection are arranged.

  As a result, a semiconductor device including a differential signal transmission line that is free from design flexibility is obtained.

  The present invention according to claim 2 is characterized in that the resistor connects between two external connection pads.

  As a result, a semiconductor device including a differential signal transmission line including resistors arranged in the optimum shortest without detouring or branching can be obtained.

  The present invention according to claim 3 is characterized in that the two external connection pads are arranged adjacent to each other.

  This makes it possible to provide a differential termination resistor arranged at the optimum shortest without detouring or branching between the pads for differential signal transmission lines that are adjacent and close to each other.

  According to a fourth aspect of the present invention, the two external connection pads are differential signal transmission pads for transmitting a differential signal with the two different external connection pads as a pair, and the resistor Is a termination resistor for a differential signal transmission line that terminates the differential signal transmission line.

  As a result, even in a semiconductor device having a differential signal transmission line, it is possible to obtain a semiconductor device having a differential transmission path in which both differential mode noise and common mode noise are suppressed and there is no constraint on the degree of freedom of design. Become.

  The present invention according to claim 5 is characterized in that the resistor is a forming resistor.

  As a result, the differential termination resistor can be arranged regardless of the distance between the pair of differential lines 2 and the distance between the pads.

  According to the present invention, it is possible to provide a semiconductor device provided with a differential transmission path that is free from design flexibility.

  An embodiment of the present invention will be described with reference to FIGS. 1 (a) and 1 (b).

  FIG. 1A is a schematic plan view of a semiconductor device of the present invention. In FIG. 1A, reference numeral 1 denotes a semiconductor device that uses a differential signal 1A in a circuit in a substrate, and a plurality of ball grid array type package IC external connection solder ball receiving pads (hereinafter referred to as "receiving pads"). 2, a region 4 where two receiving pads used for differential transmission among the receiving pads 2 are arranged adjacent to each other, and a differential transmission path 3 connected to the two receiving pads used for differential transmission And a forming resistor 5 connected between the two receiving pads 2 used for the differential transmission.

  FIG. 1B is an enlarged schematic cross-sectional explanatory view of the forming resistor 5 in FIG. In FIG. 1B, the same reference numerals as those in FIG. 1A denote the same components, 6 a connection conductor for connecting a semiconductor bare chip (not shown) and the receiving pad 2, and 7 a main body of the semiconductor device 1. An insulator 8 is a solder ball welded to the receiving pad 2.

  FIG. 1 (b) shows the embodiment in a state where solder balls 8 are added to the receiving pad 2 in the region 4 of FIG. 1 (a) for easier understanding. .

  As shown in FIG. 1 (a), the semiconductor device 1 of the present invention has a forming resistor 5 between two receiving pads 2 used for differential transmission in the region 4, and therefore bypasses and branches. In other words, it is possible to obtain a differential termination resistor arranged in the shortest optimum for the differential transmission path 3.

  As a result, even in a semiconductor device provided with a differential signal transmission line, it is possible to obtain a semiconductor device provided with a differential transmission path in which both differential mode noise and common mode noise are suppressed and design freedom is not restricted.

  In addition, by using the termination method of the present invention, the differential termination resistor arranged at the optimum shortest without detouring or branching between the pads for differential signal transmission lines adjacent to and adjacent to each other by two pads can be provided. Obtainable.

  Therefore, it is possible to obtain a semiconductor device including a differential transmission path corresponding to a semiconductor package IC that is becoming smaller year by year regardless of the distance between a pair of differential two wires and the distance between pads.

  The forming resistor 5 may be a thick film forming resistor using a so-called thick film technology using a paste having a resistance function, and in this case, only a necessary portion on a solder ball bonding surface of a normal semiconductor package IC is used. It is possible to provide a thick film resistor, which is excellent in convenience and economy.

  The forming resistor 5 may be a thin film forming resistor using a thin film technique such as sputtering. In this case, the forming resistor is highly formed and the thickness of the resistor itself is about 1 μm or less. Therefore, the resistance value accuracy of the resistor in the product is extremely excellent.

  The forming resistor 5 may be a wiring resistor obtained by processing a copper foil with a resistance layer. In this case, other forming resistors on the same surface as the forming resistor can be processed simultaneously. In addition, there are no additional or repeated processes in the manufacturing process, no increase in tact (manufacturing speed) and manufacturing cost, and excellent economy.

  Incidentally, at present, a chip resistor having a shape small enough to match the forming resistance 5 is difficult to obtain without being available in the general market. However, a chip resistor having a shape small enough to match the forming resistance in the future is difficult. If the vessel can be easily obtained, it can naturally be used as an alternative to the forming resistor.

  For convenience of explanation, the semiconductor device 1 of the present invention is expressed using a semiconductor package substrate provided with receiving pads having the number and shape shown in FIG. 1A. The invention is not particularly limited by the type of the semiconductor package substrate, and is not limited to the semiconductor package substrate, and may be implemented by a printed wiring board having the same configuration.

  In the description of the present invention, the above-described embodiment has been described as an example. However, the configuration of the present invention is not limited to these, and is not limited to these examples, and is within the scope of the present invention. Various changes are possible.

(A) is a schematic plane explanatory view of the semiconductor device of the present invention, (b) is an enlarged schematic cross-sectional explanatory view of a forming resistance portion in the semiconductor device. FIG. 7 is a schematic plan view showing an example of a conventional semiconductor device. FIG. 10 is a schematic plan view showing another example of a conventional semiconductor device.

Explanation of symbols

1: Semiconductor devices 2, 22, 32: receiving pads 3, 23, 33: differential transmission paths 4, 24, 34: regions including receiving pads used for differential transmission 5: forming resistor 6: connecting conductor 7: insulator 8: Solder balls 20, 30: Semiconductor devices 21, 31: Regions 2A, 3A where differential transmission ICs are mounted: Differential signals 2B, 3B: GND
2C, 3C: Chip resistor 3D: Chip capacitor

Claims (5)

  In a semiconductor device including a differential signal transmission line in which a semiconductor integrated circuit is disposed at least on the surface layer or inside and a plurality of pads for external connection for electrically connecting the semiconductor integrated circuit and the outside are disposed, the pad for external connection A semiconductor device, wherein a resistor is provided on a surface on which a plurality of semiconductor devices are arranged.   2. The semiconductor device according to claim 1, wherein the resistor connects between two external connection pads.   3. The semiconductor device according to claim 1, wherein the two external connection pads are arranged adjacent to each other.   The two external connection pads are differential signal transmission pads for transmitting a differential signal with the two external connection pads as a pair, and the differential body terminates the differential signal transmission line. The semiconductor device according to claim 1, wherein the semiconductor device is a transmission line termination resistor.   The semiconductor device according to claim 1, wherein the resistor is a forming resistor.