JP2009021360A - Mos transistor and mos transistor circuit using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide MOS transistors capable of preventing output variation even when stress is applied to maintain high-precision characteristics, and a MOS transistor circuit using the same. <P>SOLUTION: The MOS transistors Tr1, Tr2, Tr3, Tr3a, Tr4, and Tr4a have a plurality of transistor cells M1 to Mn, N1 to Nn in the same shape disposed having sources and drains extended on both sides of gates in parallel. The plurality of transistor cells in the same shape have a plurality of transistor cells M1, M3, M11, M13, Mn-1, N1, N3, N11, N13, and Nn-1 which are disposed in the same direction and belong to a first group, and a plurality of transistor cells M2, M4, M12, M14, Mn, N2, N4, N12, N14, and Nn which are disposed in the same direction and belong to a second group, the number of the transistor cells belonging to the first group and that of the transistor cells belonging to the second group are the same. The disposition direction of the transistor cells belonging to the first group and that of the transistor cells belonging to the second group are different from each other. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a MOS transistor and a MOS transistor circuit using the same, and more particularly to a MOS transistor having a plurality of transistor cells and a MOS transistor circuit using the same.

  Conventionally, a CMOS type reference in which a depletion type MOS (Metal-Oxide Semiconductor) transistor and an enhancement type MOS transistor are connected in series, the depletion type MOS transistor is configured as a constant current source, and the enhancement type MOS transistor is configured as a constant voltage generation source. Voltage circuits are known.

  FIG. 8 is a diagram showing a circuit configuration of a conventional reference voltage circuit 150. In FIG. 8, a conventional reference voltage circuit 150 includes two MOS transistors Tr11 and Tr12, one of which is a depletion type MOS transistor Tr11 and the other is an enhancement type MOS transistor Tr12. The source of the depletion type MOS transistor Tr11 is connected in series with the drain of the enhancement type MOS transistor Tr12. The drain of the depletion type MOS transistor Tr11 is connected to the high potential side power supply line Vin, and the source of the enhancement type MOS transistor Tr12 is connected to the ground side wiring. The gates and back gates of the MOS transistors Tr11 and Tr12 are connected in common to the output line Vout together with the source of the depletion type MOS transistor Tr11 and the drain of the enhancement type MOS transistor Tr12, and output a reference voltage VREF therefrom.

  In FIG. 8, the depletion type MOS transistor Tr11 serves as a constant current source, and the enhancement type MOS transistor Tr12 outputs, for example, a reference voltage of 0.9V. Thus, a reference voltage circuit can be easily configured by combining two MOS transistors Tr11 and Tr12.

  FIG. 9 is a conventional pattern configuration diagram showing an example of how the circuit diagram of FIG. 8 is arranged and configured on an actual semiconductor substrate. In FIG. 9, MOS transistors Tr11 and Tr12 each have an elongated gate, and a drain and a source are formed at both ends thereof. In this manner, by arranging the drain and source at both ends of the elongated gate in the longitudinal direction, the MOS transistors Tr11 and Tr12 can be simply configured by one or two transistor cells, for example.

  By the way, such a reference voltage circuit is also used as a detection circuit for a lithium ion battery or a detection circuit for various sensors. Therefore, it is desirable that a highly accurate reference voltage can be output. In order to meet such a demand, conventionally, trimming, zapping and the like have been performed after manufacturing a semiconductor wafer, and fine adjustment has been made to cope with higher accuracy.

In the reference voltage semiconductor device having the depletion type N channel MOSFET and the enhancement type N channel MOSFET, the reference voltage circuit is more strongly affected by stress in the vertical direction than in the parallel direction with respect to the current flowing through the circuit. Therefore, of the stresses in two orthogonal directions in a plane at one point on the semiconductor chip, the stress voltage is arranged so that the direction in which the stress value is small and the direction of the current in the reference voltage circuit are perpendicular to each other. A reference voltage semiconductor device that is reduced is known (see, for example, Patent Document 1).
JP 2002-217369 A

  However, in the configuration of the above-described prior art, when the wafer is manufactured and mounted on a package or the like by a mold or the like, a stress is generated at the time of mounting, the characteristics of the MOS transistor fluctuate due to the piezoelectric effect due to the stress, and the normal distribution of variations in the reference voltage There was a problem that spread.

  Further, in the configuration described in Patent Document 1 described above, when the direction in which the stress is small cannot be specified, there is a problem that actual application becomes difficult and the reference voltage cannot be reduced.

  Accordingly, an object of the present invention is to provide a MOS transistor capable of preventing output fluctuation due to a piezo effect at the time of molding even when stress is applied and maintaining high-accuracy characteristics, and a MOS transistor circuit using the same. And

In order to achieve the above object, the MOS transistors (Tr1, Tr2, Tr3, Tr3a, Tr4, Tr4a) according to the first invention have a plurality of identical transistors in which the source and drain are arranged in parallel on both sides of the gate. MOS transistors (Tr1, Tr2, Tr3, Tr3a, Tr4, Tr4a) having transistor cells (M1 to Mn, N1 to Nn) having a shape,
The plurality of transistor cells (M1 to Mn, N1 to Nn) having the same shape are a plurality of transistor cells (M1, M3, M11, M13, Mn-1, N1, N1) belonging to the first group arranged in the same direction. N3, N11, N13, Nn-1) and a plurality of transistor cells (M2, M4, M12, M14, Mn, N2, N4, N12, N14, Nn) belonging to the second group arranged in the same direction Have
Transistor cells (M1, M3, M11, M13, Mn-1, N1, N3, N11, N13, Nn-1) belonging to the first set, and transistor cells (M2, M4, M12, M14, Mn, N2, N4, N12, N14, and Nn) are the same number and have different arrangement directions.

  As a result, even if stress is applied in one direction of the MOS transistor, the transistor cells belonging to the first group and the transistor cells belonging to the second group have different stresses in the transistor cells. As a result, the transistor deformation direction is dispersed and relaxed as a whole, and a highly accurate MOS transistor in which the influence of stress is reduced can be obtained. Also, a plurality of first transistor cells and second transistor cells are provided, and each transistor cell can be configured as a shape closer to a square rather than as one or two elongated transistor cells. Therefore, resistance to stress is improved, and deformation of the transistor cell itself can be reduced to reduce output fluctuation. Furthermore, when the direction and magnitude of stress generation are predictable, transistor cells can be arranged in accordance with those directions, and the influence of stress can be effectively reduced.

The second invention is the MOS transistor according to the first invention (Tr1, Tr2, Tr3, Tr3a, Tr4, Tr4a),
The arrangement direction of the transistor cells (M1, M3, M11, M13, Mn-1, N1, N3, N11, N13, Nn-1) belonging to the first group and the transistor cells (M2 belonging to the second group) , M4, M12, M14, Mn, N2, N4, N12, N14, Nn) are arranged at right angles.

  As a result, even if a stress in a certain direction is applied to the MOS transistor, there are the same number of transistor cells to which stress is applied in the gate width direction and transistor cells to which stress is applied in the gate length direction. The deformation of the entire MOS transistor is balanced, output fluctuation can be greatly reduced, and a highly accurate MOS transistor can be obtained.

  According to a third invention, in the MOS transistors (Tr1, Tr2, Tr3, Tr3a, Tr4, Tr4a) according to the first or second invention, the transistor cells (M1, M3, M11, M13, Mn-1, N1, N3, N11, N13, Nn-1) and transistor cells (M2, M4, M12, M14, Mn, N2, N4, N12, N14, Nn) belonging to the second set are gates The shape of is a square.

  As a result, each transistor cell is configured in a shape having the strongest tolerance in the vertical and horizontal directions of the plane, so that the resistance to stress can be greatly improved, the output fluctuation of the MOS transistor can be further reduced, and high accuracy can be achieved.

A fourth invention is the MOS transistor (Tr1, Tr2, Tr3, Tr3a, Tr4, Tr4a) according to any one of the first to third inventions,
The first transistor cells (M1, M3, M11, M13, Mn-1, N1, N3, N11, N13, Nn-1) and the second transistor cells (M2, M4, M12, M14, Mn, N2) , N4, N12, N14, Nn) are connected alternately.

  As a result, the first transistor cell and the second transistor cell can be arranged in a well-balanced manner, the layout can be facilitated, and the influence of stress can be made close to uniform.

A MOS transistor circuit according to a fifth invention is a MOS transistor circuit having two MOS transistors (Tr1, Tr2, Tr3, Tr3a, Tr4, Tr4a) according to any one of the first to fourth inventions,
The two MOS transistors (Tr1, Tr2, Tr3, Tr3a, Tr4, Tr4a) include a circuit portion commonly connected to one wiring.

  Thereby, the output fluctuation of the MOS transistor circuit including the MOS transistors symmetrically connected to one wiring can be reduced, and a highly accurate circuit can be obtained. In MOS transistor circuits in which MOS transistors are connected symmetrically with respect to one wiring, the layout is also often arranged symmetrically with respect to one wiring, and when subjected to stress, the two transistors are the same Therefore, the effect of applying the MOS transistor of the present invention is extremely large.

A sixth invention is the MOS transistor circuit according to the fifth invention, wherein
The MOS transistor circuit is a reference voltage circuit (50) in which the one wiring is an output line (Vout),
One of the MOS transistors (Tr1) is a depletion type MOS transistor that performs a constant current operation in which a source is connected to the output line and a drain is connected to a high potential supply wiring,
The other of the MOS transistors (Tr2) is an enhancement type MOS transistor having a drain connected to the output line (Vout) and a source connected to a low potential side wiring and receiving a constant current of the depletion type MOS transistor. It is characterized by that.

  Thereby, the fluctuation | variation of the reference voltage output from a reference voltage circuit can be reduced significantly. Since the reference voltage circuit is a simple circuit composed of two MOS transistors connected in series, the output fluctuations of the two MOS transistors have an extremely large effect. A reference voltage circuit capable of supplying a reference voltage can be obtained.

A seventh invention is the MOS transistor circuit according to the fifth invention, wherein
The MOS transistor circuit is a differential amplifier circuit (100, 100a) in which the one wiring is a ground line (LG),
One of the MOS transistors (Tr3, Tr3a) has a source connected to the ground line and a gate connected to one input terminal (Vin1) of the differential amplifier circuit,
The other of the MOS transistors (Tr4, Tr4a) has a source connected to the ground line (LG) and a gate connected to the other input terminal (Vin2) of the differential amplifier circuit. .

  As a result, the output fluctuation of the differential amplifier circuit used in the input stage of the operational amplifier can be reduced.

  In addition, the code | symbol in the said parenthesis is attached | subjected in order to make an understanding easy, is only an example, and is not limited to the aspect of illustration.

  According to the present invention, it is possible to obtain a highly accurate MOS transistor and MOS transistor circuit in which output fluctuation due to stress is reduced.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram illustrating MOS transistors Tr1 and Tr2 and a reference voltage circuit 50 using the same according to a first embodiment to which the present invention is applied. Note that the same reference numerals are assigned to the same components as those described so far.

  In FIG. 1, the reference voltage circuit 50 includes a MOS transistor Tr1 and a MOS transistor Tr2. The MOS transistor Tr1 is a depletion type N-channel MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor, MOS field effect transistor), and the MOS transistor Tr2 is an enhancement type N-channel MOSFET. In the reference voltage circuit 50 according to the present embodiment, a depletion-type N-channel MOSFET and an enhancement-type N-channel MOSFET constitute a CMOS (Complementary Metal-Oxide Semiconductor).

  The MOS transistor Tr1 is composed of four elements of transistor cells M1, M2, M3, and M4. The MOS transistor Tr1 is configured in series connection in which the source and drain of each of the transistor cells M1 to M4 are connected, and the drain of the transistor cell M1 closest to the high potential supply line Vin is a high potential that is a power supply line. Connected to the supply line Vin. The source of the transistor cell M4 closest to the output line Vout is connected to the output line Vout. The gates and back gates of the transistor cells M1 to M4 are all connected to the output line Vout in common.

  Similarly, the MOS transistor Tr2 is composed of four elements of transistor cells N1, N2, N3, and N4. The MOS transistor Tr2 is also configured in series connection in which the sources and drains of the transistor cells N1 to N4 are connected, and the drain of the transistor cell N1 closest to the output line Vout is connected to the output line Vout. The source of the transistor cell N4 closest to the ground GND is grounded. Further, all the gates are commonly connected to the output line Vout, and all the back gates are commonly grounded.

  Although details will be described later, the size of one of the transistor cells M1 to M4 and N1 to N4 is reduced by configuring the MOS transistors Tr1 and Tr2 with a plurality of transistor cells M1 to M4 and N1 to N4. In addition, the transistor can have a shape close to a square, and the physical resistance of the transistor cells M1 to M4 and N1 to N4 against stress can be improved. Further, since a plurality of transistor cells M1 to M4 and N1 to N4 are provided, various arrangements are possible, and the MOS transistors Tr1 and Tr2 can be configured with an arrangement that achieves high accuracy.

  The transistor cells M1 to M4 and N1 to N4 are divided into small transistor cells M1 to M4 and N1 to N4 rather than a plurality of the single MOS transistors Tr11 and Tr12 described in the prior art. Is appropriate. Therefore, it can be considered that the four transistor cells M1 to M4 constitute one MOS transistor Tr1, and the four transistor cells N1 to N4 constitute one MOS transistor Tr2. Therefore, the reference voltage circuit 50 according to the present embodiment has a configuration in which an increase in the area occupied on the semiconductor substrate is suppressed even if the number of transistor cells M1 to M4 and N1 to N4 increases.

  As described above, the MOS transistor Tr1 having four transistor cells M1 to M4 and the MOS transistor Tr2 having four transistor cells N1 to N4 correspond to one MOS transistor Tr1 and Tr2, respectively. Accordingly, in the reference voltage circuit 50 as a whole, like a general reference voltage circuit, the MOS transistor Tr1 composed of a depletion type N channel MOSFET serves as a constant current source, and is composed of an enhancement type N channel MOSFET. The MOS transistor Tr2 serves as a constant voltage generation source that receives the constant current from the MOS transistor Tr1 and outputs a reference voltage VREF of about 0.9 V to the output line Vout.

  Next, the pattern configuration on the semiconductor substrate of the MOS transistors Tr1 and Tr2 according to the first embodiment will be described with reference to FIG. FIG. 2 is a diagram showing an example of a planar pattern configuration on the semiconductor substrate of the MOS transistor Tr1.

  In FIG. 2, the transistor cells M1 to M4 are independently arranged in one horizontal row. In FIG. 2, the horizontal direction is represented by X and the vertical direction is represented by Y in order to indicate the arrangement direction. The transistor cells M1 to M4 are configured such that the drain and the source are arranged on both sides of the gate. The drain and the source are configured in an elongated rectangular or rectangular shape, whereas the central gate is configured in a square. ing. In addition, in the transistor cells M1 and M3, the extending direction of the drain and the source is the X direction, whereas in the transistor cells M2 and M4, the extending direction of the drain and the source is the Y direction. Orthogonal. In the transistor cells M1 to M4, the source of the transistor cell M1 is connected to the drain of the transistor cell M2 via the connection wiring LC, and the source of the transistor cell M2 is connected to the drain of the transistor cell M3 via the connection wiring LC. Thus, each is connected in series. Further, the drain of the transistor cell M1 is connected to the high potential supply line Vin, and the source of the transistor cell M4 is connected to the output line Vout, which corresponds to the MOS transistor Tr1 in FIG.

  Here, the length of the gate sandwiched between the drain and the source, that is, the length of the gate perpendicular to the extending direction of the drain and the source is the gate length L, and the width of the gate parallel to the extending direction of the drain and the source is the gate. It will be called the width W.

  In FIG. 2, each of the transistor cells M1 to M4 has the same shape, and is configured by transistor cells having the same ratio W / L of the gate width W to the gate length L. In the transistor cells M1 and M3, the gate length L is parallel to the Y axis, and the gate width W is parallel to the X axis. In the transistor cells M2 and M4, the gate length L is parallel to the X axis, and the gate width W is parallel to the Y axis. Therefore, when the direction is determined by the relationship between the gate lengths L and the gate widths W, the transistor cells M1 and M3 and the transistor cells M2 and M4 are in an arrangement relationship that is orthogonal or intersects at right angles. Two transistor cells M1 and M3 and two transistor cells M2 and M4 that are orthogonal to each other are equal in number. As described above, in the MOS transistor Tr1 according to the present embodiment, the transistor cells M1 and M3 whose drains and sources extend in the X direction in the same direction are the transistor cells, drains, and sources that belong to the first group in the same direction. If the transistor cells M2 and M4 extending in the Y direction are transistor cells belonging to the second set, the transistor cells M1 and M3 belonging to the first set and the transistor cells M2 and M4 belonging to the second set The same number exists, and as a whole, there are an even number of transistor cells M1 to M4. That is, it may be considered that the transistor cells M1 to M4 that are orthogonal to each other form a one-to-one pair.

  In the MOS transistor Tr1 having such a configuration, consider a case where, for example, stress is applied such that the transistor cells M1 to M4 extend in the X direction. When stress is applied in the X direction, the gate width W of the transistor cells M1 and M3 belonging to the first group increases, and the ratio W / L of the gate width W to the gate length L increases. On the other hand, in the transistor cells M2 and M4 belonging to the second set, the gate length L increases, and the ratio W / L of the gate width W to the gate length L decreases. As a result, the fluctuation of the ratio W / L of the gate width W to the gate length L as a whole can be reduced. In other words, in the present embodiment, if there is a variation in one direction in the prior art, the MOS transistor Tr1 is subdivided into the gate length L and the MOS transistor Tr1 that has affected the MOS transistor Tr1 as a variation in absolute value. The arrangement is such that the influence of stress is equally distributed to both the gate widths W, and converted into relative fluctuations. As described above, when a unidirectional stress is applied to the MOS transistor Tr1, the influence of the stress cannot be completely avoided. However, according to the MOS transistor Tr1 of the present embodiment, the influence is mitigated and the fluctuation is suppressed. Even if stress is applied, the characteristics of the high-precision MOS transistor Tr1 can be maintained.

  In the present embodiment, in order to facilitate understanding, the case where stress is applied only in one direction (X direction) has been described. However, even if other stress is further applied, the same applies to that. Since it is configured to convert to relative variation, the MOS transistor Tr1 according to the present embodiment can be similarly applied even when stress is applied from a plurality of directions. Further, even if stress is applied in a direction different from the X direction and Y direction, the stress can be decomposed into stress in the X direction and Y direction by a vector, and this can be similarly applied.

  The transistor cells M1 to M4 are preferably divided into units as fine as possible because deformation due to stress is reduced and the effect of suppressing variation is enhanced. In the MOS transistor Tr1 according to this embodiment, the gate shape is described as an example of a square that is considered to have the highest resistance to stress, that is, the ratio of the gate width W to the gate length L is 1: 1. However, as long as the ratio W / L of the gate width W to the gate length L is constant, various modes may be applied. For example, the shape of the gate may be a rectangle close to a square, or the semiconductor substrate to which the MOS transistor Tr1 according to the present embodiment is applied is easily affected by stress in a certain direction, and in a certain direction. In the case where resistance to stress varies depending on the direction, such as being hardly affected by stress, it may be configured by transistor cells M1 to M4 having a ratio W / L of gate width W to gate length L considering them. .

  Further, in the MOS transistor Tr1 according to the present embodiment, the arrangement direction of the transistor cells M1 and M3 belonging to the first group and the arrangement direction of the transistor cells M2 and M4 belonging to the second group are arranged to be orthogonal to each other. Although an example of the configuration has been described, for example, in consideration of the characteristics of the semiconductor substrate as described above, the way of applying stress in molding, and the like, it may be arranged at an angle shifted from 90 degrees at right angles. By arranging the same number of transistor cells M1 to M4 having different angles, the stress in one direction can be converted into the fluctuation of the relative transistor cells M1 to M4, so that the fluctuation due to the stress can also be reduced and the accuracy is improved. be able to. Thus, the relationship in the arrangement direction between the transistor cells M1 and M3 belonging to the first group and the transistor cells M2 and M4 belonging to the second group may be appropriately changed according to the application. In the MOS transistor Tr1 according to the present embodiment, the different arrangement directions mean an arrangement relationship in which the extending directions of the drains and sources of the transistor cells M1 to M4 cross each other, and are mutually point-symmetric. In other words, the extending direction of the drain and the source is the same X direction, but does not include a state in which the drain and the source face each other. Even if the arrangement relationship between the drain and the source is different, as long as these extending directions are the same, the extending directions of the gate length L and the gate width W are the same, and the stress is applied to the gate length L and the gate width W. This is because the effects of are the same.

  In the MOS transistor Tr1 according to the present embodiment, the transistor cells M1 to M4 have been described as examples using a single cell having the same size. However, the transistors in different arrangement directions form a one-to-one pair. If transistor cells M1 to M4 having the same size exist among the cells M1 to M4, the sizes of the transistor cells M1 to M4 may not be the same. For example, as long as the transistor cell M1 and the transistor cell M2 have the same size, and the transistor cell M3 and the transistor cell M4 have the same size, the sizes of the transistor cell M1 and the transistor cell M3 may be different. This is because even in such a configuration, the balance between the gate length L and the gate width W affected by the stress is maintained. For example, in the case where the number of transistor cells M1 to M4 is larger and the size of the transistor cells must be included because of the layout, the transistor cells belonging to the first set and the second set belong to the second set. Various sizes of transistor cells may be used while maintaining a one-to-one relationship between the transistor cells.

  In the MOS transistor Tr1 according to the present embodiment, an example in which the transistor cells M1 and M3 belonging to the first set and the transistor cells M2 and M4 belonging to the second set are alternately arranged and connected alternately will be described. However, as long as the same number exists, the arrangement relationship and the connection relationship do not necessarily have to be alternate. However, when the number of transistor cells M1 to M4 is larger, if the transistor cells belonging to the same group are hardened in one place, the influence from the stress may differ depending on the arrangement position. It is preferable that the configuration be close to the connection.

  As described above, the MOS transistor Tr1 according to the present embodiment can reduce fluctuations and realize highly accurate characteristics even when stress is applied, and can be applied to various modes. In FIG. 2, the MOS transistor Tr1 is described as an example, but the same applies to the MOS transistor Tr2.

  Next, an example in which the MOS transistor Tr1 according to this embodiment is expanded will be described with reference to FIG. FIG. 3 is a diagram showing an arrangement configuration of the MOS transistor Tr1 having n transistor cells M1 to Mn on the semiconductor substrate.

  3, transistor cells M1, M3,... Mn-1 belonging to the first group and transistor cells M2, M4,... Mn belonging to the second group are alternately arranged in a line in the X direction. Thus, the MOS transistor Tr1 according to the present embodiment may be set by appropriately increasing or decreasing the number of transistor cells M1 to Mn according to the application. Even in this case, the transistor cells M1, M3,... Mn-1 belonging to the first group arranged in the same direction and the transistor cells M2, M4,. The same number of Mn is present and the arrangement directions are different from each other. The arrangement direction, size, and connection relationship of the transistor cells M1 to Mn are the same as those described in FIG. 2, and the transistor cells M1 to Mn can be applied to many more modes as the number of the transistor cells M1 to Mn increases. .

  Thus, the MOS transistor Tr1 according to the present embodiment is applicable even if the total number is further increased as long as the total number of the transistor cells M1 to Mn is 4 or more. Needless to say, this content can also be applied to the MOS transistor Tr2. When the MOS transistor Tr1 of the reference voltage circuit 50 shown in FIG. 1 is composed of transistor cells M1 to Mn, the MOS transistor Tr2 is also composed of transistor cells N1 to Nn in order to maintain the same transistor characteristics. It is preferable.

  Here, in the case of n = 6, there are three transistor cells belonging to the first group and three transistor cells belonging to the second group, respectively, and the ratio of the gate width W to the gate length L W / L = 10 / Consider an example in which a stress is applied in the X direction or the Y direction and 10% variation occurs in the MOS transistor Tr1 in which ten transistor cells M1 to M6 are connected in series. The 10% fluctuation is a value that is too large from the normal viewpoint, but here, an example of the 10% fluctuation will be described for easy understanding.

  First, the initial value of the entire MOS transistor Tr1 with the ratio L / W of the gate length L to the gate width W before stress is applied is L / W = 10/10 × 6 = 60/10.

  Next, when stress is applied, in the conventional example, when the gate length is reduced by 10%, L / W = 9/10 × 6 = 54/10, and the gate length L is 10%. % Change as it is ((54/10) × (10/60) = 54/60 = 9/10).

  On the other hand, in this embodiment, L / W = 9/10 × 3 + 10/9 × 3 = 543/90 = 60.33 / 10, and the variation of the gate length L is 0.55% ((60.33 /10)×(10/60)=60.33/60=10.055/10).

  As described above, the MOS transistor Tr1 according to the present embodiment can greatly reduce the fluctuation due to the piezo effect to 1/20 compared with the conventional one, and can maintain high-precision characteristics even when stress is applied. It can be seen that the configuration is possible.

  Next, an example of the arrangement configuration on the semiconductor substrate of the MOS transistors Tr1 and Tr2 applied to the reference voltage circuit 50 according to this embodiment of FIG. 1 will be described with reference to FIG.

  FIG. 4 is a diagram showing a layout on the semiconductor substrate of the reference voltage circuit 50 according to the present embodiment. In FIG. 4, a depletion type N channel MOS transistor Tr1 and an enhancement type N channel MOS transistor Tr2 are connected in series. The MOS transistor Tr1 includes four transistor cells M1 to M4, and the MOS transistor Tr2 also includes four transistor cells N1 to N4.

  The MOS transistors Tr1 and Tr2 are connected in series connection in which the source S and drain D of the transistor cells M1 to M4 and N1 to N4 are connected by a connection wiring LC. The drain D of the transistor M1 is connected to the high potential supply line Vin, and the source S of the transistor N4 is grounded. Further, the source S of the transistor cell M4 and the drain D of the transistor cell N1 are both connected to the output line Vout. In FIG. 4, the connection between the gate G and the back gate is omitted.

  In FIG. 4, MOS transistors Tr1 and Tr2 according to the present embodiment have transistor cells M1 to M4 and N1 to N4 arranged in a square matrix of 2 rows × 2 columns. The arrangement of devices on a semiconductor substrate of a semiconductor device such as a semiconductor integrated circuit device is preferably arranged as close to a square as possible from the viewpoint of minimizing the area of the semiconductor substrate. In consideration of such points, for example, in FIG. 4, the transistor cells M1 to M4 and N1 to N4 are arranged in 2 rows × 2 columns so that the MOS transistors Tr1 and Tr2 each have a square shape. Arranged like a square matrix. As a result, the area occupied by the reference voltage circuit 50 in the semiconductor device can be reduced, and a MOS transistor circuit having high resistance to stress can be obtained. For example, such an arrangement may be applied to the MOS transistors Tr1 and Tr2 and the reference voltage circuit 50 using the same according to the present embodiment.

  In the reference voltage circuit 50 according to the present embodiment, both the source of the MOS transistor Tr1 and the drain of the MOS transistor Tr2 are connected to the output line Vout, and the arrangement configuration is symmetrical with respect to the output line Vout. Tr1 and MOS transistor Tr2 are arranged. As described above, in the MOS transistor circuit having the MOS transistor structure symmetric with respect to one wiring, the deformation correction effect due to stress by the MOS transistor according to the present embodiment is high due to the symmetry. It is particularly preferable to apply a MOS transistor.

  In addition, the MOS transistor circuit to which the MOS transistors Tr1 and Tr2 are applied may have various other planar configuration modes, and these may be appropriately set according to the application.

  Thus, by applying the MOS transistors Tr1 and Tr2 according to the present embodiment to the reference voltage circuit 50, the reference voltage circuit 50 has a small area occupied on the semiconductor substrate and is a highly accurate MOS even when stress is applied. It can be configured as a transistor circuit.

  FIG. 5 is a circuit diagram illustrating MOS transistors Tr3 and Tr4 and a differential amplifier circuit 100 using the same according to the second embodiment.

  5, the differential amplifier circuit 100 according to the second embodiment includes a Vin1 and Vin2 that constitute input terminals of the differential amplifier circuit, an output terminal Vout, and a MOS transistor according to the present embodiment that constitutes the differential input circuit. Tr3 and Tr4, MOS transistors Tr5 and Tr6 constituting a current mirror circuit, and a MOS transistor Tr7 which is a constant current source are included. The drains of the MOS transistors Tr5 and Tr6 are connected to a high potential supply line VDD which is a power supply line, and the source of the MOS transistor Tr7 is grounded. The MOS transistors Tr3, Tr4, Tr7 are N channel MOS transistors, and the MOS transistors Tr5, Tr6 are P channel MOS transistors.

  The MOS transistors Tr3 and Tr4 according to the present embodiment include four transistor cells M11 to M14 and N11 to N14, each of which is plural and even. The transistor cells M11 to M14 and N11 to N14 are connected in parallel, and the drains and back gates of the transistor cells M11 to M14 are commonly connected to the source of the MOS transistor Tr5, and the transistor cells M11 to M14 are connected. Are commonly connected to the ground line LG. The connection line LG is provided with a MOS transistor Tr7. The MOS transistor Tr7 has a drain connected to the sources of the transistor cells M11 to M14 and a source grounded. Similarly, the drains and back gates of the transistor cells N11 to N14 are commonly connected to the source of the MOS transistor Tr6, and the sources of the transistor cells N11 to N14 are commonly connected to the drain of the MOS transistor Tr7 via the ground line LG. It is connected to the. The gates of the transistor cells M11 to M14 are commonly connected to the input terminal Vin1 of the differential amplifier circuit, and the gates of the transistor cells N11 to N14 are commonly connected to the input terminal Vin2 of the differential amplifier circuit. As described above, in the MOS transistors Tr3 and Tr4 according to the present embodiment, the transistor cells M11 to M14 and N11 to N14 may be configured in parallel connection. Even in parallel connection, the transistor cells M11 to M14 and N11 to N14 can be arranged in the same number of arrangement directions and can be connected by the connection wiring LC. Can be applied.

  In the differential amplifier circuit 100 according to this embodiment, when the voltage input to the input terminal Vin1 is larger than the voltage input to the input terminal Vin2, the bias voltage is supplied and the MOS transistor Tr7 that is a constant current source is turned on. Since the flowing current is constant, the current flowing through the MOS transistor Tr3 flows more than the current flowing through the MOS transistor Tr4. Then, a large amount of current flows through the P-channel MOS transistor Tr5, and the same current also flows through the MOS transistor Tr5 and the upper part of the MOS transistor Tr6 constituting the current mirror circuit. On the other hand, since a small amount of current flows through the MOS transistor Tr4 constituting the differential input circuit, the differential current between the MOS transistor Tr6 and the MOS transistor Tr4 is output from the output line Vout, and the difference between the input voltages is differentiated. The current can be extracted from the output line Vout as a current.

  Here, the MOS transistors Tr3 and Tr4 according to the present embodiment constituting the differential input circuit are both connected to the ground line LG to which the MOS transistor Tr7 which is a constant current source is connected, and are symmetrical with respect to the ground line LG. It has become a structure. As described above, when the entire circuit is configured symmetrically with respect to one wiring, the symmetrically arranged MOS transistors Tr3 and Tr4 both play the same symmetrical role. Even if a common stress is applied to both of the two stresses, the common absolute value fluctuation is converted into a relative change, and the change in the ratio W / L of the gate width and gate length of the transistor cells M11 to M14 and N11 to N14 It is significant to apply the present invention to suppress the above.

  FIG. 6 is a diagram illustrating an example of an arrangement configuration on the semiconductor substrate of the MOS transistor Tr3 according to the second embodiment. In the differential amplifier circuit 100 according to the second embodiment, since the MOS transistors Tr3 and Tr4 are configured in parallel, they are also configured correspondingly in FIG.

  In FIG. 6, in the transistor cells M11 and M13 belonging to the first group, the extending direction of the drain and the source is the X direction, and in the transistor cell M12 and M14 belonging to the second group, the extending direction of the drain and the source Is the Y direction, and they are arranged at a right angle. Each of the transistor cells M11 to M14 is configured with the same W / L ratio, and here, W / L is approximately 10/10. Two transistor cells M11 and M13 belonging to the first set and two transistor cells M12 and M14 belonging to the second set are the same number. The points described so far are the same as the configuration of the MOS transistor Tr1 described in FIG. 2, but in FIG. 6, the drain of the transistor cell M11 is connected to the drain of the transistor cell M12, and the drain of the transistor cell M12 is the transistor As being connected to the drain of the cell M13, the transistor cells M11 to M14 are different from FIG. 2 in that the drains and sources of adjacent transistor cells are connected to each other. By configuring in this way, even in the case of parallel connection, fluctuation due to stress can be reduced and the MOS transistor can be configured with high accuracy.

  The other principles and various aspects are the same as those described in FIGS. 2, 3, and 4, and the description thereof is omitted.

  FIG. 7 is a diagram showing a differential amplifier circuit 100a to which MOS transistors Tr3a and Tr4a having a mode different from that in FIG. 5 are applied. In FIG. 7, the overall configuration of the differential amplifier circuit 100a is the same as that of the differential amplifier circuit 100 according to FIG. 5, but the MOS transistors Tr3a and Tr4a configuring the differential input circuit include transistor cells M11 to M14 and N11. ˜N14 is different from the differential amplifier circuit 100 according to FIG.

  Thus, even if the MOS transistors Tr3a and Tr4a are configured by connecting the transistor cells M11 to M14 and N11 to N14 in series, the MOS transistors Tr3a and Tr4a can be applied to the differential amplifier circuit 100a. In this case, the arrangement configuration of the transistor cells M11 to M14 and N11 to N14 is the same as the arrangement described with reference to FIGS.

  In the differential amplifier circuits 100 and 100a shown in FIGS. 5 and 7, the MOS transistors Tr1 to Tr4 according to the embodiment of the present invention are not applied to the MOS transistors Tr5, Tr6, and Tr7. Accordingly, the same aspects as those of the MOS transistors Tr1 to Tr4 according to the embodiments of the present invention may be applied thereto. The MOS transistors Tr1 to Tr4 according to the embodiments of the present invention may be applied not only to a symmetrically configured circuit but also to a single MOS transistor. Against this, the fluctuation due to stress is reduced and high-precision characteristics are achieved. Can keep.

  As described above, the MOS transistors Tr1 to Tr4 according to the present embodiment can be applied to various types of MOS transistor circuits. As described in the first and second embodiments, the transistor configuration is symmetric with respect to one wiring. The present invention can be particularly preferably applied to the MOS transistor circuit having the above.

  The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the present invention. Can be added.

FIG. 3 is a diagram illustrating MOS transistors Tr1 and Tr2 and a reference voltage circuit 50 according to the first embodiment. It is the figure which showed an example of the plane structure on the semiconductor substrate of MOS transistor Tr1. It is the figure which showed the arrangement configuration on the semiconductor substrate of MOS transistor Tr1. It is the figure which showed the layout on the semiconductor substrate of the reference voltage circuit 50 which concerns on a present Example. FIG. 6 is a circuit diagram illustrating MOS transistors Tr3 and Tr4 and a differential amplifier circuit 100 according to a second embodiment. It is the figure which showed the example of arrangement configuration on the semiconductor substrate of MOS transistor Tr3. FIG. 6 is a diagram showing a differential amplifier circuit 100a to which MOS transistors Tr3a and Tr4a having a mode different from that in FIG. 5 are applied. FIG. 6 is a diagram showing a circuit configuration of a conventional reference voltage circuit 150. FIG. 10 is a plan configuration diagram showing a configuration example of a conventional reference voltage circuit 150 on a semiconductor substrate.

Explanation of symbols

Tr1, Tr2, Tr3, Tr3a, Tr4, Tr4a, Tr5, Tr6, Tr7 MOS transistors M1-Mn, N1-N4, M11-M14, N11-N14 Transistor cells G Gate D Drain S Source Vin, VDD High potential supply line Vout Output line Vin1, Vin2 Input terminal LC connection wiring LG Ground line 50, 150 Reference voltage circuit 100, 100a Differential amplifier circuit

Claims (7)

A MOS transistor having a plurality of identically-shaped transistor cells arranged on both sides of the gate with the source and drain extending in parallel;
The plurality of transistor cells having the same shape include a plurality of transistor cells belonging to a first group arranged in the same direction and a plurality of transistor cells belonging to a second group arranged in the same direction,
A MOS transistor characterized in that the number of transistor cells belonging to the first group and the number of transistor cells belonging to the second group are the same, and the arrangement directions are different.   2. The MOS transistor according to claim 1, wherein an arrangement direction of the transistor cells belonging to the first group is perpendicular to an arrangement direction of the transistor cells belonging to the second group.   3. The MOS transistor according to claim 1, wherein the transistor cell belonging to the first group and the transistor cell belonging to the second group have a square gate shape. 4.   4. The MOS transistor according to claim 1, wherein the transistor cells belonging to the first group and the transistor cells belonging to the second group are alternately connected. 5. A MOS transistor circuit comprising two MOS transistors according to any one of claims 1 to 4,
2. The MOS transistor circuit according to claim 2, wherein the two MOS transistors include a circuit portion commonly connected to one wiring. The MOS transistor circuit is a reference voltage circuit in which the one wiring is an output line,
One of the MOS transistors is a depletion type MOS transistor that performs a constant current operation in which a source is connected to the output line and a drain is connected to a high potential supply wiring,
The other of the MOS transistors is an enhancement type MOS transistor having a drain connected to the output line and a source connected to a low potential side wiring and receiving a constant current of the depletion type MOS transistor. Item 6. The MOS transistor circuit according to Item 5. The MOS transistor circuit is a differential amplifier circuit in which the one wiring is a ground line,
One of the MOS transistors has a source connected to the ground line and a gate connected to one input terminal of the differential amplifier circuit,
6. The MOS transistor circuit according to claim 5, wherein the other of the MOS transistors has a source connected to the ground line and a gate connected to the other input terminal of the differential amplifier circuit.

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