JP2009020971A - Semiconductor test device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor test device which can detect efficiently data by decreasing the data of the number which has been determined as being a failure in a test result. <P>SOLUTION: In a semiconductor test device 100, respective address is referred successively for each row of a fail memory 120, a change point at which fail information is changed is detected, and continuous number data are generated. Also the continuous number data generated at a previous row is stored in a storage memory 180, and it is discriminated whether continuous number data output from data FIFO 140a agrees with continuous number data output to the data FIFO 140a. Based on the discrimination of the agreement, when they agree, distribution region data are generated, and processing in which continuous number data stored in the storage memory 180 are overwritten is performed. Processings in which continuous number data are generated, up to the final row, is executed repeatedly. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor test apparatus for performing a test for determining pass or fail by outputting a test signal to an object to be tested such as a memory device, and more particularly, a fail memory in which fail information representing a pass or fail is stored as a test result. Thus, the present invention relates to a circuit configuration for efficiently acquiring fail information.

  2. Description of the Related Art Conventionally, a semiconductor that performs a test such as confirmation of a read or a write operation by outputting a test signal to a device under test (hereinafter referred to as a DUT) such as a memory device having a plurality of addresses to access each address. In the test apparatus, the signal output from the DUT and the expected value are compared to determine pass or fail. The semiconductor test apparatus stores the information determined to be pass or fail in a fail memory having an address that is the same as that of the DUT or is compressed to a fraction.

  In the memory test apparatus described in Patent Document 1 below, when the pattern generator is generating a back pattern, the fail bit counter counts the number of fail bits in the previous test by the fail bit counter, After the count, a count end signal is given to the pattern generator. After receiving the count end signal, the pattern generator generates a test pattern in the memory under test and an address to shorten the DUT test time (see, for example, Patent Document 1).

  Moreover, in the conventional semiconductor test apparatus, the number determined to be failed was detected as follows. FIG. 9 is an explanatory diagram showing a configuration of a conventional semiconductor test apparatus 200. In the semiconductor test apparatus 200, fail information is accumulated and stored in a fail memory 220 having an address that is the same as that of the DUT or that is compressed to a fraction. For example, as shown in FIG. 10, the fail memory 220 has a two-dimensional storage area composed of the same column (X axis) and row (Y axis) as the DUT, and the fail address is assigned to the same address determined as fail. The information of “x” shown is stored.

  When fail information is read sequentially from the address of the fail memory 220 in accordance with the address generated by the address generation circuit 210, the fail detection circuit 230 detects fail information from these test results. The address of the fail information is written in the FIFO 240, and the repair operation circuit 250 sequentially reads the address from the FIFO 240 and performs the repair operation.

  Then, when fail information is read from the fail memory 220 and the number determined to be failed is detected, the address generation circuit 210 (X, Y) = (0, 0) → (0, 1) → (0, 2)... Generate addresses that sequentially specify the addresses of the fail memory 220. The fail memory 220 sequentially reads and outputs fail information from each address in accordance with these addresses, and the fail detection circuit 230 detects fail information from the fail information.

  The fail detection circuit 230 writes the address where the detected fail information is stored in the FIFO 240, and the relief calculation circuit 250 reads out these addresses and the like from the FIFO 240 and performs calculations. That is, an operation for replacing a cell at an address determined to be a failure is performed using a spare cell on a line along a predetermined X axis and Y axis. For example, if two spare cells are prepared along each of the X and Y axes, as shown in FIG. 10, cells on the X = 3, Y = 2 line are used as spare cells. Further, an operation is performed to replace the cell of (X, Y) = (1, 1) with the remaining spare cell along the X axis or Y axis.

JP 2004-348892 A

  However, the conventional semiconductor test apparatus 200 has the following problems. That is, when there is a lot of fail information detected by the fail detection circuit 230, data such as addresses for each fail information written in the FIFO 240 increases, and accordingly, each address of these information from the FIFO 240, etc. There is a problem that the time for reading out becomes longer. For example, as shown in FIG. 10, in the fail memory 220, there are a bit fail in which cells each having an address determined to be a fail are scattered one by one, and a line fail that exists on a line along the X axis or the Y axis. However, if the number of line failures increases, the amount of data written to the FIFO 240 increases significantly.

  Here, if three or more cells at the address determined to be failed are arranged on the line, these are replaced with spare cells, so data such as the addresses of the fourth and subsequent cells on the same line is unnecessary. It is. However, conventionally, since the fourth and subsequent data are also written in the FIFO 240, the time is increased accordingly.

  Note that the address generation circuit 210 stops the process of generating an address when it is determined that the repair operation circuit 250 performs the operation in parallel while performing the process of reading each address and the like from the FIFO 240 and is replaced with a spare cell. It is also possible to clear the address data including the fourth and subsequent cells and prevent further reading. However, in this case, there is a problem that a time for performing an operation and a time for clearing data are required, and the time as a whole becomes long.

  Accordingly, an object of the present invention is to provide a semiconductor test apparatus capable of efficiently detecting data with a reduced number of data determined to be a failure as a result of the test.

  In order to achieve the above-described problems, a semiconductor test apparatus according to the present invention refers to a fail memory that stores a plurality of pieces of fail information determined to be a pass or a fail for a test target, and the fail memory. An area detecting unit that detects an area in which the distribution of pass or fail information is repeatedly stored multiple times, and the distribution of pass or fail information is repeated multiple times for the area detected by the area detecting unit. And a data generation means for generating distribution area data indicating that the data is distributed.

  With such a configuration, it is not necessary to repeatedly read from the fail memory what has the same distribution of pass or fail information on the fail memory, and the amount of data that has been determined as fail (the fail to read) ) Can be reduced. Further, the subsequent calculation (relief calculation) can be performed using the data reduced after the search for fail information, and the calculation efficiency can be improved accordingly.

  Another semiconductor test apparatus according to the present invention includes a fail memory that stores a plurality of pieces of fail information determined to be a pass or a fail for a test object, and the pass or fail information is continuous with reference to the fail memory. Change point detection means for generating continuous number data indicating the number stored in the memory, a storage memory for storing continuous number data generated by the change point detection means, and a continuous number generated by the change point detection means Area detection means for detecting an area where the distribution of data is repeated a plurality of times, and distribution area data indicating that the distribution of continuous number data is repeated a plurality of times for the area detected by the area detection means And a data generation means for overwriting the continuous number data stored in the storage memory.

  According to such a configuration, when it is detected that the same fail information is continuously stored in the fail memory, continuous number data representing the continuous number is stored in the storage memory. In addition, each time an area where the same continuous number data is continuously stored on the fail memory is detected, the storage memory is overwritten with the distribution area data, so it is necessary to store all the continuous number data. In addition, the capacity of the storage memory can be reduced accordingly. Even after all the fail memories have been searched, the fail information is stored in the storage memory in a compressed state as information having a small capacity (continuous number data or distribution area data). For this reason, after the search of the fail memory is completed, an operation (relief operation) can be performed using a smaller amount of data, and the efficiency of the operation is increased accordingly.

  In the above-described semiconductor test apparatus, the fail memory has an address including the same column and row as the object to be tested, and the area detection means has a plurality of distributions of continuous number data generated by the change point detection means. The repetition may be detected for each row included in the fail memory.

  When the object under test has a two-dimensional (column × row) address, for example, if the failure occurs continuously along the same column (one column), the same continuous number data is obtained from the fail memory for each row. It will be detected repeatedly. In this case, the region detecting means detects the repetition of the distribution of the continuous number data for each row, so that the operation according to the configuration of the object to be tested becomes possible.

  In the above-described semiconductor test apparatus, the continuous number data includes bit information indicating a pass or a fail and bit information indicating a number in which pass or fail information is continuously stored, and the distribution region data May include bit information indicating that the distribution of the continuous number data is repeated a plurality of times and bit information indicating the number of times the continuous number data is repeated a plurality of times.

  As described above, assuming that the failure occurred continuously in the same column of the object under test having a two-dimensional address, the storage memory has a continuous failure when all reading of the failure memory is completed. Since the number of repetitions of information is stored as distribution area data, the information in the final storage memory can be compressed small. Therefore, the subsequent calculation can be performed more efficiently.

  According to the semiconductor test apparatus of the present invention, it is possible to reduce the number of data determined to be failed based on the test result and efficiently perform fail detection.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
FIG. 1 is an explanatory diagram showing a configuration example of a semiconductor test apparatus 100 according to an embodiment of the present invention. Hereinafter, each component will be described.

  In the fail memory 120, a two-dimensional storage area including a plurality of columns (X axis) and rows (Y axis) is formed. The fail memory 120 has the same address as that of the DUT, and the fail memory 120 accumulates and stores fail information determined as a pass or fail by performing a plurality of tests on the DUT. For example, as shown in FIG. 3, “x” information indicating failure is stored at the same address in the fail memory 120 where the failure is determined by the DUT.

  The address generation circuit 110 generates an address that is specified by sequentially incrementing a plurality of addresses arranged for each row in the fail memory 120. For example, as shown in FIG. 3, the address generation circuit 110 sets each address arranged along the X axis from “0” to “F” for each row along the Y axis from “0” to “F”. The address specified by incrementing in order is generated as (X, Y) = (0, 0) → (0, 1) → (0, 2).

  The change point detection circuit 130 refers to each address in turn for each row in the fail memory 120 in accordance with the address generated by the address generation circuit 110. At this time, the change point detection circuit 130 detects a change point where the fail information changes at each address, and generates continuous number data indicating the number of pieces of information in which the pass or fail information is continuously stored. The continuous number data is, for example, data indicating 16 bits for each word. Bit information indicating path (0), fail (1), etc. in the upper 4 bits in 16 bits, and path or fail information in the lower 12 bits are continuous. Bit information indicating the number of items stored in the memory is included. As described above, the change point detection circuit 130 has a function as a change point detection means.

  For example, as illustrated in FIG. 3, the change point detection circuit 130 sequentially refers to each address arranged along the X axis from “0” to “F” in the row “0”, and passes the path. , 3 fail, and 12 paths are detected, and continuous number data of “0003”, “1001”, and “000C” is generated. The change point detection circuit 130 does not have to fix the address unit for detecting the change point one by one. For example, when four address units are used, the arrangement of “0, 0, 0, 1” is only once in the row of “0” in X = 0 to 3, and “0, 0” in X = 4 to 7. The arrangement of “0, 0, 0” is repeated three times even when X = 8 to B and X = C to F, so that continuous number data of “8001” and “0003” can be generated. In the following description, for the sake of simplicity, continuous address data is generated with one address unit.

  The data FIFO 140a temporarily stores the continuous number data generated for each row in the fail memory 120 by the change point detection circuit 130, and then outputs and stores the data in the storage memory 180. Further, in parallel with storing the continuous number data, the data FIFO 140a outputs and stores the continuous number data for the immediately previous row stored in the storage memory 180.

  The row data detection circuit 145 matches the continuous number data for the previous row output from the data FIFO 140a to the storage memory 180 and the continuous number data output from the change point detection circuit 130 to the data FIFO 140a. It is possible to determine whether or not the region (row) in which the distribution of the continuous number data is repeated a plurality of times based on the result. Thus, the row data detection circuit 145 has a function as a region detection means.

  If the row data detection circuit 145 determines that the continuous number data match, the row data detection circuit 145 generates distribution region data indicating that the distribution of the continuous number data is repeated a plurality of times, and outputs this to the change point detection circuit 130. . This distribution area data is, for example, data indicating 1 Word in 16 bits, and bit information indicating the repetition of distribution is included in the upper 4 bits in 16 bits, and bit information indicating the number of repetitions of distribution is included in the lower 12 bits. When the distribution area data is output from the row data detection circuit 145 to the data FIFO 140a, the storage memory 180 is overwritten. Thus, the row data detection circuit 145 has a function as data generation means.

  The relief calculation circuit 150 grasps the address determined to be failed based on the continuous number data generated by the change point detection circuit 130, and reserves cells on the lines along the X and Y axes prepared in advance in the DUT. Is used to replace the cell at the address determined to be failed. For example, if two spare cells are prepared along each of the X and Y axes, as shown in FIG. 3, the cells on the X = 3 and Y = 2 lines are used as spare cells. Further, an operation for replacing the cell of (X, Y) = (1, 1) with the remaining spare cell along the X axis or the Y axis is performed.

  Whenever the change point detection circuit 130 generates continuous number data, the address conversion circuit 160 increments the address and generates it. For example, as shown in FIG. 3, when the change point detection circuit 130 generates continuous number data of “0003”, “1001”, and “000C” in the row of “0”, The addresses corresponding to the continuous number data are sequentially incremented and generated as “0”, “1”, “2”.

  The storage memory 180 receives each address temporarily stored in the address FIFO 140b via the address selection circuit 170 and stores it in association with the continuous number data.

  Next, the fail search operation of the semiconductor test apparatus 100 in the present embodiment will be described with reference to the flowchart shown in FIG. First, the semiconductor test apparatus 100 performs a test such as an operation check on the DUT connected to the test head a plurality of times, and accumulates fail information determined to pass or fail for each address of the DUT in the fail memory 120. And memorize it. Following this, the following procedure is executed.

  Step S201: The address generation circuit 110 performs a process of generating an address to be specified by incrementing each row in the fail memory 120 in order. For example, as shown in FIGS. 3 to 8, for each row of “0” to “F” included in the fail memory 120, the address is incremented sequentially from “0” to “F” in the X-axis direction. The address designated by the address generation circuit 110 is generated as (X, Y) = (0, 0) → (0, 1) → (0, 2).

  Step S202: In accordance with the address generated by the address generation circuit 110 in the previous step S201, the change point detection circuit 130 refers to each address in turn for each row in the fail memory 120, and is stored in each address. A change point where the fail information changes is detected. When the change point is detected, the change point detection circuit 130 generates continuous number data based on the path or fail information that has continued until the change point, and stores the data in the data FIFO 140a. This process is repeated until the end of each line.

  At this time, the address conversion circuit 160 generates an address corresponding to each continuous number of data by incrementing each time it is generated by the change point detection circuit 130, and stores it in the address FIFO 140b. For example, as illustrated in FIGS. 3 to 8, the change point detection circuit 130 sequentially refers to the addresses arranged along the X axis from “0” to “F” in the row “0”. Then, the number of consecutive numbers in which three paths, one fail, and 12 paths are stored is detected, and continuous number data of “0003”, “1001”, and “000C” is generated and stored in the data FIFO 140a. .

  When the above-described continuous number data is generated, the address conversion circuit 160 sequentially increments the address corresponding to each continuous number data to generate them as “0”, “1”, “2”, It is stored in the address FIFO 140b.

  Step S203: Here, in parallel with step S202, the continuous number data generated in the previous row already stored in the data FIFO 140a is output. In addition, the address stored in the address FIFO 140b is output, and the continuous number data and the address are associated with each other and stored in the storage memory 180.

  Step S204: The row data detection circuit 145 refers to the continuous number data output to the data FIFO 140a in step S202 and the continuous number data generated in the previous row output from the data FIFO 140a in step S203. It is determined whether or not the continuous number data of these two rows match, that is, whether or not the distribution of the continuous number data is repeated a plurality of times in two rows. As a result, if they do not match (NO in step S204), the process in step S206 is executed.

  Step S205: When it is determined that the continuous number data match (YES in Step S204), the row data detection circuit 145 obtains distribution area data including bit information indicating the repetition of the distribution and bit information indicating the number of repetitions of the distribution. It is generated and stored in the data FIFO 140a following the continuous number data.

  At this time, the address conversion circuit 160 again generates an address corresponding to the continuous number data generated by the change point detection circuit 130 in step S202, and stores it in the address FIFO 140b.

  The row data detection circuit 145 stores the continuous number data and address generated in step S202 in the storage memory 180 in parallel with the generation of continuous number data in the next row, and overwrites the continuous number data. . Thus, the row data detection circuit 145 has a function as data generation means of the present invention. Further, the distribution area data and the address are output from the data FIFO 140 a and the address FIFO 140 b, respectively, and stored in the storage memory 180.

  For example, as illustrated in FIGS. 5 to 8, the row data detection circuit 145 includes the continuous number data corresponding to the addresses “B”, “C”, and “D” generated in the row “3”, and “4”. When it is determined that the continuous number data corresponding to the addresses “E”, “F”, and “10” generated in the row of “1” match, the value “3” indicating repetition at the beginning and the number of repetitions thereafter The distribution area data “3001” in which “1” is expressed as one word is generated, and this is written into the data FIFO 140a. If there is a mismatch, no particular processing is performed. The address conversion circuit 160 generates again the address “E” corresponding to the continuous number data generated in the row “4”, and writes this in the address FIFO 140b.

  Then, when the continuous number data and address generated in the row “4” are output from the data FIFO 140a and the address FIFO 140b to the storage memory 180, the continuous number data is overwritten in the storage memory 180, and the distribution area of “3001” Data and address “E” are stored in the storage memory 180. At this time, data “3001” remains in the address “E”.

  Step S206: The change point detection circuit 130 determines whether or not the continuous number data generated in step S202 is the last column and the last row. As a result, when it is not the last column and the last row (NO in step S206), the processing after step S201 is executed again.

  FIG. 6 shows an example of the operation that has advanced to the row “5”. Similar to the operation in the row “4”, data “0003” is written in the address “F”, “1001” is written in the address “10”, and “000C” is written in the address “11”. At the same time, since it is determined in step S204 that the continuous number data for each row match, the address “E” is written in the address FIFO 140b and the data “3002” is written in the data FIFO 140a.

  Also, after “E” / “0003”, “F” / “1001”, “10” / “000C” are written as address / data pairs from the address FIFO 140b and the data FIFO 140a to the storage memory 180, “E” / “3001” is overwritten. As a result, data “3001” remains at the address “E”.

  FIG. 7 shows an operation example for the rows from “6” to “F”. When the detection is completed up to the row “F”, the distribution region data “300C” representing the repetition of 12 rows is generated, and the data “300C” and the address “E” are respectively stored in the data FIFO 140a and the address FIFO 140b. Written.

  Step S207: On the other hand, if the result of determination by the change point detection circuit 130 is the last column and last row (YES in Step S206), the continuous number data and address generated in Step S202 are converted into the data FIFO 140a, the address The data is output from the FIFO 140b to the storage memory 180 and stored, followed by processing for storing data end information. Then, the repair operation circuit 150 performs an operation for replacing the cell at the address determined to be failed using the spare cell.

  For example, as shown in FIGS. 7 to 8, the change point detection circuit 130 generates “0000” of the data end following the continuous number data generated in the row “F”, and this is generated via the data FIFO 140a. The storage memory 180 is overwritten. If “0000” is defined in advance as the data end, the repair operation circuit 150 does not read the data at the address “10”.

  As described above, in the present embodiment, the continuous number data stored in the storage memory 180 is generated by detecting the region (row) in which the distribution of the continuous number data is repeated a plurality of times in the row direction. Therefore, the relief calculation circuit 150 does not need to repeatedly read the continuous number data having the same distribution. Further, the arithmetic circuit 150 can efficiently perform an operation using the reduced data.

  Furthermore, in this embodiment, the data is compressed using bit information indicating the repetition of the distribution and the number of repetitions, so the capacity of the storage memory 180 can be reduced accordingly. In addition, by referring to each address of the fail memory in order without being stopped once in the fail search operation, the number determined as fail can be detected accurately and efficiently. Therefore, there is no need to perform a return operation such as stopping during the search and making a determination, or clearing the fail memory.

It is explanatory drawing which shows the structure of the semiconductor test apparatus of this embodiment. It is a flowchart which shows operation | movement of the semiconductor test apparatus of this embodiment. It is explanatory drawing which shows operation | movement with the fail memory of the semiconductor test apparatus of this embodiment, a data FIFO, and an address FIFO. It is explanatory drawing which shows operation | movement with the fail memory of the semiconductor test apparatus of this embodiment, a data FIFO, and an address FIFO. It is explanatory drawing which shows operation | movement with the fail memory of the semiconductor test apparatus of this embodiment, a data FIFO, and an address FIFO. It is explanatory drawing which shows operation | movement with the fail memory of the semiconductor test apparatus of this embodiment, a data FIFO, and an address FIFO. It is explanatory drawing which shows operation | movement with the fail memory of the semiconductor test apparatus of this embodiment, a data FIFO, and an address FIFO. It is explanatory drawing which shows operation | movement with the fail memory of the semiconductor test apparatus of this embodiment, a data FIFO, and an address FIFO. It is explanatory drawing which shows the structure of the semiconductor test apparatus of a prior art. It is explanatory drawing which shows operation | movement by the fail memory of a semiconductor test apparatus of a prior art, a data FIFO, and an address FIFO.

Explanation of symbols

100, 200 Semiconductor test equipment 110, 210 Address generation circuit 120, 220 Fail memory 130 Change point detection circuit 140a Data FIFO
140b Address FIFO
145 row data detection circuit 150, 250 relief operation circuit 160 address conversion circuit

Claims (4)

A fail memory for storing a plurality of pieces of information determined as pass or fail for the test object;
Referring to the fail memory, an area detecting means for detecting an area in which a distribution of pass or fail information is repeatedly stored;
Data generation means for generating distribution area data indicating that the distribution of pass or fail information is repeated a plurality of times for the area detected by the area detection means; Test equipment. A fail memory for storing a plurality of pieces of information determined as pass or fail as a result of a test performed on the test object;
A change point detecting means for generating continuous number data indicating the number of pieces of information in which pass or fail information is continuously stored with reference to the fail memory;
A storage memory for storing continuous number data generated by the change point detection means;
An area detecting means for detecting an area where the distribution of the continuous number data generated by the change point detecting means is repeated a plurality of times;
Data generation for generating the distribution area data indicating that the distribution of the continuous number data is repeated a plurality of times for the area detected by the area detecting means, and overwriting the continuous number data stored in the storage memory And a semiconductor testing apparatus. The semiconductor test apparatus according to claim 2,
The fail memory has an address including the same column and row as the object under test,
The semiconductor testing apparatus according to claim 1, wherein the area detecting unit detects, for each row of the fail memory, that the distribution of the continuous number data generated by the change point detecting unit is repeated a plurality of times. The semiconductor test apparatus according to claim 2 or 3,
The continuous number data includes bit information indicating pass or fail, and bit information indicating the number of stored pass or fail information,
The distribution area data includes bit information indicating that the distribution of the continuous number data is repeated a plurality of times, and bit information indicating the number of times the distribution of the continuous number data is repeated a plurality of times. .

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