JP2009020148A - Plasma display device and method of driving plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a plasma display device and a method of driving plasma display panel capable of stably generating sustain discharge while reducing power consumption. <P>SOLUTION: A first sustain pulse as reference and a second sustain pulse of which the period of operating a power recovery circuit upon start-up of the sustain pulse is made to be shorter than that of the first sustain pulse are produced while being switched to each other so that the first sustain pulse succeeds just behind the second sustain pulse. The length of a superpose period formed by superposing the period of operating the power recovery circuit for starting up the sustain pulse and the period of operating the power recovery circuit for falling the just preceding sustain pulse is switched between at least two different lengths of a first superpose period and a second superpose period, only a superpose period between the fall of the second sustain pulse and the start-up of the first sustain pulse is made to be a second superpose period and, according to an all-cell lighting rate outputted from an all-cell lighting rate detection circuit 46 and a partial lighting rate outputted from a partial lighting rate detection circuit 47, the frequency of generating the second sustain pulse is controlled. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a plasma display device and a plasma display panel driving method used for a wall-mounted television or a large monitor.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other. In the front plate, a plurality of display electrode pairs each consisting of a pair of scan electrodes and sustain electrodes are formed in parallel with each other on the front glass substrate, and a dielectric layer and a protective layer are formed so as to cover the display electrode pairs. Yes. The back plate has a plurality of parallel data electrodes on the back glass substrate, a dielectric layer so as to cover them, and a plurality of barrier ribs in parallel with the data electrodes formed on the back glass substrate. A phosphor layer is formed on the side walls of the barrier ribs. Then, the front plate and the back plate are arranged opposite to each other so that the display electrode pair and the data electrode are three-dimensionally crossed and sealed, and a discharge gas containing, for example, 5% xenon is enclosed in the internal discharge space. Has been. Here, a discharge cell is formed at a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet rays are generated by gas discharge in each discharge cell, and the phosphors of red (R), green (G) and blue (B) colors are excited and emitted by the ultraviolet rays, thereby performing color display. It is carried out.

  As a method of driving the panel, a subfield method, that is, a method of performing gradation display by combining subfields to emit light after dividing one field period into a plurality of subfields is generally used.

  Each subfield has an initialization period, an address period, and a sustain period. In the initializing period, initializing discharge is generated, wall charges necessary for the subsequent address operation are formed on each electrode, and priming particles for stably generating the address discharge (priming agent for discharge = excited particles) ). In the address period, an address pulse voltage is selectively applied to the discharge cells to be displayed to generate an address discharge to form wall charges (hereinafter, this operation is also referred to as “address”). In the sustain period, a sustain pulse voltage is alternately applied to the display electrode pair composed of the scan electrode and the sustain electrode, and a sustain discharge is generated in the discharge cell that has caused the address discharge, and the phosphor layer of the corresponding discharge cell emits light. To display an image.

  In addition, among the subfield methods, initializing discharge is performed using a slowly changing voltage waveform, and further, initializing discharge is selectively performed on discharge cells that have undergone sustain discharge. A driving method is disclosed in which the light emission that is not generated is reduced as much as possible to improve the contrast ratio.

  Specifically, among the plurality of subfields, in the initialization period of one subfield, an all-cell initializing operation for generating an initializing discharge in all discharge cells is performed, and in an initializing period of the other subfield. Performs a selective initializing operation in which initializing discharge is generated only in the discharge cells that have undergone sustain discharge in the immediately preceding sustain period. By driving in this way, the luminance of the black display area that changes depending on the light emission not related to the image display (hereinafter abbreviated as “black luminance”) is only weak light emission in the all-cell initialization operation, High-contrast image display is possible (see, for example, Patent Document 1).

  In the above-mentioned Patent Document 1, the pulse width of the last sustain pulse in the sustain period is made shorter than the pulse widths of the other sustain pulses, and so-called narrow erasure is performed to alleviate the potential difference due to wall charges between the display electrode pairs. It also describes the discharge. By this narrow erase discharge, the address operation in the address period of the subsequent subfield can be stabilized, and a plasma display device with a high contrast ratio can be realized.

In addition, a plasma display device has been proposed in which scan electrodes and sustain electrodes constituting display electrode pairs are alternately replaced and arranged for each display electrode pair to improve luminance (for example, see Patent Document 2).
JP 2000-242224 A Japanese Patent Application Laid-Open No. 8-212933

  In recent years, the capacitance between electrodes in a panel is increasing with the increase in the screen size and the definition of the panel. The increase in the interelectrode capacitance increases the reactive power consumed ineffectively without contributing to light emission when driving the panel, and thus contributes to an increase in power consumption.

  For example, in the panel having the electrode structure disclosed in Patent Document 2 described above, the voltage change can be made in-phase between adjacent discharge cells during the sustain operation in the sustain period, so that the reactive power can be reduced. Can be planned.

  However, in a panel having such an electrode structure, variations in discharge are likely to occur.In particular, in a panel that has a large screen and a high definition, driving impedance increases, and waveform distortion such as ringing in the driving waveform easily occurs. It has been found that the variation in the discharge tends to be large, and there is a risk of causing the luminance variation called luminance unevenness.

  The present invention has been made in view of such problems, and even in a panel with a large screen and high definition, it is possible to stably generate discharge while reducing power consumption, and plasma with good image display quality. It is an object to provide a display device and a panel driving method.

  The plasma display device according to the present invention causes a sustain pulse to rise or fall by resonating a panel having a plurality of discharge cells each having a display electrode pair composed of a scan electrode and a sustain electrode, an interelectrode capacitance of the display electrode pair, and an inductor. A plurality of subfields each having an initialization period, an address period, and a sustain period provided in one field period, each of which includes a power recovery circuit that performs a decrease and a clamp circuit that clamps a sustain pulse voltage to a power supply voltage or a base potential A sustain pulse generation circuit that generates sustain pulses of the number corresponding to the luminance weight in the sustain period and applies them alternately to the display electrode pairs, and the ratio of the discharge cells to be lit to the total discharge cells in the display area of the panel As the rate, the all-cell lighting rate detection circuit that detects each subfield and the display area of the panel are divided into multiple areas. And a partial lighting rate detection circuit for detecting the ratio of discharge cells to be lit to discharge cells in each region as a partial lighting rate for each region and for each subfield. At least two types of sustain pulses, a first sustain pulse and a second sustain pulse in which a period for operating the power recovery circuit when the sustain pulse rises is shorter than the first sustain pulse, Immediately after the sustain pulse, the first sustain pulse is switched to be generated. The power recovery circuit is operated to raise the sustain pulse and the power recovery circuit is operated to lower the immediately preceding sustain pulse. Switching the length of the overlap period overlapping the period with at least two different lengths of the first overlap period and the second overlap period; Only the overlapping period between the falling edge of the holding pulse and the rising edge of the first sustaining pulse is set as the second overlapping period, and from the all-cell lighting rate detection circuit and the partial lighting rate detection circuit output from the all-cell lighting rate detection circuit The frequency of generating the second sustain pulse is controlled in accordance with the output partial lighting rate.

  Thereby, even in a panel with a large screen and high definition, it is possible to stably generate a discharge while reducing power consumption, and to improve the image display quality of the panel.

  In this plasma display device, the sustain pulse generating circuit is switched from the power recovery circuit to the clamp circuit at the fall of the sustain pulse and from the power recovery circuit to the clamp circuit at the rise of the sustain pulse during the second overlap period. It is characterized in that the discharge is generated once each at the time of switching, and the first overlap period is generated with a length less than the second overlap period including zero. Thereby, the effect of reducing power consumption and stabilizing discharge can be enhanced.

  The plasma display device further includes a maximum value detection circuit that detects the maximum value of the partial lighting rate in the display area for each subfield, and the partial lighting rate detection circuit divides the display area of the panel into at least two areas. The boundary is provided in parallel with the display electrode pair, and the sustain pulse generation circuit controls the frequency of generating the second sustain pulse according to the all-cell lighting rate and the maximum value output from the maximum value detection circuit. It is characterized by that. Thereby, the effect of reducing power consumption and stabilizing discharge can be further enhanced.

  In this plasma display device, the sustain pulse generation circuit periodically generates the second sustain pulse, and the frequency of generating the second sustain pulse is set to once every two times and zero times as the minimum. It is good.

  In this plasma display device, the panel may have the scan electrodes and the sustain electrodes arranged so that the positional relationship between the scan electrodes and the sustain electrodes alternates for each display electrode pair. Thereby, the effect of reducing power consumption can be further enhanced.

  Further, the panel driving method of the present invention provides a panel having a plurality of discharge cells each having a display electrode pair composed of a scan electrode and a sustain electrode, by resonating the interelectrode capacitance of the display electrode pair and the inductor, A panel driving method in which a sustain pulse of the number corresponding to the luminance weight is generated by rising or falling, and alternately applied to the display electrode pair for driving, and should be lit for all discharge cells in the display area of the panel. The ratio of discharge cells is detected for each subfield as the total cell lighting rate, and the display area of the panel is divided into a plurality of areas, and the ratio of discharge cells to be lit with respect to the discharge cells in each area is set as a partial lighting rate for each area and The detection is performed for each subfield, and in the sustain period, the reference first sustain pulse and the rise of the sustain pulse are detected in the first sustain pulse. The at least two types of sustain pulses, which are shorter than the second sustain pulse, are generated by switching to the first sustain pulse immediately after the second sustain pulse. The length of the overlap period that overlaps the falling edge of the pulse is switched by at least two different lengths of the first overlap period and the second overlap period, and the fall of the second sustain pulse and the first sustain period Only the overlap period between the rising edges of the pulses is set as the second overlap period, and the frequency of generating the second sustain pulse is controlled according to the all-cell lighting rate and the partial lighting rate.

  Thereby, even in a panel with a large screen and high definition, it is possible to stably generate a discharge while reducing power consumption, and to improve the image display quality of the panel.

  In the panel driving method of the present invention, the second overlap period is when switching from the power recovery circuit to the clamp circuit at the fall of the sustain pulse, and when switching from the power recovery circuit to the clamp circuit at the rise of the sustain pulse. And the length of the first overlapping period is less than the second overlapping period including 0, and the first overlapping period is generated. Thereby, the effect of reducing power consumption and stabilizing discharge can be enhanced.

  In the panel driving method of the present invention, the display area of the panel is divided into at least two areas, the boundary is provided in parallel with the display electrode pair, and the maximum value of the partial lighting rate in the display area is detected for each subfield. The frequency of generating the second sustain pulse is controlled according to the all-cell lighting rate and the maximum value. Thereby, the effect of reducing power consumption and stabilizing discharge can be further enhanced.

  In the panel driving method of the present invention, the second sustain pulse is generated periodically, and the frequency of generating the second sustain pulse is set to once every two times at the maximum and zero times as the minimum. Good.

  In the panel driving method of the present invention, a panel in which scan electrodes and sustain electrodes are arranged so that the positional relationship between the scan electrodes and the sustain electrodes alternates for each display electrode pair may be used. Thereby, the effect of reducing power consumption can be further enhanced.

  According to the present invention, it is possible to stably generate a discharge while reducing power consumption even in a large-screen and high-definition panel, and to provide a plasma display device with good image display quality and a panel driving method. It becomes possible to do.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view showing the structure of panel 10 according to Embodiment 1 of the present invention. A plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustain electrode 23 are formed on a glass front plate 21. A dielectric layer 25 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 26 is formed on the dielectric layer 25.

  The protective layer 26 has been used as a panel material in order to lower the discharge start voltage in the discharge cell, and has a large secondary electron emission coefficient and durability when neon (Ne) and xenon (Xe) gas is sealed. It is formed from a material mainly composed of MgO having excellent properties.

  A plurality of data electrodes 32 are formed on the back plate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits light of each color of red (R), green (G), and blue (B) is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front plate 21 and the back plate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect with each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. A mixed gas of neon and xenon is sealed as a discharge gas in the internal discharge space. In the present embodiment, a discharge gas having a xenon partial pressure of about 10% is used in order to improve luminous efficiency. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall. Further, the mixing ratio of the discharge gas is not limited to the above-described numerical values, and may be other mixing ratios.

  FIG. 2 is an electrode array diagram of panel 10 in accordance with the first exemplary embodiment of the present invention. In panel 10, n scanning electrodes SC1 to SCn (scanning electrode 22 in FIG. 1) and n sustaining electrodes SU1 to SUn (sustaining electrode 23 in FIG. 1) long in the row direction are arranged and long in the column direction. M data electrodes D1 to Dm (data electrode 32 in FIG. 1) are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dj (j = 1 to m), and the discharge cell is in the discharge space. M × n are formed.

  Further, in the panel 10, specifically, so that the positional relationship between the scan electrodes SC <b> 1 to SCn and the sustain electrodes SU <b> 1 to SUn alternates for each display electrode pair 24..., −scan electrode−scan electrode−sustain Electrode-sustain electrode-scan electrode-scan electrode-sustain electrode-sustain electrode-... (Hereinafter referred to as “ABBA electrode structure”. Therefore, the positional relationship between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn does not change for each display electrode pair 24, and is arranged as: scan electrode sustain electrode scan electrode sustain electrode The electrode structure is referred to as “ABAB electrode structure”).

  As shown in FIGS. 1 and 2, scan electrode SCi and sustain electrode SUi are formed in parallel with each other, and therefore, between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn. There is an interelectrode capacitance Cp. However, in the present embodiment, since panel 10 has an ABBA electrode structure, voltage changes can be made in-phase between adjacent discharge cells during the sustain operation in the sustain period, and reactive power can be reduced. .

  Next, a driving voltage waveform for driving the panel 10 and an outline of the operation will be described. The plasma display device according to the present embodiment performs gradation display by subfield method, that is, by dividing one field period into a plurality of subfields and controlling light emission / non-light emission of each discharge cell for each subfield. Each subfield has an initialization period, an address period, and a sustain period.

  In each subfield, initializing discharge is generated in the initializing period, and wall charges necessary for subsequent address discharge are formed on each electrode. In addition, it has a function of generating priming particles (priming for discharge = excited particles) for reducing discharge delay and generating address discharge stably. The initializing operation at this time is an all-cell initializing operation in which initializing discharge is generated in all discharge cells, and an initializing discharge is selectively generated only in the discharge cells that have undergone sustain discharge in the immediately preceding subfield. There is a selective initialization operation.

  In the address period, an address discharge is selectively generated in the discharge cells to emit light in the subsequent sustain period to form wall charges. In the sustain period, a number of sustain pulses proportional to the luminance weight are alternately applied to the display electrode pair 24 to generate a sustain discharge in the discharge cells that have generated the address discharge, thereby causing light emission. The proportionality constant at this time is called “luminance magnification”.

  In this embodiment, one field is composed of 10 subfields (first SF, second SF,..., 10th SF), and each subfield is, for example, (1, 2, 3, 6, 11, 18). , 30, 44, 60, 80). Then, the all-cell initialization operation is performed in the initialization period of the first SF, and the selective initialization operation is performed in the initialization period of the second SF to the tenth SF. As a result, the light emission not related to the image display is only the light emission due to the discharge of the all-cell initialization operation in the first SF, and the black luminance, which is the luminance of the black display area that does not generate the sustain discharge, is weak in the all-cell initialization operation. Only the emission of light makes it possible to display an image with high contrast. In the sustain period of each subfield, the number of sustain pulses obtained by multiplying the luminance weight of each subfield by a predetermined luminance magnification is applied to each display electrode pair 24.

  However, in the present embodiment, the number of subfields and the luminance weight of each subfield are not limited to the above values, and the subfield configuration may be switched based on an image signal or the like.

  In the present embodiment, an overlapping period in which the rising and falling edges of the sustain pulse overlap is determined according to the lighting rate for each subfield measured by the all-cell lighting rate detection circuit and the partial lighting rate detection circuit described later. I have control. This stabilizes the sustain discharge and makes the display luminance of each discharge cell uniform while reducing the power consumption in the panel 10. Hereinafter, the outline of the drive voltage waveform and the configuration of the drive circuit will be described first, and then the control of the overlapping period according to the lighting rate will be described.

  FIG. 3 is a drive voltage waveform diagram applied to each electrode of panel 10 in accordance with the first exemplary embodiment of the present invention. FIG. 3 shows driving voltage waveforms of two subfields, that is, a subfield that performs an all-cell initializing operation (hereinafter referred to as “all-cell initializing subfield”) and a subfield that performs a selective initializing operation ( Hereinafter, it is referred to as “selective initialization subfield”), but the driving voltage waveforms in the other subfields are substantially the same. Further, scan electrode SCi, sustain electrode SUi, and data electrode Dk in the following represent electrodes selected from the respective electrodes based on image data.

  First, the first SF, which is an all-cell initialization subfield, will be described.

  In the first half of the initializing period of the first SF, 0 (V) is applied to the data electrodes D1 to Dm and the sustain electrodes SU1 to SUn, respectively, and the discharge start voltage with respect to the sustain electrodes SU1 to SUn is applied to the scan electrodes SC1 to SCn. A ramp waveform voltage (hereinafter referred to as “up-ramp waveform voltage”) that gradually rises from the voltage Vi1 below toward the voltage Vi2 that exceeds the discharge start voltage is applied.

  While the rising ramp waveform voltage rises, weak initializing discharges are continuously generated between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm. Negative wall voltage is accumulated on scan electrodes SC1 to SCn, and positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SUn. The wall voltage above the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the latter half of the initialization period, positive voltage Ve1 is applied to sustain electrodes SU1 to SUn, 0 (V) is applied to data electrodes D1 to Dm, and sustain electrodes SU1 to SUn are applied to scan electrodes SC1 to SCn. In contrast, a ramp waveform voltage (hereinafter referred to as a “down-ramp waveform voltage”) that gently falls from a voltage Vi3 that is equal to or lower than the discharge start voltage to a voltage Vi4 that exceeds the discharge start voltage is applied. During this time, weak initializing discharges are continuously generated between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm. Then, the negative wall voltage above scan electrodes SC1 to SCn and the positive wall voltage above sustain electrodes SU1 to SUn are weakened, and the positive wall voltage above data electrodes D1 to Dm is adjusted to a value suitable for the write operation. The Thus, the all-cell initializing operation for performing the initializing discharge on all the discharge cells is completed.

  Note that, as shown in the initialization period of the second SF in FIG. 3, a drive voltage waveform in which the first half of the initialization period is omitted may be applied to each electrode. That is, the voltage Ve1 is applied to the sustain electrodes SU1 to SUn, 0 (V) is applied to the data electrodes D1 to Dm, and the voltage (for example, the ground potential) that is equal to or lower than the discharge start voltage is applied to the scan electrodes SC1 to SCn. A down-ramp waveform voltage that gradually falls toward is applied. As a result, a weak initializing discharge is generated in the discharge cell in which the sustain discharge has occurred in the sustain period of the previous subfield, and the wall voltage above scan electrode SCi and sustain electrode SUi is weakened. Further, in a discharge cell in which a sufficient positive wall voltage is accumulated on the data electrode Dk (k = 1 to m) by the last sustain discharge, an excessive portion of the wall voltage is discharged, and the wall voltage suitable for the address operation is obtained. Adjusted to On the other hand, the discharge cells that did not cause the sustain discharge in the previous subfield are not discharged, and the wall charges at the end of the initialization period of the previous subfield are maintained as they are. Thus, the initializing operation in which the first half is omitted is a selective initializing operation in which initializing discharge is performed on the discharge cells in which the sustaining operation has been performed in the sustain period of the immediately preceding subfield.

  In the subsequent address period, voltage Ve2 is first applied to sustain electrodes SU1 to SUn, and voltage Vc is applied to scan electrodes SC1 to SCn.

  Then, a negative scan pulse voltage Va is applied to the scan electrode SC1 in the first row, and the data electrode Dk (k = 1 to m) of the discharge cell to be emitted in the first row among the data electrodes D1 to Dm is positive. The write pulse voltage Vd is applied. At this time, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is the difference between the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1 due to the difference in externally applied voltage (Vd−Va). It becomes the sum and exceeds the discharge start voltage. As a result, a discharge is generated between data electrode Dk and scan electrode SC1. In addition, since voltage Ve2 is applied to sustain electrodes SU1 to SUn, the voltage difference between sustain electrode SU1 and scan electrode SC1 is the difference between the externally applied voltages (Ve2-Va) and on sustain electrode SU1. The difference between the wall voltage and the wall voltage on the scan electrode SC1 is added. At this time, by setting the voltage Ve2 to a voltage value that is slightly lower than the discharge start voltage, the sustain electrode SU1 and the scan electrode SC1 are not easily discharged but are likely to be discharged. Can do. Thereby, a discharge generated between data electrode Dk and scan electrode SC1 can be triggered to generate a discharge between sustain electrode SU1 and scan electrode SC1 in a region intersecting with data electrode Dk. Thus, an address discharge occurs in the discharge cell to emit light, a positive wall voltage is accumulated on scan electrode SC1, a negative wall voltage is accumulated on sustain electrode SU1, and a negative wall voltage is also accumulated on data electrode Dk. Accumulated.

  In this manner, an address operation is performed in which an address discharge is caused in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrodes D1 to Dm to which the address pulse voltage Vd is not applied and the scan electrode SC1 does not exceed the discharge start voltage, so that address discharge does not occur. The above address operation is performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, first, positive sustain pulse voltage Vs is applied to scan electrodes SC1 to SCn, and a ground potential that is a base potential, that is, 0 (V) is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. Exceeding the discharge start voltage.

  Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred during the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.

  Subsequently, 0 (V) as a base potential is applied to scan electrodes SC1 to SCn, and sustain pulse voltage Vs is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the sustain discharge has occurred, the voltage difference between the sustain electrode SUi and the scan electrode SCi exceeds the discharge start voltage, so that the sustain discharge occurs again between the sustain electrode SUi and the scan electrode SCi. A negative wall voltage is accumulated on SUi, and a positive wall voltage is accumulated on scan electrode SCi. Thereafter, similarly, the sustain electrodes of the number obtained by multiplying the luminance weight by the luminance magnification are alternately applied to the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn, and a potential difference is given between the electrodes of the display electrode pair 24, thereby writing. The sustain discharge is continuously performed in the discharge cell that has caused the address discharge in the period.

  At the end of the sustain period, a ramp waveform voltage (hereinafter referred to as “erase ramp waveform voltage”) gently rising from 0 (V) as the base potential toward voltage Vers is applied to scan electrodes SC1 to SCn. Is applied. As a result, a weak discharge is continuously generated, and some or all of the wall voltages on scan electrode SCi and sustain electrode SUi are erased while the positive wall voltage on data electrode Dk remains.

  Specifically, after the sustain electrodes SU1 to SUn are returned to 0 (V), an erase ramp waveform voltage that rises from 0 (V), which is the base potential, toward the voltage Vers exceeding the discharge start voltage is generated and scanned. Apply to electrodes SC1 to SCn. Then, a weak discharge is generated between sustain electrode SUi and scan electrode SCi of the discharge cell in which the sustain discharge has occurred. This weak discharge is continuously generated during a period in which the voltage applied to scan electrodes SC1 to SCn increases.

  At this time, the charged particles generated by the weak discharge are accumulated as wall charges on the sustain electrode SUi and the scan electrode SCi so as to reduce the voltage difference between the sustain electrode SUi and the scan electrode SCi. To go. As a result, the wall voltage between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn remains between the voltage applied to scan electrode SCi and the discharge start voltage while leaving positive wall charges on data electrode Dk. The difference is reduced to the extent of (voltage Vers−discharge start voltage). Hereinafter, the last discharge in the sustain period generated by the erase ramp waveform voltage is referred to as “erase discharge”.

  Subsequent subfield operations are substantially the same as those described above except for the number of sustain pulses in the sustain period, and thus description thereof is omitted. The above is the outline of the drive voltage waveform applied to each electrode of panel 10 in the present embodiment.

  In the present embodiment, as described above, panel 10 has an ABBA electrode structure. Therefore, in adjacent discharge cells, the scan electrode and the scan electrode are adjacent to each other, and the sustain electrode and the sustain electrode are adjacent to each other. Therefore, the change in sustain pulse voltage can be made in-phase between adjacent discharge cells, and reactive power can be reduced. For example, it was confirmed that the reactive power can be reduced by about 25% compared to the case of driving a panel having an ABAB electrode structure.

  Next, the configuration of the plasma display device in the present embodiment will be described. FIG. 4 is a circuit block diagram of the plasma display device in accordance with the first exemplary embodiment of the present invention. The plasma display apparatus 1 includes a panel 10, an image signal processing circuit 41, a data electrode driving circuit 42, a scanning electrode driving circuit 43, a sustain electrode driving circuit 44, a timing generation circuit 45, an all-cell lighting rate detection circuit 46, and a partial lighting rate detection. A circuit 47, a maximum value detection circuit 48, and a power supply circuit (not shown) for supplying power necessary for each circuit block are provided.

  The image signal processing circuit 41 converts the input image signal sig into image data indicating light emission / non-light emission for each subfield. The data electrode drive circuit 42 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes D1 to Dm.

  The all-cell lighting rate detection circuit 46 detects the ratio of the number of discharge cells to be lit to the total number of discharge cells, that is, the total cell lighting rate for each subfield, based on the image data for each subfield. The detected all-cell lighting rate is compared with a predetermined lighting rate threshold value, and a signal representing the result is output to the timing generation circuit 45.

  The partial lighting rate detection circuit 47 divides the display area of the panel into a plurality of areas to be described later, and the ratio of the number of discharge cells to be lit to the number of discharge cells for each area and for each subfield based on the image data for each subfield. That is, the partial lighting rate is detected.

  The maximum value detection circuit 48 compares the partial lighting rates detected by the partial lighting rate detection circuit 47 with each other, and detects the maximum value for each subfield. Then, the detected maximum value is compared with a predetermined maximum value threshold value, and a signal representing the result is output to the timing generation circuit 45.

  In this embodiment, the lighting rate threshold values are set to 15% and 60%, and the maximum value threshold value is set to 60%. However, each threshold value is limited to these numerical values. However, it is desirable to set the optimum value based on the characteristics of the panel and the specifications of the plasma display device.

  The timing generation circuit 45 generates various timing signals for controlling the operation of each circuit block based on outputs from the horizontal synchronization signal H, the vertical synchronization signal V, the all-cell lighting rate detection circuit 46, and the maximum value detection circuit 48. And supplied to each circuit block. As described above, in this embodiment, the overlapping period in which the rising and falling edges of the sustain pulse overlap is controlled based on the outputs from the all-cell lighting rate detection circuit 46 and the maximum value detection circuit 48. Accordingly, a timing signal corresponding thereto is output to the scan electrode drive circuit 43 and the sustain electrode drive circuit 44. Thereby, reduction of power consumption and stabilization of sustain discharge are realized.

  Scan electrode drive circuit 43 generates an initialization waveform voltage (not shown) for generating an initialization waveform voltage to be applied to scan electrodes SC1 to SCn in the initialization period, and applies to scan electrodes SC1 to SCn in the sustain period. Sustain pulse generating circuit 50 for generating sustain pulses, and a scan pulse generating circuit (not shown) for generating scan pulse voltages to be applied to scan electrodes SC1 to SCn in the address period, are based on timing signals. Each scan electrode SC1 to SCn is driven. Sustain electrode drive circuit 44 includes sustain pulse generation circuit 60 and a circuit for generating voltages Ve1 and Ve2, and drives sustain electrodes SU1 to SUn based on a timing signal.

  Next, details and operation of sustain pulse generating circuit 50 and sustain pulse generating circuit 60 will be described. FIG. 5 is a circuit diagram of sustain pulse generation circuit 50 and sustain pulse generation circuit 60 in the first exemplary embodiment of the present invention. In FIG. 5, the interelectrode capacitance of the panel 10 is shown as Cp, and the circuit for generating the scan pulse and the initialization voltage waveform is omitted.

  The sustain pulse generation circuit 50 includes a power recovery circuit 51 and a clamp circuit 52. The power recovery circuit 51 and the clamp circuit 52 include a scan pulse generation circuit (not shown because it is in a short-circuit state during the sustain period). And is connected to scan electrodes SC1 to SCn which are one end of the interelectrode capacitance Cp of the panel 10.

  The power recovery circuit 51 includes a power recovery capacitor C10, a switching element Q11, a switching element Q12, a backflow prevention diode D11, a backflow prevention diode D12, and a resonance inductor L10. Then, the interelectrode capacitance Cp and the inductor L10 are LC-resonated to raise and lower the sustain pulse. Thus, since the power recovery circuit 51 drives the scan electrodes SC1 to SCn by LC resonance without being supplied with power from the power source, the power consumption is ideally zero. The power recovery capacitor C10 has a sufficiently large capacity compared to the interelectrode capacity Cp, and is charged to about Vs / 2, which is half the voltage value Vs, so as to serve as a power source for the power recovery circuit 51.

  Clamp circuit 52 has switching element Q13 for clamping scan electrodes SC1 to SCn to voltage Vs, and switching element Q14 for clamping scan electrodes SC1 to SCn to the base potential of 0 (V). Then, scan electrodes SC1 to SCn are connected to power supply VS via switching element Q13 and clamped to voltage Vs, and scan electrodes SC1 to SCn are grounded and clamped to 0 (V) via switching element Q14. Therefore, the impedance at the time of voltage application by the clamp circuit 52 is small, and a large discharge current due to strong sustain discharge can flow stably.

  Sustain pulse generation circuit 50 is connected to power recovery circuit 51 by clamping switching element Q11, switching element Q12, switching element Q13, and switching element Q14 in accordance with a timing signal output from timing generation circuit 45. The circuit 52 is operated to generate a sustain pulse waveform.

  For example, when the sustain pulse waveform is raised, the switching element Q11 is turned on to cause the interelectrode capacitance Cp and the inductor L10 to resonate, and the power recovery capacitor C10 scans the scanning electrode through the switching element Q11, the diode D11, and the inductor L10. Power is supplied to SC1 to SCn. Then, when the voltage of scan electrodes SC1 to SCn approaches voltage Vs, switching element Q13 is turned on to switch the circuit for driving scan electrodes SC1 to SCn from power recovery circuit 51 to clamp circuit 52, and scan electrode SC1. Clamp SCn to voltage Vs.

  On the contrary, when the sustain pulse waveform is lowered, the switching element Q12 is turned on to resonate the interelectrode capacitance Cp and the inductor L10, and the interelectrode capacitance Cp is used for power recovery through the inductor L10, the diode D12, and the switching element Q12. The power is recovered in the capacitor C10. When the voltage of scan electrodes SC1 to SCn approaches 0 (V), switching element Q14 is turned on, and the circuit for driving scan electrodes SC1 to SCn is switched from power recovery circuit 51 to clamp circuit 52 for scanning. The electrodes SC1 to SCn are clamped to 0 (V) which is the base potential.

  In this way, sustain pulse generating circuit 50 generates a sustain pulse. Note that these switching elements can be configured using generally known elements such as MOSFETs and IGBTs.

  Sustain pulse generation circuit 60 has substantially the same configuration as sustain pulse generation circuit 50, and includes a power recovery capacitor C20, switching element Q21, switching element Q22, backflow prevention diode D21, backflow prevention diode D22, and resonance. A power recovery circuit 61 for recovering and reusing power when driving sustain electrodes SU1 to SUn, switching element Q23 for clamping sustain electrodes SU1 to SUn to voltage Vs, And a clamp circuit 62 having a switching element Q24 for clamping the sustain electrodes SU1 to SUn to the ground potential (0 (V)), and the sustain electrodes SU1 to SUn which are one end of the interelectrode capacitance Cp of the panel 10 are provided. It is connected. The operation of sustain pulse generating circuit 60 is the same as that of sustain pulse generating circuit 50, and therefore description thereof is omitted.

  Further, FIG. 5 shows a power source VE1 for generating the voltage Ve1, a switching element Q26 for applying the voltage Ve1 to the sustain electrodes SU1 to SUn, a switching element Q27, a power source ΔVE for generating the voltage ΔVe, and a backflow preventing diode D30. 1 shows a pump-up capacitor C30 for accumulating the voltage ΔVe on the voltage Ve1, a switching element Q28 and a switching element Q29 for accumulating the voltage ΔVe on the voltage Ve1 to obtain the voltage Ve2.

  For example, at the timing when the voltage Ve1 shown in FIG. 3 is applied, the switching element Q26 and the switching element Q27 are turned on to apply the positive voltage Ve1 to the sustain electrodes SU1 to SUn via the diode D30, the switching element Q26, and the switching element Q27. Apply. At this time, the switching element Q28 is turned on and charged so that the voltage of the capacitor C30 becomes the voltage Ve1. In addition, at the timing of applying the voltage Ve2 shown in FIG. 3, the switching element Q26 and the switching element Q27 are kept conductive, the switching element Q28 is cut off, and the switching element Q29 is turned on to apply the voltage ΔVe to the voltage of the capacitor C30. The voltage Ve1 + ΔVe, that is, the voltage Ve2 is applied to the sustain electrodes SU1 to SUn. At this time, the current from the capacitor C30 to the power source VE1 is cut off by the function of the backflow preventing diode D30.

  Note that the circuit for applying the voltage Ve1 and the voltage Ve2 is not limited to the circuit shown in FIG. 5. For example, a power source that generates the voltage Ve1 and a power source that generates the voltage Ve2 and the respective voltages are maintained electrodes. A plurality of switching elements for applying to SU1 to SUn may be used to apply each voltage to sustain electrodes SU1 to SUn at a necessary timing.

  The period of LC resonance between the inductor L10 of the power recovery circuit 51 and the interelectrode capacitance Cp of the panel 10 and the period of LC resonance between the inductor L20 of the power recovery circuit 61 and the interelectrode capacitance Cp (hereinafter referred to as “resonance period”). Can be obtained by the calculation formula “2π√ (LCp)”, where L is the inductance of the inductor L10 and the inductor L20. In this embodiment, the inductor L10 and the inductor L20 are set so that the resonance period in the power recovery circuit 51 and the power recovery circuit 61 is about 2000 nsec. However, these numerical values are merely examples in the embodiment. What is necessary is just to set to the optimal value according to the characteristic of a panel, the specification of a plasma display apparatus, etc.

  Next, details of the drive voltage waveform in the sustain period will be described.

  As described above, in this embodiment, the panel 10 has an ABBA electrode structure in order to reduce reactive power. However, it has been confirmed that discharge variations easily occur in the discharge cell having this ABBA electrode structure. It was done.

  This is because the same type of electrodes are adjacent to each other in the ABBA electrode structure (scan electrode-scan electrode, or sustain electrode-sustain electrode), so that the applied sustain pulses are in phase, and as a result, the effect of reducing reactive power is obtained. However, on the other hand, the electric field applied between the discharge cells adjacent in the column direction becomes smaller than that of the discharge cell having the ABAB electrode structure, and the charge easily moves to the discharge cells adjacent in the row direction. This is thought to be due to the increase in the amount of charge transfer, which increases the variation in wall charge.

  When the variation in wall charge increases, the variation in applied voltage necessary for generating discharge also increases, resulting in variation in discharge. Next, an example of variation in discharge generated due to variation in wall charges will be described with reference to the drawings. In the drawings used for the following description, the ground potential is denoted as “GND”.

  FIG. 6 is a schematic waveform diagram showing an example of the sustain pulse in the first embodiment of the present invention. For example, as shown in FIG. 6, in the sustain operation in which the next sustain pulse is raised after the last sustain pulse has sufficiently fallen, the power recovery circuit can sufficiently drive, so that the power consumption It is possible to perform driving while suppressing this.

  On the other hand, since the output impedance of the power recovery circuit is larger than the output impedance of the clamp circuit, discharge may be unstable when the ratio of discharge cells to be lit increases and the load during driving increases. .

  FIG. 7 is a schematic waveform diagram showing an example of the sustain pulse and the state of light emission at that time in Embodiment 1 of the present invention. The waveform shown in FIG. 7 shows the voltage observed at scan electrode SCi and sustain electrode SUi during the sustain period of the subfield having a relatively high lighting rate when driven by the sustain pulse shown in FIG. It is a waveform which shows an example of a change, and is a waveform which shows the intensity of light emission at that time.

  First, when the sustain pulse is raised by the power recovery circuit, for example, as shown in A of the drawing, the first discharge occurs when the voltage obtained by adding the wall voltage to the sustain pulse voltage exceeds the discharge start voltage. To do. At this time, in a subfield with a relatively high lighting rate, a large amount of discharge current flows instantaneously due to this discharge, and therefore the sustain pulse voltage temporarily drops. Thereafter, when the power recovery circuit is switched to the clamp circuit and the sustain pulse voltage is clamped to the voltage Vs, for example, as shown in B of the drawing, a second discharge is generated. However, since a part of wall charges is consumed by the first discharge, the second discharge is not a strong discharge. For this reason, the accumulated wall charges are reduced as compared with the case where a strong discharge is generated.

  As a result, in the immediately subsequent sustain pulse, when the sustain pulse is raised by the power recovery circuit, no discharge occurs or even if a discharge occurs, the discharge is very weak. Therefore, the phenomenon of wall charge consumption due to the first discharge at the time of rising of the sustain pulse as shown in A of the above-mentioned drawing hardly occurs. Therefore, when the power recovery circuit is subsequently switched to the clamp circuit and the sustain pulse voltage is clamped to the voltage Vs, a very strong discharge is generated as shown in FIG.

  Further, the strong discharge as shown in C of the drawing accumulates sufficient wall charges in the discharge cell, so that at the next sustain pulse, two times as shown in A and B of the drawing at the rising edge. Discharge occurs.

  As described above, in driving the panel 10 having the ABBA electrode structure, in the sustain period of the subfield where the lighting rate is relatively high, as described above, one very strong discharge and a weaker continuous 2 are performed. As a result, a variation in luminance called luminance unevenness may occur.

  Although not shown, it has been confirmed that if the lighting rate is sufficiently low, the occurrence of variations in discharge as described above is reduced and a stable sustain discharge is generated.

  On the other hand, the present inventor increases the overlapping period in which the rising and falling edges of the sustain pulse overlap, and even if the panel 10 has an ABBA electrode structure and the subfield has a high lighting rate, It was confirmed that the variation of the can be reduced.

  FIG. 8 is a schematic waveform diagram showing another example of the sustain pulse in the first embodiment of the present invention. In the present embodiment, the sustain pulse rise and fall periods, that is, the time for operating the power recovery circuit at the rise and fall of the sustain pulse is about 1050 nsec, and the pulse width of the sustain pulse is about 2 .7 μsec. Although not described in FIG. 6, the sustain period, the fall period, and the pulse width of the sustain pulse shown in FIG. 6 are the same as those of the sustain pulse shown in FIG. To do.

  As a result of the study by the present inventors, for example, in the case of the sustain pulse set as described above, if the overlap period in which the rise and fall of the sustain pulse overlap is set to about 850 nsec, the variation in discharge is reduced. It was confirmed that it can be reduced. Next, the details will be described.

  FIG. 9 is a schematic waveform diagram showing an example of the sustain pulse and the state of light emission at that time in Embodiment 1 of the present invention. Note that the waveforms shown in FIG. 9 indicate the voltages observed at scan electrode SCi and sustain electrode SUi in the sustain period of the subfield where the lighting rate is relatively high when driving by the sustain pulse shown in FIG. It is a waveform which shows an example of a change, and is a waveform which shows the intensity of light emission at that time.

  As a result of detailed examination by the inventor, if the overlap period is made sufficiently large, the power recovery circuit is switched to the clamp circuit at the fall of the last sustain pulse, and the sustain pulse voltage is clamped to the ground potential. At that time, it was confirmed that the first discharge can be forcibly generated as shown in D of the drawing. Then, by forcibly generating the first discharge, when the sustain pulse is switched from the power recovery circuit to the clamp circuit at the rising edge of the sustain pulse, the sustain pulse voltage is clamped to the voltage Vs, and then E As shown, it was confirmed that the second discharge can be generated, and that these two discharges can be generated with reduced variation.

  As described above, in the driving waveform shown in FIG. 6, depending on the state of wall charge, there are cases where a discharge occurs in the middle of raising a sustain pulse by the power recovery circuit and a case where no discharge occurs, and as a result, Dispersion of discharge occurred.

  However, in the drive waveform shown in FIG. 8, the first discharge can be forcibly generated regardless of the wall charge variation, so that two consecutive discharges can be generated while suppressing the discharge variation. And the occurrence of uneven brightness can be prevented.

  It should be noted that the above-described two continuous discharges with suppressed variations in discharge do not occur as long as an overlap period is provided, and it is necessary to set the overlap period to a sufficient length. Therefore, in the present embodiment, at the falling of the sustain pulse, the overlap period is divided depending on whether or not the first discharge is forced when the sustain pulse voltage is clamped to the ground potential. The overlap period that is extended until the first discharge occurs is referred to as a “second overlap period” and cannot be forcibly generated in the first discharge, less than the “second overlap period”. The overlap period set to the length of is called “first overlap period”. Accordingly, the overlap period set to “0” is also included in the “first overlap period”, and the drive waveform without the overlap period shown in FIG. 6 is also referred to as the “first overlap period”. Shall be set to.

  In the present embodiment, the configuration in which the “second overlap period” is set to about 850 nsec has been described. However, this numerical value is merely an example, and the panel characteristics, the specifications of the plasma display device, etc. It may be set optimally according to the above.

  Next, the relationship between the all-cell lighting rate, the partial lighting rate, and the “first overlap period” and “second overlap period” will be described.

  FIG. 10 is a schematic diagram showing the relationship between the lighting rate and the light emission efficiency when the overlap period in the first embodiment of the present invention is switched between the “first overlap period” and the “second overlap period”. It is.

  In FIG. 10, the horizontal axis represents the lighting rate (here, the whole cell lighting rate is represented), and the vertical axis represents the light emission efficiency. The solid line represents the sustain pulse shown in FIG. 6, that is, the result when the overlap period is set to “first overlap period”, and the broken line represents the sustain pulse shown in FIG. Represents the result when “overlap period” is set.

  As shown in FIG. 10, for example, when the lighting rate is 40%, the light emission efficiency is approximately 1.38 (lm / w) in the driving in which the overlap period is set to the “second overlap period”, whereas the overlap is overlapped. In the driving in which the period is set to the “first overlap period”, a light emission efficiency of about 1.45 (lm / w) can be obtained. Further, when the lighting rate is 20%, the driving with the overlapping period set to the “second overlapping period” has a light emission efficiency of about 1.33 (lm / w), whereas the overlapping period is “the first overlapping period”. In the driving set to "", a luminous efficiency of about 1.4 (lm / w) is obtained. As described above, in the drive in which the overlap period is set to the “first overlap period”, higher light emission efficiency can be obtained compared to the drive in which the overlap period is set to the “second overlap period”. It was confirmed that when the rate is about 50% or less, the difference increases as the lighting rate decreases.

  Thus, when the lighting rate is high, the overlapping period is set to “second overlapping period” to generate stable discharge, and when the lighting rate is low, the overlapping period is set to “first overlapping period” to increase the light emission efficiency and increase the power consumption. It has been confirmed that by reducing the power consumption, it is possible to reduce power consumption and improve display quality by stable discharge.

  On the other hand, even if the lighting rate is the same, the number of discharge cells (hereinafter also referred to as “lighting cells”) generated on a pair of display electrodes greatly varies depending on the design of the image to be displayed.

  FIG. 11 is a schematic diagram for explaining symbols having the same all-cell lighting rate and different distributions of lighting cells. In FIG. 11, the display electrode pairs 24 are arranged extending in the left-right direction in the drawing, as in FIG. In FIG. 11, the hatched portion represents the distribution of non-lighting cells that do not generate sustain discharge, and the white portion without hatching represents the distribution of lighted cells.

  The all-cell lighting rate in the present embodiment indicates the ratio of the lighting cells to all the discharge cells of the panel 10, but even with the same all-cell lighting rate, a pair of display electrodes depends on the distribution of the lighting cells. The number of lighting cells generated on the pair varies greatly depending on the design. For example, as shown in the upper part of FIG. 11, when the lighting cells are distributed in a vertically extending shape (in the drawing), the number of lighting cells generated on one display electrode pair is relatively small, The driving load on the pair of display electrodes is also small. However, even with the same all-cell lighting rate, as shown in the lower part of FIG. 11, when the lighting cells are distributed in a shape extending left and right (in the drawing), they are generated on one display electrode pair. The number of lighting cells to be increased increases, and the driving load of the pair of display electrodes increases.

  In this way, even with the same all-cell lighting rate, a difference in partial driving load occurs depending on the design, and depending on the design, a pair of display electrodes having a large driving load may occur.

  Although not shown, the lighting rate in the area is detected using a plurality of adjacent display electrode pairs as one area instead of the whole cell lighting rate, and the relationship between the lighting rate and the luminous efficiency is expressed as “first The result confirmed by switching between the “overlap period” and the “second overlap period” was almost the same as the result shown in FIG.

  Therefore, in this embodiment, the display area of the panel is divided into a plurality of areas in addition to the all-cell lighting ratio, and the lighting ratio in each area is detected as a partial lighting ratio.

  FIG. 12 is a schematic diagram showing an example of a region for detecting a partial lighting rate in Embodiment 1 of the present invention.

  In the present embodiment, as shown in FIG. 12, the display area of panel 10 is provided so that its boundary is parallel to display electrode pairs 24, and the number of display electrode pairs belonging to each area is as even as possible. It is assumed that the area is divided into eight areas. And a lighting rate is detected for every area | region, and it is set as a partial lighting rate. For example, if the number of display electrode pairs is 1080, the panel is divided into areas each having 135 display electrode pairs, and the lighting rate is detected in each area. Thereby, eight partial lighting rates can be detected for each subfield.

  In the present embodiment, the configuration in which the display area of the panel 10 is divided into eight areas has been described. However, this numerical value is merely an example, and depends on the panel characteristics, the specifications of the plasma display device, and the like. And set optimally. In the present embodiment, the same effect as described above can be obtained by dividing the display area of panel 10 into at least two areas and detecting the respective partial lighting rates. Further, the region may be divided according to the specifications of the IC used for driving the display electrode pair. For example, in a plasma display device configured to drive 108 scan electrodes or sustain electrodes with one IC, 108 display electrode pairs are set as one region in accordance with the IC, for example, a panel having 1080 display electrode pairs. May be divided into 10 regions. Alternatively, the number of display electrode pairs and the number of regions may be the same, and the lighting rate may be detected for each display electrode pair.

  In the present embodiment, the detected maximum value of the partial lighting rate is detected for each subfield, and the overlapping period is set to “first overlapping period” and “first overlapping period” according to the detected maximum value and the all-cell lighting rate. “Overlapping period of 2”.

  FIG. 13 is a diagram showing an example of the relationship between the maximum values of the all-cell lighting rate and the partial lighting rate and the switching of the overlap period in Embodiment 1 of the present invention.

  In the present embodiment, as shown in FIG. 13, in the subfield where the all-cell lighting rate is low (here, less than 15%), the overlapping period is set to “first overlapping period” regardless of the maximum value of the partial lighting rate. "

  As described above, even if the overlap period is set to the “first overlap period”, if the lighting rate is low, there is little variation in discharge, and stable sustain discharge can be performed. This is because the light emission efficiency can be increased by setting the “first overlap period”, so that power consumption can be reduced.

  In addition, in a subfield having a high all-cell lighting rate (here, 60% or more), the overlapping period is set as the “second overlapping period” regardless of the maximum value of the partial lighting rate. As a result, variations in discharge are reduced, luminance unevenness is suppressed, and image display quality is improved.

  In the subfield where the all-cell lighting rate is within a predetermined range (here, 15% or more and less than 60%), the overlapping period is switched according to the maximum value of the partial lighting rate. Specifically, if the maximum value of the partial lighting rate is low (here, less than 60%), the overlapping period is set as the “first overlapping period”, and if the maximum value of the partial lighting rate is high (here, 60%). As described above, the overlapping period is referred to as a “second overlapping period”.

  When the total cell lighting rate is within a predetermined range (here, 15% or more and less than 60%), luminance unevenness that occurs in a region where the partial lighting rate is high (here, 60% or more) may be conspicuous. Confirmed experimentally. Therefore, in the subfield where the all-cell lighting rate is within a predetermined range, by switching the driving according to the maximum value of the partial lighting rate as described above, an image obtained by reducing power consumption and reducing luminance unevenness. The display quality can be improved.

  Next, details of the drive voltage waveform in the sustain period will be described. FIG. 14 is a timing chart for explaining operations of sustain pulse generating circuit 50 and sustain pulse generating circuit 60 in the first embodiment of the present invention. Here, one repetition period of the sustain pulse (hereinafter abbreviated as “sustain period”) is divided into six periods indicated by T1 to T6, and each period will be described.

  In the following description, the operation for conducting the switching element is expressed as ON and the operation for blocking is expressed as OFF. In the drawing, the signal for turning on the switching element is expressed as “ON”, and the signal for turning off is expressed as “OFF”. Further, in FIG. 14, description is made using the positive electrode waveform, but the present invention is not limited to this. For example, although the embodiment in the negative waveform is omitted, the expression “rising” in the positive waveform in the following description is replaced with “falling” in the negative waveform. The same effect can be obtained even with this waveform.

(Period T1)
At time t1, switching element Q12 is turned on. Then, the charges on the scan electrodes SC1 to SCn side start to flow to the capacitor C10 through the inductor L10, the diode D12, and the switching element Q12, and the voltage on the scan electrodes SC1 to SCn starts to decrease. Since inductor L10 and interelectrode capacitance Cp form a resonance circuit, the voltage of scan electrodes SC1 to SCn drops to near 0 (V) at time t2b after the lapse of half the resonance period. However, the voltage of scan electrodes SC1 to SCn does not drop to 0 (V) due to power loss due to the resistance component of the resonance circuit. Then, switching element Q14 is turned on at time t2b. Then, since scan electrodes SC1 to SCn are directly grounded through switching element Q14, the voltages of scan electrodes SC1 to SCn are clamped to 0 (V).

  During this period, switching element Q24 is kept on, and sustain electrodes SU1 to SUn are clamped to 0 (V).

(Period T2)
Then, switching element Q14 is turned on at time t2b. Then, scan electrodes SC1 to SCn are directly grounded through switching element Q14, so that the voltages of scan electrodes SC1 to SCn are clamped to 0 (V) which is the ground potential.

  In the present embodiment, switching element Q21 is turned on at time t2a that is earlier than time t2b by a predetermined time. Thus, in the present embodiment, an overlapping period in which the period T1 and the period T2 overlap is provided by turning on the switching element Q21 at the time t2a that is earlier than the time t2b by a predetermined time. As described above, the length of the overlap period is switched according to the maximum values of the all-cell lighting rate and the partial lighting rate. As an example, when the overlap period is set to “second overlap period” (for example, about 850 nsec), the predetermined time is set to about 850 nsec, and when the overlap period is set to “first overlap period” (for example, about 0 nsec). About 0 nsec, that is, time t2a and time t2b are set to substantially the same time.

  Since the inductor L20 and the interelectrode capacitance Cp form a resonance circuit by turning on the switching element Q21, the sustain electrodes SU1 to SUn are passed from the capacitor C20 for power recovery through the switching element Q21, the diode D21, and the inductor L20. Current starts to flow, and the voltages of sustain electrodes SU1 to SUn begin to rise. Since the resonance period of inductor L20 and interelectrode capacitance Cp is set to about 2000 nsec, the voltage of sustain electrodes SU1 to SUn rises to around voltage Vs after about 1000 nsec from time t2a. However, it does not increase to the voltage Vs due to the influence of the output impedance of the drive circuit and the drive load. In this embodiment, the period T2 from time t2a to time t3, that is, the rise time of the sustain pulse using the power recovery circuit 61 is about 1050 nsec.

(Period T3)
At time t3, the switching element Q23 is turned on. Then, since sustain electrodes SU1 to SUn are directly connected to power supply VS through switching element Q23, the voltage of sustain electrodes SU1 to SUn is clamped to voltage Vs and forcibly rises to Vs. In this period T3, the voltages of the sustain electrodes SU1 to SUn are maintained at the voltage Vs.

(Period T4 to T6)
The sustain pulse applied to scan electrodes SC1 to SCn and the sustain pulse applied to sustain electrodes SU1 to SUn have the same waveform, and the operation from period T4 to period T6 scans the operation from period T1 to period T3. Since this is equivalent to the operation of driving the electrodes SC1 to SCn and the sustain electrodes SU1 to SUn, the description thereof will be omitted.

  The switching element Q12 may be turned off after time t2b and before time t5a, and the switching element Q21 may be turned off after time t3 and before time t4. Further, the switching element Q22 may be turned off by the next time t2a after the time t5b, and the switching element Q11 may be turned off by the next time t1 after the time t6. In order to lower the output impedance of sustain pulse generating circuit 50 and sustain pulse generating circuit 60, switching element Q24 is preferably turned off immediately before time t2a, switching element Q13 is preferably turned off immediately before time t1, and switching element Q14 is turned off at time. It is desirable that the switching element Q23 is turned off immediately before time t4 just before t5a.

  In the sustain period, the operations in the above periods T1 to T6 are repeated according to the required number of pulses. In this way, the sustain pulse voltage that shifts from the base potential of 0 (V) to the voltage Vs is alternately applied to each of the display electrode pairs 24 to cause the discharge cells to sustain discharge.

  As described above, in the present embodiment, the all-cell lighting rate and the partial lighting rate are detected, and the overlap period is determined according to the total cell lighting rate and the maximum value of the partial lighting rate, thereby reducing the power consumption. By switching between the “first overlap period” having a high value and the “second overlap period” having a high effect of reducing the discharge variation, it is possible to realize driving that suppresses the discharge variation while reducing power consumption. It becomes possible.

  In the present embodiment, the configuration in which the “first overlap period” is set to 0 has been described. However, the “first overlap period” may have a length that does not forcibly generate the first discharge, For example, it may be set to about 200 nsec.

(Embodiment 2)
In the first embodiment, in the case where the “second overlap period” is generated, the configuration in which the overlap period is set to the “second overlap period” in all of the sustain periods has been described. It is confirmed that the same effect as described above can be obtained even when the “first overlap period” and the “second overlap period” are generated by switching. In the second embodiment, this configuration will be described.

  As described above, when the “second overlap period” is generated, it is possible to obtain a high reduction effect with respect to discharge variation, but it is difficult to obtain a reduction effect with respect to power consumption. Therefore, the present inventor confirms how the discharge variation reduction effect and the power consumption reduction effect change when the “first overlap period” and the “second overlap period” are periodically switched. The experiment was conducted.

  Then, the inventor forcibly generates the discharge twice by setting the overlap period as the “second overlap period” in one sustain operation, so that the discharge state in the subsequent sustain operation is stabilized, And it was confirmed that the stable discharge continued to some extent. That is, only by generating the “second overlap period” at a frequency of once every time, a stable discharge can be generated even if the remaining overlap period is the “first overlap period”. It was confirmed that the reduction effect of can be obtained.

  FIG. 15 is a schematic waveform diagram showing an example of occurrence of the second overlapping period in the second embodiment of the present invention. In the present embodiment, the “first overlap period” is set to about 200 nsec, and the “second overlap period” is set to about 850 nsec. As shown in FIG. 15, even when one of the eight overlapping periods is set as the “second overlapping period” and the remaining seven times are set as the “first overlapping period”, the discharge variation is reduced. It was confirmed that an effect was obtained.

  That is, when the “second overlap period” is generated, it is not necessary to set the overlap period as the “second overlap period” in all of the maintenance periods, but once every plural times (for example, once out of 8 times). The effect of reducing the discharge variation similar to that shown in the first embodiment can be obtained only by generating the “second overlap period” at a frequency.

  In addition, the present inventor sets the remaining overlap period (7 out of 8 in the example shown in FIG. 15) as the “first overlap period”, thereby reducing the power consumption by improving the light emission efficiency. Was also confirmed.

  FIG. 16 is a schematic diagram showing the relationship between the lighting rate and the light emission efficiency when driven by changing the frequency of occurrence of the second overlapping period in the second embodiment of the present invention.

  In FIG. 16, the horizontal axis represents the lighting rate (here, the whole cell lighting rate is represented), and the vertical axis represents the light emission efficiency. In addition, the solid line represents the result when the overlap period is the “second overlap period” in all the sustain periods, and the broken line is the result when the overlap period is the “first overlap period” in all the sustain periods. 15 represents the sustain pulse shown in FIG. 15, that is, the result when one of the eight overlapping periods is set as the “second overlapping period” and the remaining seven times are set as the “first overlapping period”. To express. In this embodiment, since the experiment is performed under different conditions from those in Embodiment 1, there is a slight difference in the numerical value of the light emission efficiency from the relationship between the lighting rate and the light emission efficiency shown in FIG. However, the trend is almost the same.

  As shown in FIG. 16, the light emission efficiency is best when the overlap period is set to the “first overlap period” in all the sustain periods, but one of the eight overlap periods is referred to as the “second overlap period”. And the remaining seven times as the “first overlap period” confirms that the luminous efficiency is greatly improved compared to when the overlap period is set to the “second overlap period” in all the sustain periods. It was done. If the light emission efficiency can be improved, it is possible to drive with reduced power consumption, and power consumption can be reduced.

  Therefore, in the present embodiment, when the “second overlap period” is generated, the overlap period is not set to the “second overlap period” in all the maintenance periods, but once every plural times ( For example, the “second overlap period” is generated at a frequency of 1 out of 8 times.

  FIG. 17 is a diagram showing an example of the relationship between the maximum values of the all-cell lighting rate and the partial lighting rate and the occurrence frequency of the second overlapping period in Embodiment 2 of the present invention.

  In the present embodiment, as shown in FIG. 17, in the subfield having a high all-cell lighting rate (here, 60% or more), the “second overlap period” is repeated once out of 8 times during the sustain period. Is generated.

  Further, in the subfield where the all-cell lighting rate is within a predetermined range (here, 15% or more and less than 60%), the occurrence frequency of the “second overlap period” is switched according to the maximum value of the partial lighting rate. Specifically, if the maximum value of the partial lighting rate is low (here, less than 60%), only the “first overlap period” is generated, and if the maximum value of the partial lighting rate is high (here, 60% or more). ) The “second overlap period” is generated at an occurrence frequency of 2 out of 8 times.

  Further, in the subfield where the all-cell lighting rate is low (here, less than 15%), the occurrence of discharge variation is low, but for the purpose of improving the light emission luminance, the frequency of occurrence of “second” is 1 out of 8 times. Overlap period "is generated.

  As described above, in the configuration shown in the present embodiment, regardless of the design of the display image, the variation in discharge is reduced to suppress the luminance unevenness, the image display quality is improved, and the power consumption reduction effect is further enhanced. It becomes possible.

  The occurrence frequency of the “second overlap period”, the length of the “first overlap period” and the “second overlap period”, the lighting rate threshold value, and the maximum value threshold value shown in the present embodiment Specific numerical values such as these are merely examples, and may be optimally set in accordance with panel characteristics, plasma display device specifications, and the like.

(Embodiment 3)
In the second embodiment, when the “second overlap period” is generated, the overlap period is not changed to the “second overlap period” in all the sustain periods, but once every plural times (for example, 8 times) The configuration in which the “second overlap period” is generated at a frequency of once) has been described. At this time, it was confirmed that the stability of the discharge generated in the “second overlap period” can be further improved by making the rise of the sustain pulse that generates the “second overlap period” sharp. It was. In the third embodiment, this configuration will be described.

  FIG. 18 is a waveform diagram showing an outline of the sustain pulse waveform in the third embodiment of the present invention. In the present embodiment, two types of sustain pulses having different waveform shapes are generated by switching. However, each sustain pulse is generated by switching each switching element of sustain pulse generating circuit 50 and sustain pulse generating circuit 60. The waveform shape is only changed by controlling the drive time of each power recovery circuit and each voltage clamp circuit by controlling the timing.

  As shown in FIG. 18, in the present embodiment, two types of sustain pulses having different waveform shapes, that is, a first sustain pulse as a reference, and a period for operating the power recovery circuit when the sustain pulse rises are shown in FIG. The second sustain pulse that is shorter than the first sustain pulse and steeper than the first sustain pulse is periodically switched so that the first sustain pulse immediately after the second sustain pulse becomes the first sustain pulse. To generate.

  Specifically, the reference first sustain pulse has the same waveform shape as the sustain pulse shown in the first and second embodiments, and the time required for rising (rising period) is set to about 1050 nsec. The time for falling (falling period) is set to about 1050 nsec and the pulse width is set to about 2.7 μsec.

  The second sustain pulse has a rising period that is approximately 600 nsec shorter than the first sustain pulse, so that the rising period is steeper than the first sustain pulse, and the falling period and the pulse width are the same as those of the first sustain pulse. generate.

  FIG. 19 is a schematic waveform diagram showing an example of generation of the first sustain pulse and the second sustain pulse in the third embodiment of the present invention.

  In the present embodiment, as shown in FIG. 19, only the sustain pulse that generates the “second overlap period” at the falling edge is set as the second sustain pulse. That is, only the overlapping period between the falling edge of the second sustain pulse and the rising edge of the first sustain pulse is defined as a “second overlap period”. Then, as in the second embodiment, the frequency at which the “second overlap period” is generated, that is, the frequency at which the second sustain pulse is generated, is controlled according to the all-cell lighting rate and the maximum value of the partial lighting rate. To do.

  The sustain pulse generation pattern shown in FIG. 19 is different from the sustain pulse generation pattern shown in FIG. 15 in the second embodiment in that the sustain pulse for generating the “second overlap period” at the falling edge is the second. The only difference is that the sustain pulse is used, and other configurations such as the occurrence frequency of the “second overlap period” and the lengths of the “first overlap period” and the “second overlap period” are the same. .

  In the present embodiment, by adopting such a configuration, the stability of the discharge generated in the “second overlap period” is enhanced, and the effect of reducing the discharge variation is further enhanced. This is due to the following reason.

  The inventor has the configuration shown in the second embodiment, that is, the stability of the discharge generated in the “second overlap period” when the “second overlap period” is generated at a frequency of once every plural times. An experiment was conducted to confirm the above.

  As a result, the present inventor can further improve the stability of the discharge generated in the “second overlap period” by making the rising edge of the sustain pulse that generates the “second overlap period” steep. It was confirmed.

  FIG. 20 is a schematic waveform diagram showing an example of generation of the first sustain pulse and the second sustain pulse in the third embodiment of the present invention, and FIG. 21 is a scan in the drive by the sustain pulse shown in FIG. It is a schematic waveform diagram showing the change in voltage observed at electrode SCi and sustain electrode SUi and the intensity of light emission at that time.

  In this experiment, as shown in FIG. 19 and FIG. 20, the first sustain pulse and the second sustain pulse are periodically switched and generated, and the falling edge of the second sustain pulse and the first sustain pulse are changed. Only the overlap period between the rising edges was set as the “second overlap period”, and the “second sustain pulse” was generated at a frequency of one out of eight times to drive the panel 10.

  As a result, as shown in FIG. 21, a strong discharge (a discharge indicated by B ′ in the drawing) is generated by generating a discharge with a sharp voltage change at the rising edge of the second sustain pulse. As a result, it was confirmed that sufficient wall charges were accumulated, and the first discharge (discharge indicated by D ′ in the drawing) generated in the “second overlap period” was generated more stably.

  As described above, in the configuration shown in this embodiment, the stability of the discharge generated in the “second overlap period” can be further improved, and the effect of further reducing the unevenness of the discharge and suppressing the luminance unevenness can be further achieved. It becomes possible to raise.

  It should be noted that the numerical values and frequencies relating to the rise and fall shown in the first sustain pulse and the second sustain pulse of this embodiment are merely examples of the embodiment, and the characteristics of the panel It is desirable to set the optimum value according to the specifications of the plasma display device.

  In the embodiment of the present invention, the configuration in which the “second overlap period” is generated at an occurrence frequency of one or two times out of eight times has been described. However, the effect of suppressing variation in discharge and power consumption are reduced. In order to obtain this effect, it is desirable that the frequency of generating the “second overlap period” be set to once every two times at the maximum.

  In the embodiment of the present invention, scan electrodes SC1 to SCn are divided into a first scan electrode group and a second scan electrode group, and an address period is set for each of the scan electrodes belonging to the first scan electrode group. The first address period in which the scan pulse is sequentially applied to the first scan period and the second address period in which the scan pulse is sequentially applied to each of the scan electrodes belonging to the second scan electrode group. In at least one of the two address periods, the scan electrodes belonging to the scan electrode group to which the scan pulse is applied are scanned from the second voltage higher than the scan pulse voltage to the scan pulse voltage and again to the second voltage. For the scan electrodes belonging to the scan electrode group to which the pulse is sequentially applied and the scan pulse is not applied, either the third voltage higher than the scan pulse voltage, the second voltage, or the fourth voltage higher than the third voltage. Or It can be applied to a panel driving method by so-called two-phase driving, in which a third voltage is applied while a voltage is applied and at least a scanning pulse voltage is applied to adjacent scanning electrodes. An effect can be obtained.

  In the embodiment of the present invention, the configuration in which the erase ramp waveform voltage is applied to scan electrodes SC1 to SCn has been described. However, the erase ramp waveform voltage may be applied to sustain electrodes SU1 to SUn. Alternatively, an erasing discharge may be generated not by an erasing ramp waveform voltage but by a so-called narrow erasing pulse.

  In the embodiment of the present invention, in the power recovery circuits 51 and 61, the configuration in which one inductor is commonly used for the rise and fall of the sustain pulse has been described. However, the rise of the sustain pulse is performed using a plurality of inductors. Alternatively, different inductors may be used for the falling and falling edges.

  The specific numerical values shown in the embodiment of the present invention are set based on the characteristics of the 42-inch panel having the number of display electrode pairs 1080 used in the experiment, and merely show an example of the embodiment. It is just a thing. Embodiments of the present invention are not limited to these numerical values, and are desirably set to optimum values in accordance with panel characteristics, plasma display device specifications, and the like. Each of these numerical values is allowed to vary within a range where the above-described effect can be obtained.

  INDUSTRIAL APPLICABILITY The present invention can stably generate discharge while reducing power consumption even in a panel with a large screen and high definition, and is useful as a plasma display device with good image display quality and a panel driving method. .

The disassembled perspective view which shows the structure of the panel in Embodiment 1 of this invention. Electrode arrangement of the panel Drive voltage waveform diagram applied to each electrode of the panel Circuit block diagram of plasma display device according to Embodiment 1 of the present invention Circuit diagram of sustain pulse generating circuit according to the first embodiment of the present invention Schematic waveform diagram showing an example of a sustain pulse in Embodiment 1 of the present invention Schematic waveform diagram showing an example of sustain pulses and the state of light emission at that time in Embodiment 1 of the present invention Schematic waveform diagram showing another example of sustain pulse in Embodiment 1 of the present invention Schematic waveform diagram showing an example of sustain pulses and the state of light emission at that time in Embodiment 1 of the present invention Schematic showing the relationship between the lighting rate and the light emission efficiency when the overlap period in the first embodiment of the present invention is switched between the “first overlap period” and the “second overlap period”. Schematic for explaining symbols with the same all-cell lighting rate and different distribution of lighting cells Schematic which shows an example of the area | region which detects the partial lighting rate in Embodiment 1 of this invention. The figure which shows an example of the relationship between the maximum value of all the cell lighting rates and partial lighting rates in Embodiment 1 of this invention, and switching of an overlap period Timing chart for explaining operation of sustain pulse generating circuit in the first embodiment of the present invention Schematic waveform diagram showing an example of the occurrence of the second overlap period in the second embodiment of the present invention Schematic which shows the relationship between the lighting rate and light emission efficiency when it drives by changing the generation frequency of the 2nd duplication period in Embodiment 2 of this invention. The figure which shows an example of the relationship between the maximum value of all the cell lighting rates and partial lighting rates in Embodiment 2 of this invention, and the occurrence frequency of a 2nd duplication period. Waveform diagram showing an outline of the sustain pulse waveform in the third embodiment of the present invention Schematic waveform diagram showing an example of generation of the first sustain pulse and the second sustain pulse in Embodiment 3 of the present invention Schematic waveform diagram showing an example of generation of the first sustain pulse and the second sustain pulse in Embodiment 3 of the present invention FIG. 20 is a schematic waveform diagram showing voltage changes observed at the scan electrode and the sustain electrode and the intensity of light emission at that time in the drive by the sustain pulse shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Plasma display apparatus 10 Panel 21 Front plate (made of glass) 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 25, 33 Dielectric layer 26 Protective layer 31 Back plate 32 Data electrode 34 Partition 35 Phosphor layer 41 Image signal processing circuit 42 data electrode drive circuit 43 scan electrode drive circuit 44 sustain electrode drive circuit 45 timing generation circuit 46 all-cell lighting rate detection circuit 47 partial lighting rate detection circuit 48 maximum value detection circuit 50, 60 sustain pulse generation circuit 51, 61 power recovery circuit 52, 62 Clamp circuit Q11, Q12, Q13, Q14, Q21, Q22, Q23, Q24, Q26, Q27, Q28, Q29 Switching element C10, C20, C30 Capacitor L10, L20 Inductor D11, D12, D21, D22, D30 Diode

Claims (10)

A plasma display panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode;
A power recovery circuit that causes a sustain pulse to rise or fall by resonating the interelectrode capacitance of the display electrode pair and an inductor, and a clamp circuit that clamps the sustain pulse voltage to a power supply voltage or a base potential. In the sustain period of a plurality of subfields having an initialization period, an address period, and a sustain period provided within the period, the sustain pulse is generated a number of times corresponding to the luminance weight and applied to the display electrode pair alternately. A pulse generation circuit;
An all-cell lighting rate detection circuit that detects a ratio of discharge cells to be lit to all discharge cells in a display area of the plasma display panel as a total cell lighting rate for each subfield;
The display area of the plasma display panel is divided into a plurality of areas, and includes a partial lighting rate detection circuit that detects the ratio of discharge cells to be lit with respect to the discharge cells in each region as a partial lighting rate for each region and each subfield,
The sustain pulse generation circuit, in the sustain period,
A first sustain pulse as a reference;
At least two types of sustain pulses, ie, a second sustain pulse in which the period for operating the power recovery circuit when the sustain pulse rises, is shorter than the first sustain pulse, and immediately after the second sustain pulse, Switch to generate the first sustain pulse,
The length of the overlapping period in which the period for operating the power recovery circuit to raise the sustain pulse and the period for operating the power recovery circuit to lower the immediately preceding sustain pulse is the first overlapping period. The second overlap period is switched to at least two different lengths, and only the overlap period between the fall of the second sustain pulse and the rise of the first sustain pulse is defined as the second overlap period. And controlling the frequency of generating the second sustain pulse according to the total cell lighting rate output from the all-cell lighting rate detection circuit and the partial lighting rate output from the partial lighting rate detection circuit. A plasma display device. The sustain pulse generation circuit includes:
The second overlap period is once each at the time of switching from the power recovery circuit to the clamp circuit at the fall of the sustain pulse and at the time of switching from the power recovery circuit to the clamp circuit at the rise of the sustain pulse. 2. The plasma display apparatus according to claim 1, wherein the plasma display device is generated so that discharge occurs and the first overlap period is less than the second overlap period including zero. A maximum value detection circuit for detecting a maximum value of the partial lighting rate in the display area for each subfield;
The partial lighting rate detection circuit divides a display area of the plasma display panel into at least two areas, and a boundary thereof is provided in parallel with the display electrode pair,
The sustain pulse generation circuit controls the frequency of generating the second sustain pulse according to the all-cell lighting rate and the maximum value output from the maximum value detection circuit. 2. The plasma display device according to 1. The sustain pulse generation circuit periodically generates the second sustain pulse, and the frequency of generating the second sustain pulse is set to once at a maximum of 2 times and 0 times at a minimum. The plasma display device according to claim 3, wherein: 5. The plasma display panel according to claim 1, wherein the scan electrodes and the sustain electrodes are arranged so that a positional relationship between the scan electrodes and the sustain electrodes is alternated for each display electrode pair. The plasma display device according to any one of the above. A plasma display panel comprising a plurality of discharge cells having a display electrode pair consisting of a scan electrode and a sustain electrode,
Plasma that is driven by causing the interelectrode capacitance of the display electrode pair and the inductor to resonate to generate a sustain pulse of the number of times corresponding to the luminance weight by alternately applying and driving the sustain pulse. A display panel driving method comprising:
The ratio of discharge cells to be lit to the total discharge cells in the display area of the plasma display panel is detected for each subfield as the total cell lighting rate, and the display area of the plasma display panel is divided into a plurality of areas. The ratio of discharge cells to be lit with respect to discharge cells is detected as a partial lighting rate for each region and for each subfield,
In the maintenance period,
A first sustain pulse as a reference;
At least two types of sustain pulses, the second sustain pulse having a rise of the sustain pulse steeper than the first sustain pulse, and the first sustain pulse immediately after the second sustain pulse. Generated by switching,
The length of the overlap period that overlaps the rise of the sustain pulse and the fall of the immediately preceding sustain pulse is switched by at least two different lengths of the first overlap period and the second overlap period, and the second Only the overlapping period between the falling edge of the sustain pulse and the rising edge of the first sustain pulse is defined as the second overlapping period, and the second lighting period is determined according to the total cell lighting rate and the partial lighting rate. A method of driving a plasma display panel, wherein the frequency of generating sustain pulses is controlled. The second overlap period is once each at the time of switching from the power recovery circuit to the clamp circuit at the fall of the sustain pulse and at the time of switching from the power recovery circuit to the clamp circuit at the rise of the sustain pulse. 7. The method of driving a plasma display panel according to claim 6, wherein the length is such that discharge occurs, and the first overlap period is less than the second overlap period including zero. The display area of the plasma display panel is divided into at least two areas, and the boundary is provided in parallel with the display electrode pair,
Detecting the maximum value of the partial lighting rate in the display area for each subfield;
8. The method of driving a plasma display panel according to claim 7, wherein the frequency of generating the second sustain pulse is controlled according to the all-cell lighting rate and the maximum value. 9. The frequency of generating the second sustain pulse periodically, and generating the second sustain pulse at a maximum of once every two times and at a minimum of zero. A driving method of the plasma display panel as described. 10. The plasma display panel in which the scan electrodes and the sustain electrodes are arranged so that the positional relationship between the scan electrodes and the sustain electrodes alternates for each display electrode pair. The method for driving a plasma display panel according to any one of the above.

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