JP5130854B2 - Plasma display apparatus and driving method of plasma display panel - Google Patents

Description

  The present invention relates to a plasma display device and a plasma display panel driving method used for a wall-mounted television or a large monitor.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other. In the front plate, a plurality of display electrode pairs each consisting of a pair of scan electrodes and sustain electrodes are formed in parallel with each other on the front glass substrate, and a dielectric layer and a protective layer are formed so as to cover the display electrode pairs. Yes. The back plate has a plurality of parallel data electrodes on the back glass substrate, a dielectric layer so as to cover them, and a plurality of barrier ribs in parallel with the data electrodes formed on the back glass substrate. A phosphor layer is formed on the side walls of the barrier ribs. Then, the front plate and the back plate are arranged opposite to each other so that the display electrode pair and the data electrode are three-dimensionally crossed and sealed, and a discharge gas containing, for example, 5% xenon is enclosed in the internal discharge space. Has been. Here, a discharge cell is formed at a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet rays are generated by gas discharge in each discharge cell, and the phosphors of red (R), green (G) and blue (B) colors are excited and emitted by the ultraviolet rays, thereby performing color display. It is carried out.

  As a method of driving the panel, a subfield method, that is, a method of performing gradation display by combining subfields to emit light after dividing one field period into a plurality of subfields is generally used.

  Each subfield has an initialization period, an address period, and a sustain period. In the initializing period, initializing discharge is generated, wall charges necessary for the subsequent address operation are formed on each electrode, and priming particles for stably generating the address discharge (priming agent for discharge = excited particles) ). In the address period, an address pulse voltage is selectively applied to the discharge cells to be displayed to generate an address discharge to form wall charges (hereinafter, this operation is also referred to as “address”). In the sustain period, a sustain pulse voltage is alternately applied to the display electrode pair composed of the scan electrode and the sustain electrode, and a sustain discharge is generated in the discharge cell that has caused the address discharge, and the phosphor layer of the corresponding discharge cell emits light. To display an image.

  In addition, among the subfield methods, initializing discharge is performed using a slowly changing voltage waveform, and further, initializing discharge is selectively performed on discharge cells that have undergone sustain discharge. A driving method is disclosed in which the light emission that is not generated is reduced as much as possible to improve the contrast ratio.

  Specifically, among the plurality of subfields, in the initialization period of one subfield, an all-cell initializing operation for generating an initializing discharge in all discharge cells is performed, and in an initializing period of the other subfield. Performs a selective initializing operation in which initializing discharge is generated only in the discharge cells that have undergone sustain discharge in the immediately preceding sustain period. By driving in this way, the luminance of the black display area that changes depending on the light emission not related to the image display (hereinafter abbreviated as “black luminance”) is only weak light emission in the all-cell initialization operation, High-contrast image display is possible (see, for example, Patent Document 1).

  In the above-mentioned Patent Document 1, the pulse width of the last sustain pulse in the sustain period is made shorter than the pulse widths of the other sustain pulses, and so-called narrow erasure is performed to alleviate the potential difference due to wall charges between the display electrode pairs. It also describes the discharge. By this narrow erase discharge, the address operation in the address period of the subsequent subfield can be stabilized, and a plasma display device with a high contrast ratio can be realized.

In addition, a plasma display device has been proposed in which scan electrodes and sustain electrodes constituting display electrode pairs are alternately replaced and arranged for each display electrode pair to improve luminance (for example, see Patent Document 2).
JP 2000-242224 A Japanese Patent Application Laid-Open No. 8-212933

  In recent years, the capacitance between electrodes in a panel is increasing with the increase in the screen size and the definition of the panel. The increase in the interelectrode capacitance increases the reactive power consumed ineffectively without contributing to light emission when driving the panel, and thus contributes to an increase in power consumption.

  For example, in the panel having the electrode structure disclosed in Patent Document 2 described above, the voltage change can be made in-phase between adjacent discharge cells during the sustain operation in the sustain period, so that the reactive power can be reduced. Can be planned.

  However, in a panel having such an electrode structure, variations in discharge are likely to occur.In particular, in a panel that has a large screen and a high definition, driving impedance increases, and waveform distortion such as ringing in the driving waveform easily occurs. It has been found that the variation in the discharge tends to be large, and there is a risk of causing the luminance variation called luminance unevenness.

  The present invention has been made in view of such problems, and even in a panel with a large screen and high definition, discharge can be stably generated while reducing power consumption, and image display quality can be improved. Another object of the present invention is to provide a plasma display device and a panel driving method.

  The plasma display device according to the present invention causes a sustain pulse to rise or fall by resonating a panel having a plurality of discharge cells each having a display electrode pair composed of a scan electrode and a sustain electrode, an interelectrode capacitance of the display electrode pair, and an inductor. It has a power recovery circuit that performs a fall, generates sustain pulses in the sustain periods of a plurality of subfields having an initialization period, an address period, and a sustain period provided in one field period, and alternately applies them to the display electrode pairs A sustain pulse generating circuit that detects the ratio of the discharge cells to be lit to the total discharge cells in the display area of the panel as an all-cell lighting ratio, and a plurality of display areas on the panel. Discharge to be lit for discharge cells in each region by dividing the region and providing a boundary parallel to the display electrode pair And a partial lighting rate detection circuit that detects the ratio of the light level as a partial lighting rate for each region and for each subfield, and the sustain pulse generation circuit has a plurality of different lengths of at least one of the rising period and the falling period of the sustain pulse. And a plurality of driving patterns with different combinations of sustain pulses to be generated are generated and output from the all-cell lighting rate detection circuit and the partial lighting rate detection circuit. A plurality of drive patterns are switched according to the partial lighting rate to generate a sustain pulse, and when a plurality of drive patterns are arranged on a plane having the whole cell lighting rate and the partial lighting rate as two axes, they are adjacent. A sustain pulse is generated by providing two-dimensional hysteresis characteristics between a plurality of drive patterns.

  As a result, even in a panel with a large screen and high definition, it is possible to stably generate discharge while reducing power consumption and to improve the image display quality of the panel.

  The plasma display device further includes a maximum value detection circuit that detects the maximum value of the partial lighting rate in the display area for each subfield, and the all-cell lighting rate detection circuit includes a plurality of predetermined lighting rate threshold values. Compared with the all-cell lighting rate, the lighting rate threshold value used when the all-cell lighting rate is increasing is larger than the lighting rate threshold value used when the all-cell lighting rate is decreasing. Hysteresis characteristics are set by setting a value, and the maximum value detection circuit compares a plurality of predetermined maximum value thresholds with the detected maximum value, and is used when the detected maximum value is increasing The maximum threshold value is set to a value larger than the maximum threshold value used when the detected maximum value is decreasing to provide hysteresis characteristics. A plurality of drive patterns are generated by switching according to the output from the circuit and the output from the maximum value detection circuit, and the plurality of drive patterns are arranged on a plane having the all-cell lighting rate and the above-mentioned maximum value as two axes. In this case, a sustain pulse is generated by providing two-dimensional hysteresis characteristics between a plurality of adjacent drive patterns. Thereby, the effect which improves the image display quality of a panel can be heightened.

  Further, in this plasma display device, the all-cell lighting rate detection circuit and the maximum value detection circuit generate a sustain pulse in one driving pattern on the above-described plane due to a change in at least one of the all-cell lighting rate and the above-described maximum value. When a change occurs from the area where the hysteresis occurs to the hysteresis area where hysteresis characteristics are set between two or more drive patterns, the lighting rate threshold value or maximum value threshold value is determined according to the state immediately before that. It is good also as composition to do. Thus, stable operation can be realized in a configuration in which hysteresis characteristics are provided two-dimensionally.

  Further, in this plasma display device, the other two from the region where the sustain pulse is generated with one drive pattern on the above-described plane due to the change in at least one of the all-cell lighting rate or the above-described maximum value. When a change to the hysteresis area where hysteresis characteristics are set between the above driving patterns occurs, if the hysteresis area is an area where hysteresis characteristics are set against changes in the lighting rate of all cells, all cells The lighting rate detection circuit has an auxiliary lighting rate threshold value and an all-cell lighting rate set to a value between the lighting rate threshold value with the larger value and the lighting rate threshold value with the smaller value in the hysteresis region. If the hysteresis region is a region where hysteresis characteristics are set against the above-mentioned change in the maximum value, the maximum value detection circuit The auxiliary maximum threshold value set to a value between the maximum value threshold value with the larger value in the hysteresis region and the maximum value threshold value with the smaller value is compared with the above-mentioned maximum value. If the hysteresis region is a region where hysteresis characteristics are set for both the change in the all-cell lighting rate and the above-described change in the maximum value, the all-cell lighting rate detection circuit and the maximum value detection circuit are in the hysteresis region. In the configuration, the auxiliary lighting rate threshold value and the all-cell lighting rate may be compared and the auxiliary maximum value threshold value and the above-described maximum value may be compared based on the priority order determined in advance. This also makes it possible to realize stable operation in a configuration in which hysteresis characteristics are provided two-dimensionally.

  Further, in this plasma display device, the all-cell lighting rate detection circuit and the maximum value detection circuit generate a sustain pulse in one driving pattern on the above-described plane due to a change in at least one of the all-cell lighting rate and the above-described maximum value. A configuration that makes a determination based on a predetermined priority order for each area in which hysteresis characteristics are set when a change occurs from the area in which the hysteresis occurs to a hysteresis area in which hysteresis characteristics are set between two or more drive patterns It is good. This also makes it possible to realize stable operation in a configuration in which hysteresis characteristics are provided two-dimensionally.

  Further, the panel driving method of the present invention provides a panel having a plurality of discharge cells each having a display electrode pair composed of a scan electrode and a sustain electrode, by resonating the interelectrode capacitance of the display electrode pair and the inductor, Using a power recovery circuit that rises or falls, sustain pulses are generated alternately in a sustain period of a plurality of subfields having an initializing period, an address period, and a sustain period provided in one field period, and the display electrode pairs are alternately arranged. The panel driving method is applied to the panel, and the ratio of discharge cells to be lit to the total discharge cells in the display area of the panel is detected for each subfield as the total cell lighting rate, and a plurality of display areas of the panel are detected. In addition, the boundary is provided in parallel with the display electrode pair, and the ratio of the discharge cells to be lit to the discharge cells in each region is divided. Is detected as a partial lighting rate for each region and for each subfield, and a plurality of sustain pulses having different lengths of the rising and falling periods of the sustain pulse are generated, and the combinations of the generated sustain pulses are varied. A plurality of drive patterns are generated, and a sustain pulse is generated by switching the plurality of drive patterns in accordance with the total cell lighting rate and the partial lighting rate, and the total cell lighting rate and the partial lighting rate are set on two axes. When a plurality of drive patterns are arranged on a plane, a sustain pulse is generated by providing a two-dimensional hysteresis characteristic between a plurality of adjacent drive patterns.

  As a result, even in a panel with a large screen and high definition, it is possible to stably generate discharge while reducing power consumption and to improve the image display quality of the panel.

  Further, in the panel driving method of the present invention, a plurality of predetermined lighting rate thresholds are compared with the all-cell lighting rate, and the lighting rate threshold used when the all-cell lighting rate is increased. Set the value to a value greater than the lighting rate threshold value used when the all-cell lighting rate is decreasing, provide hysteresis characteristics, detect the maximum partial lighting rate in the display area for each subfield, Comparing a plurality of predetermined maximum value thresholds with the detected maximum value, the detected maximum value is decreased for the maximum value threshold used when the detected maximum value is increasing Hysteresis characteristics are set by setting a value larger than the maximum threshold value sometimes used, and a plurality of drive patterns are switched according to the all-cell lighting rate and the above-mentioned maximum value, and all cells are lit. And the above-mentioned maximum value are arranged on a plane having two axes, and a sustain pulse is generated by providing a two-dimensional hysteresis characteristic between a plurality of adjacent drive patterns. . Thereby, the effect which improves the image display quality of a panel can be heightened.

  Further, in the panel driving method of the present invention, two or more from the region where the sustain pulse is generated in one driving pattern on the above-mentioned plane due to the change in at least one of the all-cell lighting rate and the above-mentioned maximum value. When the fluctuation to the hysteresis region in which the hysteresis characteristic is set occurs between the driving patterns, the lighting rate threshold value or the maximum value threshold value may be determined according to the immediately preceding state. Thus, stable operation can be realized in a configuration in which hysteresis characteristics are provided two-dimensionally.

  In the panel driving method of the present invention, the sustain pulse is generated from the region where one drive pattern is generated on the above-described plane due to a change in at least one of the all-cell lighting rate or the above-described maximum value. If a hysteresis region with hysteresis characteristics is set between two or more drive patterns, the hysteresis region is a region where hysteresis characteristics are set against changes in the lighting rate of all cells. In the hysteresis region, the auxiliary lighting rate threshold value set to a value between the lighting rate threshold value with the larger value and the lighting rate threshold value with the smaller value is compared with the lighting rate of all cells. If the hysteresis region is a region where hysteresis characteristics are set against the above-mentioned change in the maximum value, the larger maximum value in the hysteresis region The auxiliary maximum threshold value set to a value between the threshold value and the smaller maximum value threshold value is compared with the above-mentioned maximum value. If the hysteresis characteristic is set for any of the above-mentioned changes in the maximum value, the auxiliary lighting rate threshold value is compared with the all-cell lighting rate based on the priority order set in advance in the hysteresis region. Further, the auxiliary maximum value threshold value may be compared with the above-described maximum value. This also makes it possible to realize stable operation in a configuration in which hysteresis characteristics are provided two-dimensionally.

  Further, in the panel driving method of the present invention, two or more from the region where the sustain pulse is generated in one driving pattern on the above-mentioned plane due to the change in at least one of the all-cell lighting rate and the above-mentioned maximum value. When a change to the hysteresis region where the hysteresis characteristic is set occurs between the drive patterns, a drive pattern based on a predetermined priority order may be generated. This also makes it possible to realize stable operation in a configuration in which hysteresis characteristics are provided two-dimensionally.

  According to the present invention, a plasma display apparatus and a panel driving method capable of stably generating discharge while reducing power consumption and improving image display quality even in a panel with a large screen and high definition. Can be provided.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view showing the structure of panel 10 according to Embodiment 1 of the present invention. A plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustaining electrode 23 are formed on a glass front substrate 21. A dielectric layer 25 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 26 is formed on the dielectric layer 25.

  The protective layer 26 has been used as a panel material in order to lower the discharge start voltage in the discharge cell, and has a large secondary electron emission coefficient and durability when neon (Ne) and xenon (Xe) gas is sealed. It is made of a material mainly composed of magnesium oxide (MgO) having excellent properties.

  A plurality of data electrodes 32 are formed on the back substrate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits light of each color of red (R), green (G), and blue (B) is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front substrate 21 and the rear substrate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. A mixed gas of neon and xenon is sealed as a discharge gas in the internal discharge space. In the present embodiment, a discharge gas having a xenon partial pressure of about 10% is used in order to improve luminous efficiency. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall. Further, the mixing ratio of the discharge gas is not limited to the above-described numerical values, and may be other mixing ratios.

  FIG. 2 is an electrode array diagram of panel 10 in accordance with the first exemplary embodiment of the present invention. In panel 10, n scanning electrodes SC1 to SCn (scanning electrode 22 in FIG. 1) and n sustaining electrodes SU1 to SUn (sustaining electrode 23 in FIG. 1) long in the row direction are arranged and long in the column direction. M data electrodes D1 to Dm (data electrode 32 in FIG. 1) are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dj (j = 1 to m), and the discharge cell is in the discharge space. M × n are formed. A region where m × n discharge cells are formed becomes a display region of the panel 10.

  Further, in the panel 10, specifically, so that the positional relationship between the scan electrodes SC <b> 1 to SCn and the sustain electrodes SU <b> 1 to SUn alternates for each display electrode pair 24..., −scan electrode−scan electrode−sustain Electrode-sustain electrode-scan electrode-scan electrode-sustain electrode-sustain electrode-... (Hereinafter referred to as “ABBA electrode structure”. Therefore, the positional relationship between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn does not change for each display electrode pair 24, and is arranged as: scan electrode sustain electrode scan electrode sustain electrode The electrode structure is referred to as “ABAB electrode structure”).

  As shown in FIGS. 1 and 2, scan electrode SCi and sustain electrode SUi are formed in parallel with each other, and therefore, between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn. There is an interelectrode capacitance Cp. However, in the present embodiment, since panel 10 has an ABBA electrode structure, voltage changes can be made in-phase between adjacent discharge cells during the sustain operation in the sustain period, and reactive power can be reduced. .

  Next, a driving voltage waveform for driving the panel 10 and an outline of the operation will be described. The plasma display device according to the present embodiment performs gradation display by subfield method, that is, by dividing one field period into a plurality of subfields and controlling light emission / non-light emission of each discharge cell for each subfield. Each subfield has an initialization period, an address period, and a sustain period.

  In each subfield, initializing discharge is generated in the initializing period, and wall charges necessary for subsequent address discharge are formed on each electrode. In addition, it has a function of generating priming particles (priming for discharge = excited particles) for reducing discharge delay and generating address discharge stably. The initializing operation at this time is an all-cell initializing operation in which initializing discharge is generated in all discharge cells, and an initializing discharge is selectively generated only in the discharge cells that have undergone sustain discharge in the immediately preceding subfield. There is a selective initialization operation.

  In the address period, an address discharge is selectively generated in the discharge cells to emit light in the subsequent sustain period to form wall charges. In the sustain period, a number of sustain pulses proportional to the luminance weight are alternately applied to the display electrode pair 24 to generate a sustain discharge in the discharge cells that have generated the address discharge, thereby causing light emission. The proportionality constant at this time is called “luminance magnification”.

  In this embodiment, one field is composed of 10 subfields (first SF, second SF,..., 10th SF), and each subfield is, for example, (1, 2, 3, 6, 11, 18). , 30, 44, 60, 80). Then, the all-cell initialization operation is performed in the initialization period of the first SF, and the selective initialization operation is performed in the initialization period of the second SF to the tenth SF. As a result, the light emission not related to the image display is only the light emission due to the discharge of the all-cell initialization operation in the first SF, and the black luminance that is the luminance of the black display area that does not generate the sustain discharge is weak in the all-cell initialization operation Only the emission of light makes it possible to display an image with high contrast. In the sustain period of each subfield, the number of sustain pulses obtained by multiplying the luminance weight of each subfield by a predetermined luminance magnification is applied to each display electrode pair 24.

  However, in the present embodiment, the number of subfields and the luminance weight of each subfield are not limited to the above values, and the subfield configuration may be switched based on an image signal or the like.

  In the present embodiment, a power recovery circuit described later is operated to start a sustain pulse in accordance with the lighting rate for each subfield measured by the all-cell lighting rate detection circuit and the partial lighting rate detection circuit described later. And controlling the length of at least one of the period of time (hereinafter referred to as “rise period”) and the period of time during which the power recovery circuit is operated to cause the sustain pulse to fall (hereinafter referred to as “fall period”) The overlap period in which the rising and falling edges of the sustain pulse overlap is controlled. Thereby, while reducing the power consumption in the panel 10, the sustain discharge is stabilized, the display luminance of each discharge cell is made uniform, and the image display quality in the panel 10 is improved. Hereinafter, the outline of the drive voltage waveform and the configuration of the drive circuit will be described first, and then control of the “rise period”, “fall period”, and overlap period according to the lighting rate will be described.

  FIG. 3 is a drive voltage waveform diagram applied to each electrode of panel 10 in accordance with the first exemplary embodiment of the present invention. FIG. 3 shows driving voltage waveforms of two subfields, that is, a subfield that performs an all-cell initializing operation (hereinafter referred to as “all-cell initializing subfield”) and a subfield that performs a selective initializing operation ( Hereinafter, it is referred to as “selective initialization subfield”), but the driving voltage waveforms in the other subfields are substantially the same. Further, scan electrode SCi, sustain electrode SUi, and data electrode Dk in the following represent electrodes selected from the respective electrodes based on image data.

  First, the first SF, which is an all-cell initialization subfield, will be described.

  In the first half of the initializing period of the first SF, 0 (V) is applied to the data electrodes D1 to Dm and the sustain electrodes SU1 to SUn, respectively, and the discharge start voltage with respect to the sustain electrodes SU1 to SUn is applied to the scan electrodes SC1 to SCn. A ramp waveform voltage (hereinafter referred to as “up-ramp waveform voltage”) that gradually rises from the voltage Vi1 below toward the voltage Vi2 that exceeds the discharge start voltage is applied.

  While the rising ramp waveform voltage rises, weak initializing discharges are continuously generated between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm. Negative wall voltage is accumulated on scan electrodes SC1 to SCn, and positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SUn. The wall voltage above the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the latter half of the initialization period, positive voltage Ve1 is applied to sustain electrodes SU1 to SUn, 0 (V) is applied to data electrodes D1 to Dm, and sustain electrodes SU1 to SUn are applied to scan electrodes SC1 to SCn. In contrast, a ramp waveform voltage (hereinafter referred to as a “down-ramp waveform voltage”) that gently falls from a voltage Vi3 that is equal to or lower than the discharge start voltage to a voltage Vi4 that exceeds the discharge start voltage is applied. During this time, weak initializing discharges are continuously generated between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm. Then, the negative wall voltage above scan electrodes SC1 to SCn and the positive wall voltage above sustain electrodes SU1 to SUn are weakened, and the positive wall voltage above data electrodes D1 to Dm is adjusted to a value suitable for the write operation. The Thus, the all-cell initializing operation for performing the initializing discharge on all the discharge cells is completed.

  Note that, as shown in the initialization period of the second SF in FIG. 3, a drive voltage waveform in which the first half of the initialization period is omitted may be applied to each electrode. That is, the voltage Ve1 is applied to the sustain electrodes SU1 to SUn, 0 (V) is applied to the data electrodes D1 to Dm, and the voltage (for example, the ground potential) that is equal to or lower than the discharge start voltage is applied to the scan electrodes SC1 to SCn. A down-ramp waveform voltage that gradually falls toward is applied. As a result, a weak initializing discharge is generated in the discharge cell in which the sustain discharge has occurred in the sustain period of the previous subfield, and the wall voltage above scan electrode SCi and sustain electrode SUi is weakened. Further, in a discharge cell in which a sufficient positive wall voltage is accumulated on the data electrode Dk (k = 1 to m) by the last sustain discharge, an excessive portion of the wall voltage is discharged, and the wall voltage suitable for the address operation is obtained. Adjusted to On the other hand, the discharge cells that did not cause the sustain discharge in the previous subfield are not discharged, and the wall charges at the end of the initialization period of the previous subfield are maintained as they are. Thus, the initializing operation in which the first half is omitted is a selective initializing operation in which initializing discharge is performed on the discharge cells in which the sustaining operation has been performed in the sustain period of the immediately preceding subfield.

  In the subsequent address period, voltage Ve2 is first applied to sustain electrodes SU1 to SUn, and voltage Vc is applied to scan electrodes SC1 to SCn.

  Then, a negative scan pulse voltage Va is applied to the scan electrode SC1 in the first row, and the data electrode Dk (k = 1 to m) of the discharge cell to be emitted in the first row among the data electrodes D1 to Dm is positive. The write pulse voltage Vd is applied. At this time, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is the difference between the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1 due to the difference in externally applied voltage (Vd−Va). It becomes the sum and exceeds the discharge start voltage. As a result, a discharge is generated between data electrode Dk and scan electrode SC1. In addition, since voltage Ve2 is applied to sustain electrodes SU1 to SUn, the voltage difference between sustain electrode SU1 and scan electrode SC1 is the difference between the externally applied voltages (Ve2-Va) and on sustain electrode SU1. The difference between the wall voltage and the wall voltage on the scan electrode SC1 is added. At this time, by setting the voltage Ve2 to a voltage value that is slightly lower than the discharge start voltage, the sustain electrode SU1 and the scan electrode SC1 are not easily discharged but are likely to be discharged. Can do. Thereby, the discharge generated between data electrode Dk and scan electrode SC1 can be triggered to generate a discharge between sustain electrode SU1 and scan electrode SC1 in the region intersecting with data electrode Dk. Thus, an address discharge occurs in the discharge cell to emit light, a positive wall voltage is accumulated on scan electrode SC1, a negative wall voltage is accumulated on sustain electrode SU1, and a negative wall voltage is also accumulated on data electrode Dk. Accumulated.

  In this manner, an address operation is performed in which an address discharge is caused in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrodes D1 to Dm to which the address pulse voltage Vd is not applied and the scan electrode SC1 does not exceed the discharge start voltage, so that address discharge does not occur. The above address operation is performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, first, positive sustain pulse voltage Vs is applied to scan electrodes SC1 to SCn, and a ground potential that is a base potential, that is, 0 (V) is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. Exceeds the discharge start voltage.

  Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred during the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.

  Subsequently, 0 (V) as a base potential is applied to scan electrodes SC1 to SCn, and sustain pulse voltage Vs is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the sustain discharge has occurred, the voltage difference between the sustain electrode SUi and the scan electrode SCi exceeds the discharge start voltage, so that the sustain discharge occurs again between the sustain electrode SUi and the scan electrode SCi. A negative wall voltage is accumulated on SUi, and a positive wall voltage is accumulated on scan electrode SCi. Thereafter, similarly, the sustain electrodes of the number obtained by multiplying the luminance weight by the luminance magnification are alternately applied to the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn, and a potential difference is given between the electrodes of the display electrode pair 24, thereby writing. The sustain discharge is continuously performed in the discharge cell that has caused the address discharge in the period.

  At the end of the sustain period, a ramp waveform voltage (hereinafter referred to as “erase ramp waveform voltage”) gently rising from 0 (V) as the base potential toward voltage Vers is applied to scan electrodes SC1 to SCn. Is applied. As a result, a weak discharge is continuously generated, and some or all of the wall voltages on scan electrode SCi and sustain electrode SUi are erased while the positive wall voltage on data electrode Dk remains.

  Specifically, after the sustain electrodes SU1 to SUn are returned to 0 (V), an erase ramp waveform voltage that rises from 0 (V), which is the base potential, toward the voltage Vers exceeding the discharge start voltage is generated and scanned. Apply to electrodes SC1 to SCn. Then, a weak discharge is generated between sustain electrode SUi and scan electrode SCi of the discharge cell in which the sustain discharge has occurred. This weak discharge is continuously generated during a period in which the voltage applied to scan electrodes SC1 to SCn increases.

  At this time, the charged particles generated by the weak discharge are accumulated as wall charges on the sustain electrode SUi and the scan electrode SCi so as to reduce the voltage difference between the sustain electrode SUi and the scan electrode SCi. To go. As a result, the wall voltage between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn remains between the voltage applied to scan electrode SCi and the discharge start voltage while leaving positive wall charges on data electrode Dk. The difference is reduced to the extent of (voltage Vers−discharge start voltage). Hereinafter, the last discharge in the sustain period generated by the erase ramp waveform voltage is referred to as “erase discharge”.

  Subsequent subfield operations are substantially the same as those described above except for the number of sustain pulses in the sustain period, and thus description thereof is omitted. The above is the outline of the drive voltage waveform applied to each electrode of panel 10 in the present embodiment.

  In the present embodiment, as described above, panel 10 has an ABBA electrode structure. Therefore, in adjacent discharge cells, the scan electrode and the scan electrode are adjacent to each other, and the sustain electrode and the sustain electrode are adjacent to each other. Therefore, the change in sustain pulse voltage can be made in-phase between adjacent discharge cells, and reactive power can be reduced. For example, it was confirmed that the reactive power can be reduced by about 25% compared to the case of driving a panel having an ABAB electrode structure.

  Next, the configuration of the plasma display device in the present embodiment will be described. FIG. 4 is a circuit block diagram of the plasma display device in accordance with the first exemplary embodiment of the present invention. The plasma display apparatus 1 includes a panel 10, an image signal processing circuit 41, a data electrode driving circuit 42, a scanning electrode driving circuit 43, a sustain electrode driving circuit 44, a timing generation circuit 45, an all-cell lighting rate detection circuit 46, and a partial lighting rate detection. A circuit 47, a maximum value detection circuit 48, and a power supply circuit (not shown) for supplying power necessary for each circuit block are provided.

  The image signal processing circuit 41 converts the input image signal sig into image data indicating light emission / non-light emission for each subfield. The data electrode drive circuit 42 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes D1 to Dm.

  The all-cell lighting rate detection circuit 46 detects the ratio of the number of discharge cells to be lit to the total number of discharge cells, that is, the total cell lighting rate for each subfield, based on the image data for each subfield. Then, the detected all-cell lighting rate is compared with a plurality of predetermined lighting rate threshold values (15%, 30%, and 60% in this embodiment), and a signal representing the result is sent to the timing generation circuit 45. Output to.

  The partial lighting rate detection circuit 47 divides the display area of the panel into a plurality of areas to be described later, and the ratio of the number of discharge cells to be lit to the number of discharge cells for each area and for each subfield based on the image data for each subfield. That is, the partial lighting rate is detected.

  The maximum value detection circuit 48 compares the partial lighting rates detected by the partial lighting rate detection circuit 47 with each other, and detects the maximum value for each subfield. Then, the detected maximum value is compared with a predetermined maximum value threshold value, and a signal representing the result is output to the timing generation circuit 45.

  In the present embodiment, the lighting rate threshold is set to 15%, 30%, and 60%, and the maximum value threshold is set to 60%. It is not limited to a numerical value, and it is desirable to set an optimal value based on the characteristics of the panel, the specifications of the plasma display device, and the like.

  The timing generation circuit 45 generates various timing signals for controlling the operation of each circuit block based on outputs from the horizontal synchronization signal H, the vertical synchronization signal V, the all-cell lighting rate detection circuit 46, and the maximum value detection circuit 48. And supplied to each circuit block. As described above, in the present embodiment, the “rising period” at the rising edge of the sustain pulse, the “falling period” at the falling edge of the sustain pulse, and the overlapping period in which the rising edge and the falling edge of the sustain pulse overlap each other. Control is performed based on outputs from the all-cell lighting rate detection circuit 46 and the maximum value detection circuit 48, and timing signals corresponding to the outputs are output to the scan electrode drive circuit 43 and the sustain electrode drive circuit 44. Thereby, reduction of power consumption and stabilization of sustain discharge are realized.

  Scan electrode drive circuit 43 generates an initialization waveform voltage (not shown) for generating an initialization waveform voltage to be applied to scan electrodes SC1 to SCn in the initialization period, and applies to scan electrodes SC1 to SCn in the sustain period. Sustain pulse generating circuit 50 for generating sustain pulses, and a scan pulse generating circuit (not shown) for generating scan pulse voltages to be applied to scan electrodes SC1 to SCn in the address period, are based on timing signals. Each scan electrode SC1 to SCn is driven. Sustain electrode drive circuit 44 includes sustain pulse generation circuit 60 and a circuit for generating voltages Ve1 and Ve2, and drives sustain electrodes SU1 to SUn based on a timing signal.

  Next, details and operation of sustain pulse generating circuit 50 and sustain pulse generating circuit 60 will be described. FIG. 5 is a circuit diagram of sustain pulse generation circuit 50 and sustain pulse generation circuit 60 in the first exemplary embodiment of the present invention. In FIG. 5, the interelectrode capacitance of the panel 10 is shown as Cp, and the circuit for generating the scan pulse and the initialization voltage waveform is omitted.

  The sustain pulse generation circuit 50 includes a power recovery circuit 51 and a clamp circuit 52. The power recovery circuit 51 and the clamp circuit 52 include a scan pulse generation circuit (not shown because it is in a short-circuit state during the sustain period). And is connected to scan electrodes SC1 to SCn which are one end of the interelectrode capacitance Cp of the panel 10.

  The power recovery circuit 51 includes a power recovery capacitor C10, a switching element Q11, a switching element Q12, a backflow prevention diode D11, a backflow prevention diode D12, and a resonance inductor L10. Then, the interelectrode capacitance Cp and the inductor L10 are LC-resonated to cause the sustain pulse to rise and fall. Thus, since the power recovery circuit 51 drives the scan electrodes SC1 to SCn by LC resonance without being supplied with power from the power source, the power consumption is ideally zero. The power recovery capacitor C10 has a sufficiently large capacity compared to the interelectrode capacity Cp, and is charged to about Vs / 2, which is half of the voltage value Vs, so as to serve as a power source for the power recovery circuit 51.

  Clamp circuit 52 has switching element Q13 for clamping scan electrodes SC1 to SCn to voltage Vs, and switching element Q14 for clamping scan electrodes SC1 to SCn to the base potential of 0 (V). Then, scan electrodes SC1 to SCn are connected to power supply VS via switching element Q13 and clamped to voltage Vs, and scan electrodes SC1 to SCn are grounded and clamped to 0 (V) via switching element Q14. Therefore, the impedance at the time of voltage application by the clamp circuit 52 is small, and a large discharge current due to strong sustain discharge can flow stably.

  Sustain pulse generation circuit 50 is connected to power recovery circuit 51 by clamping switching element Q11, switching element Q12, switching element Q13, and switching element Q14 in accordance with a timing signal output from timing generation circuit 45. The circuit 52 is operated to generate a sustain pulse waveform.

  For example, when the sustain pulse waveform is raised, the switching element Q11 is turned on to cause the interelectrode capacitance Cp and the inductor L10 to resonate, and the power recovery capacitor C10 scans the scanning electrode through the switching element Q11, the diode D11, and the inductor L10. Power is supplied to SC1 to SCn. Then, when the voltage of scan electrodes SC1 to SCn approaches voltage Vs, switching element Q13 is turned on to switch the circuit for driving scan electrodes SC1 to SCn from power recovery circuit 51 to clamp circuit 52, and scan electrode SC1. Clamp SCn to voltage Vs.

  On the contrary, when the sustain pulse waveform is lowered, the switching element Q12 is turned on to resonate the interelectrode capacitance Cp and the inductor L10, and the interelectrode capacitance Cp is used for power recovery through the inductor L10, the diode D12, and the switching element Q12. The power is recovered in the capacitor C10. When the voltage of scan electrodes SC1 to SCn approaches 0 (V), switching element Q14 is turned on, and the circuit for driving scan electrodes SC1 to SCn is switched from power recovery circuit 51 to clamp circuit 52 for scanning. The electrodes SC1 to SCn are clamped to 0 (V) which is the base potential.

  In this way, sustain pulse generating circuit 50 generates a sustain pulse. Note that these switching elements can be configured using generally known elements such as MOSFETs and IGBTs.

  Sustain pulse generation circuit 60 has substantially the same configuration as sustain pulse generation circuit 50, and includes a power recovery capacitor C20, switching element Q21, switching element Q22, backflow prevention diode D21, backflow prevention diode D22, and resonance. A power recovery circuit 61 for recovering and reusing power when driving sustain electrodes SU1 to SUn, switching element Q23 for clamping sustain electrodes SU1 to SUn to voltage Vs, And a clamp circuit 62 having a switching element Q24 for clamping the sustain electrodes SU1 to SUn to the ground potential (0 (V)), and the sustain electrodes SU1 to SUn which are one end of the interelectrode capacitance Cp of the panel 10 are provided. It is connected. The operation of sustain pulse generating circuit 60 is the same as that of sustain pulse generating circuit 50, and therefore description thereof is omitted.

  Further, FIG. 5 shows a power source VE1 for generating the voltage Ve1, a switching element Q26 for applying the voltage Ve1 to the sustain electrodes SU1 to SUn, a switching element Q27, a power source ΔVE for generating the voltage ΔVe, and a backflow preventing diode D30. 1 shows a pump-up capacitor C30 for accumulating the voltage ΔVe on the voltage Ve1, a switching element Q28 and a switching element Q29 for accumulating the voltage ΔVe on the voltage Ve1 to obtain the voltage Ve2.

  For example, at the timing when the voltage Ve1 shown in FIG. 3 is applied, the switching element Q26 and the switching element Q27 are turned on to apply the positive voltage Ve1 to the sustain electrodes SU1 to SUn via the diode D30, the switching element Q26, and the switching element Q27. Apply. At this time, the switching element Q28 is turned on and charged so that the voltage of the capacitor C30 becomes the voltage Ve1. In addition, at the timing of applying the voltage Ve2 shown in FIG. 3, the switching element Q26 and the switching element Q27 are kept conductive, the switching element Q28 is cut off, and the switching element Q29 is turned on to apply the voltage ΔVe to the voltage of the capacitor C30. The voltage Ve1 + ΔVe, that is, the voltage Ve2 is applied to the sustain electrodes SU1 to SUn. At this time, the current from the capacitor C30 to the power source VE1 is cut off by the function of the backflow preventing diode D30.

  Note that the circuit for applying the voltage Ve1 and the voltage Ve2 is not limited to the circuit shown in FIG. 5. For example, a power source that generates the voltage Ve1 and a power source that generates the voltage Ve2 and the respective voltages are maintained electrodes. A plurality of switching elements for applying to SU1 to SUn may be used to apply each voltage to sustain electrodes SU1 to SUn at a necessary timing.

  The period of LC resonance between the inductor L10 of the power recovery circuit 51 and the interelectrode capacitance Cp of the panel 10 and the period of LC resonance between the inductor L20 of the power recovery circuit 61 and the interelectrode capacitance Cp (hereinafter referred to as “resonance period”). Can be obtained by the calculation formula “2π√ (LCp)”, where L is the inductance of the inductor L10 and the inductor L20. In this embodiment, the inductor L10 and the inductor L20 are set so that the resonance period in the power recovery circuit 51 and the power recovery circuit 61 is 2000 nsec. However, this numerical value is only an example in the embodiment. What is necessary is just to set to the optimal value according to the characteristic of a panel, the specification of a plasma display apparatus, etc.

  Next, details of the drive voltage waveform in the sustain period will be described.

  As described above, in this embodiment, the panel 10 has an ABBA electrode structure in order to reduce reactive power. However, it has been confirmed that discharge variations easily occur in the discharge cell having this ABBA electrode structure. It was done.

  This is because the same type of electrodes are adjacent to each other in the ABBA electrode structure (scan electrode-scan electrode, or sustain electrode-sustain electrode), so that the applied sustain pulses are in phase, and as a result, the effect of reducing reactive power is obtained. However, on the other hand, the electric field applied between the discharge cells adjacent in the column direction becomes smaller than that of the discharge cell having the ABAB electrode structure, and the charge easily moves to the discharge cells adjacent in the row direction. This is thought to be due to the increase in the amount of charge transfer, which increases the variation in wall charge.

  When the variation in wall charge increases, the variation in applied voltage necessary for generating discharge also increases, resulting in variation in discharge. Next, an example of variation in discharge generated due to variation in wall charges will be described with reference to the drawings. In the drawings used for the following description, the ground potential is denoted as “GND”.

  FIG. 6 is a schematic waveform diagram showing an example of the sustain pulse in the first embodiment of the present invention. For example, as shown in FIG. 6, in the sustain operation in which the next sustain pulse is raised after the last sustain pulse has sufficiently fallen, the power recovery circuit can sufficiently drive, so that the power consumption It is possible to perform driving while suppressing this.

  On the other hand, since the output impedance of the power recovery circuit is larger than the output impedance of the clamp circuit, discharge may be unstable when the ratio of discharge cells to be lit increases and the load during driving increases. .

  FIG. 7 is a schematic waveform diagram showing an example of the sustain pulse and the state of light emission at that time in Embodiment 1 of the present invention. The waveform shown in FIG. 7 shows the voltage observed at scan electrode SCi and sustain electrode SUi during the sustain period of the subfield having a relatively high lighting rate when driven by the sustain pulse shown in FIG. It is a waveform which shows an example of a change, and is a waveform which shows the intensity of light emission at that time.

  First, when the sustain pulse is raised by the power recovery circuit, for example, as shown in A of the drawing, the first discharge occurs when the voltage obtained by adding the wall voltage to the sustain pulse voltage exceeds the discharge start voltage. To do. At this time, in a subfield with a relatively high lighting rate, a large amount of discharge current flows instantaneously due to this discharge, and therefore the sustain pulse voltage temporarily drops. Thereafter, when the power recovery circuit is switched to the clamp circuit and the sustain pulse voltage is clamped to the voltage Vs, for example, as shown in B of the drawing, a second discharge is generated. However, since a part of wall charges is consumed by the first discharge, the second discharge is not a strong discharge. For this reason, the accumulated wall charges are reduced as compared with the case where a strong discharge is generated.

  As a result, in the immediately subsequent sustain pulse, when the sustain pulse is raised by the power recovery circuit, no discharge occurs or even if a discharge occurs, the discharge is very weak. Therefore, the phenomenon of wall charge consumption due to the first discharge at the time of rising of the sustain pulse as shown in A of the above-mentioned drawing hardly occurs. Therefore, after that, when the power recovery circuit is switched to the clamp circuit and the sustain pulse voltage is clamped to the voltage Vs, a very strong discharge is generated as shown in FIG.

  Further, the strong discharge as shown in C of the drawing accumulates sufficient wall charges in the discharge cell, so that at the next sustain pulse, two times as shown in A and B of the drawing at the rising edge. Discharge occurs.

  As described above, in driving the panel 10 having the ABBA electrode structure, in the sustain period of the subfield where the lighting rate is relatively high, as described above, one very strong discharge and a weaker continuous 2 are performed. As a result, a variation in luminance called luminance unevenness may occur.

  Although not shown, it was confirmed that when the lighting rate is low, the above-described variation in discharge is reduced, and stable sustain discharge is generated.

  On the other hand, if the overlap period in which the rise and fall of the sustain pulse overlap is increased, the variation in discharge can be reduced even in the subfield having a high lighting rate in the panel 10 having the ABBA electrode structure. Was confirmed.

  FIG. 8 is a schematic waveform diagram showing another example of the sustain pulse in the first embodiment of the present invention. In the present embodiment, the “rising period” and “falling period” of the sustain pulse, that is, the time for operating the power recovery circuit when the sustain pulse rises and falls, Although controlled according to the detection result in the value detection circuit 48, here, the waveform shape in which the “rising period” and “falling period” of the sustain pulse are 1050 nsec and the pulse width of the sustain pulse is 2.7 μsec. An example is shown. The “pulse width” represents a period from when the sustain pulse starts to rise from the base potential (0 (V)) toward the sustain pulse voltage Vs until it is clamped to the base potential again. Although not described in FIG. 6, the “rising period”, “falling period”, and pulse width of the sustain pulse shown in FIG. 6 are the same as those of the sustain pulse shown in FIG. Shall be different.

  As a result of investigation by the present inventor, for example, in the case of the sustain pulse set as described above, if the overlap period in which the rise and fall of the sustain pulse overlap is set to 850 nsec, the variation in discharge is reduced. It was confirmed that it was possible. Next, the details will be described.

  FIG. 9 is a schematic waveform diagram showing an example of the sustain pulse and the state of light emission at that time in Embodiment 1 of the present invention. Note that the waveforms shown in FIG. 9 indicate the voltages observed at scan electrode SCi and sustain electrode SUi in the sustain period of the subfield where the lighting rate is relatively high when driving by the sustain pulse shown in FIG. It is a waveform which shows an example of a change, and is a waveform which shows the intensity of light emission at that time.

  As a result of detailed examination by the inventor, if the overlap period is made sufficiently large, the power recovery circuit is switched to the clamp circuit at the fall of the last sustain pulse, and the sustain pulse voltage is clamped to the ground potential. At that time, it was confirmed that the first discharge can be forcibly generated as shown in D of the drawing. Then, by forcibly generating the first discharge, when the sustain pulse is switched from the power recovery circuit to the clamp circuit at the rising edge of the sustain pulse, the sustain pulse voltage is clamped to the voltage Vs, and then E As shown, it was confirmed that the second discharge can be generated, and that these two discharges can be generated with reduced variation.

  As described above, in the driving waveform shown in FIG. 6, depending on the state of wall charge, there are cases where a discharge occurs in the middle of raising a sustain pulse by the power recovery circuit and a case where no discharge occurs, and as a result, Dispersion of discharge occurred.

  However, in the drive waveform shown in FIG. 8, the first discharge can be forcibly generated regardless of the wall charge variation, so that two consecutive discharges can be generated while suppressing the discharge variation. And the occurrence of uneven brightness can be prevented.

  It should be noted that the above-described two continuous discharges with suppressed variations in discharge do not occur as long as an overlap period is provided, and it is necessary to set the overlap period to a sufficient length. Therefore, in the present embodiment, at the falling of the sustain pulse, the overlap period is divided depending on whether or not the first discharge is forced when the sustain pulse voltage is clamped to the ground potential. The overlap period that is extended until the first discharge occurs is referred to as a “second overlap period” and cannot be forcibly generated in the first discharge, less than the “second overlap period”. The overlap period set to the length of is called “first overlap period”. Accordingly, the overlap period set to “0” is also included in the “first overlap period”, and the drive waveform without the overlap period shown in FIG. 6 is also referred to as the “first overlap period”. Shall be set to.

  Further, the inventor of the present invention can generate the discharge twice by forcing the overlap period to be the “second overlap period” in one sustain operation, and the discharge state in the subsequent sustain operation is stabilized. And it was confirmed that the stable discharge continued to some extent.

  FIG. 10 is a schematic waveform diagram showing an example of occurrence of the “second overlap period” in the first embodiment of the present invention. Here, the “first overlap period” is set to 200 nsec, and the “second overlap period” is set to 850 nsec. Then, as shown in FIG. 10, a “second overlap period” is generated at a frequency of once every plural times (in the example shown in FIG. 10, one of eight overlap periods), and the remaining Even if the overlapping period (in the example shown in FIG. 10, the remaining seven of the eight overlapping periods) is set as the “first overlapping period”, stable discharge can be generated, and variation in discharge can be reduced. It was confirmed that the effect of reducing was obtained.

  That is, when the “second overlap period” is generated, it is not always necessary to set the overlap period as the “second overlap period” in the entire maintenance period, but once every plural times (for example, once out of 8 times) It is possible to obtain the effect of reducing the variation in discharge only by generating the “second overlap period” at the frequency of

  In addition, the present inventor sets the remaining overlap period (7 out of 8 in the example shown in FIG. 10) as the “first overlap period”, thereby reducing the power consumption by improving the light emission efficiency. Was also confirmed.

  FIG. 11 is a schematic diagram showing the relationship between the lighting rate and the light emission efficiency when driven by changing the occurrence frequency of the “second overlap period” in the first embodiment of the present invention.

  In FIG. 11, the horizontal axis represents the lighting rate (here, the whole cell lighting rate is represented), and the vertical axis represents the light emission efficiency. In addition, the solid line represents the result when the overlap period is the “second overlap period” in all the sustain periods, and the broken line is the result when the overlap period is the “first overlap period” in all the sustain periods. 10 represents the sustain pulse shown in FIG. 10, that is, the result when one of the eight overlapping periods is set as the “second overlapping period” and the remaining seven times are set as the “first overlapping period”. Represent.

  As shown in FIG. 11, when the overlap period is set to the “first overlap period” in all the sustain periods, the light emission efficiency is the best, but one of the eight overlap periods is set to “second overlap period”. By setting the remaining seven times as the “first overlapping period” and the remaining seven times as the “first overlapping period”, the light emission efficiency can be greatly improved as compared to the case where the overlapping period is set as the “second overlapping period” in all the maintenance periods. confirmed. If the light emission efficiency can be improved, it is possible to drive with reduced power consumption, and power consumption can be reduced.

  8 and 10, the “second overlap period” is set to 850 nsec, and in FIG. 10, the “first overlap period” is set to 200 nsec, and one of the eight overlap periods is set to “ Although a configuration has been described in which the “second overlap period” is set as the remaining seven times and the “first overlap period” is described, these numerical values are merely examples. The length of the “first overlap period”, the “second overlap period”, and the occurrence frequency of the “second overlap period” depend on the waveform shape of the sustain pulse, the characteristics of the panel, the specifications of the plasma display device, etc. And set optimally.

  On the other hand, the discharge variation and power consumption are related to the “rise period” of the sustain pulse, and the discharge variation and power consumption change depending on the length of the “rise period”. First, the discharge variation and the “rise period” will be described.

  FIGS. 12, 13, and 14 are waveform diagrams showing the relationship between the “rising period” of the sustain pulse and the variation in discharge in the first embodiment of the present invention. 12 is a diagram showing a measurement result when the “rise period” is set to 400 nsec, and FIG. 13 is a diagram showing a measurement result when the “rise period” is set to 500 nsec. These are the figures which showed the measurement result when "rise period" is set to 550 nsec. In FIG. 12, FIG. 13, and FIG. 14, the measurement results in a plurality of discharge cells are shown superimposed on one graph.

  12, 13, and 14, the vertical axis represents the emission intensity, and the horizontal axis represents the elapsed time from the start of the operation of the power recovery circuit. The unit (au) on the vertical axis represents an arbitrary unit. Further, here, the resonance period of the power recovery circuit is set to 1200 nsec, the pulse width is set to 2.7 μsec, the overlapping period is set to 0 nsec, the “falling period” is set to 900 nsec, and the “rising period” is set to 400 nsec (FIG. 12), 500 nsec ( FIG. 13) Experiments were carried out with three variations of 550 nsec (FIG. 14).

  For example, as shown in FIG. 12, it was confirmed that when the “rise period” is set to a relatively short 400 nsec, most of the discharge cells emit light at substantially the same time, and discharge variation is suppressed. This is considered to be because the first discharge described in FIG. 7 is strongly generated in most discharge cells because the “rise period” is short.

  In addition, as shown in FIG. 13, it was confirmed that when the “rise period” was set to 500 nsec, which was longer than that of FIG. 12, the light emission time of the discharge cells varied, and the variation in discharge increased. This is considered to be because the “rise period” is not set appropriately, so that it is divided into a discharge cell in which the first discharge described in FIG. 7 is strongly generated and a discharge cell in which the second discharge is also generated strongly. It is done.

  Further, as shown in FIG. 14, when the “rise period” is set to a sufficiently long 550 nsec, most discharge cells emit light at substantially the same time later than the light emission timing shown in FIG. It was confirmed that it was suppressed. This is probably because the “rising period” is sufficiently long, and the second discharge described in FIG. 7 is strongly generated in most discharge cells.

  In this way, the “rising period” in the sustain pulse is one of the following two, that is, the length at which the first discharge described in FIG. 7 occurs strongly in most discharge cells, or the same in most discharge cells. By setting it to one of the lengths at which the second discharge is strongly generated, it is possible to reduce the variation in the discharge.

  Next, power consumption and “rise period” will be described. Note that, as items that affect the power consumption, the light emission efficiency, the light emission luminance, the reactive power, and the sustain pulse voltage Vs necessary for stably generating the sustain discharge can be considered. Therefore, here, the relationship between each item and the “rise period” will be described in order.

  FIG. 15 is a characteristic diagram showing the relationship between the “rising period” of the sustain pulse and the light emission efficiency in the first embodiment of the present invention. In FIG. 15, the vertical axis represents the relative ratio of the luminous efficiency, and the horizontal axis represents the length of the “rise period”. Note that the unit (%) on the vertical axis is obtained by converting the detection result of the light emission efficiency (lm / W: light emission luminance per unit power) into a relative ratio with a predetermined value being 100%. Represents a good thing. 15 and subsequent FIGS. 16 to 18, the resonance period of the power recovery circuit is set to 2000 nsec, the pulse width is set to 2.7 μsec, the overlap period is set to 0 nsec, the “falling period” is set to 900 nsec, and the “rising period” is set to The experiment was performed by extending 50 nsec from 500 nsec to 1000 nsec.

  As shown in FIG. 15, the light emission efficiency varies depending on the length of the “rise period”. Then, as shown in FIG. 15, as the “rise period” is lengthened, the light emission efficiency gradually decreases, then increases, and then decreases again. From this, it can be seen that there are two points where the luminous efficiency can be improved (in FIG. 15, two places of about 500 nsec and about 900 nsec). This is because by gradually extending the “rise period”, a single discharge is generated from a state where a single discharge was stably generated by one sustain pulse at the beginning (first luminous efficiency improvement point). It is considered that the state has shifted to a state in which two continuous discharges are repeated, and then has shifted to a state in which two consecutive discharges are stably generated (second luminous efficiency improvement point).

  FIG. 16 is a characteristic diagram showing the relationship between the “rising period” of the sustain pulse and the light emission luminance in the first embodiment of the present invention. In FIG. 16, the vertical axis represents the relative ratio of the light emission luminance, and the horizontal axis represents the length of the “rise period”. Note that the unit (%) on the vertical axis is obtained by converting the detection result of the light emission luminance (lm) into a relative ratio with a predetermined value being 100%, and the larger the value, the higher the light emission luminance.

  As shown in FIG. 16, the light emission luminance varies depending on the length of the “rise period”.

  As in FIG. 15, as the “rise period” is lengthened, the light emission luminance gradually decreases, then increases, and then decreases again. From this, it can be seen that there are two points where light emission luminance can be improved, as in FIG. 15 (two places of about 500 nsec and about 800 nsec in FIG. 16). As in FIG. 15, this is a state in which one discharge is stably generated at one initial sustain pulse by gradually extending the “rise period” (first emission luminance improvement point). From the transition to a state in which one discharge and two consecutive discharges are repeated, and then to a state in which two consecutive discharges are stably generated (second emission luminance improvement point) Conceivable. Regarding the second improvement point, there is a shift of about 100 nsec between FIG. 15 and FIG. 16, which is a “rise period” in which the light emission efficiency is the best and a “rise period” in which the light emission luminance is the best. This difference is considered to be related to whether the first discharge or the second discharge of the two consecutive discharges is strengthened.

  FIG. 17 is a characteristic diagram showing the relationship between the “rising period” of the sustain pulse and the reactive power in the first embodiment of the present invention. In FIG. 17, the vertical axis represents the relative ratio of reactive power, and the horizontal axis represents the length of the “rising period”. Note that the unit (%) on the vertical axis is obtained by converting the reactive power (W) detection result into a relative ratio with a predetermined value being 100%, and the larger the value, the larger the reactive power.

  As shown in FIG. 17, the reactive power varies depending on the length of the “rise period”. The shorter the “rise period”, the greater the reactive power. This is presumably because the ratio of the power recovered by the power recovery circuit used for the occurrence of discharge decreases by shortening the “rise period”.

  FIG. 18 is a characteristic diagram showing the relationship between the “rising period” of the sustain pulse and the sustain pulse voltage Vs in the first embodiment of the present invention. In FIG. 18, the vertical axis represents the sustain pulse voltage Vs necessary for generating a stable sustain discharge, and the horizontal axis represents the length of the “rising period”.

  As shown in FIG. 18, the voltage value of the sustain pulse voltage Vs necessary for generating a stable sustain discharge varies depending on the length of the “rising period”, and the longer the “rising period”, the more necessary sustain pulse voltage. Vs is increasing. This is because the “rising period” becomes longer, so that a strong discharge as in the case of generating a sustain discharge in the clamp circuit cannot be generated, and the wall charge accumulated in the discharge cell is reduced accordingly. it is conceivable that.

  From these facts, by appropriately controlling the “rise period”, it is possible to adjust the sustain pulse voltage Vs necessary for stably generating items that affect power consumption, that is, light emission efficiency, light emission luminance, reactive power, and sustain discharge. It was confirmed that improvements could be made for each. In addition, it was confirmed that the “rise period” for optimizing the improvement effect does not necessarily match in each item, and the “rise period” may be set according to the item to be emphasized.

  Since the relationship between each effect described above and the length of the “rise period” varies depending on the resonance period, it is desirable that the length of the “rise period” is optimally set according to the resonance period.

  Next, the all-cell lighting rate and the partial lighting rate will be described.

  As described above, the frequency of generating the “second overlap period” and the length of the “rise period” are optimally set according to the panel characteristics and the like, thereby reducing the effect of reducing discharge variation and power consumption. The effect to reduce can be acquired. However, the range considered to be optimal also changes depending on the lighting rate of the discharge cells. This is because the output impedance of the power recovery circuit is larger than the output impedance of the clamp circuit, so the ratio of the discharge cells to be lit (hereinafter also referred to as “lighting cells”) changes, and the “rise period” This is because the waveform shape changes.

  Therefore, each setting can be optimized by detecting the lighting rate and performing control according to the detection result. And in this Embodiment, the all-cell lighting rate which shows the ratio of the lighting cell with respect to all the discharge cells of the panel 10 is detected, and it uses for each control. However, even with the same all-cell lighting rate, the number of lighting cells generated on a pair of display electrodes greatly varies and the driving load also varies greatly depending on the pattern of the image to be displayed, that is, the distribution of the lighting cells. .

  FIG. 19 is a schematic diagram for explaining symbols having the same all-cell lighting rate and different distributions of lighting cells. In FIG. 19, the display electrode pair 24 is arranged extending in the left-right direction in the drawing, as in FIG. In FIG. 19, the hatched portion represents the distribution of non-lighting cells that do not generate a sustain discharge, and the white portion without hatching represents the distribution of lighted cells.

  For example, as shown in the upper part of FIG. 19, when the lighting cells are distributed in a vertically extending shape (in the drawing), the number of lighting cells generated on one display electrode pair is relatively small, The driving load on the pair of display electrodes is also small. However, even with the same all-cell lighting rate, as shown in the lower part of FIG. 19, when the lighting cells are distributed in a shape extending left and right (in the drawing), they are on a certain pair of display electrodes. The number of generated lighting cells increases, and the driving load of the pair of display electrodes increases.

  As described above, even with the same all-cell lighting rate, a difference in the partial driving load occurs depending on the design, and depending on the design, a pair of display electrodes having a large driving load may occur.

  Therefore, in this embodiment, the display area of the panel is divided into a plurality of areas in addition to the all-cell lighting ratio, and the lighting ratio in each area is detected as a partial lighting ratio.

  FIG. 20 is a schematic diagram illustrating an example of a region for detecting a partial lighting rate according to Embodiment 1 of the present invention.

  In the present embodiment, as shown in FIG. 20, the display area of panel 10 is provided so that the boundary thereof is parallel to display electrode pairs 24, and the number of display electrode pairs belonging to each area is made as uniform as possible. It is assumed that the area is divided into eight areas. And a lighting rate is detected for every area | region, and it is set as a partial lighting rate. For example, if the number of display electrode pairs is 1080, the panel is divided into areas each having 135 display electrode pairs, and the lighting rate is detected in each area. Thereby, eight partial lighting rates can be detected for each subfield.

  In the present embodiment, the configuration in which the display area of the panel 10 is divided into eight areas has been described. However, this numerical value is merely an example, and depends on the panel characteristics, the specifications of the plasma display device, and the like. And set optimally. In the present embodiment, the same effect as described above can be obtained by dividing the display area of panel 10 into at least two areas and detecting the respective partial lighting rates. Further, the region may be divided according to the specifications of the IC used for driving the display electrode pair. For example, in a plasma display device configured to drive 108 scan electrodes or sustain electrodes with one IC, 108 display electrode pairs are set as one region in accordance with the IC, for example, a panel having 1080 display electrode pairs. May be divided into 10 regions. Alternatively, the number of display electrode pairs and the number of regions may be the same, and the lighting rate may be detected for each display electrode pair.

  In the present embodiment, a plurality of sustain pulses having different lengths of at least one of the “rising period” and the “falling period” are generated, a combination of the generated sustain pulses, and the “second overlap period” Are generated at different frequencies (here, five drive patterns including a first drive pattern, a second drive pattern, a third drive pattern, a fourth drive pattern, and a fifth drive pattern). Then, the maximum value of the detected partial lighting rate is detected for each subfield, and the sustain pulse is generated by switching the drive pattern according to the detected maximum value and the all-cell lighting rate.

  It has been confirmed that if a strong discharge is generated at the rising edge of the sustain pulse, a weak discharge may occur at the falling edge of the sustain pulse. Since this discharge reduces the wall charge formed by the sustain discharge, if the discharge due to this falling occurs, the wall charge may be insufficient and the sustain discharge may be unstable, which is not preferable. It was experimentally confirmed that the weak discharge at the fall can be reduced by increasing the time taken for the fall. On the other hand, the intensity of the discharge generated at the rising edge of the sustain pulse varies depending on the driving load of the panel and the waveform shape at the rising edge of the sustain pulse. Therefore, in this embodiment, the “falling period” is set in consideration of the detected all-cell lighting rate, the maximum value of the partial lighting rate, the “rising period” of the sustain pulse to be generated, and the like.

  FIG. 21 is a diagram showing an example of the relationship between the maximum value of the all-cell lighting rate and the partial lighting rate and the switching of the drive pattern in the first embodiment of the present invention.

  In this embodiment, as shown in FIG. 21, a sustain pulse is generated in the first drive pattern in a subfield having a low all-cell lighting rate (here, less than 15%) regardless of the maximum partial lighting rate. Let This first drive pattern is a drive pattern for the purpose of improving the light emission luminance, thereby improving the light emission luminance when the all-cell lighting rate is low, that is, when the driving load of the panel 10 is generally low. To improve image display quality.

  Further, in a subfield having a high all-cell lighting rate (here, 60% or more), a sustain pulse is generated in the second drive pattern regardless of the maximum value of the partial lighting rate. This second drive pattern is a drive pattern for the purpose of reducing reactive power and improving light emission efficiency. As a result, when all-cell lighting rate is high, that is, when the driving load of the panel 10 is high as a whole, reactive power is reduced. Reduce power consumption by improving luminous efficiency.

  Then, in the subfield where the total cell lighting rate is within a predetermined range (here, 15% or more and less than 60%), the driving pattern is switched according to the maximum value of the partial lighting rate. Specifically, if the total cell lighting rate is within a predetermined range (here, 15% or more and less than 60%) and the maximum value of the partial lighting rate is high (here, 60% or more), the third A sustain pulse is generated with a drive pattern. This third drive pattern is a drive pattern for the purpose of improving the light emission luminance, reducing reactive power, and improving the light emission efficiency, whereby the total cell lighting rate is within a predetermined range and the maximum value of the partial lighting rate is When it is high, that is, when the driving load of the panel 10 is partially high, the image display quality is improved by improving the light emission luminance, and the power consumption is reduced by reducing the reactive power and the light emission efficiency.

  If the total cell lighting rate is within a predetermined range (here, 15% or more and less than 60%) and the maximum value of the partial lighting rate is low (here, less than 60%), Switch the drive pattern. Specifically, if the total cell lighting rate is the lower one in the predetermined range (here, 15% or more and less than 30%) and the maximum value of the partial lighting rate is low (here, less than 60%). A sustain pulse is generated in the fourth drive pattern. This fourth drive pattern is a drive pattern for the purpose of maximizing the effect of reducing reactive power and improving light emission efficiency. As a result, all-cell lighting that is considered to have a relatively high display frequency in normal video display When displaying an image having a slightly lower rate and a lower partial lighting rate maximum value, the power consumption can be reduced by reducing reactive power and improving light emission efficiency.

  Further, if the total cell lighting rate is higher within a predetermined range (here, 30% or more and less than 60%) and the maximum value of the partial lighting rate is low (here, less than 60%), the fifth A sustain pulse is generated with a drive pattern. This fifth drive pattern is a drive pattern for the purpose of enhancing the effect of reducing reactive power and improving the light emission efficiency. With this, when the total cell lighting rate is slightly high and the maximum value of the partial lighting rate is low, that is, When the third drive pattern is applied to the region where the driving load is high in the panel 10, the reactive power is reduced and the power consumption is reduced by improving the light emission efficiency when the driving load is slightly high as a whole.

  Next, details of each drive pattern will be described. FIG. 22 is a schematic diagram showing a first drive pattern in the first embodiment of the present invention, FIG. 23 is a schematic diagram showing a second drive pattern in the first embodiment of the present invention, and FIG. FIG. 25 is a schematic diagram showing a third drive pattern in the first embodiment of the present invention, FIG. 25 is a schematic diagram showing a fourth drive pattern in the first embodiment of the present invention, and FIG. 26 is an implementation of the present invention. It is the schematic which shows the 5th drive pattern in the form 1. In FIG. 22, FIG. 23, FIG. 24, FIG. 25, and FIG. 26, the figure shown in the upper part of the drawing shows the schematic waveform shape of the sustain pulse to be generated. Is the length of each of “rise period”, “fall period”, “first overlap period”, “second overlap period”, and “first overlap period”, “second overlap period” It is the figure which showed the generating location. In FIG. 22, FIG. 23, FIG. 24, FIG. 25, and FIG. 26, it is assumed that the pulse width of each sustain pulse is 2.7 μsec.

  In this embodiment, as shown in FIGS. 22, 23, 24, 25, and 26, one pattern composed of eight sustain pulses is repeatedly generated. In all drive patterns, the resonance period in the power recovery circuit is set to 2000 nsec.

  In the first drive pattern in the present embodiment, as shown in FIG. 22, the first sustain pulse (A in the drawing) has a “rise period” of 700 nsec and a “fall period” of 1150 nsec. The sustain pulses (B in the drawing) are 1100 nsec and 900 nsec, respectively, the third sustain pulse (C in the drawing) is 700 nsec and 900 nsec, respectively, and the fourth sustain pulse (D in the drawing) is 600 nsec. 900 nsec, the fifth sustain pulse (E in the drawing) is 600 nsec and 1000 nsec, respectively, the sixth sustain pulse (F in the drawing), the seventh sustain pulse (G in the drawing), and the eighth The sustain pulses (H in the drawing) are 700 nsec and 900 nsec, respectively. Then, a “second overlap period” (here, 850 nsec) is provided between the falling edge of the first sustain pulse (A in the drawing) and the rising edge of the second sustain pulse (B in the drawing), Other than that, the “first overlap period” (here, 200 nsec) is set. Further, by performing the driving by the first driving pattern, it was possible to improve the light emission luminance by about 9.6% as compared with the conventional driving. Here, the conventional driving means driving with a sustain pulse waveform having an overlap period of 0 nsec, a resonance period of 2000 nsec, a pulse width of 2.7 μsec, a “rise period” of 800 nsec, and a “fall period” of 900 nsec.

  In the second drive pattern in the present embodiment, as shown in FIG. 23, the first sustain pulse (A in the drawing) has a “rise period” of 600 nsec and a “fall period” of 1100 nsec. The first sustain pulse (B in the drawing) is 1000 nsec and 900 nsec, respectively, the third sustain pulse (C in the drawing) is 750 nsec and 900 nsec, and the fourth sustain pulse (D in the drawing) is respectively Are 600 nsec and 900 nsec, the fifth sustain pulse (E in the drawing), the sixth sustain pulse (F in the drawing), the seventh sustain pulse (G in the drawing), and the eighth sustain pulse (drawing). H) is 750 nsec and 900 nsec, respectively. Then, a “second overlap period” (here, 850 nsec) is provided between the falling edge of the first sustain pulse (A in the drawing) and the rising edge of the second sustain pulse (B in the drawing), Other than that, the “first overlap period” (here, 200 nsec) is set. Then, by driving with the second drive pattern, the light emission luminance is improved by about 1.7%, the reactive power is reduced by about 1.3%, and the light emission efficiency is about 2.% as compared with the conventional drive. It was possible to improve 9%.

  In the third drive pattern of the present embodiment, as shown in FIG. 24, the first sustain pulse (A in the drawing) has a “rise period” of 1000 nsec and a “fall period” of 1050 nsec. The first sustain pulse (B in the drawing) is 1000 nsec and 900 nsec, respectively, the third sustain pulse (C in the drawing) is 800 nsec and 900 nsec, and the fourth sustain pulse (D in the drawing) is respectively Are 650 nsec and 900 nsec, the fifth sustain pulse (E in the drawing), the sixth sustain pulse (F in the drawing), and the seventh sustain pulse (G in the drawing) are 800 nsec and 900 nsec, respectively. The first sustain pulses (H in the drawing) are 800 nsec and 1050 nsec, respectively. Then, between the falling edge of the first sustain pulse (A in the drawing) and the rising edge of the second sustain pulse (B in the drawing), and the falling edge of the eighth sustain pulse (H in the drawing) A “second overlap period” (here, 850 nsec) is provided between the rising edge of the first sustain pulse (A in the drawing), and “the first overlap period” (here, 200 nsec) is set otherwise. Yes. Then, by driving with the third drive pattern, the light emission luminance is improved by about 3%, the reactive power is reduced by about 4.2%, and the light emission efficiency is about 6.8% compared with the conventional drive. I was able to improve.

  In the fourth drive pattern of the present embodiment, as shown in FIG. 25, the first sustain pulse (A in the drawing) has a “rise period” of 850 nsec and a “fall period” of 900 nsec. The first sustain pulse (B in the drawing), the third sustain pulse (C in the drawing) are 850 nsec and 900 nsec, respectively, and the fourth sustain pulse (D in the drawing) is 550 nsec and 900 nsec, respectively. The first sustain pulse (E in the drawing) is set to 550 nsec and 1000 nsec, the sixth sustain pulse (F in the drawing) and the seventh sustain pulse (G in the drawing) are set to 850 nsec and 900 nsec, respectively. The first sustain pulses (H in the drawing) are 550 nsec and 1000 nsec, respectively. In this drive pattern, the “second overlap period” is not provided, and all of them are set to the “first overlap period” (here, 0 nsec). Then, by performing the driving by the fourth driving pattern, it was possible to reduce the reactive power by about 6.3% and to improve the light emission efficiency by about 11.1% as compared with the conventional driving.

  In the fifth drive pattern according to the present embodiment, as shown in FIG. 26, the first sustain pulse (A in the drawing) has a “rise period” of 850 nsec and a “fall period” of 900 nsec. The third sustain pulse (B in the drawing) is 800 nsec and 900 nsec, respectively, and the third sustain pulse (C in the drawing) is 850 nsec and 900 nsec, respectively. The fourth sustain pulse (D in the drawing), 5 The first sustain pulse (E in the drawing) is 550 nsec and 900 nsec, the sixth sustain pulse (F in the drawing) is 800 nsec and 900 nsec, and the seventh sustain pulse (G in the drawing) is respectively Are 850 nsec and 900 nsec, and the eighth sustain pulse (H in the drawing) is 550 nsec and 90 nsec, respectively. It is set to nsec. In this drive pattern as well, the “second overlap period” is not provided, and all are set to the “first overlap period” (here, 0 nsec). Then, by performing the driving by the fifth driving pattern, it was possible to reduce the reactive power by about 4.5% and improve the light emission efficiency by about 8.2% as compared with the conventional driving.

  And by switching these five driving patterns according to the maximum values of the all-cell lighting rate and the partial lighting rate, the panel 10 is driven, and depending on the pattern of the display image, Thus, the effect of reducing power consumption by about 10W to 30W could be confirmed. In addition, it was confirmed that the image display quality was improved by the effect of reducing the variation in discharge.

  In the present embodiment, the “rising period” of the sustain pulse constituting the “second overlap period” is generated so that the two forced discharges generated by the “second overlap period” are generated more stably. ”And“ falling period ”are set longer than others.

  Further, in the present embodiment, a sustain pulse having a gradual fall is generated in a drive pattern used in a subfield that is considered to have a relatively small drive load and a relatively strong discharge. Specifically, in the first drive pattern and the fourth drive pattern, the fifth sustain pulse (E in the drawing) falls relatively slowly, and in the fourth drive pattern, the eighth drive pattern. The “falling period” is set so that the falling of the sustain pulse (H in the drawing) also becomes relatively gradual. This is because, in the first drive pattern and the fourth drive pattern, strong discharge may continuously occur between the fourth sustain pulse (D in the drawing) and the fifth sustain pulse (E in the drawing). This is because, in the fourth drive pattern, strong discharge may occur even with the eighth sustain pulse (H in the drawing). As a result, it is possible to prevent a weak discharge that may occur at the falling edge of the sustain pulse, and to stably generate the subsequent sustain discharge.

  Further, in the present embodiment, the “second overlap period” is not provided in the fourth drive pattern and the fifth drive pattern, but this is because all the overlap periods are set to the “first overlap period”. This is because, if the partial lighting rate is low, the driving load as seen from the sustain pulse generation circuit is reduced, the variation in discharge is reduced, and stable sustain discharge can be performed. Further, by setting all the overlapping periods to the “first overlapping period”, the light emission efficiency can be increased and the power consumption can be reduced.

  In the present embodiment, the “second overlap period” is provided although the all-cell lighting rate is low in the first drive pattern. This is due to the following reason. The first drive pattern is a drive pattern for the purpose of improving the light emission luminance. Therefore, a strong sustain discharge is likely to occur, and since the driving load is sufficiently small due to a low all-cell lighting rate, a stronger discharge is achieved. Is likely to occur. In the panel 10 having the ABBA electrode structure, when a strong discharge is generated, the wall charge variation is likely to increase, and as a result, there is a fear that the discharge variation occurs. However, by providing the “second overlap period” in the first drive pattern, it is possible to prevent this discharge variation.

  In the present embodiment, the configuration in which one pattern composed of eight sustain pulses is repeatedly generated has been described. However, in the sustain period in which the total number of sustain pulses is less than 8, all the sustain pulses have the same waveform. The shape may be used, or may be arbitrarily set according to the specifications of the plasma display device.

  The configuration of each drive pattern shown here is merely an example, and may be set optimally as appropriate. Further, the present invention is not limited to an example in which one sustain pattern is configured by eight sustain pulses, and one pattern may be configured by more sustain pulses or fewer sustain pulses.

  Next, generation of the drive voltage waveform in the sustain period will be described. FIG. 27 is a timing chart for explaining operations of sustain pulse generating circuit 50 and sustain pulse generating circuit 60 in the first embodiment of the present invention. Here, one repetition period of the sustain pulse (hereinafter abbreviated as “sustain period”) is divided into six periods indicated by T1 to T6, and each period will be described.

  In the following description, the operation for conducting the switching element is expressed as ON and the operation for blocking is expressed as OFF. In the drawing, the signal for turning on the switching element is expressed as “ON”, and the signal for turning off is expressed as “OFF”. In FIG. 27, the positive waveform is used for explanation, but the present invention is not limited to this. For example, although the embodiment in the negative waveform is omitted, the expression “rising” in the positive waveform in the following description is replaced with “falling” in the negative waveform. The same effect can be obtained even with this waveform.

(Period T1)
At time t1, switching element Q12 is turned on. Then, the charges on the scan electrodes SC1 to SCn side start to flow to the capacitor C10 through the inductor L10, the diode D12, and the switching element Q12, and the voltage on the scan electrodes SC1 to SCn starts to decrease. Since inductor L10 and interelectrode capacitance Cp form a resonance circuit, the voltage of scan electrodes SC1 to SCn drops to near 0 (V) at time t2b after the lapse of half the resonance period. However, the voltage of scan electrodes SC1 to SCn does not drop to 0 (V) due to power loss due to the resistance component of the resonance circuit. Then, switching element Q14 is turned on at time t2b. Then, since scan electrodes SC1 to SCn are directly grounded through switching element Q14, the voltages of scan electrodes SC1 to SCn are clamped to 0 (V).

  During this period, switching element Q24 is kept on, and sustain electrodes SU1 to SUn are clamped to 0 (V).

(Period T2)
Then, switching element Q14 is turned on at time t2b. Then, scan electrodes SC1 to SCn are directly grounded through switching element Q14, so that the voltages of scan electrodes SC1 to SCn are clamped to 0 (V) which is the ground potential.

  In the present embodiment, switching element Q21 is turned on at time t2a that is earlier than time t2b by a predetermined time. Thus, in the present embodiment, an overlapping period in which the period T1 and the period T2 overlap is provided by turning on the switching element Q21 at the time t2a that is earlier than the time t2b by a predetermined time. As an example, this predetermined time is set to 850 nsec when the overlapping period is set to “second overlapping period” (for example, 850 nsec), and 0 nsec is set to set the overlapping period to “first overlapping period” (for example, 0 nsec), that is, The time t2a and the time t2b are set to substantially the same time.

  Since the inductor L20 and the interelectrode capacitance Cp form a resonance circuit by turning on the switching element Q21, the sustain electrodes SU1 to SUn are passed from the capacitor C20 for power recovery through the switching element Q21, the diode D21, and the inductor L20. Current starts to flow, and the voltages of sustain electrodes SU1 to SUn begin to rise. Since the resonance period of inductor L20 and interelectrode capacitance Cp is set to 2000 nsec, the voltage of sustain electrodes SU1 to SUn rises to around voltage Vs after 1000 nsec from time t2a. However, it does not increase to the voltage Vs due to the influence of the output impedance of the drive circuit and the drive load. In this embodiment, the period T2 from time t2a to time t3, that is, the rise time of the sustain pulse using the power recovery circuit 61 is set to 1050 nsec.

(Period T3)
At time t3, the switching element Q23 is turned on. Then, since sustain electrodes SU1 to SUn are directly connected to power supply VS through switching element Q23, the voltage of sustain electrodes SU1 to SUn is clamped to voltage Vs and forcibly rises to voltage Vs. In this period T3, the voltages of the sustain electrodes SU1 to SUn are maintained at the voltage Vs.

(Period T4 to T6)
The sustain pulse applied to scan electrodes SC1 to SCn and the sustain pulse applied to sustain electrodes SU1 to SUn have the same waveform, and the operation from period T4 to period T6 scans the operation from period T1 to period T3. Since this is equivalent to the operation of driving the electrodes SC1 to SCn and the sustain electrodes SU1 to SUn, the description thereof will be omitted.

  In this embodiment, the period T1 and the period T4 are set as the “falling period”, and the period T2 and the period T5 are set as the “rise period”. And the “falling period” is controlled.

  The switching element Q12 may be turned off after time t2b and before time t5a, and the switching element Q21 may be turned off after time t3 and before time t4. Further, the switching element Q22 may be turned off by the next time t2a after the time t5b, and the switching element Q11 may be turned off by the next time t1 after the time t6. In order to lower the output impedance of sustain pulse generating circuit 50 and sustain pulse generating circuit 60, switching element Q24 is preferably turned off immediately before time t2a, switching element Q13 is preferably turned off immediately before time t1, and switching element Q14 is turned off at time. It is desirable that the switching element Q23 is turned off immediately before time t4 just before t5a.

  In the sustain period, the operations in the above periods T1 to T6 are repeated according to the required number of pulses. In this way, the sustain pulse voltage that shifts from the base potential of 0 (V) to the voltage Vs is alternately applied to each of the display electrode pairs 24 to cause the discharge cells to sustain discharge.

  As described above, in the present embodiment, a plurality of sustain pulses having different lengths of at least one of the “rising period” and the “falling period” are generated, a combination of sustain pulses to be generated, and “second” A plurality of (here, five) drive patterns having different occurrence frequencies of “overlapping periods” are generated. Then, the sustain pulse is generated by switching the drive pattern in accordance with the detected all-cell lighting rate and the maximum value of the partial lighting rate. As a result, it is possible to realize driving that suppresses variations in discharge while reducing power consumption, and to improve image display quality of the panel.

(Embodiment 2)
In the first embodiment, the configuration in which the maximum values of the all-cell lighting rate and the partial lighting rate are detected and a plurality of drive patterns are switched has been described. At this time, if the detected all-cell lighting rate frequently fluctuates across the lighting rate threshold value, or the maximum value of the detected partial lighting rate fluctuates frequently across the maximum value threshold, There is a risk of frequent switching of drive patterns.

  As described above, each drive pattern in the present embodiment is a sustain pulse pattern generated according to a desired effect, such as one intended to improve light emission luminance or one intended to reduce reactive power. It is changing. For this reason, there is a case where the luminance of the display image changes due to the switching of the drive pattern. However, when a still image or a moving image with a slow motion is displayed, it is desirable that the luminance change is easily noticeable and the luminance change is as small as possible.

  Therefore, in the present embodiment, a hysteresis characteristic is provided between the drive patterns to reduce the occurrence of frequent switching of the drive patterns.

  In the present invention, as described in the first embodiment, the drive pattern is switched with two parameters of the total cell lighting rate and the maximum value of the partial lighting rate. If each drive pattern is arranged in a row, one drive pattern is adjacent to a plurality of different drive patterns. For example, as shown in FIG. 21, the third drive pattern is adjacent to any of the first drive pattern, the second drive pattern, the fourth drive pattern, and the fifth drive pattern.

  Therefore, merely providing a one-dimensional hysteresis characteristic between two different drive patterns does not correspond to a configuration in which each drive pattern is arranged on a plane having two parameters as two axes as in the present invention. .

  Therefore, in the present embodiment, when each drive pattern is arranged on the above-described plane, a sustain pulse is generated by providing a two-dimensional hysteresis characteristic between adjacent drive patterns. In the following description, a region where hysteresis characteristics are set on the above-described plane is referred to as a “hysteresis region”.

  FIG. 28 is a schematic diagram showing an example of each drive pattern and hysteresis region arranged on a plane having two axes of two parameters of the total cell lighting rate and the maximum value of the partial lighting rate in Embodiment 2 of the present invention. It is. In FIG. 28, as in FIG. 21, the vertical axis represents the total cell lighting rate, and the horizontal axis represents the maximum partial lighting rate. In addition, the hysteresis region is represented by diagonal lines, the threshold value having a larger value in the hysteresis region is represented by a solid line, and the threshold value having a smaller value is represented by a broken line. In addition, since each of the first to fifth drive patterns shown in FIG. 28 is the same as the drive pattern having the same name described in the first embodiment, detailed description thereof is omitted here.

  In the present embodiment, as shown in FIG. 28, the region where the total cell lighting rate is less than 14% is set as the first drive pattern regardless of the fluctuations in the maximum values of the total cell lighting rate and the partial lighting rate. Similarly, a region having an all-cell lighting rate of 61% or more is set as the second drive pattern. Similarly, the region where the total cell lighting rate is 16% or more and less than 59% and the partial lighting rate is 61% or more is the third drive pattern. Similarly, a region in which the total cell lighting rate is 16% or more and less than 29% and the partial lighting rate is less than 59% is the fourth drive pattern. Similarly, a region where the total cell lighting rate is 31% or more and less than 59% and the partial lighting rate is less than the maximum value 59% is set as the fifth drive pattern. Then, as indicated by hatching in the drawing, a hysteresis region is provided two-dimensionally between adjacent drive patterns.

  Specifically, hysteresis characteristics with respect to fluctuations in the all-cell lighting rate are provided between the first drive pattern and the third drive pattern and between the first drive pattern and the fourth drive pattern. More specifically, in the all-cell lighting rate detection circuit 46, a lighting rate threshold value used when switching from the first driving pattern to the third driving pattern or the fourth driving pattern occurs due to an increase in the all-cell lighting rate. (Here, 16%) is a lighting rate threshold value (14% here) used when switching from the third driving pattern or the fourth driving pattern to the first driving pattern occurs due to the decrease in the lighting rate of all cells. ) To provide a hysteresis characteristic.

  Similarly, hysteresis characteristics with respect to fluctuations in the all-cell lighting rate are provided between the second drive pattern and the fifth drive pattern and between the second drive pattern and the third drive pattern. Specifically, in the all-cell lighting rate detection circuit 46, the lighting rate threshold value (when the switching from the third driving pattern or the fifth driving pattern to the second driving pattern occurs due to the increase in the all-cell lighting rate) 61%) is a lighting rate threshold value (59% here) used when switching from the second driving pattern to the third driving pattern or the fifth driving pattern occurs due to a decrease in the lighting rate of all cells. A hysteresis characteristic is provided by setting a larger value.

  Similarly, a hysteresis characteristic is provided between the fourth drive pattern and the fifth drive pattern with respect to fluctuations in the all-cell lighting rate. Specifically, in the all-cell lighting rate detection circuit 46, a lighting rate threshold value (here, 31%) used when switching from the fourth drive pattern to the fifth drive pattern occurs due to an increase in the all-cell lighting rate. ) Is set to a value larger than the lighting rate threshold value (29% in this case) used when switching from the fifth driving pattern to the fourth driving pattern occurs due to a decrease in the lighting rate of all cells. Is provided.

  In addition, hysteresis characteristics with respect to fluctuations in the maximum value of the partial lighting rate are provided between the third drive pattern and the fourth drive pattern, and between the third drive pattern and the fifth drive pattern. Specifically, in the maximum value detection circuit 48, the maximum threshold value (when the switching from the fourth drive pattern or the fifth drive pattern to the third drive pattern occurs due to the increase in the maximum value of the partial lighting rate ( Here, 61%) is a maximum value threshold value (here, 59%) used when switching from the third drive pattern to the fourth drive pattern or the fifth drive pattern occurs due to a decrease in the maximum value of the partial lighting rate. %) To provide a hysteresis characteristic.

  Next, how the drive patterns are switched due to fluctuations in the maximum values of the all-cell lighting rate and the partial lighting rate when the hysteresis region is set as described above will be described with a specific example. FIG. 29 is a schematic diagram showing a state in which at least one of the maximum value of the total cell lighting rate or the partial lighting rate varies on the plane shown in FIG.

  Note that A, B, C, and D shown in FIG. 29 are examples of the maximum values of the detected all-cell lighting rate and partial lighting rate displayed on the plane shown in FIG. An example of the fluctuation | variation of the maximum value of a rate and a partial lighting rate is shown. In addition, when the maximum value of the partial lighting rate is set as the X coordinate, the whole cell lighting rate is set as the Y coordinate, and the coordinates are displayed as (the maximum value of the partial lighting rate, the total cell lighting rate), It is assumed that A (61.5, 58.5), B (61.5, 60.5), C (59.5, 60.5), and D (58.5, 60.5). It is assumed that fluctuations occur in the order of A, B, C, and D.

  As described above, the region where the total cell lighting rate is 16% or more and less than 59% and the maximum value of the partial lighting rate is 61% or more regardless of fluctuations in the maximum values of the all-cell lighting rate and the partial lighting rate. Therefore, A is the third drive pattern.

  Subsequently, B is arranged in the hysteresis region set between the second drive pattern and the third drive pattern, but since the immediately preceding A is the third drive pattern, the second drive pattern and the third drive are arranged. The lighting rate threshold between the patterns is 61%, and B is the third drive pattern.

  Subsequently, C is arranged in a hysteresis region set between the three drive patterns of the second drive pattern, the third drive pattern, and the fifth drive pattern, but B immediately before is the third drive pattern. The lighting rate threshold value remains 61%, and the maximum value threshold value between the third drive pattern and the fifth drive pattern is 59%, and C becomes the third drive pattern.

  Subsequently, D is arranged in a hysteresis region set between the second drive pattern and the fifth drive pattern. At this time, if C immediately before is either the second drive pattern or the fifth drive pattern, the lighting rate threshold value between the second drive pattern and the fifth drive pattern is determined according to the C drive pattern. Then, the driving pattern of D is determined. However, since C is the third drive pattern here, the lighting rate threshold between the second drive pattern and the fifth drive pattern cannot be determined as it is, and the drive pattern of D is determined. Can not do it.

  In this way, in a configuration in which a hysteresis region is provided two-dimensionally on a plane having two parameters as two axes, the relationship between the immediately preceding state and the current determination is interrupted, and the current determination is indefinite. May be. Specifically, from a region where the sustain pulse is generated in one certain drive pattern (for example, the third drive pattern), between two or more other drive patterns (for example, the second and fifth drive patterns). Such a state occurs when a fluctuation to the hysteresis region provided between the two occurs.

  Therefore, in the present embodiment, a change occurs from a region where a sustain pulse is generated with a certain drive pattern to a hysteresis region provided between two or more other drive patterns, and the current threshold is reached. When the value cannot be determined, the threshold value is determined according to the state immediately before it.

  For example, since the lighting rate threshold value 61% is used in the determination of C here, the lighting rate threshold value between the second drive pattern and the fifth drive pattern is also set to 61% in the determination of D. . Thereby, the drive pattern of D can be made into the 5th drive pattern.

  Thus, in the present embodiment, when each drive pattern is arranged on a plane having two axes of the two parameters of the total cell lighting rate and the maximum value of the partial lighting rate, between the adjacent driving patterns, The sustain pulse is generated by providing two-dimensional hysteresis characteristics. As a result, it is possible to reduce the frequent change of the drive pattern by reducing the frequent fluctuation of the maximum value of the all-cell lighting rate and the partial lighting rate across the threshold value, and the image The display quality can be further improved. Furthermore, a change in parameters causes a change from a region where a sustain pulse is generated in one drive pattern to a hysteresis region provided between two or more other drive patterns. When the threshold value cannot be determined, the threshold value is determined according to the state immediately before the threshold value. This makes it possible to realize a stable operation.

(Embodiment 3)
In the second embodiment, an example of a configuration for realizing stable operation when a situation in which the current threshold value cannot be determined has occurred, but a configuration other than the configuration shown in the second embodiment However, it is possible to realize a stable operation. In this embodiment, an example of this configuration will be described.

  FIG. 30 is a schematic diagram showing an example of each drive pattern and hysteresis region arranged on a plane having two axes of two parameters of the total cell lighting rate and the maximum value of the partial lighting rate in Embodiment 3 of the present invention. It is. In this embodiment, in addition to the threshold value described above, a new auxiliary threshold value is used. In FIG. 30, the threshold value having the larger value is indicated by a solid line in the hysteresis region. The threshold value having the smaller value is represented by a broken line, and the auxiliary threshold value to be newly used is represented by a dashed line.

  In the present embodiment, due to a change in parameters, a change occurs from a region where a sustain pulse is generated in one drive pattern to a hysteresis region provided between two or more other drive patterns, Thus, when the current threshold value cannot be determined, the determination is made using the auxiliary threshold value provided in the hysteresis region.

  Specifically, in the hysteresis region between the first drive pattern and the third drive pattern and between the first drive pattern and the fourth drive pattern, the larger lighting rate threshold (here, 16 %) And a smaller lighting rate threshold value (here 14%), an auxiliary lighting rate threshold value (here 15%) is provided.

  Similarly, between the second drive pattern and the fifth drive pattern and between the second drive pattern and the third drive pattern, the larger lighting rate threshold value in this hysteresis region (here, 61%). ) And the smaller lighting rate threshold value (here, 59%), an auxiliary lighting rate threshold value (here, 60%) is provided.

  Similarly, between the fourth drive pattern and the fifth drive pattern, the larger lighting rate threshold value (here, 31%) and the smaller lighting rate threshold value (here, in this hysteresis region) 29%) is provided with an auxiliary lighting rate threshold value (here, 30%).

  Similarly, between the third drive pattern and the fourth drive pattern, and between the third drive pattern and the fifth drive pattern, the larger maximum threshold value in this hysteresis region (here, 61%). ) And the smaller maximum threshold value (here 59%), an auxiliary maximum value threshold value (here 60%) is provided.

  Then, a change occurs from a region where a sustain pulse is generated in one drive pattern to a hysteresis region where hysteresis characteristics are set between two or more other drive patterns, and the hysteresis region If the hysteresis characteristic is set in response to the change in the cell lighting rate, the all-cell lighting rate detection circuit 46 compares the auxiliary lighting rate threshold value in the hysteresis region with the all-cell lighting rate. The result is output.

  Similarly, if the hysteresis region is a region where hysteresis characteristics are set with respect to the change in the maximum value of the partial lighting rate, the maximum value detection circuit 48 determines the auxiliary maximum value threshold value and the partial lighting in the hysteresis region. The comparison is made with the maximum value of the rate and the result is output.

  Similarly, if the hysteresis region is a region in which hysteresis characteristics are set for both the change in the all-cell lighting rate and the change in the maximum value of the partial lighting rate, the all-cell lighting rate detection circuit 46 and the maximum value are set. The detection circuit 48 compares the auxiliary lighting rate threshold value with the all-cell lighting rate and the auxiliary maximum value threshold value with the maximum partial lighting rate based on a predetermined priority order in the hysteresis region. And the result is output.

  Next, an example of the operation when the hysteresis characteristic is set as described above will be described with reference to a specific example. FIG. 31 is a schematic diagram showing a state in which at least one of the maximum value of the total cell lighting rate or the partial lighting rate varies on the plane shown in FIG.

  Note that A, B, C, and D shown in FIG. 31 are the same as those of the same name described in FIG. 29, and E is E (58.5, 59.5). Also, the operation accompanying the change from A to B and from B to C is the same as the description in FIG. 29, and the description is omitted here.

  D is arranged in the hysteresis region set between the second drive pattern and the fifth drive pattern, but as described in FIG. 29, C immediately before is either the second drive pattern or the fifth drive pattern. However, the lighting rate threshold value between the second drive pattern and the fifth drive pattern cannot be determined, and the D drive pattern cannot be determined.

  In such a case, in the present embodiment, the auxiliary lighting rate threshold (here, 60%) is compared with the D total cell lighting rate (60.5%), and based on the result of the comparison. The driving pattern of D is determined (here, determined as the second driving pattern).

  Similarly, when a change from C to E occurs, the auxiliary lighting rate threshold (60%) is compared with the E all-cells lighting rate (59.5%). First, the drive pattern for E is determined (here, determined as the fifth drive pattern).

  Further, in the present embodiment, in the hysteresis region in which hysteresis characteristics are set for both the change in the all-cell lighting rate and the change in the maximum value of the partial lighting rate, the comparison is performed based on a predetermined priority order. It is said.

  For example, a hysteresis region having a maximum threshold value of 59% to 61% and a lighting rate threshold value of 14% to 16% (a hysteresis characteristic is set between the first drive pattern, the third drive pattern, and the fourth drive pattern). Area), the auxiliary lighting rate threshold value less than 15% is set as the first drive pattern, the auxiliary lighting rate threshold value of 15% or more and the auxiliary maximum value threshold value less than 60% is set as the fourth drive pattern, and auxiliary lighting is performed. A rate threshold value of 15% or more and an auxiliary maximum value threshold value of 60% or more are set as the third drive pattern.

  Further, a hysteresis region having a maximum threshold value of 59% to 61% and a lighting rate threshold value of 59% to 61% (a hysteresis characteristic is set between the second drive pattern, the third drive pattern, and the fifth drive pattern). ), The auxiliary lighting rate threshold value of 60% or more is set as the second driving pattern, and the auxiliary lighting rate threshold value of less than 60% and the auxiliary maximum value threshold value of less than 60% is set as the fifth driving pattern. If the ratio threshold value is less than 60% and the auxiliary maximum value threshold value is 60% or more, the third drive pattern is used.

  Further, a hysteresis region having a maximum threshold value of 59% to 61% and a lighting rate threshold value of 29% to 31% (a hysteresis characteristic is set between the third drive pattern, the fourth drive pattern, and the fifth drive pattern). Area), the auxiliary maximum threshold value of 60% or more is set as the third driving pattern, and the auxiliary maximum value threshold value of less than 60% and the auxiliary lighting rate threshold value of less than 30% is set as the fourth driving pattern. The fifth drive pattern is used when the value threshold is less than 60% and the auxiliary lighting rate threshold is 30% or more.

  Thus, in the present embodiment, an auxiliary threshold value is provided in the hysteresis region, and when the current threshold value cannot be determined, a determination is made using the auxiliary threshold value. To do. Thereby, a stable operation similar to that of the second embodiment can be realized.

(Embodiment 4)
In the present embodiment, another example of a configuration for realizing a stable operation when a situation in which the current threshold value cannot be determined occurs will be described.

  FIG. 32 is a schematic diagram showing an example of each drive pattern and hysteresis region arranged on a plane having two axes of two parameters of the total cell lighting rate and the maximum value of the partial lighting rate in Embodiment 4 of the present invention. It is.

  In the present embodiment, due to a change in parameters, a change occurs from a region where a sustain pulse is generated in one drive pattern to a hysteresis region provided between two or more other drive patterns, Thus, when the current threshold value cannot be determined, a drive pattern based on a predetermined priority order is generated.

  In the present embodiment, for example, the fourth drive pattern is the drive pattern with the highest priority, followed by the fifth drive pattern and the third drive pattern, and the priority is lowered, and the first drive pattern and the second drive pattern are the highest. The driving pattern has a low priority.

  Specifically, as shown in FIG. 32, when the current threshold value cannot be determined in the hysteresis region between the first drive pattern and the third drive pattern, based on the above-described priority order, Let the current drive pattern be the third drive pattern. Similarly, in the hysteresis region between the first drive pattern and the fourth drive pattern, the fourth drive pattern is used. Similarly, the fourth drive pattern is set in the hysteresis region between the first drive pattern, the third drive pattern, and the fourth drive pattern. Similarly, in the hysteresis region between the third drive pattern and the fourth drive pattern, the fourth drive pattern is used. Similarly, the fourth drive pattern is used in the hysteresis region between the fourth drive pattern and the fifth drive pattern. Similarly, the fourth drive pattern is used in the hysteresis region between the third drive pattern, the fourth drive pattern, and the fifth drive pattern. Similarly, in the hysteresis region between the third drive pattern and the fifth drive pattern, the fifth drive pattern is used. Similarly, in the hysteresis region between the second drive pattern and the third drive pattern, the third drive pattern is used. Similarly, in the hysteresis region between the second drive pattern and the fifth drive pattern, the fifth drive pattern is used. Similarly, the fifth drive pattern is set in the hysteresis region between the second drive pattern, the third drive pattern, and the fifth drive pattern.

  Thus, in this embodiment, the priority order of the drive patterns to be generated is set in advance, and when the current threshold value cannot be determined, the drive pattern is generated based on the priority order. The configuration. As a result, the same stable operation as in the second and third embodiments can be realized.

  In the second to fourth embodiments, it is desirable to set the interval between the larger threshold value and the smaller threshold value in the hysteresis region to 2% or more.

  The length of the “rise period” and “fall period”, the frequency of occurrence of the “second overlap period”, the “first overlap period”, and the “second overlap period” shown in the embodiment of the present invention ”, Each lighting rate threshold value, maximum value threshold value and the like are set based on the characteristics of a 42-inch panel with 1080 display electrode pairs used in the experiment, It is just an example. Embodiments of the present invention are not limited to these numerical values, and are desirably set optimally in accordance with panel characteristics, plasma display device specifications, and the like. Each of these numerical values is allowed to vary within a range where the above-described effect can be obtained.

  In the embodiment of the present invention, scan electrodes SC1 to SCn are divided into a first scan electrode group and a second scan electrode group, and an address period is set for each of the scan electrodes belonging to the first scan electrode group. The first address period in which the scan pulse is sequentially applied to the first scan period and the second address period in which the scan pulse is sequentially applied to each of the scan electrodes belonging to the second scan electrode group. In at least one of the two address periods, the scan electrodes belonging to the scan electrode group to which the scan pulse is applied are scanned from the second voltage higher than the scan pulse voltage to the scan pulse voltage and again to the second voltage. For the scan electrodes belonging to the scan electrode group to which the pulse is sequentially applied and the scan pulse is not applied, either the third voltage higher than the scan pulse voltage, the second voltage, or the fourth voltage higher than the third voltage. Or It can be applied to a panel driving method by so-called two-phase driving, in which a third voltage is applied while a voltage is applied and at least a scanning pulse voltage is applied to adjacent scanning electrodes. An effect can be obtained.

  In the embodiment of the present invention, the configuration in which the erase ramp waveform voltage is applied to scan electrodes SC1 to SCn has been described. However, the erase ramp waveform voltage may be applied to sustain electrodes SU1 to SUn. Alternatively, an erasing discharge may be generated not by an erasing ramp waveform voltage but by a so-called narrow erasing pulse.

  In the embodiment of the present invention, in the power recovery circuits 51 and 61, the configuration in which one inductor is commonly used for the rise and fall of the sustain pulse has been described. However, the rise of the sustain pulse is performed using a plurality of inductors. Alternatively, different inductors may be used for the falling and falling edges.

  INDUSTRIAL APPLICABILITY The present invention is useful as a plasma display device and a panel driving method capable of stably generating discharge while reducing power consumption even in a panel with a large screen and high definition, and improved image display quality. It is.

The disassembled perspective view which shows the structure of the panel in Embodiment 1 of this invention. Electrode arrangement of the panel Drive voltage waveform diagram applied to each electrode of the panel Circuit block diagram of plasma display device according to Embodiment 1 of the present invention Circuit diagram of sustain pulse generating circuit according to the first embodiment of the present invention Schematic waveform diagram showing an example of a sustain pulse in Embodiment 1 of the present invention Schematic waveform diagram showing an example of sustain pulses and the state of light emission at that time in Embodiment 1 of the present invention Schematic waveform diagram showing another example of sustain pulse in Embodiment 1 of the present invention Schematic waveform diagram showing an example of sustain pulses and the state of light emission at that time in Embodiment 1 of the present invention Schematic waveform diagram showing an example of occurrence of the second overlap period in the first embodiment of the present invention Schematic showing the relationship between the lighting rate and the light emission efficiency when driven by changing the frequency of occurrence of the second overlap period FIG. 5 is a waveform diagram showing the relationship between the sustain pulse rising period and discharge variation in the first embodiment of the present invention; Waveform diagram showing the relationship between the rise period of the sustain pulse and the variation in discharge Waveform diagram showing the relationship between the rise period of the sustain pulse and the variation in discharge Characteristic diagram showing the relationship between the rise period of the sustain pulse and the luminous efficiency A characteristic diagram showing the relationship between the rising period of the sustain pulse and the light emission luminance Characteristic diagram showing the relationship between the rising period of the sustain pulse and reactive power A characteristic diagram showing the relationship between the rising period of the sustain pulse and the sustain pulse voltage Vs Schematic for explaining symbols with the same all-cell lighting rate and different distribution of lighting cells Schematic which shows an example of the area | region which detects the partial lighting rate in Embodiment 1 of this invention. The figure which shows an example of the relationship between the maximum value of the all-cell lighting rate and the partial lighting rate in Embodiment 1 of this invention, and switching of a drive pattern Schematic which shows the 1st drive pattern in Embodiment 1 of this invention. Schematic which shows the 2nd drive pattern in Embodiment 1 of this invention. Schematic which shows the 3rd drive pattern in Embodiment 1 of this invention. Schematic which shows the 4th drive pattern in Embodiment 1 of this invention. Schematic which shows the 5th drive pattern in Embodiment 1 of this invention. Timing chart for explaining operation of sustain pulse generating circuit in the first embodiment of the present invention Schematic which shows an example of each drive pattern and hysteresis area | region arrange | positioned on the plane which uses the two parameters of the total cell lighting rate and the maximum value of a partial lighting rate in Embodiment 2 of this invention as 2 axes | shafts Schematic showing a state when at least one of the maximum value of all-cell lighting rate or partial lighting rate fluctuates on the plane shown in FIG. Schematic which shows an example of each drive pattern and hysteresis area | region arrange | positioned on the plane which uses two parameters of the total cell lighting rate and the maximum value of a partial lighting rate in Embodiment 3 of this invention as 2 axes | shafts Schematic showing a state when at least one of the maximum value of all-cell lighting rate or partial lighting rate fluctuates on the plane shown in FIG. Schematic which shows an example of each drive pattern and a hysteresis area | region arrange | positioned on the plane which uses two parameters of the total cell lighting rate and the maximum value of a partial lighting rate in Embodiment 4 of this invention as 2 axes | shafts

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Plasma display apparatus 10 Panel 21 Front substrate (made of glass) 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 25,33 Dielectric layer 26 Protective layer 31 Back substrate 32 Data electrode 34 Partition 35 Phosphor layer 41 Image signal processing circuit 42 data electrode drive circuit 43 scan electrode drive circuit 44 sustain electrode drive circuit 45 timing generation circuit 46 all-cell lighting rate detection circuit 47 partial lighting rate detection circuit 48 maximum value detection circuit 50, 60 sustain pulse generation circuit 51, 61 power recovery circuit 52, 62 Clamp circuit Q11, Q12, Q13, Q14, Q21, Q22, Q23, Q24, Q26, Q27, Q28, Q29 Switching element C10, C20, C30 Capacitor L10, L20 Inductor D11, D12, D21, D22, D30 Diode

Claims (10)

A plasma display panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode;
A power recovery circuit for causing the sustain pulse to rise or fall by resonating the interelectrode capacitance of the display electrode pair and the inductor, and having an initialization period, an address period, and a sustain period provided within one field period A sustain pulse generating circuit for generating the sustain pulses in the sustain periods of a plurality of subfields and alternately applying the sustain pulses to the display electrode pairs;
An all-cell lighting rate detection circuit for detecting a ratio of discharge cells to be lit to all discharge cells in a display area of the plasma display panel as a total cell lighting rate for each subfield;
The display area of the plasma display panel is divided into a plurality of areas and the boundaries thereof are provided in parallel with the display electrode pairs, and the ratio of discharge cells to be lit with respect to the discharge cells in each area is set as a partial lighting rate for each area and each subfield. And a partial lighting rate detection circuit to detect
The sustain pulse generating circuit generates a plurality of sustain pulses having different lengths of at least one of a rising period and a falling period of the sustain pulse, and a plurality of drive patterns having different combinations of the generated sustain pulses. And generating the sustain pulse by switching a plurality of drive patterns according to the total cell lighting rate output from the all-cell lighting rate detection circuit and the partial lighting rate output from the partial lighting rate detection circuit. In addition, when the plurality of drive patterns are arranged on a plane having the total cell lighting rate and the partial lighting rate as two axes, a hysteresis characteristic is provided two-dimensionally between the plurality of adjacent drive patterns. A plasma display apparatus that generates the sustain pulse. A maximum value detection circuit for detecting a maximum value of the partial lighting rate in the display area for each subfield;
The all-cell lighting rate detection circuit compares a plurality of predetermined lighting rate thresholds with the all-cell lighting rate and uses the lighting rate threshold used when the all-cell lighting rate is increasing. Setting the value to a value larger than the lighting rate threshold value used when the all-cell lighting rate is decreasing, providing a hysteresis characteristic,
The maximum value detection circuit compares a plurality of predetermined maximum value thresholds with the maximum value, and uses the maximum value threshold used when the maximum value is increasing as the maximum value. Is set to a value larger than the maximum value threshold value used when is decreasing, providing a hysteresis characteristic,
The sustain pulse generation circuit is configured to switch and generate a plurality of the drive patterns according to the output from the all-cell lighting rate detection circuit and the output from the maximum value detection circuit, and the all-cell lighting rate and the maximum value The sustain pulse is generated by two-dimensionally providing a hysteresis characteristic between a plurality of adjacent drive patterns when a plurality of the drive patterns are arranged on a plane having two axes as an axis. 2. The plasma display device according to 1. The all-cell lighting rate detection circuit and the maximum value detection circuit are configured to detect a sustain pulse from a region where a sustain pulse is generated with one drive pattern on the plane due to a change in at least one of the all-cell lighting rate and the maximum value. When the fluctuation to the hysteresis region in which the hysteresis characteristic is set occurs between two or more drive patterns, the lighting rate threshold value or the maximum value threshold value is determined according to the immediately preceding state. The plasma display device according to claim 2. A hysteresis characteristic is set between two or more drive patterns from a region where a sustain pulse is generated in one drive pattern on the plane by changing at least one of the all-cell lighting rate or the maximum value. When a change to the specified hysteresis region occurs,
If the hysteresis region is a region in which hysteresis characteristics are set with respect to the change in the all-cell lighting rate, the all-cell lighting rate detection circuit has the larger lighting rate threshold value in the hysteresis region. The auxiliary lighting rate threshold value set to a value between the lighting rate threshold value and the smaller value is compared with the all cell lighting rate,
If the hysteresis region is a region in which hysteresis characteristics are set with respect to the change of the maximum value, the maximum value detection circuit has a smaller value of the maximum value threshold value with a larger value in the hysteresis region. Compare the auxiliary maximum threshold value set to a value between the maximum threshold value and the maximum value,
If the hysteresis region is a region where hysteresis characteristics are set for both the change in the all-cell lighting rate and the change in the maximum value, the all-cell lighting rate detection circuit and the maximum value detection circuit are: The auxiliary lighting rate threshold value is compared with the all-cell lighting rate and the auxiliary maximum value threshold value is compared with the maximum value based on a predetermined priority order in the hysteresis region. The plasma display device according to claim 2. The all-cell lighting rate detection circuit and the maximum value detection circuit are configured to detect a sustain pulse from a region where a sustain pulse is generated with one drive pattern on the plane due to a change in at least one of the all-cell lighting rate and the maximum value. 3. The plasma display apparatus according to claim 2, wherein when a change to a hysteresis region in which hysteresis characteristics are set occurs between two or more drive patterns, a determination based on a predetermined priority order is performed. A plasma display panel comprising a plurality of discharge cells having a display electrode pair consisting of a scan electrode and a sustain electrode,
A plurality of power recovery circuits that cause the sustain pulse to rise or fall by resonating the interelectrode capacitance of the display electrode pair and the inductor, and have a plurality of initialization periods, write periods, and sustain periods provided within one field period A method of driving a plasma display panel, wherein the sustain pulse is generated in the sustain period of the subfield and the display electrode pair is alternately applied and driven.
The ratio of discharge cells to be lit to the total discharge cells in the display area of the plasma display panel is detected for each subfield as the total cell lighting rate, and the display area of the plasma display panel is divided into a plurality of areas, and the boundary Is provided in parallel with the display electrode pair, and the ratio of the discharge cells to be lit with respect to the discharge cells in each region is detected as a partial lighting rate for each region and for each subfield,
A plurality of sustain pulses having different lengths of at least one of the sustain pulse rising period and the falling period are generated, and a plurality of drive patterns with different combinations of the sustain pulses to be generated are generated, so that all the cells are turned on. The sustain pulse is generated by switching a plurality of drive patterns in accordance with a rate and the partial lighting rate, and a plurality of the driving is performed on a plane having the whole cell lighting rate and the partial lighting rate as two axes. A method for driving a plasma display panel, wherein when the pattern is arranged, the sustain pulse is generated by providing a two-dimensional hysteresis characteristic between a plurality of adjacent drive patterns. A comparison is made between a plurality of predetermined lighting rate threshold values and the all cell lighting rate, and the lighting rate threshold value used when the all cell lighting rate is increasing is set to the all cell lighting rate. Set to a value larger than the lighting rate threshold value used when decreasing, providing a hysteresis characteristic,
When the maximum value of the partial lighting rate in the display area is detected for each subfield, a plurality of predetermined maximum value threshold values are compared with the maximum value, and the maximum value is increased The maximum threshold value used is set to a value larger than the maximum threshold value used when the maximum value is decreasing, and a hysteresis characteristic is provided,
A plurality of drive patterns are generated by switching according to the all-cell lighting rate and the maximum value, and the plurality of driving patterns are arranged on a plane having the all-cell lighting rate and the maximum value as two axes. 7. The method of driving a plasma display panel according to claim 6, wherein the sustain pulse is generated by providing two-dimensional hysteresis characteristics between the plurality of adjacent drive patterns. A hysteresis region in which hysteresis characteristics are set between two or more drive patterns from a region in which a sustain pulse is generated in one drive pattern on the plane due to a change in at least one of the all-cell lighting rate and the maximum value 8. The method of driving a plasma display panel according to claim 7, wherein when the fluctuation occurs, the lighting rate threshold value or the maximum value threshold value is determined according to a state immediately before the fluctuation. A hysteresis characteristic is set between two or more drive patterns from a region where a sustain pulse is generated in one drive pattern on the plane by changing at least one of the all-cell lighting rate or the maximum value. When a change to the specified hysteresis region occurs,
If the hysteresis region is a region in which hysteresis characteristics are set with respect to the change in the all-cell lighting rate, the lighting rate threshold value with the larger value in the hysteresis region and the lighting rate with the smaller value are set. Compare the auxiliary lighting rate threshold value set to a value between the threshold value and the all-cell lighting rate,
If the hysteresis region is a region in which hysteresis characteristics are set with respect to the change in the maximum value, the maximum value threshold value with the larger value in the hysteresis region and the maximum value threshold value with the smaller value are set. Compare the auxiliary maximum threshold value set to a value between the maximum value and the maximum value,
If the hysteresis region is a region where hysteresis characteristics are set for both the change in the all-cell lighting rate and the change in the maximum value, the auxiliary region is determined based on the priority order set in advance in the hysteresis region. 8. The method of driving a plasma display panel according to claim 7, wherein a comparison between a lighting rate threshold value and the all-cell lighting rate and a comparison between the auxiliary maximum value threshold value and the maximum value are performed. A hysteresis region in which hysteresis characteristics are set between two or more drive patterns from a region in which a sustain pulse is generated in one drive pattern on the plane due to a change in at least one of the all-cell lighting rate and the maximum value 8. The method of driving a plasma display panel according to claim 7, wherein when the fluctuation occurs, a driving pattern based on a predetermined priority order is generated.

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