JP2009016561A - Nitride semiconductor light emitting element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nitride semiconductor light emitting element capable of substantially improving an yield. <P>SOLUTION: The nitride semiconductor light emitting element includes: a substrate; and a nitride semiconductor laminate configuration comprising a plurality of nitride semiconductor layers laminated on the surface of the substrate. A dug region dug in a recessed shape and a non-dug region which is not dug are formed on the surface of the substrate, the dug region is provided with a bottom surface and a side face extending upwards from the end part of the bottom surface, and the side face of the dug region and the surface of the non-dug region are connected through a curved surface. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a nitride semiconductor light emitting device such as a nitride semiconductor laser device.

  Nitride semiconductor laser devices that emit light in the ultraviolet to visible wavelength range using GaN (gallium nitride), AlN (aluminum nitride), InN (indium nitride), and nitride semiconductor materials typified by their mixed crystals are prototyped. Has been. Here, a GaN substrate is often used as the substrate of the nitride semiconductor laser device, and has been energetically studied by each research institution.

  Currently, since the yield of nitride semiconductor laser devices is low, improvement of the yield of nitride semiconductor laser devices is required in order to reduce manufacturing costs.

Therefore, for example, in Patent Document 1, the use of a compound containing GaN in the nitride semiconductor layer first formed on the surface of the processed substrate including the recessed digging region prevents the occurrence of cracks. In addition, it is described that the nitride semiconductor layer formed thereafter has high uniformity in thickness and the surface becomes flat (for example, paragraphs [0006] and [0007] of Patent Document 1). Etc.).
JP 2006-156953 A

  However, a nitride semiconductor laser using a processed substrate described in Patent Document 1 and growing a nitride semiconductor layer on the processed substrate by MOCVD (Metal Organic Chemical Vapor Deposition) method or the like. In the case of producing the element, an effect of suppressing the generation of cracks was obtained, but no significant yield improvement was observed.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a nitride semiconductor light emitting device that can greatly improve the yield.

  The present invention includes a substrate and a nitride semiconductor multilayer structure including a plurality of nitride semiconductor layers stacked on the surface of the substrate, and the surface of the substrate is recessed with a digging region and a digging region. An unexcavated non-excavated region is formed, and the excavated region has a bottom surface and a side surface extending upward from the end of the bottom surface, and the side surface of the excavated region and the surface of the non-excavated region are curved surfaces This is a nitride semiconductor light emitting device connected through the.

  Here, in the nitride semiconductor light emitting device of the present invention, the curvature radius of the curved surface is preferably 1 μm or more and 70 μm or less.

  In the nitride semiconductor light emitting device of the present invention, the bottom width of the digging region is preferably 1 μm or more and 100 μm or less.

  In the nitride semiconductor light emitting device of the present invention, the height of the side surface of the digging region is preferably 0.5 μm or more and 50 μm or less.

  ADVANTAGE OF THE INVENTION According to this invention, the nitride semiconductor light-emitting device which can improve a yield significantly can be provided.

  Embodiments of the present invention will be described below. In the drawings of the present invention, the same reference numerals represent the same or corresponding parts.

  FIG. 1A is a schematic cross-sectional view of an example of a nitride semiconductor laser device according to the present invention. FIG. 1B is a schematic top view of the nitride semiconductor laser element shown in FIG.

Here, on the surface of the substrate 10 made of n-type GaN, a nitride semiconductor multilayer structure 13 formed by sequentially epitaxially growing a plurality of nitride semiconductor layers is formed. A ridge stripe portion 15 serving as a laser light waveguide is formed on the upper surface of 13. In addition, an SiO ₂ layer 16 as an insulating layer is formed so as to confine both sides of the ridge stripe portion 15 for the purpose of current confinement, and the p-type ohmic electrode 17 is in contact with the upper surface of the ridge stripe portion 15. Is formed. An n-type ohmic electrode 18 is formed on the back surface of the substrate 10.

FIG. 2 schematically shows a cross section of the nitride semiconductor multilayer structure 13 shown in FIG. Here, the nitride semiconductor multilayer structure 13 has an n-type Al _0.062 Ga _0.938 N first cladding layer 21 having a thickness of 2.3 μm and a thickness of 0.2 μm on the n-type GaN layer 20 having a thickness of 3.5 μm. N-type Al _0.1 Ga _0.9 N second cladding layer 22, 0.1 μm thick n-type Al _0.062 Ga _0.938 N third cladding layer 23, 0.1 μm thick n-type GaN guide layer 24, 4 nm thick An active layer 25 having a multiple quantum well structure in which InGaN layers and GaN layers having a thickness of 8 nm are alternately stacked three periods, a p-type Al _0.3 Ga _0.7 N evaporation preventing layer 26 having a thickness of 20 nm, and a p having a thickness of 0.05 μm A p-type Al _0.062 Ga _0.938 N clad layer 28 _having a thickness of 0.5 μm and a p-type GaN contact layer 29 having a thickness of 0.1 μm are stacked in this order.

  As shown in FIG. 1A, a defect concentration region 11 is formed in the substrate 10, and a region other than the defect concentration region 11 is a low defect region 12. The substrate 10 is formed with a dug area 14 dug into a portion including the defect concentration area 11. The digging region 14 includes a bottom surface 14a and two side surfaces 14b extending upward from both ends of the bottom surface 14a.

  Further, on the surface of the substrate 10, a curved surface region 34 having a curved surface 19 is formed at a position adjacent to the digging region 14, and non-digging is not performed at a position adjacent to the curved surface region 34. Region 44 is located.

  As a result of the inventors investigating the reason why the yield is not improved in the invention of Patent Document 1, in the invention of Patent Document 1, the side surface of the recessed digging region formed on the surface of the processed substrate is not dug. Since the surface of the digging region is directly connected at an angle of approximately 90 °, when a nitride semiconductor layer is grown on the digging region, the growth that rises at the end of the digging region Thus, a nitride semiconductor layer whose surface is not flat is formed. Therefore, it has been found that the thickness of the nitride semiconductor layer is non-uniform, and the surface flatness of the nitride semiconductor layer is deteriorated.

  Therefore, as a result of intensive studies by the inventor, for example, as shown in FIGS. 1A and 1B, the side surface 14b of the digging region 14 and the surface 44a of the non-digging region 44 are connected by the curved surface 19. As a result, it has been found that the yield is greatly improved, and the present invention has been completed.

  As in the present invention, the connecting portion between the side surface 14b of the digging region 14 and the surface 44a of the non-digging region 44 is not a shape having a corner, but a curved surface 19, so that the local surface with respect to the growth surface of the substrate 10 is obtained. Generation of a non-uniform nitride semiconductor layer can be suppressed. On the curved surface 19, the growth of the nitride semiconductor layer becomes uniform, the flatness of the surface of the nitride semiconductor layer grown on the curved surface 19 is improved, the characteristics in the wafer surface are made uniform, and the yield is increased. Can be improved.

  The digging region 14 can be formed by digging the surface of the substrate 10 with, for example, ICP (Inductively Coupled Plasma).

  The distance D between the center of the ridge stripe portion 15 and the end of the digging region 14 on the ridge stripe portion 15 side is about 130 μm here, but is not particularly limited in the present invention. .

  In the present invention, the radius of curvature of the curved surface 19 is preferably 1 μm or more and 70 μm or less, and more preferably 2 μm or more and 10 μm or less. When the radius of curvature of the curved surface 19 is 1 μm or more and 70 μm or less, particularly 2 μm or more and 10 μm or less, the flatness of the surface of the nitride semiconductor layer grown on the curved surface 19 tends to be improved.

  In the present invention, the width d of the bottom surface 14a of the digging region 14 is preferably 1 μm or more and 100 μm or less, and more preferably 3 μm or more and 20 μm or less. When the width d of the bottom surface 14a of the digging region 14 is 1 μm to 100 μm, particularly 3 μm to 20 μm, the in-plane uniformity of the thickness of the nitride semiconductor layer grown on the substrate 10 tends to be improved. growing.

  In the present invention, the height h of the side surface 14b of the digging region 14 is preferably 0.5 μm or more and 50 μm or less, and more preferably 5 μm or more and 10 μm or less. When the height h of the side surface 14b of the digging region 14 is not less than 0.5 μm and not more than 50 μm, particularly not less than 5 μm and not more than 10 μm, the crack generation rate of the nitride semiconductor layer grown on the substrate 10 tends to decrease. Become.

Hereinafter, an example of a method for manufacturing the nitride semiconductor laser element shown in FIG. First, a method for manufacturing the substrate 10 having the linear defect concentration region 11 will be described. An n-type underlying GaN layer having a thickness of, for example, 2.5 μm is grown on the n-type GaN plate by MOCVD, and a SiO ₂ mask pattern (period 20 μm) having periodic stripe-shaped openings is formed thereon, The substrate 10 is formed by laminating an n-type GaN layer having a thickness of 15 μm, for example, by MOCVD again.

Here, since n-type GaN does not grow on the SiO ₂ mask, the growth of n-type GaN starts from the stripe-shaped opening. Then, n-type GaN is becomes thicker than the SiO ₂ mask, n-type GaN is grown laterally from the opening on the SiO ₂ mask.

Then, SiO ₂ mask center SiO ₂ each growing has n-type GaN is associated from the left and right of the mask in the association portion becomes a defect concentration region 11 having a high defect density. Since the SiO ₂ mask is formed in a linear shape, the defect concentration region 11 is also formed in a linear shape. Here, the width of the defect concentration region 11 is about 40 μm, and the interval between the defect concentration regions 11 is about 400 μm.

  In the above description, the manufacturing method of the substrate 10 using the ELOG (Epitaxial Lateral Over Growth) method is shown, but other manufacturing methods can be used in the present invention.

  That is, in the present invention, it is sufficient if the nitride semiconductor layer is grown on the surface of the substrate 10 in which the concave digging region 14 is provided and the defect concentration region 11 and the low defect region 12 are formed. The substrate 10 may be a substrate made of GaN, SiC, sapphire, GaAs, Si, spinel, ZnO, or the like other than those described above.

Next, a mask made of SiO ₂ or the like is formed on the entire surface of the substrate 10 to a thickness of, for example, 400 nm by EB (Electron Beam) deposition or the like, and thereafter [1-100] by a general photolithography process. A stripe-shaped resist is formed in the direction, and a stripe-shaped opening having a width of, for example, 60 μm is formed between adjacent resists. Here, the opening is formed so as to include the defect concentration region. The region below the opening is a region corresponding to the digging region 44 shown in FIG. 1A, and the region below the resist is a region corresponding to the non-digging region 44 and the curved region 34.

  In addition, when expressing a crystal plane and a direction, it should be expressed by adding a bar on a required number. However, because there are restrictions on expression means, in this specification and drawings Instead of the expression with a bar above the number, the symbol “−” is added in front of the required number.

Thereafter, using ICP capable of controlling the bias power, the mask made of SiO ₂ or the like and the substrate 10 are dry-etched (first dry etching). Here, as the conditions for the first dry etching, for example, when the gas pressure is set to 1 to 2 mTorr and the bias voltage is set to 200 to 300 V, the boundary (interface) between the mask made of SiO ₂ and the substrate 10 is reached. A dug region 44 having a highly perpendicular side surface 14b is formed. Here, the etching depth of the substrate 10 is 3 μm, but is not particularly limited thereto. Thereafter, the mask made of SiO ₂ or the like is removed with an etchant such as hydrogen fluoride (HF).

Then, again, a mask made of SiO ₂ or the like is EB-deposited to a thickness of, for example, 400 nm on the entire surface of the substrate 10, and a stripe-like resist is formed in the [1-100] direction by a general photolithography process. A stripe-shaped opening having a width of 61 μm, for example, slightly wider than the width of the opening in the first dry etching is formed between adjacent resists. Here, the openings are formed so as to include all the openings at the time of the first dry etching. Unlike the opening at the time of the first dry etching, the region below the opening becomes a region corresponding to the digging region 44 and the curved region 34 shown in FIG. 1A, and the region below the resist. Is a region corresponding to the non-dig region 44.

Thereafter, similarly to the first dry etching, the mask and the substrate 10 made of SiO ₂ or the like are dry-etched (second dry etching) using ICP whose bias power can be controlled.

Here, during the second dry etching, as a condition for reaching the boundary (interface) between the mask made of SiO ₂ or the like and the substrate 10 and hardly causing anisotropy, for example, the gas pressure is set to 10 to 20 mTorr, bias When the voltage is 100 V or less, the curved surface 19 is formed. After that, the mask made of SiO ₂ or the like is removed with an etchant such as HF as in the first dry etching.

Thereby, the board | substrate 10 shown to Fig.1 (a) is obtained. Then, a plurality of nitride semiconductor layers are stacked on the surface of the substrate 10 to form a nitride semiconductor multilayer structure 13, and a ridge stripe portion 15, an SiO ₂ layer 16, a p-type ohmic electrode 17 and an n-type ohmic electrode. 18 are formed sequentially. Thereafter, the chip-shaped nitride semiconductor laser element shown in FIG. 1A is obtained by dividing the wafer after the formation of the n-type ohmic electrode 18.

  As described above, when the nitride semiconductor layer is grown on the surface of the substrate 10 in which the side surface 14 b of the digging region 14 and the surface 44 a of the non-digging region 44 are connected by the curved surface 19, the nitride semiconductor layer is uniformly formed on the curved surface 19. The nitride semiconductor layer 13 is formed by growing the nitride semiconductor layer.

  Therefore, a flat region is secured without the defect concentration region 11 entering the region where the ridge stripe portion 15 is formed. Then, by forming the ridge stripe portion 15 in this flat region, it is possible to suppress variations in device characteristics within the wafer surface and to improve the yield.

  The nitride semiconductor laser device having the structure shown in FIG. 1A obtained as described above is driven (APC drive) by controlling the drive current value so that the light output is constant at 30 mW at a temperature of 60 ° C. Thus, a life test was conducted.

The life here refers to the time when _Io (drive current value when the optical output is 30 mW) at the start of the life test becomes 1.5 times as long as the life test. The emission wavelength of each nitride semiconductor laser element was 405 ± 5 nm. Further, 50 nitride semiconductor laser elements were randomly taken out from each wafer manufactured as described above, and the ratio of the number of nitride semiconductor laser elements whose lifetime exceeded 3000 hours was evaluated as a yield.

  As a result, the yield of the nitride semiconductor laser device having the configuration shown in FIG. 1A exceeded 90%.

  On the other hand, as in Patent Document 1, a nitride semiconductor manufactured in the same manner as described above except that a substrate in which the side surface 14b of the digging region 14 and the surface 44a of the non-digging region 44 form an angle of 90 ° is used. The yield of the laser element was 60% or less.

  Thus, the improvement of the surface flatness (location other than the dug region 14) of the nitride semiconductor multilayer structure 13 enables the thickness and composition of each nitride semiconductor layer in the wafer surface to be uniform, and the yield. It can be said that it leads to improvement.

In the present invention, it goes without saying that the configuration of the nitride semiconductor multilayer structure 13 and the material of each nitride semiconductor layer constituting the nitride semiconductor multilayer structure 13 are not limited to those described above. The material of the nitride semiconductor layer constituting the nitride semiconductor stacked structure 13, _{e.g., Al x In y Ga z N} (0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ z ≦ 1, x + y + z = A crystal layer composed of a compound of at least one group 3 element selected from the group consisting of aluminum, indium and gallium represented by the composition formula 1) and nitrogen which is a group 5 element can be used. Each nitride semiconductor layer constituting the nitride semiconductor multilayer structure 13 may be appropriately doped with an n-type dopant or a p-type dopant.

  In the present invention, the material and configuration of the active layer 25 are not limited to those described above, and the active layer 25 may have a single quantum well structure instead of a multiple quantum well structure.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  In the present invention, by connecting the concave digging region and the non-digging region on the surface of the substrate with a curved surface, the edge growth of the nitride semiconductor layer grown on the curved surface (the end of the non-digging region) The surface flatness of the nitride semiconductor layer in the vicinity of the end of the digging region is improved, and the nitride semiconductor layer in the wafer plane is suppressed. As a result, the yield of the nitride semiconductor light emitting device can be improved.

  The nitride semiconductor light emitting device with improved yield is considered to be applicable not only to nitride semiconductor laser devices but also to light emitting devices such as nitride semiconductor light emitting diode devices other than nitride semiconductor laser devices. .

(A) is typical sectional drawing of an example of the nitride semiconductor laser element concerning this invention, (b) is a typical top view of the nitride semiconductor laser element shown to (a). It is a figure which shows typically the cross section of the nitride semiconductor laminated structure shown to Fig.1 (a).

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Substrate, 11 Defect concentration region, 12 Low defect region, 13 Nitride semiconductor laminated structure, 14 Excavation region, 14a Bottom surface, 14b Side surface, 15 Ridge stripe part, 16 SiO ₂ layer, 17 p-type ohmic electrode, 18 n Type ohmic electrode, 19 curved surface, 20 n-type GaN layer, 21 n-type Al _0.062 Ga _0.938 N first cladding layer, 22 n-type Al _0.1 Ga _0.9 N second cladding layer, 23 n-type Al _0.062 Ga _0.938 N third cladding Layer, 24 n-type GaN guide layer, 25 active layer, 26 p-type Al _0.3 Ga _0.7 N evaporation prevention layer, 27 p-type GaN guide layer, 28 p-type Al _0.062 Ga _0.938 N clad layer, 29 p-type GaN contact layer, 34 curved surface area, 44 non-digged area, 44a surface.

Claims (4)

A substrate, and a nitride semiconductor multilayer structure composed of a plurality of nitride semiconductor layers stacked on the surface of the substrate,
On the surface of the substrate, a digging region dug in a concave shape, and a non-digging region that is not dug, are formed,
The digging region has a bottom surface and a side surface extending upward from an end of the bottom surface,
A nitride semiconductor light emitting device, wherein a side surface of the digging region and a surface of the non-digging region are connected via a curved surface.   2. The nitride semiconductor light emitting device according to claim 1, wherein a curvature radius of the curved surface is not less than 1 μm and not more than 70 μm.   3. The nitride semiconductor light emitting device according to claim 1, wherein a width of a bottom surface of the digging region is 1 μm or more and 100 μm or less.   4. The nitride semiconductor light emitting device according to claim 1, wherein a height of a side surface of the digging region is 0.5 μm or more and 50 μm or less. 5.

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