JP2009010519A - A/d conversion circuit, a/d conversion method, and semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an A/D conversion circuit, A/D conversion method, and semiconductor integrated circuit, capable of correcting non-linear distortions with an A/D converter, that occur at an analog part while avoiding a design period for an analog part from becoming longer. <P>SOLUTION: The A/D conversion circuit comprises a track hold circuit (12) which tracks the changes in an analog input value and holds an analog input value at a specified timing to output an analog input hold value; a reference value generating circuit (13) for generating a plurality of specified reference values; a plurality of preamplifiers (14) that amplify the analog input hold value and respective reference value, a comparator (15) for generating a logic signal, corresponding to each preamplifier output; and an encoder (16) which converts the logic signal generated by the comparator to the digital output value of specified code. The encoder changes a conversion logic that converts the logic signal to the specified code, based on the correction data from the outside. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an A / D converter, and more particularly to a technique for correcting non-linear distortion of a parallel A / D converter.

In recent years, there is an increasing demand for A / D converters that digitize analog information. In particular, in digital TVs and DVD recorders, there is a high demand for digitizing broadband analog signals at high speed.
As a high-speed A / D converter that meets the demand for higher speeds, a technique is known in which a track hold circuit is provided in the first stage to hold an input analog signal, thereby reducing the limitation of the dynamic range due to clock skew. .
However, when the sampling frequency is further increased, the settling time of the track hold circuit is not in time, and nonlinear distortion of the A / D converter occurs.

Patent Document 1 discloses a technique for correcting nonlinear distortion by detecting nonlinear distortion of a pipeline A / D converter and controlling the gain of an operational amplifier at each stage.
JP 2006-25399 A

  However, the technique described in Patent Document 1 has a problem in that the analog unit including the operational amplifier is controlled, so that the design of the analog unit becomes complicated.

  In recent years, power supply voltage has decreased due to miniaturization of devices, and digital circuits have received many benefits such as higher speed, lower power consumption, and higher density. Various problems such as a decrease in dynamic range due to a decrease and an increase in nonlinear distortion have become apparent, leading to a longer design period.

Therefore, it is desired to avoid an increase in the design period of the analog part and to correct the non-linear distortion of the A / D converter generated in the analog part.
The present invention has been made in view of such circumstances, and it is possible to avoid an increase in the design period of the analog unit and to correct non-linear distortion of the A / D converter generated in the analog unit. It is an object to provide a conversion circuit, an A / D conversion method, and a semiconductor integrated circuit.

  To solve the problem, the present invention follows a change in an analog input value, holds the analog input value at a predetermined timing and outputs the analog input hold value, and generates a plurality of predetermined reference values A reference value generating circuit for performing the processing, a plurality of preamplifiers for amplifying the analog input hold value and each reference value, a comparator for generating a logic signal corresponding to each preamplifier output, and the logic generated by the comparator An encoder that converts a signal into a digital output value of a predetermined code, and the encoder is an A / D conversion circuit that changes conversion logic for converting the logic signal into the predetermined code based on correction data from the outside. is there.

  Further, the present invention is a semiconductor integrated circuit including the A / D conversion circuit according to the invention described above.

  The present invention also provides a track hold circuit that follows a change in an analog input value, holds the analog input value at a predetermined timing, and outputs the analog input hold value, and a reference value generation circuit that generates a plurality of predetermined reference values A plurality of preamplifiers that amplify the analog input hold value and each reference value; a comparator that generates a logic signal corresponding to each preamplifier output; and the logic signal generated by the comparator with a predetermined code A / D conversion comprising an A / D converter having an encoder for converting to a digital output value, and a digital correction circuit for generating correction data for changing the input / output conversion characteristics of the A / D converter A circuit A / D conversion method, wherein the digital correction circuit is a digital input value corresponding to a predetermined analog input value. And generating an output data value corresponding to a value obtained by A / D converting the predetermined analog input value, and a plurality of sets of the predetermined analog input value and the output data value are converted into the correction data. Is output to the encoder, and the encoder is an A / D conversion method that changes conversion logic for converting the logic signal into the predetermined code based on the correction data from the digital correction circuit.

  According to the A / D conversion circuit, the A / D conversion method, and the semiconductor integrated circuit of the present invention, it is possible to avoid an increase in the design period of the analog unit and to reduce the nonlinear distortion of the A / D converter generated in the analog unit. It can be corrected.

[First Embodiment]
FIG. 1 is a block diagram showing a configuration of an A / D conversion circuit 1 according to the first embodiment of the present invention.
The A / D conversion circuit 1 is provided with an A / D converter 2, a digital correction circuit 3, and a D / A converter 4.

  The A / D converter 2 is connected with an analog input signal Ain, an analog correction input signal Ain2, a selection signal SEL, correction data, and a clock signal CLK. The A / D converter 2 outputs the conversion result as a digital output. Output as signal Dout.

The digital correction circuit 3 outputs correction data for correcting non-linear distortion to the A / D converter 2.
The digital correction circuit 3 inputs an analog correction input signal Ain2 to the A / D converter 2 via the D / A converter 4 in order to generate correction data, and a digital output that is the A / D conversion result The signal Dout is captured.

The digital correction circuit 3 includes a data generation unit 5, a data buffer 6, a correction value calculation unit 7, an address buffer 8, and an address decoder 9.
The data generation unit 5 outputs the input data D to the D / A converter 4 and the data buffer 6. The input data D is input to the A / D converter 2 through the D / A converter 4 as the analog correction input signal Ain2. The input data D is input to the A / D converter 2 as correction data via the data buffer 6.
The correction value calculator 7 generates a signal obtained by correcting the digital output signal Dout, and inputs the signal to the A / D converter 2 as a correction signal via the address buffer 8 and the address recorder 9.

  Note that each unit of the A / D conversion circuit 1 is controlled in an integrated manner by a controller (not shown).

FIG. 2 is a diagram showing a detailed configuration of the A / D converter 2. The A / D converter 2 having this configuration is a parallel A / D converter, which samples the analog input signal Ain in synchronization with the clock signal CLK, converts it to an n-bit digital output signal Dout, and outputs it.
The A / D converter 2 includes a selector 11, a track hold circuit 12, a reference voltage generation circuit 13, a preamplifier 14, a comparator 15, and an encoder 16.
The encoder 16 is provided with a code converter 18 and a RAM 19.

  The selector 11 switches and outputs the analog input signal Ain and the analog correction input signal Ain2 according to the selection signal SEL. The track hold circuit 12 follows the change of the analog input value, holds the analog input value in synchronization with the clock signal CLK, and outputs the analog input hold value. The reference voltage generation circuit 13 generates a predetermined reference voltage value for each of the plurality of preamplifiers.

The preamplifier 14 amplifies the analog input hold value and the reference voltage value. The comparator 15 compares the analog input hold value with the reference voltage value in synchronization with the clock signal CLK, and outputs the result as a logical value (0, 1). The encoder 16 converts the logical value generated by the comparator 15 into a binary code and generates a digital output value.
That is, the code converter 18 converts the thermometer code output from the comparator 15 into a 1-of-n code, and the RAM 19 converts the 1-of-n code into a binary code.

FIG. 3 is a diagram illustrating an encoding method of the encoder 16.
FIG. 3A shows a thermometer code that is input to the code converter 18. The input of the code converter 18 is 7 bits T1 to T7, T1 is LSB (Least Significant Bit), and T7 is MSB (Most Significant Bit).
In this thermometer code, all the bits are 0 in the bottom row where the analog input value is the smallest, and as the analog input value increases, the direction from the lower bit to the higher bit, that is, T1 → T7. The bit changes to 1. In the top row where the analog input value is maximum, all bits are 1.

FIG. 3B shows a 1-of-n code that is an output of the code converter 18. The output of the code converter 18 is 7 bits from O1 to O7, where O1 is LSB and O7 is MSB.
In this 1-of-n code, all the bits are 0 in the bottom row where the analog input value is minimum. As the analog input value increases, the bit changes to 1 in the direction from the lower bit to the upper bit, that is, from O1 to O7, but only 1 that has changed to 1 is retained, and the other bits are 0. Reset to. In the top row where the analog input value is maximum, only the bit O7 is 1.

FIG. 3 (3) shows a binary code that is output from the RAM 19. The output of the RAM 19 is 3 bits B1 to B3, B1 is LSB, and B3 is MSB.
The RAM 19 converts the input 1-of-n code into a binary code and outputs it as a digital output signal Dout.
Note that the digital output signal Dout may be output as data converted into a binary code as a parallel signal or as a serial signal.

When the digital output signal Dout is converted into an n-bit binary code when the encoder 16 is configured, the A / D converter needs to have a (2 ⁿ −1) -bit input terminal. Therefore, the required size of the RAM 19 is (2 ⁿ −1) × n bits.

Generally, in a parallel type A / D converter, the dynamic range is limited by the skew of the clock signal CLK supplied to the comparator at high speed, so the track hold circuit 12 is provided in the first stage to hold the input analog signal. Thus, the skew of the clock signal CLK distributed to the (2 ⁿ −1) comparators 15 in the subsequent stage is allowed.

  However, as the sampling frequency becomes faster, the settling time of the track hold circuit 12 will not be in time, and the performance of the A / D converter 2 will deteriorate. The settling error of the track hold circuit 12 causes non-linear distortion of the A / D converter 2.

FIG. 4 is a diagram for explaining nonlinear distortion of the A / D converter 2.
Correct input / output characteristics are indicated by dotted lines, and input / output characteristics due to nonlinear distortion are indicated by solid lines.
In order to increase the settling time of the track hold circuit 12, it is necessary to reduce the time constant of the track hold output. However, the track hold circuit 12 must drive a plurality of preamplifiers 14 as shown in FIG. Therefore, it is not easy to lower the time constant.

In the A / D conversion circuit 1 of the present embodiment, the nonlinear distortion is corrected using the digital correction circuit 3 and the D / A converter 4.
Here, the digital correction circuit 3 and the D / A converter 4 function only when correcting non-linear distortion, and do not normally function. For example, the nonlinear distortion is automatically corrected when the apparatus is turned on for the first time, or the nonlinear distortion is corrected by an operator setting.

FIG. 5 is a flowchart showing a procedure for correcting nonlinear distortion.
The nonlinear distortion correction operation will be described below with reference to FIGS. This operation is controlled in an integrated manner by the controller (not shown).

  In step S01, the controller sets an initial value in the RAM 19 of the A / D converter 2. Here, the set initial value is a value for converting a 1-of-n code into a binary code as shown in FIG. 3, for example. In step S02, the controller initializes the data buffer 6 and the address buffer 8 of the digital correction circuit 3.

In step S03, the controller sets the selection signal SEL to 1, and the data generation unit 5 sets the input data D to 0. The input data D is converted into an analog correction input signal Ain2 by the D / A converter 4 and output to the A / D converter 2.
In the A / D converter 2, when the selection signal SEL is set to 1, the selector 11 selects the analog correction input signal Ain 2 and outputs it to the track hold circuit 12. Then, in accordance with the A / D conversion operation described above, the input data D is converted into a digital signal and output as a digital output signal Dout.

  In step S04, the correction value calculation unit 7 samples and inputs N digital output signals Dout. In step S05, an average value of the sampled N digital output signals Dout is obtained and set as a correction value CORR. The correction value CORR obtained in step 5 corresponds to the input data D. That is, the expected value of the correction value CORR is the input data D.

In step S 06, the input data D is set in the data buffer 6, and the correction value CORR is set in the address buffer 8. In step S07, it is checked whether or not the input data D is the maximum value (2 ⁿ −1).

If No in step S07, that is, if the input data D is not the maximum value (2 ⁿ −1), the input data D is updated to new input data D increased by 1 in step S08. Then, the process returns to step S04, and the above process is repeated.

If Yes in step S07, that is, if the input data D is the maximum value (2 ⁿ −1), the input data D stored in the data buffer 6 and the address buffer 8 and the correction value CORR are stored in step S09. Is written in the RAM 19 as correction data. At this time, the correction value CORR is converted into a 1-of-n code in the address decoder 9.
As a result, the RAM 19 sets the conversion code so that the correction value CORR is the input / output characteristic before correction and the input data D is the input / output characteristic after correction. FIG. 6 shows the result of improvement of nonlinear distortion by correction.

  Note that the selection signal SEL may be set to 0 when the A / D converter 2 is actually used after the correction data for the non-linear distortion is written to the RAM 19. Further, if the digital correction circuit 3 and the D / A converter 4 are powered down, power consumption can be reduced.

[Second Embodiment]
The second embodiment is different from the first embodiment in that no D / A converter is used. Accordingly, the same parts as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

FIG. 7 is a block diagram showing a configuration of the A / D conversion circuit 1 according to the second embodiment.
The A / D conversion circuit 1 is provided with an A / D converter 10 and a digital correction circuit 3. Unlike the first embodiment shown in FIG. 1, the input data D generated by the data generator 5 is directly input to the A / D converter 10.

  FIG. 8 is a diagram showing a detailed configuration of the A / D converter 10. The A / D converter 10 is newly provided with an analog multiplexer 20. Then, the multiplexer operates based on the input data D, and the analog correction input signal Aout is generated by switching the terminal voltage of the ladder resistor of the reference voltage generation circuit 13. The analog correction input signal Aout is input to the selector 11, selected when the selection signal SEL becomes 1, and output to the track hold circuit 12.

  FIG. 9 is a diagram illustrating a configuration of the analog multiplexer 20. The analog multiplexer 20 is provided with a plurality of switch elements M11 to M22, and a switch element corresponding to the state of each bit D1, D2,... Of the input data D is selected and turned on.

For example, when the input data D = “00”, the switch elements M14 and M22 are turned on, and the analog correction input signal Aout is V1. When the input data D = "10", the switch elements M13 and M22 are turned on, and the analog correction input signal Aout is V2. When the input data D = “01”, the switch elements M12 and M21 are turned on, and the analog correction input signal Aout is V2 ⁿ −2. When the input data D = “11”, the switch elements M11 and M21 are turned on, and the analog correction input signal Aout is V2 ⁿ −2.
If a switch element is further added to the analog multiplexer 20, a case where the number of bits of the input data D is large can be dealt with.

  Since the configuration and operation of other parts are the same as those of the A / D conversion circuit of the first embodiment, detailed description thereof is omitted.

  According to the second embodiment, since the analog multiplexer 20 is used instead of the D / A converter, the second embodiment can be configured at a lower cost than the first embodiment. However, since there is nonlinear distortion due to the reference voltage generation circuit, when the nonlinear distortion of the reference voltage generation circuit is sufficiently small compared to the nonlinear distortion of the entire A / D converter, A / D conversion circuit of the form can be used.

Further, the above-described A / D conversion circuit can be widely applied. For example, in an optical disk reproducing apparatus, it is used in the following form.
FIG. 10 is a diagram showing a configuration of an optical disc reproducing apparatus using the A / D converter of each embodiment.

  The optical disc apparatus 100 is a device that reads information from the optical disc medium D, and mainly includes a pickup head (PUH) 111, an A / D converter (ADC) 112, a phase comparator 113, and a frequency error detector 114. A loop filter 115, a VCO (Voltage Controlled Oscillator) 116, an adaptive equalizer 117, a maximum likelihood decoder 118, and the like.

  The pickup head 111 reproduces a signal corresponding to information recorded on the optical disk medium D, and receives a laser light source that irradiates the optical disk medium D with laser light and a laser beam that receives the laser light reflected from the optical disk medium D. (Not shown). The reproduction signal output from the light receiver is amplified by the reproduction amplifier 111b to become a reproduction RF signal, and is further guided to the A / D converter 112 via the pre-waveform equalizing means 111c.

  The A / D converter 112 is an element that performs A / D conversion on the input reproduction RF signal and outputs a digital RF signal (multi-level RF signal). This digital RF signal is a multivalued digital value output at substantially constant time intervals.

  A / D conversion in the A / D converter 112 is controlled by a control signal output from a VCO (voltage controlled oscillator) 116. That is, the A / D conversion cycle (time interval) is determined based on the oscillation frequency of the VCO 116.

  The output of the A / D converter 112 is connected to the input of an adjustment mechanism 112b (a kind of amplifier) that adjusts the offset (zero level / slice level) and amplitude of the input reproduction RF signal, and is adjusted by the adjustment mechanism 112b. The reproduced reproduction RF signal is configured to be a signal corrected by the next asymmetry correction 112c.

  The adaptive equalizer 117 is a filter that equalizes the multilevel RF signal into a PR (Partial Response) waveform. The adaptive equalizer 117 includes a transversal filter and the like, functions as a waveform equalizer, corrects reproduction distortion, and adjusts the offset (zero level / slice level) and amplitude of the reproduction RF signal. Are output to the maximum likelihood decoder 118.

  Maximum Likelihood decoder 118 is composed of a Viterbi decoder or the like, and is configured to decode data equalized by adaptive equalizer 117. The output of the maximum likelihood decoder 118 is used as digital demodulated data. The output of maximum likelihood decoder 118 is also fed back to adaptive equalizer 117.

  The phase comparator 113 is a circuit that compares the phases of the multilevel RF signal output from the maximum likelihood decoder 118 and the output signal (not shown) from the VCO 116 and outputs a phase difference.

  The frequency error detector 114 detects (measures) the frequency of the multilevel RF signal input from the A / D converter 112 and outputs a frequency error signal representing the difference between this frequency and the frequency of the output signal from the VCO 116. It is a circuit to do. The frequency error detector 114 also outputs a peripheral wave number error detection signal used as an error information control signal for controlling whether or not the output frequency error signal is used in the loop filter 115.

  The loop filter 115 is a circuit that generates a voltage for controlling the VCO 116 based on the phase error output from the phase comparator 113 and the frequency error output from the frequency error detector 114.

  The VCO 116 is an oscillation circuit that oscillates at a frequency corresponding to the control voltage output from the loop filter 115, and functions as a control signal generator.

[Effect of each embodiment]
The A / D conversion circuit of each embodiment described above corrects the non-linear distortion generated in the analog unit using the digital correction circuit. As described above, various problems such as an increase in variation due to miniaturization, a decrease in dynamic range due to a decrease in power supply voltage, and an increase in non-linear distortion have become apparent in analog circuits, leading to an increase in design period. For this reason, compared with the configuration in which the non-linear distortion is corrected in the analog unit, the A / D conversion circuit of each of the above embodiments avoids an increase in the design period of the analog unit and occurs in the analog unit. The non-linear distortion of the A / D converter to be corrected can be corrected.

  Note that the A / D conversion circuit can be included in a semiconductor integrated circuit.

  The typical components of the present invention can be illustrated as follows.

<About Figures 1 and 2>
1. A track hold circuit (12) that follows the change of the analog input value, holds the analog input value at a predetermined timing, and outputs the analog input hold value;
A reference value generation circuit (13) for generating a plurality of predetermined reference values;
A plurality of preamplifiers (14) for amplifying the analog input hold values and the respective reference values;
A comparator (15) for generating a logic signal corresponding to each preamplifier output;
An encoder (16) for converting the logic signal generated by the comparator into a digital output value of a predetermined code;
The A / D conversion circuit, wherein the encoder changes conversion logic for converting the logic signal into the predetermined code based on correction data from the outside.

<About Figure 1>
2. A digital input value corresponding to a predetermined analog input value is generated, an output data value is generated corresponding to a value obtained by A / D converting the predetermined analog input value, and the predetermined analog input value and the output data An A / D conversion circuit comprising a digital correction circuit (3) for outputting a plurality of sets of values and values as correction data to the encoder.

<About Figure 2>
3. The encoder is
An A / D conversion circuit, wherein the conversion logic is changed so that the digital input value is output when the output data value is input based on the correction data.

<About FIGS. 1 and 8>
4). An A / D conversion circuit comprising a D / A converter (4, 20) for converting the digital input value generated by the digital correction circuit into the analog input value.

<About FIGS. 8 and 9>
5). The D / A converter is
An A / D conversion circuit comprising: a multiplexer (20) for generating the analog input value by switching a plurality of reference values of the reference value generation circuit based on the digital input value.

<About FIGS. 2 and 8>
6). 5. A selection circuit (11) for selecting either an analog input value from the D / A converter or another analog input value and outputting the selected analog input value to the track hold circuit. A / D conversion circuit.

  7. A semiconductor integrated circuit comprising the A / D conversion circuit according to claim 1.

<About FIG. 1, FIG. 2, FIG. 5>
8). A track hold circuit that follows a change in an analog input value, holds the analog input value at a predetermined timing and outputs an analog input hold value, a reference value generation circuit that generates a plurality of predetermined reference values, and the analog input A plurality of preamplifiers for amplifying the hold value and each reference value, a comparator for generating a logic signal corresponding to each preamplifier output, and converting the logic signal generated by the comparator into a digital output value of a predetermined code An A / D converter having an encoder to perform,
An A / D conversion method for an A / D conversion circuit comprising a digital correction circuit for generating correction data for changing the input / output conversion characteristics of the A / D converter,
The digital correction circuit includes:
Generating a digital input value corresponding to a predetermined analog input value, and generating an output data value corresponding to a value obtained by A / D converting the predetermined analog input value;
Outputting a plurality of sets of data of the predetermined analog input value and the output data value as the correction data to the encoder;
The encoder is
A conversion logic for converting the logic signal into the predetermined code is changed based on the correction data from the digital correction circuit.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Further, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine suitably the component covering different embodiment.

1 is a block diagram showing a configuration of an A / D conversion circuit according to a first embodiment of the present invention. The figure which shows the structure of the detail of an A / D converter. The figure which shows the encoding method of an encoder. The figure explaining the nonlinear distortion of an A / D converter. The flowchart which shows the procedure which correct | amends nonlinear distortion. The figure which shows the improvement result of the nonlinear distortion by correction | amendment. The block diagram which shows the structure of the A / D conversion circuit which concerns on 2nd Embodiment. The figure which shows the structure of the detail of an A / D converter. The figure which shows the structure of an analog multiplexer. The figure which shows the structure of the optical disk reproducing | regenerating apparatus using the A / D converter of each embodiment.

Explanation of symbols

  D: Input data, CORR: Correction value, M11 to M22: Switch element, 1 ... A / D conversion circuit, 2 ... A / D converter, 3 ... Digital correction circuit, 4 ... D / A converter, 5 ... Data Generation unit, 7 ... correction value calculation unit, 11 ... selector, 12 ... track hold circuit, 13 ... reference voltage generation circuit, 14 ... preamplifier, 15 ... comparator, 16 ... encoder, 18 ... code converter, 19 ... RAMm, 20 ... analog multiplexer.

Claims (8)

A track hold circuit that follows the change in the analog input value, holds the analog input value at a predetermined timing, and outputs the analog input hold value;
A reference value generation circuit for generating a predetermined plurality of reference values;
A plurality of preamplifiers for amplifying the analog input hold value and each reference value;
A comparator that generates a logic signal corresponding to each preamplifier output;
An encoder that converts the logic signal generated by the comparator into a digital output value of a predetermined code;
The A / D conversion circuit, wherein the encoder changes conversion logic for converting the logic signal into the predetermined code based on correction data from the outside. A digital input value corresponding to a predetermined analog input value is generated, an output data value is generated corresponding to a value obtained by A / D converting the predetermined analog input value, and the predetermined analog input value and the output data The A / D conversion circuit according to claim 1, further comprising: a digital correction circuit that outputs a plurality of sets of data and values as the correction data to the encoder. The encoder is
3. The A / D conversion circuit according to claim 2, wherein the conversion logic is changed so that the digital input value is output when the output data value is input based on the correction data.   4. The A / D converter circuit according to claim 3, further comprising a D / A converter that converts the digital input value generated by the digital correction circuit into the analog input value. The D / A converter is
5. The A / D conversion circuit according to claim 4, wherein the A / D conversion circuit is a multiplexer that generates the analog input value by switching a plurality of reference values of the reference value generation circuit based on the digital input value.   5. An A / according to claim 4, further comprising: a selection circuit that selects an analog input value from the D / A converter and another analog input value and outputs the selected analog output value to the track hold circuit. D conversion circuit.   A semiconductor integrated circuit comprising the A / D conversion circuit according to claim 1. A track hold circuit that follows a change in an analog input value, holds the analog input value at a predetermined timing and outputs an analog input hold value, a reference value generation circuit that generates a plurality of predetermined reference values, and the analog input A plurality of preamplifiers for amplifying the hold value and each reference value, a comparator for generating a logic signal corresponding to each preamplifier output, and converting the logic signal generated by the comparator into a digital output value of a predetermined code An A / D converter having an encoder to perform,
An A / D conversion method for an A / D conversion circuit comprising a digital correction circuit for generating correction data for changing the input / output conversion characteristics of the A / D converter,
The digital correction circuit includes:
A digital input value corresponding to a predetermined analog input value, and an output data value corresponding to a value obtained by A / D converting the predetermined analog input value;
Outputting a plurality of sets of data of the predetermined analog input value and the output data value as the correction data to the encoder;
The encoder is
A conversion logic for converting the logic signal into the predetermined code is changed based on the correction data from the digital correction circuit.

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