JP2009009596A - Microcomputer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve usability and efficiency of microcomputer in debugging. <P>SOLUTION: A microcomputer (5) comprises an emulation control means (EMC) capable of outputting a control signal for emulation control, a central processing unit (CPU) capable of controlling operation of the emulation control means, and a performance counter (PCNT). The central processing unit comprises a means for detecting subroutine branch instruction execution, exception handling execution, and their return instruction execution therefor, and changes with the control signal into an emulation program running state based on a result of detection by the detection means. Thus, user program execution time is allowed to be detected, and usability and efficiency of microcomputer in debugging are improved. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an on-chip debugging technique such as a data processing apparatus, and more particularly to a system LSI such as a microcomputer having a built-in emulation function, and a technique that is effective when used in its development apparatus.

  In order to develop an application system using a single chip microcomputer, a so-called microcomputer development apparatus called an in-circuit emulator is used. The microcomputer development device is a single-chip microcomputer that is connected to a system development device such as a personal computer and an application system (user system) under development via a cable or the like and is to be attached to the application system. It functions as a debugger while acting as a function of the target microcomputer), and supports the development of software or application systems. This microcomputer development apparatus is equipped with an evaluation emulation processor called an evaluation chip corresponding to the single chip microcomputer. Emulation processor facilitates development of microcomputer development equipment by adding dedicated functions to output the internal state of the microcomputer and control the operation of the microcomputer to functions that include a single-chip microcomputer. To be. The microcomputer development apparatus is described in, for example, “LSI Handbook”, pages 562 and 563 issued on November 30, 1984, and the emulation processor is described in, for example, No. 106840 and the like.

  When an in-circuit emulator is used, a connector provided at the end of a cable extending from the in-circuit emulator is often connected to a microcomputer socket on an application system such as a user system. When the emulation processor in the in-circuit emulator is connected to the application system via the cable or socket described above, the signal delay increases, noise occurs in the signal line, or the accuracy of the analog signal decreases. There is.

  In an in-circuit emulator, it is desired to use a debugging function without stopping execution of a user program. This is because the microcomputer uses the input / output function to control the application system. If the execution of the user program is stopped, the application system cannot be controlled and the operation cannot be continued. This is because it becomes.

  Japanese Patent Laid-Open No. 8-328898 discloses an example of a technique in which a emulation DMA controller is provided in the emulation processor, a bus right is obtained from the CPU, and a required data transfer is described. In this example, a DMA transfer memory is prepared on an in-circuit emulator, and the emulation DMA controller is controlled. Two DMA transfer memories are prepared, and addresses are switched to perform read / write with the host CPU.

  Such a DMA controller has a transfer source address, a transfer destination address, a transfer counter, a control register, and the like, and each channel has a start factor selection and acceptance logic. Many sets of the above registers must be provided. Also, having a dedicated DMAC requires the microcomputer to have logic such as transfer of bus rights in addition to the DMAC logic. These increase the logical and physical scale of the entire semiconductor integrated circuit device. Furthermore, the increase in scale increases manufacturing costs. In the above example, it is also described that an existing DMAC is shared as an emulation DMAC, but this limits the use of the user. For example, in an application in which DMAC is used to perform motor control, data transfer with various interfaces, etc., a large number of DMAC channels are required, and it is not desirable to allocate resources to the emulation DMAC.

  Built-in data transfer device, so-called data transfer controller (DTC), in which information to be placed in the above registers is placed on a general-purpose RAM (random access memory) with a high storage density, preventing an increase in logical and physical scale Examples of the literature described for the above are JP-A-1-125944 and JP-A-7-129537.

  Japanese Patent Laid-Open No. 7-129537 further discloses that at least one information of an address, data, the number of transfer data, or a transfer method of data transfer performed by the data transfer apparatus can be stored in the storage means. The above information describes an example including information that can specify data transfer by a plurality of sets of at least one piece of information in one operation of the data transfer apparatus.

JP 63-10684 A JP-A-8-328898 Japanese Patent Laid-Open No. 1-125944 Japanese Patent Laid-Open No. 7-129537

  As an emulator function, it is necessary to measure the execution time of the user program. This is to check whether the processing of the user system is within the required time or to examine the breakdown of the processing time when the processing speed needs to be improved. Since many user programs are developed using C language or the like, it is desirable to be able to measure the processing time in units of functions.

  On the other hand, there are increasing examples of debugging using an on-chip debugging method as a form of emulator. In other words, a debugging function and interface are provided on an actual chip such as a microcomputer, which is mounted on a user system, and connected to a card emulator in the form of a card using the debugging interface. The card emulator is inserted into a card slot of a host computer such as a personal computer for debugging.

  If such an on-chip debugging method is employed, since the microcomputer is mounted on the user system, there is no cause for causing an undesired delay, increasing noise, or reducing the accuracy of analog or the like. If the debugging interface is disconnected, the user system can be used as it is. A semiconductor integrated circuit is also excellent in development efficiency because it is not necessary to separately develop an emulation processor and a mass production microcomputer, and is particularly suitable for a small variety of products such as a system LSI. In addition, even after the application system is built into the final product, it can be used for operation analysis and adjustment. In such an on-chip debugging system, the debugging function is dedicated to debugging and is not necessary for actual operation. Therefore, it is desirable to minimize the logical and physical scale for debugging in order to reduce the manufacturing cost of the microcomputer. Further, since the interface with the emulator is limited in the number of signal lines, it is difficult to input / output sufficient debugging information.

  An object of the present invention is to provide a technique for improving debugging efficiency without complicating a microcomputer system and increasing an interface signal.

  Another object of the present invention is to provide a technique for monitoring or rewriting the contents of a required memory of a microcomputer during operation of a user system.

  Another object of the present invention is to provide a technique for easily measuring the processing time for each function in a program using C language or the like.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  A representative one of the inventions disclosed in the present application will be briefly described as follows.

  That is, a debugging interface and a data transfer device that arranges transfer information in a memory such as a RAM and performs data transfer by reading the transfer information. The debug interface includes a data register, an instruction register, Means for decoding the contents of the instruction register, and when the instruction has a predetermined content, generates a transfer request to the data transfer device, and the data transfer device, according to the given transfer information, Perform data transfer to and from the memory.

  The data transfer apparatus is also used as a user function, and this switching is recognized by a vector given in the same way as the activation request.

  The bus control means arbitrates the bus right between the data transfer device and the central processing unit, regardless of whether for debugging or for the user. It also controls bus access between the data transfer device and the central processing unit.

  When providing a means for generating a break request by monitoring the internal bus such as an address or tracing the state of the internal bus, avoid the undesired break request or the undesired trace. Ignore the state of the internal bus at.

  In addition, break processing is performed so that a predetermined status signal is output when a subroutine branch, subroutine return, exception processing branch, and exception processing return instruction is executed.

  Furthermore, it is possible to incorporate a performance counter that can be counted by the signal or a signal indicating break processing.

  According to the above means, by adding the start command of the data transfer device to the user debug interface circuit, the number of signal lines can be reduced and the addition to the original microcomputer function can be minimized, and the debugging function It is possible to read or write the contents of a desired address by minimizing the increase in the time and minimizing the time for stopping the operation of the central processing unit.

  The data transfer apparatus is also used as a user function. Therefore, the bus arbitration is the same as the user function, the transfer request can be shared with the user function, the increase in logical scale is suppressed, and the microcomputer system is also used. Is not complicated. The data transfer apparatus can place transfer information on a memory, make it possible to place it in the emulation controller, and eliminate restrictions on user resources.

  If there is a means to monitor the internal bus such as an address to generate a break request or trace the internal bus state, ignore the internal bus state during the debugging data transfer, and the user program It is possible to suppress inconveniences that are not caused by execution, for example, a break occurs in debug data transfer or is acquired by a trace. The debug data transfer may be acquired by tracing. Note that it may be possible to select whether or not the debug data transfer is acquired in the trace.

  The performance counter can easily measure the execution time of each function without increasing the emulation signal.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, the time for stopping the execution of the user program by starting the data transfer device, reading the required data, writing to the data register of the debug interface, and enabling the data to be output from the debug interface The required memory contents can be read with a minimum. In addition, by reversing the direction of data transfer, the required data can be rewritten. As a result, the usability and efficiency of microcomputer debugging can be improved.

  FIG. 2 shows a configuration example of an on-chip debugger including a microcomputer according to the present invention.

  The on-chip debugger includes a card emulator 2, an interface cable 3, a host computer 4, and a microcomputer 5 with a debugging function. The card emulator 2 takes the form of, for example, a PCMCIA card or a PCI card. The host computer is a personal computer equipped with a PC slot such as a PCMCIA slot or a PCI slot. The microcomputer 5 is provided with a flash memory for storing a user program to be debugged. The microcomputer 5 with a built-in debugging function is mounted on a printed circuit board PCB as a user system.

  The card emulator 2 is inserted into the PC card slot of the host computer 4, and the card emulator 2 and the printed wiring board PCB are connected via an interface cable 3 that realizes a required communication means. Then, in response to a command input to the host computer 4, the user program is downloaded to a flash memory or the like and debugged.

  By using the host computer 4 as a portable personal computer or the like, debugging in an actual use state is also possible. For example, when the application system is a digital camera, debugging and adjustment outdoors are possible.

  FIG. 1 shows a configuration example of the microcomputer.

  The microcomputer 5 is not particularly limited, but is a single-chip type, and a ROM (Read Only Memory) that is a memory for storing a CPU (Central Processing Unit) that controls the whole, an interrupt controller INT, a processing program of the CPU, and the like. Functional blocks or modules of a CPU working area and a RAM (random access memory) that can be used as a temporary memory and stack memory for data, a data transfer device DTC, a bus controller BSC, and an input / output device I / O These are functions open to the user. A flash memory can be applied to the ROM.

  Examples of the input / output device I / O include a timer, a serial communication interface (SCI), an A / D converter, an input / output port (IOP), a clock oscillator (CPG), and the like. Each input / output port is also used as an external interrupt input or as an input / output of a timer, SCI, or A / D converter. That is, the timer, the SCI, and the A / D converter each have an input / output signal, and are input / output to / from the outside through a terminal also used as an input / output port. Similarly, the address bus, data bus, and bus control signal input / output can also be used.

  As a debugging function, a memory ERAM in which a part of the emulation program is stored is provided, an emulation control circuit EMC that forms a control signal for a module related to emulation, an internal bus such as an address, or a CPU program counter is monitored, A break controller EBC that requests the CPU to stop program execution at a breakpoint specified by the user during emulation, a trace buffer TBF for collecting signals on the bus BUS during emulation, an external control signal, A user debug interface circuit UDI that receives a transfer clock and synchronizes with the transfer clock and inputs a command and outputs required contents to the outside, and a performance counter P that measures a processing time And the like NT, block or these functional modules are connected to each other via an internal bus BUS including an address bus and a data bus.

  These are formed on a single semiconductor substrate by a known semiconductor manufacturing technique. However, as a multichip module or the like, a configuration in which a plurality of semiconductor integrated circuits are enclosed in a single package may be employed.

  The CPU includes an instruction decoder, a break request reception function, a break instruction execution function, a break return instruction execution function, and the like. Further, when a signal specifying a function break described later is in an active state, break exception processing can be performed after execution of a subroutine branch instruction, subroutine return instruction, exception processing, and exception processing return instruction.

  When the break exception process is executed, although there is no particular limitation, the process branches to the memory ERAM on the emulation control circuit EMC.

  The emulation control circuit EMC has a required control register and the like, and controls the microcomputer with a built-in debug function according to control by the CPU in a predetermined break mode. A signal FCBRK designating the function break is supplied to the CPU. A break mode signal BRKM indicating a break mode in which execution of the user program is stopped and a debug program is being executed is supplied to the break controller EBC, the performance counter PCNT, and the trace buffer TBF.

  The debug interface UDI performs data communication with an external card emulator as needed under the control of the CPU in a predetermined break mode. Although not particularly limited, this data communication is serial communication, and the number of signal lines for emulation is reduced.

  In this example, the execution time for each function can be measured in a mode other than the break mode. For example, the performance counter PCNT is provided with two 48-bit counters, and is configured so that the occurrence of a state to be counted can be set independently.

  The bus controller BSC performs bus right arbitration at a predetermined timing based on the bus right request signal from the CPU and the data transfer device DTC. This bus arbitration result is transmitted to the CPU, the data transfer device DTC and other modules as a bus acknowledge signal BSACK. The bus controller BSC controls the required bus access according to the built-in memory, internal I / O register, external address, and the like.

  The interrupt controller INT inputs the timer, SCI, A / D converter, and external input interrupt signals, and outputs an interrupt request signal to the CPU or a transfer request to the data transfer device DTC.

  When an interrupt request signal is given to the CPU, the CPU interrupts the processing being executed, branches to the predetermined processing routine through the interrupt exception processing state, performs the desired processing, and clears the interrupt factor. To do. At the end of the predetermined processing routine, a normal return instruction is given, and the interrupted process is resumed by executing this instruction.

  When a transfer activation request is given to the data transfer device DTC, the data transfer device DTC activates the bus right request signal. When the bus right can be acquired, the transfer information is read from a predetermined address and data is transferred based on the transfer information. Transfer is performed, and then the transfer information is written back to the original address.

  When the reset signal RES is given to the microcomputer 5, the microcomputer 5 including the CPU is reset. When this reset is released, the CPU performs reset exception processing from a predetermined address on the emulation control circuit EMC and waits for a command input via the user debug interface circuit UDI. During this time, other user functions continue to be in the reset state. After performing the required processing according to the input command, it branches (returns) to the user program. Thereafter, an instruction is read from the ROM or the like, decoded, and based on the decoded contents, data processing or data transfer with the RAM, timer, SCI, A / D converter, input / output port, or the like is performed. That is, the CPU refers to data input from a timer, SCI, A / D converter, input / output port, etc., or an instruction stored in a ROM or the like while referring to device status or instructions (switch, volume, etc.) Based on the result, the signal is output to the outside and the device is controlled using the input / output port, the timer, and the like.

  FIG. 3 shows a configuration example of the user debug interface circuit UDI.

  The host interface (interface with the card emulator) has control signal input (reset, mode, clock), data input, and data output. Data is input / output in accordance with the control signal. Selection of a register to be described later is performed by a control signal input (mode).

  The user debug interface circuit UDI has an instruction register SDIR, a status register SDSR, and a data register SDDR. The instruction includes a reset request, reset request release, break request, break request, DTC activation request (two types), etc., and decodes the contents of the instruction register to generate a predetermined control signal.

  Status register SDSR includes an SDTRF flag. When SDTRF is cleared to logical value “0”, the data register SDDR is writable from the inside of a microcomputer such as a CPU, and when the SDTRF flag is set to logical value “1”, the host interface Is ready to be transferred to the data register SDDR.

  Further, it is connected to the internal bus and can be read / written from the CPU in the break mode. Further, the data transfer device DTC can read / write the data register SDDR according to the status EDTC indicating the data transfer device DTC for debugging data transfer.

  FIG. 4 shows a configuration example of the data transfer device DTC.

  The DTC activation request of the user debug interface circuit UDI and the interrupt request of the input / output device (I / O) of the microcomputer are input to the interrupt controller. These are designated by the corresponding DTC enable register (DTER) as to whether an interrupt request to the CPU or a transfer request to the DTC is to be performed, respectively, the priority order is determined, and together with the vector corresponding to the selected factor An interrupt request or a transfer request is given.

  The data transfer device DTC takes in the DTC transfer request DTCRQ and the vector DTVEC. When a transfer request is generated, the bus right is requested from the bus controller by DTBRQ, the bus right is confirmed by BSACK, the transfer information start address is read from a predetermined vector, and the transfer information start address is Transfer information (mode, transfer source / destination address, counter) is read and stored in the data transfer device DTC, and data transfer is performed according to the transfer information. After the data transfer, the updated transfer information is written back to the original address.

  FIG. 5 shows a memory map of the microcomputer 5.

  The vector address of the user DTC is assigned to the ROM area, but the debug vector address of the data transfer device DTC is arranged in the emulation control circuit EMC, for example, the memory ERAM.

  The transfer information is arranged at an address indicated by the vector. Normally, DTC transfer information for users is placed in RAM. The DTC transfer information for debugging is arranged in ERAM or RAM. If it is arranged in the ERAM, the user's resources are not used, so that the user is not restricted. When the ERAM is not used, more emulation programs can be arranged in the ERAM, and the execution efficiency of the emulation program can be improved.

  FIG. 6 shows the required operation timing in the debug data transfer.

  When a predetermined DTC activation request command is input to the debugging interface UDI, the debugging interface UDI generates an activation request. This is accepted by the interrupt controller, the priority order is determined, and at a predetermined timing, a transfer request and a vector indicating debug data transfer are given to the data transfer device DTC.

When the data transfer device DTC receives a transfer request, it requests a bus right. When the data transfer device DTC receives the transfer request, the data transfer device DTC reads transfer information from an address given by a vector. At this time, the vector indicating the data transfer for debugging is indicated by the fact that the upper bits (bits 7 to 2) are all 1, and in this case, the address (parameter such as an acebase of the ERAM) in the emulation control circuit EMC is used. Is the first address). An example of this logical description is shown below.
always @ (vec)
if (vec [7: 2] == 6′b111111)
dt_vec_out = {asebase, vec [1: 0], 2′b00};
else
dt_vec_out = {20′h00000, 2′b00, vec, 2′b00};
That is, transfer information is read from an address indicated by a vector, and data transfer is performed based on the read information. When the status signal EDTC indicating the debug data transfer is activated, the SDIF is set to the logical value “1” in accordance with the status signal EDTC and the reading or writing of the UDI data register. Thereafter, the transfer information is written back to the original address. By rewriting the transfer information, it is possible to repeatedly use the contents of the same address, monitoring the change, and a plurality of DTC transfers can be sequentially performed.

  The data transfer device DTC acquires the bus right for a vector read cycle, transfer information read cycle, data transfer cycle, and transfer information write cycle cycle (for example, 9 bus cycles when the transfer information is read / written three times). When the CPU loses the bus right, the execution of the user program is temporarily stopped, but this time is shorter than the time when the break exception processing and the emulation program are executed.

  The emulation functions are as follows.

  That is, an instruction is input to the instruction register (SDIR) via the host interface, a DTC transfer request is generated, and the necessary data transfer is performed, and then via the data register (SDDR) of the user debug interface circuit UDI, The contents of the memory (or I / O register) can be read.

  This procedure is as follows.

  First, in the execution state of the emulation program, the interrupt controller and DTC transfer information are set in advance.

  The contents of the memory of the microcomputer 5 can be read by the following procedure.

  (1) In a predetermined sequence, the state machine of the debugging interface UDI is initialized, and the SDTRF bit is set to the logical value “1”.

  (2) A DTC transfer request command is input from the emulator to the user debug interface circuit UDI. Data is copied from the shift register to the instruction register.

  (3) The emulator confirms that the SDTRF bit is a logical value “1”.

  (4) Although not particularly limited, dummy data is transferred in order to clear the SDTRF bit.

  (5) A DTC transfer request to the interrupt controller INT is made, a transfer request and a predetermined vector are given to the data transfer device DTC, and the data transfer device DTC is activated.

  (6) The data transfer device DTC performs data transfer from the memory to the data register SDDR of the user debug interface circuit UDI based on preset transfer information. At the time of debugging data transfer, the data transfer device DTC activates a status signal EDTC indicating debugging data transfer. When the status signal EDTC is active, the break controller and the trace buffer ignore the address and data of the data transfer device DTC that are not based on the execution of the user program, and do not acquire an undesired break or trace. Like that. The user debug interface circuit UDI monitors the EDTC signal and sets the SDTRF bit to a logical value “1” at a predetermined timing such as data register write.

  (7) Next, the emulator 2 monitors the SDTRF bit, confirms that the reading of the data transfer device DTC has been completed when the logical value is “1”, and takes in the data. When rewriting the contents of the memory of the microcomputer 5, the following points are different from the above.

  (8) The emulator 2 confirms that the SDTRF bit is a logical value “1”. If the SDTRF bit is a logical value “1”, data can be transferred to the data register SDDR. Transfer to the data register SDDR.

  (9) The emulator 2 observes the logical value “1” in the SDTRF bit and confirms the end of writing of the data transfer device DTC.

  FIG. 7 shows a debugging data transfer method.

  Using the two DTC activation commands, the above procedure is executed twice as a set, information of an arbitrary plurality of addresses (adr1 to 4) can be taken out and displayed on the host computer 4.

  The card emulator 2 first writes the second transfer information in the UDI data register. For example, a transfer instruction from the address adr1 to the UDI data register is issued.

  The DTC activation request command 1 is input to activate the first DTC transfer. In the first DTC transfer, the second transfer information on the UDI data register is stored in the second DTC transfer information area.

  Next, the DTC activation request command 2 is input to activate the second DTC transfer. In the second DTC transfer, the designated address (adr1) is stored in the UDI data register.

  Then, the UDI data register is read out to the host computer 4. This may be executed as many times as necessary (in this example, four times), changing the designated address (adr1 to 4). The transfer information from the emulator 2 can be displayed on a display device (monitor) of the host computer 4 in a desired arrangement such as a desired window.

  Instead of having two DTC transfer request commands, chain transfer can also be used. In the chain transfer, for example, as described in Japanese Patent Application Laid-Open No. 7-129537, data transfer is performed based on a plurality of pieces of transfer information arranged at consecutive addresses in response to a single activation request. Data input to the data register of the debug interface UDI is stored at the address of the second transfer information by the first transfer information. Thereafter, data transfer is performed based on the second transfer information.

  Various modifications can be made corresponding to the number of bytes of the data register of the debug interface UDI and the arrangement of the transfer information of the data transfer device DTC.

  FIG. 8 shows a block configuration of control logic necessary for a function break of the CPU, and FIG. 9 shows an operation timing of the function break.

  When the function break permission bit of the emulation control circuit EMC is set to the logical value “1”, the function break permission signal FCBRK is activated. The CPU is a logical product of a subroutine branch instruction, a subroutine return instruction, a user exception process (including an interrupt), and a decode signal dec_fcb for executing the user exception process return instruction, and the operation code of the break exception process is stored in the instruction register. And break exception handling is executed. With the instruction code executed by the CPU as opcode, this logic can be described as follows.

always @ (possible clk)
if (rst) opcode <= 'reset
. . . .
else if (load & FCBRK & dec_fcb & ~ brkm)
opcode <= 'break
. . . .
That is, at the end of execution of the instruction, the load signal indicating the load of the next instruction is activated, and at this time, the function break permission signal FCBRK is activated, and after the execution of the instruction (dec_fcb), If not (~ brkm), the instruction code 'break' indicating break exception handling is taken in. Note that brkm is a signal equivalent to BRKM in FIG.

  By executing the instruction code 'break, break exception processing is realized, and at this time, the break mode signal brkm is activated. As a result, the performance counter PCNT is stopped. The execution time of the user program can be obtained by reading the contents of the performance counter and subtracting it from the previous performance counter value during emulation processing in the break mode. In addition, the execution time of the corresponding function can be measured by obtaining the execution time in the emulation process after the execution of the subroutine return instruction. If a function is called multiple times or an exception process such as an interrupt is inserted, the break also occurs in that case, and the time can be measured and deducted.

  FIG. 10 shows an outline of the CPU development environment.

  The user creates a program in C language or assembly language using various editors. This is usually created by dividing it into a plurality of modules. The C compiler 101 inputs each C language source program created by the user and outputs an assembly language source program or an object module.

  The assembler 102 inputs an assembly language source program and outputs an object module.

  The linkage editor 103 inputs a plurality of object modules generated by the C compiler and assembler, resolves external references and relative addresses of each module, combines them into one program, and outputs a load module. .

  The load module can be input to the simulator / debugger 104 to simulate the operation of the CPU on a system development device such as a personal computer, display the execution result, and analyze and evaluate the program. Further, it is input to the emulator 105 and written in the ROM such as the flash memory of the microcomputer 5 in the break mode state via the user debug interface circuit UDI to be operated on an actual application system. The so-called in-circuit emulation is performed, and the actual operation of the microcomputer 5 as a whole can be analyzed and evaluated. By taking the form shown in FIG. 2, it is possible to rewrite the ROM such as a flash memory at any time, which is suitable for debugging or emulation.

At this time, for example, the function seq is used as follows.
if (flag0)
seq ();
else
seqrep & = 1;
At this time, it is compiled as follows.

BTST # 0, flag
BEQ L1
JSR @_seq
BRA L2
L1: BCLR # 0, seqrep
L2:
The function seq becomes the subroutine branch instruction JSR, the function processing is described after the address_seq, and at the end, the subroutine return instruction RTS is arranged as follows.
_Seq:. . .
RTS
By using the function break, it is possible to measure the processing time of the function seg from JSR execution to RTS execution.

  According to said example, the following effects are obtained.

  (1) The data transfer device DTC is activated by a command of the debug interface UDI, reads required data, writes to the data register of the debug interface, and enables the data to be output from the debug interface. Thus, it is possible to read the contents of the required memory while minimizing the time for stopping execution of the user program. In addition, by reversing the direction of data transfer, the required data can be rewritten. As a result, the usability and efficiency in debugging of the microcomputer 5 can be improved.

  (2) By arranging transfer information such as an address register in the data transfer device DTC in the RAM, the use of user resources is minimized, and at least without limiting the data transfer resources of the user, The effect (1) can be obtained. This makes it possible to use the memory ERAM for emulation, and the limited memory ERAM can be used effectively. If there is a large amount of memory to be monitored or rewritten at the initial stage of debugging, the user RAM can be used and the memory ERAM can be used for the emulation program. When a small number of memories are monitored or adjusted in a state where debugging is almost completed, the memory ERAM is not used to restrict user resources. By giving a vector to the data transfer device DTC and identifying the data transfer for debugging, the number of factors to be used can be easily increased.

  (3) Using a plurality of DTC activation request commands or the chain transfer function of the data transfer device DTC, transfer information is input via the debug interface and the data transfer device DTC, and then the required data transfer is performed. Thus, it is possible to read / write any address without causing the CPU to break. The transfer information can be input and the data transfer can be performed by the same means, and the resources can be effectively used. In addition, any address can be designated and read or written at any time, and this can be repeated to read or write a plurality of addresses, thereby further improving usability and efficiency.

  (4) Since the data transfer device DTC is shared with the user, it is possible to share the priority determination of the activation request and the bus arbitration, and the development efficiency of the microcomputer itself without complicating the microcomputer system. Can be improved. Even if a second data transfer device (DMAC or the like) is added, it is only necessary to implement the function as a user function, and there is no direct influence on the debugging function, which may impair development efficiency and effective use of resources. Absent. Under the control of the bus controller, any address can be accessed regardless of the type of the bus interface at the address.

  (5) By using the debug interface, it is possible to emulate with a small number of signal lines, enable emulation in a mounted state, and eliminate the need to separately develop a mass production microcomputer.

  (6) The function execution time can be easily measured by the subroutine branch, the exception processing execution, and the function break function that breaks after execution of these return instructions. By using the performance counter PCNT that stops counting in the break state, it is possible to easily measure the execution time of the function without increasing the interface signal for emulation.

  (7) By adding a decoding circuit to the CPU, it is not necessary to set breakpoints. Since the decoding circuit of the CPU can be shared by decoding other instruction functions and logic synthesis, an increase in the logic scale can be minimized.

  Although the invention made by the present inventor has been specifically described above, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, module functions and signal input / output can be arbitrarily changed.

  It is not necessary to provide a DTC enable register for a DTC activation request by UDI. If this is provided, a user interrupt can be executed by the user debug interface circuit UDI.

  The function of the present invention can also be used as an in-circuit emulator by providing a debugging interface UDI in an emulation processor.

  Function breaks can also be used in emulation processors or in-circuit emulators.

  The details of the data transfer device can be variously modified. For example, the control register, transfer information arrangement / configuration, data transfer mode, and the like can be arbitrarily set. As a data transfer mode, a repeat mode, a block transfer mode, or the like can be applied. In the chain transfer, the second transfer can be performed only when the counter value of the first transfer information becomes zero.

  In the above description, the case where the invention made mainly by the present inventor is applied to an on-chip debugger including a card emulator which is a field of use that is the background of the invention has been described. Can be applied.

  The present invention can be applied on the condition that it has at least an emulation or debugging function and interface.

It is a block diagram of a configuration example of a microcomputer according to the present invention. It is explanatory drawing of the structural example of the on-chip debugger containing the said microcomputer. It is a block diagram of a configuration example of a debugging interface included in the microcomputer. It is a block diagram of a configuration example of a data transfer device included in the microcomputer. It is explanatory drawing of the memory map in the said microcomputer. It is a timing diagram of the data transfer for debugging in the said on-chip debugger. It is explanatory drawing of the data transfer method for debugging in the said on-chip debugger. It is a block diagram of a configuration example of control logic necessary for a function break of a CPU in the on-chip debugger. It is an operation timing diagram of a function break in the on-chip debugger. It is a schematic explanatory drawing of the development environment of CPU contained in the said microcomputer.

Explanation of symbols

2 Card emulator 3 Interface cable 4 Host computer 5 Microcomputer CPU Central processing unit DTC Data transfer device BSC Bus controller ROM Flash memory RAM Random access memory I / O I / O device UDI User debug interface circuit TBF Trace buffer PCNT Performance counter EBC Break controller INT interrupt controller EMC emulation control circuit

Claims (5)

An emulation control means capable of outputting a control signal for emulation control, and a central processing unit capable of controlling the operation of the emulation control means,
The central processing unit includes means for detecting execution of a subroutine branch instruction, execution of exception processing, and execution of their return instructions, and transitions to an emulation program execution state based on the detection result of the detection means by the control signal. A microcomputer characterized by that.   3. The execution time of the subroutine branch instruction, the exception handling execution, and the execution of the return instruction can detect a user program execution time by using a function break. Microcomputer.   2. The microcomputer according to claim 1, further comprising: a counter that counts in response to execution of a user program; and means for stopping the counting operation of the counter in the emulation program execution state.   4. The microcomputer according to claim 3, wherein a user program execution time can be detected based on a count value of the counter. An emulation control means capable of outputting a predetermined control signal for emulation control, and a central processing unit capable of controlling the operation of the emulation control means,
A microcomputer characterized in that the central processing unit can execute subroutine branch instruction execution, exception processing execution, and return instruction thereof.

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