JP2004086447A - Microcomputer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve debugging efficiency without complicating the system of a microcomputer and without increasing an interface signal. <P>SOLUTION: By a command of an interface for debugging (UDI), a data transfer unit (DTC) is started up, required data are read and written in a data register of the interface for debugging to allow the data to be outputted from the interface for debugging so that time for stopping the execution of a user program is minimized. The contents of a required memory can be read, and the required data can be rewritten by reversing the direction of data transfer. Thereby, the improvement in usability and efficiency in the debugging of the microcomputer (5) is achieved. <P>COPYRIGHT: (C)2004,JPO

Description

【００６０】
すなわち、ベクタに示されるアドレスから転送情報がリードされ、これに基づいてデータ転送が行われる。デバッグ用データ転送を示すステータス信号ＥＤＴＣが活性化されると、ステータス信号ＥＤＴＣと、ＵＤＩデータレジスタのリードまたはライトに従って、ＳＤＩＦが論理値“１”にセットされる。その後、転送情報を元のアドレスに書き戻す。転送情報を書き戻すことにより、同じアドレスの内容を繰返しリードし、変化を監視するような、繰返し利用を可能にでき、また、複数のＤＴＣ転送を順次行うことができる。
【００６１】
データ転送装置ＤＴＣは、ベクタのリード、転送情報のリード、データ転送、転送情報のライトのサイクル（例えば、転送情報を３回リード／ライトする場合、９バスサイクル）の期間バス権を獲得する。ＣＰＵがバス権を失うことによって、ユーザプログラムの実行が一時停止されるが、この時間は、ブレーク例外処理や、エミュレーションプログラムが実行される時間に比較して短い。
【００６２】
エミュレーションの機能としては以下の通りである。
【００６３】
すなわち、ホストインタフェースを介して、インストラクションレジスタ（ＳＤＩＲ）へインストラクションを入力しＤＴＣ転送要求を発生させ、所要のデータ転送を行った後、ユーザデバッグインタフェース回路ＵＤＩのデータレジスタ（ＳＤＤＲ）を経由して、メモリ（またはＩ／Ｏレジスタ）の内容を読み出すことができる。
【００６４】
この手順は以下の通りである。
【００６５】
まず、エミュレーション用プログラム実行状態で、あからじめ割込みコントローラや、ＤＴＣの転送情報の設定を行う。
【００６６】
マイクロコンピュータ５のメモリの内容は、以下の手順でリードすることが出きる。
【００６７】
（１）所定のシーケンスで、デバッグ用インタフェースＵＤＩのステートマシンが初期化され、ＳＤＴＲＦビットが論理値“１”にセットされる。
【００６８】
（２）エミュレータからユーザデバッグインタフェース回路ＵＤＩへＤＴＣ転送要求コマンドを入力する。シフトレジスタからインストラクションレジスタへデータがコピーされる。
【００６９】
（３）エミュレータはＳＤＴＲＦビットが、論理値“１”であることを確認する。
【００７０】
（４）特に制限はされないものの、ＳＤＴＲＦビットをクリアするために、ダミーデータの転送を行う。
【００７１】
（５）割込みコントローラＩＮＴへのＤＴＣ転送要求が行われ、データ転送装置ＤＴＣへ転送要求と所定のベクタが与えられ、データ転送装置ＤＴＣが起動される。
【００７２】
（６）データ転送装置ＤＴＣは、予め設定された転送情報に基づきメモリからユーザデバッグインタフェース回路ＵＤＩのデータレジスタＳＤＤＲへデータ転送を行う。デバッグ用データ転送時には、データ転送装置ＤＴＣはデバッグ用データ転送を示すステータス信号ＥＤＴＣを活性化する。このステータス信号ＥＤＴＣが活性状態のときは、ブレークコントローラやトレースバッファは、ユーザのプログラムの実行に基づかない、データ転送装置ＤＴＣのアドレスやデータを無視し、不所望のブレークやトレースの取得を行わないようにする。ユーザデバッグインタフェース回路ＵＤＩは、ＥＤＴＣ信号をモニタし、データレジスタライトなどの所定のタイミングでＳＤＴＲＦビットを論理値“１”にセットする。
【００７３】
（７）次にエミュレータ２はＳＤＴＲＦビットをモニタし、論理値“１”であることにより、データ転送装置ＤＴＣのリードが終了していることを確認し、データを取り込む。マイクロコンピュータ５のメモリの内容を書換える場合、上記に対して以下の点で相違する。
【００７４】
（８）エミュレータ２はＳＤＴＲＦビットが、論理値“１”であることを確認し、ＳＤＴＲＦビットが論理値“１”ならデータレジスタＳＤＤＲへデータ転送が可能な為エミュレータから、メモリに書き込みたいデータをデータレジスタＳＤＤＲへ転送する。
【００７５】
（９）エミュレータ２はＳＤＴＲＦビットが論理値“１”を観測し、データ転送装置ＤＴＣのライト終了を確認する。
【００７６】
図７には、デバッグ用データ転送方法が示される。
【００７７】
２つのＤＴＣ起動コマンドを使用して、上記手順を２回１組で実行し、任意の複数のアドレス（ａｄｒ１〜４）の情報を取り出して、それをホストコンピュータ４上に表示することができる。
【００７８】
カードエミュレータ２は、まず、ＵＤＩデータレジスタに第２の転送情報を書き込む。例えば、アドレスａｄｒ１からＵＤＩデータレジスタへの転送指示がなされる。
【００７９】
ＤＴＣ起動要求コマンド１を入力して、第１のＤＴＣ転送を起動する。第１のＤＴＣ転送では、上記ＵＤＩデータレジスタ上の第２の転送情報が、第２のＤＴＣ転送情報領域に格納される。
【００８０】
次に、ＤＴＣ起動要求コマンド２を入力して、第２のＤＴＣ転送を起動する。第２のＤＴＣ転送では、指定されたアドレス（ａｄｒ１）が、ＵＤＩデータレジスタに格納される。
【００８１】
そして、上記ＵＤＩデータレジスタをホストコンピュータ４へ読み出す。これを必要な回数（本例では４回）、指定するアドレスを変えて（ａｄｒ１〜４）実行すればよい。エミュレータ２からの転送情報は、ホストコンピュータ４の表示装置（モニタ）に、所望のウィンドウなどの所望の配置で表示することができる。
【００８２】
２つのＤＴＣ転送要求コマンドを持つ代わりに、チェイン転送を用いることもできる。チェイン転送は、例えば特開平７−１２９５３７号公報などに記載されている通り、１回の起動要求に対し、連続したアドレスに配置された複数の転送情報に基づいて、データ転送が行われる。第１の転送情報によって、デバッグ用インタフェースＵＤＩのデータレジスタに入力されたデータを、第２の転送情報のアドレスに格納する。その後第２の転送情報に基づき、データ転送を行う。
【００８３】
尚、デバッグ用インタフェースＵＤＩのデータレジスタのバイト数や、データ転送装置ＤＴＣの転送情報の配置に対応して、種々の変形が可能である。
【００８４】
図８にはＣＰＵの関数ブレークに必要な制御論理のブロック構成が示され、図９には関数ブレークの動作タイミングが示される。
【００８５】
エミュレーション制御回路ＥＭＣの、関数ブレーク許可ビットを論理値“１”にセットすると、関数ブレーク許可信号ＦＣＢＲＫが活性化される。ＣＰＵは、サブルーチン分岐命令、サブルーチンリターン命令、ユーザ例外処理（割込みなどを含む）、ユーザ例外処理リターン命令の実行のデコード信号ｄｅｃ＿ｆｃｂとの論理積で、ブレーク例外処理のオペレーションコードが、インストラクションレジスタに格納され、ブレーク例外処理が実行される。ＣＰＵが実行する命令コードをｏｐｃｏｄｅとして、この論理は以下のように記述できる。
【００８６】

【００８７】すなわち、命令の実行終了時点で、次の命令のロードを示すｌｏａｄ信号が活性状態とされ、このとき、関数ブレーク許可信号ＦＣＢＲＫが活性化され、上記命令実行後であり（ｄｅｃ＿ｆｃｂ）、ブレークモードでなければ（〜ｂｒｋｍ）、ブレーク例外処理を示す命令コード‘ｂｒｅａｋが取込まれる。尚、ｂｒｋｍは、図２のＢＲＫＭと等価な信号である。
【００８８】
命令コード‘ｂｒｅａｋを実行することにより、ブレーク例外処理が実現され、このとき、ブレークモード信号ｂｒｋｍが活性化される。これによってパフォーマンスカウンタＰＣＮＴは停止される。ブレークモード中のエミュレーション処理で、パフォーマンスカウンタの内容をリードし、前回のパフォーマンスカウンタの値と減算することによって、ユーザプログラムの実行時間を得ることができる。また、サブルーチンリターン命令実行後のエミュレーション処理で、上記実行時間を得ることによって、対応する関数の実行時間を計測することができる。関数が多重に呼び出されたり、割込みなどの例外処理が挿入されたりした場合は、その場合もブレークするから、その時間も計測して、差し引けばよい。
【００８９】
図１０に、上記ＣＰＵの開発環境の概略を示す。
【００９０】
使用者は、各種エディタなどを用いて、Ｃ言語乃至アセンブリ言語でプログラムを作成する。これは通常、複数のモジュールに分割して作成される。Ｃコンパイラ１０１は、使用者の作成したそれぞれのＣ言語ソースプログラムを入力し、アセンブリ言語ソースプログラム乃至オブジェクトモジュールを出力する。
【００９１】
アセンブラ１０２は、アセンブリ言語ソースプログラムを入力し、オブジェクトモジュールを出力する。
【００９２】
リンケージエディタ１０３は、上記Ｃコンパイラやアセンブラの生成した、複数のオブジェクトモジュールを入力して、各モジュールの外部参照や相対アドレスなどの解決を行い、１つのプログラムに結合して、ロードモジュールを出力する。
【００９３】
ロードモジュールは、シミュレータ／デバッガ１０４に入力して、パーソナルコンピュータなどのシステム開発装置上で、ＣＰＵの動作をシミュレーションし、実行結果を表示し、プログラムの解析や評価を行うことができる。また、エミュレータ１０５に入力して、上記ユーザデバッグインタフェース回路ＵＤＩを介して、ブレークモード状態で、上記マイクロコンピュータ５のフラッシュメモリでなるようなＲＯＭに書きこみ、実際の応用システム上などで動作させる、いわゆるインサーキットエミュレーションを行ない、マイクロコンピュータ５全体としての実動作の解析や評価を行うことができる。図２の形態をとることにより、随時フラッシュメモリでなるようなＲＯＭの書換えを行うことができ、デバッグないしエミュレーションに好適である。
【００９４】
このとき、例えば、関数ｓｅｑが以下のように使用される。

【００９５】
このとき、次のようにコンパイルされる。

【００９６】
関数ｓｅｑは、サブルーチン分岐命令ＪＳＲになり、関数の処理はアドレス＿ｓｅｑ以降に記述され、その最後には次のようにサブルーチンリターン命令ＲＴＳが配置される。

【００９７】
関数ブレークを使用することにより、ＪＳＲ実行からＲＴＳ実行までの関数ｓｅｇの処理時間を測定することができる。
【００９８】
上記の例によれば、以下の作用効果を得るものである。
【００９９】
（１）デバッグ用インタフェースＵＤＩのコマンドにより、データ転送装置ＤＴＣを起動して、所要のデータをリードし、デバッグ用インタフェースのデータレジスタにライトして、当該データをデバッグ用インタフェースから出力可能にすることにより、ユーザプログラムの実行を停止する時間を最小限にして、所要のメモリの内容をリードできる。また、データ転送の方向を逆にすることによって、所要のデータを書きかえることができる。これらにより、マイクロコンピュータ５のデバッグにおける使い勝手や効率の向上を実現できる。
【０１００】
（２）データ転送装置ＤＴＣにおけるアドレスレジスタなどの転送情報をＲＡＭに配置するようにすることにより、ユーザのリソースを使用することを最小限にし、少なくともユーザのデータ転送の資源を制限することなく、上記（１）の作用効果を得ることができる。これはエミュレーション用のメモリＥＲＡＭを使用することを可能にし、限られたメモリＥＲＡＭを有効活用することができる。デバッグ初期の段階などで、モニタしたり、書換えたりするメモリの量が多ければ、ユーザＲＡＭを使用し、メモリＥＲＡＭを、エミュレーション用プログラムに使用できる。デバッグがほぼ完了した状態で、少数のメモリのモニタや調整を行う場合には、メモリＥＲＡＭを使用して、ユーザ資源に制約を与えることがない。データ転送装置ＤＴＣにベクタを与えて、デバッグ用データ転送を識別することにより、使用する要因数の増加が容易にできる。
【０１０１】
（３）複数のＤＴＣ起動要求コマンドないし、データ転送装置ＤＴＣのチェイン転送機能を用いて、転送情報を、デバッグ用インタフェースとデータ転送装置ＤＴＣを介して入力し、その後、所要のデータ転送を行うことによって、ＣＰＵがブレークすることなく、任意のアドレスのリード／ライトを行うことができる。転送情報の入力も、データ転送も同じ手段で行うことができ、資源の有効利用を図ることができる。また、随時、任意のアドレスを指定して、リードしたりライトしたりでき、これを繰返して、複数のアドレスをリードしたりライトしたりできるから、さらに使い勝手や効率の向上を実現できる。
【０１０２】
（４）データ転送装置ＤＴＣは、ユーザと共用することから、起動要求の優先順位の判定や、バス権調停なども共用でき、マイクロコンピュータシステムを複雑にすることがなく、マイクロコンピュータ自体の開発効率を向上できる。第２のデータ転送装置（ＤＭＡＣなど）を追加しても、ユーザ機能としての当該機能を実装すればよく、デバッグ用機能には直接の影響がなく、開発効率や資源の有効利用を損なうことがない。バスコントローラの制御を受け、任意のアドレスに、当該アドレスのバスインタフェースの種類に関係なく、アクセスすることが可能である。
【０１０３】
（５）デバッグ用インタフェースを用いることにより、少ない信号線数でのエミュレーションを可能にし、実装状態でのエミュレーションを可能にし、量産用のマイクロコンピュータとを別個に開発することを不要にできる。
【０１０４】
（６）サブルーチン分岐、例外処理実行、これらのリターン命令実行後にブレークする関数ブレーク機能により、関数の実行時間の測定が容易にできる。ブレーク状態でカウントを停止するパフォーマンスカウンタＰＣＮＴを用いることにより、エミュレーション用のインタフェース信号を増加させることなく、容易に関数の実行時間を計測できる。
【０１０５】
（７）ＣＰＵにデコード回路を追加することにより、ブレークポイントの設定などが不要である。ＣＰＵのデコード回路は、ほかの命令機能のデコードと、論理合成などによって共通化が実現できるから、論理規模の増加を最小限にすることができる。
【０１０６】
以上本発明者によってなされた発明を具体的に説明したが、本発明はそれに限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。
【０１０７】
例えば、モジュールの機能や信号入出力は、任意に変更可能である。
【０１０８】
ＵＤＩによるＤＴＣ起動要求に対して、ＤＴＣイネーブルレジスタを設ける必要はない。これを設ければ、ユーザデバッグインタフェース回路ＵＤＩによって、ユーザ割り込みを実行させることもできる。
【０１０９】
デバッグ用インタフェースＵＤＩを、エミュレーション用プロセッサに設けて、インサーキットエミュレータとしても、本発明の機能を利用することもできる。
【０１１０】
関数ブレークも、エミュレーション用プロセッサないしインサーキットエミュレータでも利用可能である。
【０１１１】
データ転送装置の詳細も種々変形が可能である。例えば、制御レジスタや、転送情報の配置・構成、データ転送のモードなどは任意にできる。データ転送のモードとしては、リピートモードやブロック転送モードなどを適用することができる。チェイン転送も第１の転送情報のカウンタの値が０になったときのみ、第２の転送を行うことができる。
【０１１２】
以上の説明では主として本発明者によってなされた発明をその背景となった利用分野であるカードエミュレータを含むオンチップデバッガに適用した場合について説明したが、それに限定されるものではなく、その他のデバッガに適用することができる。
【０１１３】
本発明は少なくとも、エミュレーション乃至デバッグ用の機能とインタフェースを有することを条件に適用することができる。
【０１１４】
【発明の効果】
本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば下記の通りである。
【０１１５】
すなわち、データ転送装置を起動して、所要のデータをリードし、デバッグ用インタフェースのデータレジスタにライトして、当該データをデバッグ用インタフェースから出力可能にすることにより、ユーザプログラムの実行を停止する時間を最小限にして、所要のメモリの内容をリードできる。また、データ転送の方向を逆にすることによって、所要のデータを書きかえることができる。それにより、マイクロコンピュータのデバッグにおける使い勝手や効率の向上を実現できる。
【図面の簡単な説明】
【図１】本発明にかかるマイクロコンピュータの構成例ブロック図である。
【図２】上記マイクロコンピュータを含むオンチップデバッガの構成例説明図である。
【図３】上記マイクロコンピュータに含まれるデバッグ用インタフェースの構成例ブロック図である。
【図４】上記マイクロコンピュータに含まれるデータ転送装置の構成例ブロック図である。
【図５】上記マイクロコンピュータにおけるメモリマップの説明図である。
【図６】上記オンチップデバッガにおけるデバッグ用データ転送のタイミング図である。
【図７】上記オンチップデバッガにおけるデバッグ用データ転送方法の説明図である。
【図８】上記オンチップデバッガにおけるＣＰＵの関数ブレークに必要な制御論理の構成例ブロック図である。
【図９】上記オンチップデバッガにおける関数ブレークの動作タイミング図である。
【図１０】上記マイクロコンピュータに含まれるＣＰＵの開発環境の概略説明図である。
【符号の説明】
２　カードエミュレータ
３　インタフェースケーブル
４　ホストコンピュータ
５　マイクロコンピュータ
ＣＰＵ　中央処理装置
ＤＴＣ　データ転送装置
ＢＳＣ　バスコントローラ
ＲＯＭ　フラッシュメモリ
ＲＡＭ　ランダムアクセスメモリ
Ｉ／Ｏ　入出力装置
ＵＤＩ　ユーザデバッグインタフェース回路
ＴＢＦ　トレースバッファ
ＰＣＮＴ　パフォーマンスカウンタ
ＥＢＣ　ブレークコントローラ
ＩＮＴ　割込コントローラ
ＥＭＣ　エミュレーション制御回路[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an on-chip debugging technology for a data processing device and the like, and particularly to a system LSI such as a microcomputer having an emulation function and a technology effective when used for a development device thereof.
[0002]
[Prior art]
In order to develop an application system using a single-chip microcomputer, a microcomputer development device called an in-circuit emulator is used. The microcomputer development device is connected between a system development device such as a personal computer and an application system (user system) under development via a cable or the like, and is a single-chip microcomputer ( It has the function of a debugger while acting on behalf of the function of the target microcomputer, and supports the development of software or application systems. This microcomputer development device is equipped with an evaluation emulation processor called an evaluation chip corresponding to the single-chip microcomputer. The emulation processor can easily develop a microcomputer development device by adding functions dedicated to outputting the internal state of the microcomputer and controlling the operation of the microcomputer to the functions including the single-chip microcomputer. To be. A microcomputer development apparatus is described in, for example, pages 562 and 563 of "LSI Handbook" issued by Ohmsha on November 30, 1984, and a processor for emulation is disclosed in, for example, No. 106840, and the like.
[0003]
When an in-circuit emulator is used, a connector provided at the end of a cable extended from the in-circuit emulator is often connected to a microcomputer socket on an application system such as a user system. The emulation processor in the in-circuit emulator is connected to the application system via the above-mentioned cable or socket, so the signal delay will increase, causing noise on the signal line or reducing the accuracy of the analog signal. There is.
[0004]
In an in-circuit emulator, it is desired to use a debugging function without stopping execution of a user program. This is because the microcomputer uses the input / output function to control the application system, and when the execution of the user program is stopped, the control of the application system becomes impossible, and the operation cannot be continued. It is because it becomes.
[0005]
Japanese Patent Application Laid-Open No. H8-328898 is an example of a document that describes a technique in which an emulation DMA controller is provided in the emulation processor, a bus right is acquired from the CPU, and required data transfer is performed. In this example, a DMA transfer memory is prepared on an in-circuit emulator, and the emulation DMA controller is controlled. Two DMA transfer memories are prepared, and the addresses are switched to perform read / write with the host CPU.
[0006]
Such a DMA controller, when having a transfer source address, a transfer destination address, a transfer counter, a control register, and the like, and a selection and an accepting logic of an activation factor in each channel, performs data transfer of a large number of channels. Many sets of the above registers must be provided. In addition, having a dedicated DMAC requires the microcomputer to have logic such as transfer of a bus right in addition to the logic of the DMAC. These increase the logical and physical scale of the entire semiconductor integrated circuit device. In addition, the increase in scale increases manufacturing costs. Although the above example describes that the existing DMAC is shared as the emulation DMAC, the use of the DMAC is restricted. For example, in an application in which a DMAC is used to perform motor control, data transfer between various interfaces, and the like, a large number of DMAC channels are required, and it is not desirable to allocate resources to the emulation DMAC.
[0007]
Information to be arranged in the register is arranged on a general-purpose RAM (random access memory) having a high storage density, and a data transfer device that prevents an increase in logical and physical scales, that is, a so-called data transfer controller (DTC) is incorporated. Examples of documents describing the above-mentioned documents include JP-A-1-125944 and JP-A-7-129537.
[0008]
Japanese Unexamined Patent Application Publication No. 7-129537 further discloses that at least one of address, data, number of transfer data, and transfer method of data transfer performed by a data transfer device can be stored in a storage means. The above information describes an example including information that can designate data transfer by at least one or more pieces of information in one operation of the data transfer apparatus.
[0009]
[Problems to be solved by the invention]
As a function of the emulator, measurement of the execution time of a user program is also required. This is for confirming whether the processing of the user system can be completed within a required time, and for examining the breakdown of the processing time when the processing speed needs to be improved. Since user programs are often developed using C language or the like, it is desirable to be able to measure the processing time in function units.
[0010]
On the other hand, as an emulator, an example in which debugging is performed by an on-chip debugging method is increasing. That is, a real chip such as a microcomputer is provided with a debugging function and an interface, mounted on a user system, and connected to a card emulator in the form of a card using the debugging interface. Then, the card emulator is inserted into a card slot of a host computer such as a personal computer to perform debugging.
[0011]
According to such an on-chip debugging method, since the microcomputer is mounted on the user system, there are no factors that cause an undesired delay, increase noise, or decrease accuracy of analog or the like. Also, if the debug interface is separated, it can be used as it is as a user system. Since it is not necessary to separately develop an emulation processor and a mass-production microcomputer as a semiconductor integrated circuit, the semiconductor integrated circuit is excellent in development efficiency, and is particularly suitable for a small number of products such as a system LSI. Even after the application system is incorporated into the final product, it can be used for motion analysis and adjustment. In such an on-chip debugging system, the function for debugging is dedicated to debugging and is not necessary for actual operation. Therefore, it is desirable to minimize the logical and physical scale for debugging in order to reduce the manufacturing cost of the microcomputer. Also, since the interface with the emulator is limited in the number of signal lines, it is difficult to input and output sufficient debugging information.
[0012]
An object of the present invention is to provide a technique for improving the debugging efficiency without complicating the microcomputer system and increasing the number of interface signals.
[0013]
It is another object of the present invention to provide a technique for monitoring or rewriting the contents of a required memory of a microcomputer during operation of a user system.
[0014]
Another object of the present invention is to provide a technique for making it possible to easily measure the processing time of each function in a program using C language or the like.
[0015]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0016]
[Means for Solving the Problems]
The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.
[0017]
That is, the debugging interface includes a data transfer device that arranges transfer information in a memory such as a RAM and reads the transfer information to perform data transfer. The debug interface includes a data register, an instruction register, Means for decoding the contents of the instruction register, and when the instruction has predetermined contents, issues a transfer request to the data transfer device, and the data transfer device communicates with the data register according to given transfer information. Transfer data to and from memory.
[0018]
The data transfer device is also used as a user function, and this switching is recognized by a vector given in the same manner as the activation request.
[0019]
The bus control means arbitrates the bus rights of the data transfer device and the central processing unit regardless of whether the bus is for debugging or for the user. Further, it controls bus access between the data transfer device and the central processing unit.
[0020]
When providing a means for monitoring the internal bus such as an address to generate a break request or tracing the state of the internal bus, use the above debug data transfer to avoid an undesired break request or an undesired trace. Ignoring the state of the internal bus.
[0021]
Further, a break process is performed so as to output a predetermined status signal when executing a subroutine branch, subroutine return, exception processing branch, or exception processing return instruction.
[0022]
Further, a performance counter that can be counted by the above signal or a signal indicating a break process can be incorporated.
[0023]
According to the above-described means, by adding a start command of the data transfer device to the user debug interface circuit, the number of signal lines is reduced, and addition to the original microcomputer function is minimized, and a function for debugging is provided. Thus, the contents of a desired address can be read or written while minimizing the increase in the number of operations and the time during which the operation of the central processing unit is stopped.
[0024]
The data transfer device is also used for the user function, so that the bus arbitration is the same as the user function, the transfer request and the like can be shared with the user function, the increase in logical scale is suppressed, and the microcomputer system Is not complicated. The data transfer device arranges the transfer information on the memory, enables the transfer information to be arranged in the emulation controller, and eliminates restrictions on user resources.
[0025]
If a means for monitoring the internal bus such as an address to generate a break request or trace the state of the internal bus is provided, the state of the internal bus is ignored during the above-mentioned debugging data transfer, and the user program Inconveniences such as a break occurring in a state not depending on execution, for example, data transfer for debugging, or being acquired in a trace can be suppressed. The debug data transfer may be acquired in a trace. It should be noted that it may be possible to select whether or not to acquire the debug data transfer in a trace.
[0026]
With the performance counter, it is possible to easily measure the execution time of each function without increasing the number of emulation signals.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 2 shows a configuration example of an on-chip debugger including a microcomputer according to the present invention.
[0028]
The on-chip debugger includes a card emulator 2, an interface cable 3, a host computer 4, and a microcomputer 5 with a built-in debugging function. The card emulator 2 takes the form of, for example, a PCMCIA card or a PCI card. The host computer is a personal computer equipped with a PC slot such as a PCMCIA slot or a PCI slot. Further, the microcomputer 5 is provided with a flash memory or the like for storing a user program to be debugged, and the microcomputer 5 with a built-in debugging function is mounted on a printed circuit board PCB or the like which is a user system.
[0029]
The card emulator 2 is inserted into a PC card slot of a host computer 4, and the card emulator 2 and the printed wiring board PCB are connected via an interface cable 3 for realizing required communication means. In response to a command or the like input to the host computer 4, the user program is downloaded to a flash memory or the like, and is debugged.
[0030]
When the host computer 4 is a portable personal computer or the like, debugging in an actual use state is also possible. For example, when the application system is a digital camera, debugging and adjustment can be performed outdoors.
[0031]
FIG. 1 shows a configuration example of the microcomputer.
[0032]
Although not particularly limited, the microcomputer 5 is a single-chip type, and a ROM (read only memory) which is a memory for storing a CPU (Central Processing Unit) for controlling the entire control, an interrupt controller INT, a processing program of the CPU, and the like. (Random access memory) that can be used as a work area of the CPU and a memory for temporarily storing and stacking data, a data transfer device DTC, a bus controller BSC, and functional blocks or modules of an input / output device I / O These are functions that are open to the user. A flash memory can be applied to the ROM.
[0033]
The input / output device I / O includes, for example, a timer, a serial communication interface (SCI), an A / D converter, an input / output port (IOP), a clock oscillator (CPG), and the like. Each input / output port is also used as an input of an external interrupt or an input / output of a timer, an SCI, and an A / D converter. That is, the timer, the SCI, and the A / D converter have input / output signals, respectively, and are input / output to / from the outside via the terminal shared with the input / output port. Similarly, it can also be used as an address bus, a data bus, and a bus control signal input / output.
[0034]
As a debugging function, a memory ERAM in which a part of an emulation program is stored is provided, an emulation control circuit EMC that forms a control signal for a module related to emulation, an internal bus such as an address, or a program counter of a CPU is monitored. A break controller EBC that requests the CPU to stop the program execution at a breakpoint specified by the user at the time of emulation, a trace buffer TBF for collecting a signal on the bus BUS during emulation, an external control signal, A user debug interface circuit UDI for receiving a transfer clock or synchronizing with the transfer clock, inputting a command, or outputting required contents to the outside, a performance counter P for measuring a processing time And the like NT, block or these functional modules are connected to each other via an internal bus BUS including an address bus and a data bus.
[0035]
These are formed on one semiconductor substrate by a known semiconductor manufacturing technique. However, a configuration in which a plurality of semiconductor integrated circuits are sealed in one package as a multichip module or the like may be adopted.
[0036]
The CPU includes an instruction decoder, a break request receiving function, a break instruction execution function, a break return instruction execution function, and the like. When a signal for designating a function break, which will be described later, is active, break exception processing can be performed after execution of a subroutine branch instruction, subroutine return instruction, exception processing, and exception processing return instruction.
[0037]
When the break exception processing is executed, the processing branches to the memory ERAM on the emulation control circuit EMC, although there is no particular limitation.
[0038]
The emulation control circuit EMC has a necessary control register and the like, and controls the microcomputer with a built-in debug function according to the control by the CPU in a predetermined break mode. The signal FCBRK designating the function break is supplied to the CPU. The break mode signal BRKM indicating the break mode in which the execution of the user program is stopped and the debug program is being executed is supplied to the break controller EBC, the performance counter PCNT, and the trace buffer TBF.
[0039]
The debug interface UDI performs data communication with an external card emulator at any time according to control by the CPU in a predetermined break mode. Although not particularly limited, this data communication is serial communication, and the number of signal lines for emulation is reduced.
[0040]
In this example, the execution time of each function can be measured in a mode other than the break mode. For example, the performance counter PCNT includes two 48-bit counters, and is configured to be able to independently set the occurrence of a state to be counted.
[0041]
The bus controller BSC performs bus right arbitration at a predetermined timing based on a bus right request signal of the CPU and the data transfer device DTC. This bus arbitration result is transmitted to the CPU, the data transfer device DTC, and other modules as a bus acknowledgment signal BSACK. The bus controller BSC controls required bus access according to the built-in memory, the internal I / O register, the external address, and the like.
[0042]
The interrupt controller INT inputs each of the timer, SCI, A / D converter and external input interrupt signals, and outputs an interrupt request signal to the CPU or a transfer request to the data transfer device DTC.
[0043]
When an interrupt request signal is given to the CPU, the CPU interrupts the processing being executed, branches to a predetermined processing routine through an interrupt exception processing state, performs desired processing, and clears an interrupt factor. I do. At the end of the predetermined processing routine, a normal return instruction is placed, and the interrupted processing is resumed by executing this instruction.
[0044]
When a transfer start request is given to the data transfer device DTC, the data transfer device DTC activates a bus right request signal. When the bus right can be acquired, the data transfer device DTC reads transfer information from a predetermined address and performs data transfer based on the transfer information. After the transfer, the transfer information is written back to the original address.
[0045]
When a reset signal RES is given to the microcomputer 5, the microcomputer 5 including the CPU is reset. When the reset is released, the CPU performs reset exception processing from a predetermined address on the emulation control circuit EMC and waits for a command input via the user debug interface circuit UDI. During this time, other user functions continue in the reset state. After performing required processing in accordance with the input command, branch (return) to the user program. Thereafter, the instruction is read from a ROM or the like, decoded, and based on the decoded content, data processing or data transfer with a RAM, a timer, an SCI, an A / D converter, an input / output port, and the like is performed. That is, the CPU refers to data input from a timer, an SCI, an A / D converter, an input / output port, or the like, or a state or an instruction (switch, volume, etc.) of a device, and transmits an instruction stored in a ROM or the like. Based on the result, a signal is output to the outside using the input / output port, the timer, and the like, and the device is controlled.
[0046]
FIG. 3 shows a configuration example of the user debug interface circuit UDI.
[0047]
The host interface (interface with the card emulator) has a control signal input (reset, mode, clock), a data input, and a data output. Data input / output is performed according to the control signal. Selection of a register described later is performed by a control signal input (mode).
[0048]
The user debug interface circuit UDI has registers of an instruction register SDIR, a status register SDSR, and a data register SDDR. The instruction includes a reset request, a reset request release, a break request, a break request, and a DTC activation request (two types). The instruction decodes the contents of the instruction register and generates a predetermined control signal.
[0049]
Status register SDSR includes an SDTRF flag. When the SDTRF is cleared to the logical value "0", the data register SDDR can be written from the inside of the microcomputer such as the CPU, and when the SDTRF flag is set to the logical value "1", the host interface Through the data register SDDR.
[0050]
It is connected to an internal bus and can be read / written by the CPU in the break mode. Further, the data transfer device DTC can read / write the data register SDDR in accordance with the status EDTC indicating the debug data transfer of the data transfer device DTC.
[0051]
FIG. 4 shows a configuration example of the data transfer device DTC.
[0052]
The DTC activation request of the user debug interface circuit UDI and the interrupt request of the input / output device (I / O) of the microcomputer are input to the interrupt controller. For these, whether to issue an interrupt request to the CPU or a transfer request to the DTC is designated by the corresponding DTC enable register (DTER), the priority is determined for each, and a vector corresponding to the selected factor is determined. , An interrupt request or a transfer request is given.
[0053]
The data transfer device DTC takes in the DTC transfer request DTCRQ and the vector DTVEC. When a transfer request is generated, a bus right is requested to the bus controller by DTBRQ, it is confirmed that the bus right is accepted by BSACK, and a transfer information start address is read from a predetermined vector. The transfer information (mode, transfer source / destination address, counter) is read and stored in the data transfer device DTC, and data transfer is performed according to the transfer information. After the data transfer, the updated transfer information is written back to the original address.
[0054]
FIG. 5 shows a memory map of the microcomputer 5.
[0055]
The vector address of the DTC for the user is allocated to the ROM area, whereas the vector address for debugging of the data transfer device DTC is arranged in the emulation control circuit EMC, for example, in the memory ERAM.
[0056]
The transfer information is arranged at the address indicated by the vector. Usually, the DTC transfer information for the user is arranged in the RAM. The transfer information of the DTC for debugging is arranged in ERAM or RAM. By arranging in the ERAM, the resources of the user are not used, so that there is no restriction on the user. When the ERAM is not used, more emulation programs can be arranged in the ERAM, and the execution efficiency of the emulation program can be improved.
[0057]
FIG. 6 shows the required operation timing in the debug data transfer.
[0058]
When a predetermined DTC start request command is input to the debug interface UDI, the debug interface UDI generates a start request. This is received by the interrupt controller, the priority order is determined, and at a predetermined timing, a transfer request and a vector indicating debug data transfer are given to the data transfer device DTC.
[0059]
When receiving the transfer request, the data transfer device DTC requests the bus right, and when the request is received, reads the transfer information from the address given by the vector. At this time, the vector indicating the debug data transfer is indicated by all the high-order bits (bits 7 to 2) being 1. In this case, the emulation control circuit EMC, for example, the address of ERAM (asebase which is a parameter or the like) Is the start address). An example of this logical description is shown below.

[0060]
That is, transfer information is read from the address indicated by the vector, and data transfer is performed based on this. When the status signal EDTC indicating the debug data transfer is activated, the SDIF is set to the logical value "1" according to the status signal EDTC and the reading or writing of the UDI data register. Thereafter, the transfer information is written back to the original address. By rewriting the transfer information, the contents of the same address can be repeatedly read and the change can be monitored, and a plurality of DTC transfers can be sequentially performed.
[0061]
The data transfer device DTC acquires a bus right during a vector read, transfer information read, data transfer, and transfer information write cycle (for example, 9 bus cycles when transfer information is read / written three times). When the CPU loses the bus right, the execution of the user program is suspended, but this time is shorter than the time during which the break exception handling and the emulation program are executed.
[0062]
The emulation functions are as follows.
[0063]
That is, an instruction is input to an instruction register (SDIR) via a host interface to generate a DTC transfer request, and after performing required data transfer, via a data register (SDDR) of the user debug interface circuit UDI, The contents of the memory (or I / O register) can be read.
[0064]
The procedure is as follows.
[0065]
First, in the execution state of the emulation program, the interrupt controller and the transfer information of the DTC are set in advance.
[0066]
The contents of the memory of the microcomputer 5 can be read by the following procedure.
[0067]
(1) In a predetermined sequence, the state machine of the debug interface UDI is initialized, and the SDTRF bit is set to a logical value “1”.
[0068]
(2) A DTC transfer request command is input from the emulator to the user debug interface circuit UDI. Data is copied from the shift register to the instruction register.
[0069]
(3) The emulator confirms that the SDTRF bit is a logical value “1”.
[0070]
(4) Although there is no particular limitation, dummy data is transferred to clear the SDTRF bit.
[0071]
(5) A DTC transfer request is made to the interrupt controller INT, a transfer request and a predetermined vector are given to the data transfer device DTC, and the data transfer device DTC is activated.
[0072]
(6) The data transfer device DTC transfers data from the memory to the data register SDDR of the user debug interface circuit UDI based on transfer information set in advance. At the time of debugging data transfer, the data transfer device DTC activates a status signal EDTC indicating the debugging data transfer. When the status signal EDTC is in the active state, the break controller and the trace buffer ignore the address and data of the data transfer device DTC, which are not based on the execution of the user's program, and do not acquire an undesired break or trace. To do. The user debug interface circuit UDI monitors the EDTC signal and sets the SDTRF bit to a logical value “1” at a predetermined timing such as a data register write.
[0073]
(7) Next, the emulator 2 monitors the SDTRF bit, confirms that the reading of the data transfer device DTC has been completed by setting the logical value to "1", and takes in the data. When rewriting the contents of the memory of the microcomputer 5, the following points are different from the above.
[0074]
(8) The emulator 2 confirms that the SDTRF bit is a logical value “1”, and if the SDTRF bit is a logical value “1”, data can be transferred to the data register SDDR. Transfer to data register SDDR.
[0075]
(9) The emulator 2 observes the logical value "1" of the SDTRF bit and confirms that the data transfer device DTC has finished writing.
[0076]
FIG. 7 shows a debug data transfer method.
[0077]
By using two DTC start commands, the above procedure can be executed twice in a set, and information of arbitrary plural addresses (adr1 to adr4) can be extracted and displayed on the host computer 4.
[0078]
The card emulator 2 first writes the second transfer information in the UDI data register. For example, a transfer instruction from the address adr1 to the UDI data register is issued.
[0079]
The first DTC transfer request command 1 is input to start the first DTC transfer. In the first DTC transfer, the second transfer information on the UDI data register is stored in the second DTC transfer information area.
[0080]
Next, a DTC start request command 2 is input to start the second DTC transfer. In the second DTC transfer, the specified address (adr1) is stored in the UDI data register.
[0081]
Then, the UDI data register is read out to the host computer 4. This may be performed a required number of times (four times in this example) and changing the designated address (adr1 to adr4). The transfer information from the emulator 2 can be displayed on a display device (monitor) of the host computer 4 in a desired arrangement such as a desired window.
[0082]
Instead of having two DTC transfer request commands, a chain transfer can be used. In chain transfer, as described in, for example, Japanese Patent Application Laid-Open No. 7-129537, data transfer is performed in response to one activation request based on a plurality of transfer information arranged at consecutive addresses. According to the first transfer information, the data input to the data register of the debug interface UDI is stored at the address of the second transfer information. Thereafter, data transfer is performed based on the second transfer information.
[0083]
Note that various modifications are possible according to the number of bytes of the data register of the debug interface UDI and the arrangement of the transfer information of the data transfer device DTC.
[0084]
FIG. 8 shows a block configuration of control logic necessary for a function break of the CPU, and FIG. 9 shows operation timing of the function break.
[0085]
When the function break permission bit of the emulation control circuit EMC is set to the logical value “1”, the function break permission signal FCBRK is activated. The CPU stores the operation code of the break exception processing in the instruction register by the logical product of the decode signal dec_fcb of the execution of the subroutine branch instruction, the subroutine return instruction, the user exception processing (including an interrupt, etc.), and the user exception processing return instruction. Then, break exception handling is executed. This logic can be described as follows, where the instruction code executed by the CPU is opcode.
[0086]

That is, at the end of the execution of the instruction, the load signal indicating the loading of the next instruction is activated. At this time, the function break permission signal FCBRK is activated, and after the execution of the instruction (dec_fcb), If not in the break mode (（brkm), an instruction code 'break indicating break exception handling is taken in. In addition, brkm is a signal equivalent to BRKM of FIG.
[0088]
By executing the instruction code 'break, break exception processing is realized, and at this time, the break mode signal brkm is activated. Thus, the performance counter PCNT is stopped. In the emulation process in the break mode, the execution time of the user program can be obtained by reading the contents of the performance counter and subtracting it from the previous value of the performance counter. Further, by obtaining the above execution time in the emulation processing after execution of the subroutine return instruction, the execution time of the corresponding function can be measured. If a function is called multiple times or an exception process such as an interrupt is inserted, a break occurs in such a case, so that the time may be measured and subtracted.
[0089]
FIG. 10 shows an outline of the development environment of the CPU.
[0090]
The user creates a program in C language or assembly language using various editors or the like. This is usually created by dividing into a plurality of modules. The C compiler 101 inputs each C language source program created by the user and outputs an assembly language source program or an object module.
[0091]
The assembler 102 inputs an assembly language source program and outputs an object module.
[0092]
The linkage editor 103 inputs a plurality of object modules generated by the C compiler or assembler, resolves external references and relative addresses of each module, combines them into one program, and outputs a load module. .
[0093]
The load module can be input to the simulator / debugger 104 to simulate the operation of the CPU on a system development device such as a personal computer, display the execution result, and analyze and evaluate the program. Also, the data is input to the emulator 105 and written in the ROM such as the flash memory of the microcomputer 5 in the break mode state via the user debug interface circuit UDI to be operated on an actual application system or the like. By performing so-called in-circuit emulation, it is possible to analyze and evaluate the actual operation of the microcomputer 5 as a whole. By adopting the form shown in FIG. 2, it is possible to rewrite a ROM such as a flash memory at any time, which is suitable for debugging or emulation.
[0094]
At this time, for example, the function seq is used as follows.

[0095]
At this time, it is compiled as follows.

[0096]
The function seq becomes a subroutine branch instruction JSR, and the processing of the function is described after the address _seq. At the end, a subroutine return instruction RTS is arranged as follows.

[0097]
By using the function break, the processing time of the function seg from JSR execution to RTS execution can be measured.
[0098]
According to the above example, the following operation and effect can be obtained.
[0099]
(1) Activating the data transfer device DTC by a command of the debug interface UDI, reading required data, writing the data in the data register of the debug interface, and enabling the data to be output from the debug interface. Accordingly, the time required to stop the execution of the user program can be minimized, and the required memory contents can be read. Also, by reversing the direction of data transfer, required data can be rewritten. As a result, the usability and efficiency in debugging the microcomputer 5 can be improved.
[0100]
(2) By arranging the transfer information such as the address register in the data transfer device DTC in the RAM, it is possible to minimize the use of the resources of the user and at least without limiting the resources of the data transfer of the user The operation and effect of the above (1) can be obtained. This makes it possible to use the memory ERAM for emulation, and can effectively utilize the limited memory ERAM. If the amount of memory to be monitored or rewritten is large at the initial stage of debugging or the like, the user RAM can be used, and the memory ERAM can be used for an emulation program. When monitoring or adjusting a small number of memories while debugging is almost completed, the use of the memory ERAM does not limit user resources. By providing a vector to the data transfer device DTC to identify the data transfer for debugging, the number of factors to be used can be easily increased.
[0101]
(3) Using a plurality of DTC activation request commands or the chain transfer function of the data transfer device DTC, input transfer information via the debug interface and the data transfer device DTC, and then perform required data transfer. Thus, an arbitrary address can be read / written without breaking the CPU. Input of transfer information and data transfer can be performed by the same means, and effective use of resources can be achieved. Also, an arbitrary address can be designated and read or written at any time, and this can be repeated to read or write a plurality of addresses, thereby further improving usability and efficiency.
[0102]
(4) Since the data transfer device DTC is shared with the user, it can share the determination of the priority of the activation request, arbitrate the bus right, and the like, without complicating the microcomputer system and the development efficiency of the microcomputer itself. Can be improved. Even if a second data transfer device (e.g., DMAC) is added, it is sufficient to implement the function as a user function, and there is no direct effect on the function for debugging, which may impair development efficiency and effective use of resources. Absent. Under the control of the bus controller, an arbitrary address can be accessed regardless of the type of the bus interface of the address.
[0103]
(5) The use of the debugging interface enables emulation with a small number of signal lines, enables emulation in a mounted state, and eliminates the need to separately develop a microcomputer for mass production.
[0104]
(6) The function break function that breaks after subroutine branching, execution of exception processing, and execution of these return instructions facilitates measurement of function execution time. By using the performance counter PCNT that stops counting in the break state, the execution time of the function can be easily measured without increasing the number of emulation interface signals.
[0105]
(7) By adding a decoding circuit to the CPU, it is not necessary to set a breakpoint or the like. Since the decoding circuit of the CPU can be shared by decoding other instruction functions and performing logic synthesis, an increase in logic scale can be minimized.
[0106]
Although the invention made by the present inventors has been specifically described above, the present invention is not limited thereto, and it goes without saying that various modifications can be made without departing from the gist of the invention.
[0107]
For example, the function and signal input / output of the module can be arbitrarily changed.
[0108]
It is not necessary to provide a DTC enable register for a DTC activation request by UDI. If this is provided, the user interrupt can be executed by the user debug interface circuit UDI.
[0109]
By providing the debugging interface UDI in the emulation processor, the functions of the present invention can also be used as an in-circuit emulator.
[0110]
Function breaks are also available on emulation processors or in-circuit emulators.
[0111]
The details of the data transfer device can be variously modified. For example, the arrangement and configuration of the control register, transfer information, data transfer mode, and the like can be arbitrarily set. As a data transfer mode, a repeat mode, a block transfer mode, or the like can be applied. In the chain transfer, the second transfer can be performed only when the value of the counter of the first transfer information becomes zero.
[0112]
In the above description, the case where the invention made by the present inventor is mainly applied to an on-chip debugger including a card emulator, which is a field of application, has been described. However, the present invention is not limited to this. Can be applied.
[0113]
The present invention can be applied on the condition that it has at least a function and an interface for emulation or debugging.
[0114]
【The invention's effect】
The following is a brief description of an effect obtained by a representative one of the inventions disclosed in the present application.
[0115]
That is, the data transfer device is started, required data is read, the data is written to the data register of the debug interface, and the data can be output from the debug interface, thereby stopping the execution of the user program. And the required memory contents can be read. Also, by reversing the direction of data transfer, required data can be rewritten. This makes it possible to improve usability and efficiency in debugging the microcomputer.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration example of a microcomputer according to the present invention.
FIG. 2 is an explanatory diagram of a configuration example of an on-chip debugger including the microcomputer.
FIG. 3 is a block diagram illustrating a configuration example of a debugging interface included in the microcomputer.
FIG. 4 is a block diagram illustrating a configuration example of a data transfer device included in the microcomputer.
FIG. 5 is an explanatory diagram of a memory map in the microcomputer.
FIG. 6 is a timing chart of debug data transfer in the on-chip debugger.
FIG. 7 is an explanatory diagram of a data transfer method for debugging in the on-chip debugger.
FIG. 8 is a block diagram illustrating a configuration example of control logic necessary for a function break of a CPU in the on-chip debugger.
FIG. 9 is an operation timing chart of a function break in the on-chip debugger.
FIG. 10 is a schematic explanatory diagram of a development environment of a CPU included in the microcomputer.
[Explanation of symbols]
2 Card emulator
3 Interface cable
4 Host computer
5 Microcomputer
CPU Central processing unit
DTC data transfer device
BSC bus controller
ROM flash memory
RAM random access memory
I / O input / output device
UDI user debug interface circuit
TBF trace buffer
PCNT performance counter
EBC break controller
INT interrupt controller
EMC emulation control circuit

Claims (5)

Debugging interface means for debugging;
Data transfer means for enabling data transfer;
Bus control means for bus control;
A central processing unit capable of controlling the operation of the data transfer unit, the data transfer unit, and the bus control unit,
The debug interface means performs input / output with the emulator, an instruction register inputtable by the interface, a means for decoding the contents thereof, and generating a data transfer request, a data register inputtable / outputtable by the interface, A status register indicating a status of data transfer;
The data transfer means executes a data transfer between a required memory and the data register in response to the data transfer request, and sets the status register to a predetermined state upon completion of the data transfer. Means to
A microcomputer according to claim 1, wherein said bus control means arbitrates a bus right between said data transfer means and said central processing unit, and includes means for controlling access to the buses. Emulation control means for emulation control;
A break unit that monitors an address to request a break, and a trace unit that obtains address information,
The transfer information can be stored in the emulation means, and a status signal indicating the data transfer is provided. When the status signal is active, at least one of the break means or the trace means ignores the address information. The microcomputer according to 1. 3. The microcomputer according to claim 1, wherein said microcomputer comprises an on-chip debugger which can be connected to an emulator via said debug interface means when mounted on an application system. Emulation control means capable of outputting a predetermined control signal for emulation control, and a central processing unit capable of controlling the operation of the emulation control means,
The central processing unit includes means for detecting execution of a subroutine branch instruction, execution of exception processing, and execution of those return instructions. When the control signal is in a predetermined state, an emulation program is executed based on a detection result of the detection means. A microcomputer that transitions to an execution state. 5. The microcomputer according to claim 4, further comprising: a counter that counts in accordance with a program execution; and means for stopping the counting operation of the counter in the emulation program execution state.

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