JP2009005230A - Solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a size of a semiconductor chip while mounting both of an imaging part and a drive circuit for driving the imaging part on one semiconductor chip. <P>SOLUTION: The solid-state imaging device 10 formed on the semiconductor chip is provided with the imaging part 11 having a pixel region with pixels 12 arranged two-dimensionally, the drive circuit 20 for driving the imaging part 11 so as to generate an imaging signal based on a projected image projected on the pixel region, and a signal output circuit 17 for selectively outputting an image signal generated by the imaging part 11 and an internal signal (SCANOUT) of the drive circuit 20 through a common electrode 18 arranged on a surface of the semiconductor chip to an external of the semiconductor chip. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device formed on a semiconductor chip, and more particularly to a technique for reducing the size of a semiconductor chip.

In general, in a semiconductor chip, a function test of a built-in circuit is performed after manufacture and before shipment. In a MOS type solid-state imaging device, an imaging unit and a drive circuit that drives the imaging unit are mixedly mounted on a single semiconductor chip, and an imaging unit and a drive circuit are used to identify which part has a fault. Functional tests are often performed separately.
FIG. 10 is a diagram illustrating a configuration of a solid-state imaging device according to the related art.

The solid-state imaging device 50 includes an imaging unit 51, a drive circuit 60, a signal output circuit 57, and a scan path test circuit 61. The functional inspection of the imaging unit 51 is performed by reading the image signal generated by the imaging unit 51 with a test device. At this time, the image signal is read from the electrode 58 formed on the surface of the semiconductor chip. The function test of the drive circuit 60 is performed by reading the internal signal of the drive circuit, which is generated by the scan path test circuit 61 and serves as a material for determining whether or not the drive circuit is functioning normally, with a test device ( For example, see Patent Document 1). At this time, the internal signal is read from the electrode 59 arranged on the surface of the semiconductor chip.
JP-A-9-61495

As described above, in the solid-state imaging device according to the related art, the electrode for outputting the image signal and the electrode for outputting the internal signal of the drive circuit are separately provided. For this reason, there is a restriction in reducing the size of the semiconductor chip.
SUMMARY OF THE INVENTION An object of the present invention is to provide a solid-state imaging device capable of reducing the size of a semiconductor chip while mounting an imaging unit and a drive circuit for driving the imaging unit on one semiconductor chip. To do.

  A solid-state imaging device according to the present invention is a solid-state imaging device formed on a semiconductor chip, and is based on an imaging unit having a pixel region in which a plurality of pixels are two-dimensionally arranged, and a projection image projected on the pixel region. A driving circuit for driving the imaging unit so as to generate an imaging signal, and an image signal generated by the imaging unit and an internal signal of the driving circuit are provided on a common electrode disposed on the surface of the semiconductor chip. And a signal output circuit that selectively outputs to the outside of the semiconductor chip.

According to the above configuration, the image signal and the internal signal of the drive signal are output via the common electrode. Therefore, the size of the semiconductor chip can be reduced as compared with the case where the image signal and the internal signal of the drive signal are output via separate electrodes.
Further, the internal signal of the drive circuit may be a signal that is used to determine whether or not the drive circuit is functioning normally. Thereby, it can be determined whether or not the drive circuit is functioning normally.

The signal output circuit selectively amplifies an input signal as a power by amplifying an input signal and outputting the external signal using the electrode, and the image signal or the internal signal as the input signal. An input selection circuit for inputting may be provided.
According to the above configuration, not only the electrodes but also the buffer circuit is provided in common. Therefore, the size of the semiconductor chip can be reduced as compared with the case where the buffer circuit is provided individually.

  In the buffer circuit, a first MOS transistor, a second MOS transistor, and a load resistor are arranged in series in this order on a path connecting the positive electrode and the negative electrode of the power source, and the second MOS transistor and the load resistor And the input selection circuit connects the gate of the second MOS transistor to the gate of the second MOS transistor while keeping the first MOS transistor on in the first mode. An image signal may be input, and in the second mode, the internal signal may be input to the gate of the first MOS transistor while the second MOS transistor is turned on.

According to the above configuration, the image signal and the internal signal of the drive circuit can be selectively output to the outside using the common electrode and the common buffer circuit.
The signal output circuit outputs a test signal given to a logic circuit to be subjected to a scan path test when a scan path test is performed on all or part of the logic circuits included in the drive circuit. In response, a response signal obtained from the logic circuit may be externally output as an internal signal of the drive circuit.

The signal output circuit may externally output a drive signal supplied from the drive circuit to the imaging unit when the imaging unit is driven as an internal signal of the drive circuit.
By reading out the response signal and the drive signal, it can be determined whether or not the drive circuit is functioning normally.

The best mode for carrying out the present invention will be described in detail with reference to the drawings.
(Embodiment 1)
FIG. 1 is a perspective view showing an appearance of a solid-state imaging device according to Embodiment 1 of the present invention.
The solid-state imaging device 10 is formed on a semiconductor chip. A plurality of pixels are two-dimensionally arranged in the pixel region 1. Electrodes 2 are arranged in the peripheral region on the surface of the semiconductor chip.

FIG. 2 is a diagram showing a configuration of the solid-state imaging device according to Embodiment 1 of the present invention.
The solid-state imaging device 10 includes an imaging unit 11, a signal output circuit 17, a drive circuit 20, a scan path test circuit 21, and a mode control circuit 22.
The imaging unit 11 includes a pixel 12, a load circuit 13, a row selection circuit 14, a signal processing circuit 15, and a column selection circuit 16. The pixel 12 generates a pixel signal corresponding to the intensity of incident light. The load circuit 13 is composed of a load resistor arranged for each column. The row selection circuit 14 is a circuit that operates the pixels 12 in units of rows. The signal processing circuit 15 is a circuit that performs signal processing such as noise removal on the pixel signal generated by the pixel 12. The column selection circuit 16 is a circuit that causes the signal processing circuit 15 to output a pixel signal for each column. By these circuits, the pixel signal of each pixel is serially output as an image signal.

Based on the control signal (MODESEL) supplied from the mode control circuit 22, the signal output circuit 17 outputs the image signal output from the imaging unit 11 and the response signal (SCANOUT) output from the scan path test circuit 21. This circuit selectively outputs to the outside via a common electrode 18. The electrode 18 corresponds to one of the electrodes 2 shown in FIG.
The drive circuit 20 is a circuit that supplies drive signals to the load circuit 13, the row selection circuit 14, the signal processing circuit 15, the column selection circuit 16, and the signal output circuit 17. With these drive signals, the imaging unit 11 can generate an image signal based on the projected image projected onto the pixel region 1.

  The scan path test circuit 21 is a circuit for performing a scan path test on all or part of the logic circuits included in the drive circuit 20. Specifically, a test signal is given to the logic circuit to be subjected to the scan path test, and a response signal (SCANOUT) obtained from the logic circuit is output in response to the test signal. This response signal is an internal signal of the drive circuit 20 and serves as a material for determining whether or not the drive circuit 20 is functioning normally.

The mode control circuit 22 is a circuit that supplies control signals to the signal output circuit 17, the drive circuit 20, and the scan path test circuit 21, respectively. By these control signals, an image test and a scan path test can be selectively performed.
FIG. 3 is a diagram illustrating an example of a scan path test.
In this example, the logic circuit to be subjected to the scan path test includes flip-flops FF1, FF2, FF3 and an AND circuit, and the logical product of the output of the flip-flop FF1 and the output of the flip-flop FF2 is passed through the flip-flop FF3. It is configured to output. Each of the flip-flops FF1, FF2, and FF3 includes a regular input terminal D and a test input terminal DT. The flip-flops FF1 and FF2 are connected in cascade using the test input terminal DT, and function as a shift register when the control signal nt is at a high level (when the logical value is “1”).

The outline of the scan path test is shown below.
First, the logic value “1” is held in both the flip-flops FF1 and FF2. Therefore, the data string “1, 1” as the test signal is shifted in while the control signal nt is set to the high level.
Next, the control signal nt is set to a low level, and the output signal of the AND circuit is captured by the flip-flop FF3.

Next, while setting the control signal nt to the high level, the data string as the response signal is shifted out, and the shifted out data string is observed.
If the logic circuit subject to the scan path test functions normally, the logical value of the shifted-out data becomes “1”. However, if a 0 stuck-at fault has occurred, the logical value of the shifted-out data becomes “0”. Thus, by comparing the actually observed data with the data (expected value) observed when normal, the failure location and failure mode can be estimated.

FIG. 4 is a diagram showing a detailed configuration of the signal output circuit 17 according to the first embodiment of the present invention.
The signal output circuit 17 includes an input selection circuit 31 and a buffer circuit 32.
The input selection circuit 31 selectively inputs either the image signal output from the imaging unit 11 or the response signal (SCANOUT) output from the scan path test circuit 21 to the buffer circuit 32.

  In the buffer circuit 32, MOS transistors TR1, TR2, and TR3 are arranged in series in this order on a path connecting the positive electrode (VDD) and the negative electrode (ground) of the power supply, and the connection point between TR2 and TR3 is connected to the electrode 18. It has the composition which is. A bias voltage is supplied to the gate of the MOS transistor TR3 so that the MOS transistor TR3 functions as a load resistor.

FIG. 5 is a diagram illustrating a drive signal supplied to the signal output circuit 17 and an output signal output from the signal output circuit 17 during the image test period and the scan path test period. 6 is an enlarged view of the area A shown in FIG. 5, and FIG. 7 is an enlarged view of the area B shown in FIG.
During the image test period, the control signal (MODESEL) is at a high level (see FIG. 5), the reset signal (SIGRS) is at a high level during the image signal reset period, and is at a low level during the image signal readout period (see FIG. 5). 6).

  Thus, since the control signal (MODESEL) is at a high level, the output signal of the NOR circuit is at a low level regardless of the signal level of the response signal (SCANOUT). The output signal of the NOR circuit is supplied to the gate of the MOS transistor TR1 through the level shift circuit LS. As a result, the P-type MOS transistor TR1 remains on during the image test period.

  The image signal is inverted and amplified by the inverting amplifier circuit AMP and supplied to the gate of the MOS transistor TR2. During the reset period of the image signal, the MOS transistor TR4 is turned on, and the reset level is supplied to the gate of the MOS transistor TR2 as the signal level of the image signal. During the readout period of the image signal, the MOS transistor TR4 is turned off, and the inverted and amplified level is supplied to the gate of the MOS transistor TR2 as the signal level of the image signal (see FIG. 6).

In this way, during the image test period, the inverted and amplified image signal is supplied to the gate of the MOS transistor TR2 while the MOS transistor TR1 is kept on. Therefore, the signal output circuit 17 can externally output the image signal after voltage amplification and power amplification (see FIGS. 5 and 6).
On the other hand, during the scan path test period, the control signal (MODESEL) is at a low level (see FIG. 5), and the reset signal (SIGRS) is at a high level (see FIG. 5).

  Thus, since the control signal (MODESEL) is at the low level, the output signal of the NOR circuit outputs an inverted signal of the response signal (SCANOUT). This inverted signal is supplied to the gate of the MOS transistor TR1 through the level shift circuit LS. As a result, the P-type MOS transistor TR1 is turned on when the response signal (SCANOUT) is at a high level, and is turned off when the response signal (SCANOUT) is at a low level.

In the scan path test period, since the reset signal (SIGRS) is at a high level, the MOS transistor TR4 is turned on. Therefore, the reset level is supplied to the gate of the MOS transistor TR2 regardless of the signal level of the image signal.
In this way, during the scan path test period, the inverted signal of the response signal (SCANOUT) is supplied to the MOS transistor TR1 while the MOS transistor TR2 remains in the on state. Therefore, the signal output circuit 17 can amplify the response signal (SCANOUT) and output it externally (see FIGS. 5 and 7).

FIG. 8 is a diagram for explaining signal processing in the function inspection.
The function inspection of the solid-state imaging device 10 is performed using a test device. The test apparatus can read out the imaging signal generated by the imaging unit 11 and the response signal that is an internal signal of the drive circuit 20 by bringing the probe into contact with the electrode 18.
The read image signal is used for an image test in a test apparatus. The read response signal (SCANOUT) is used for a scan path test in the test apparatus. In the scan path test according to the first embodiment of the present invention, the response signal is treated as an image (the output image in FIG. 8). The test apparatus stores in advance an expected value image obtained when the drive circuit 20 functions normally, and compares the stored expected value image with the actually read output image for each pixel. . If the drive circuit 20 is functioning normally, the comparison results will be the same for all pixels, and if the drive circuit 20 is not functioning normally, the comparison results will be inconsistent for any pixel. The test apparatus can determine whether or not the drive circuit 20 is functioning normally using the above principle, and identify the failure location and failure mode of the drive circuit 20 by analyzing the mismatched location. be able to.

As described above, in the solid-state imaging device 10, the image signal and the response signal are output via the common electrode 18. Therefore, the size of the semiconductor chip can be reduced as compared with the case where the image signal and the response signal are output via separate electrodes. Further, since the image signal and the response signal are output via the common electrode 18, the response signal can be continuously output after the output of the image signal (see FIG. 5). Therefore, it is possible to shorten the time for the test apparatus to acquire the image signal and the response signal, and as a result, it is possible to shorten the test period.
(Embodiment 2)
In the second embodiment, the drive signal generated by the drive circuit 20 is output as an internal signal of the drive circuit 20.

FIG. 9 is a diagram showing a configuration of the solid-state imaging apparatus according to Embodiment 2 of the present invention.
The solid-state imaging device 10 according to the second embodiment includes a pulse monitor circuit 41 instead of the scan path test circuit 21. Other configurations are the same as those in the first embodiment.
The pulse monitor circuit 41 is a circuit that outputs a drive signal (MONIOUT) arbitrarily selected from the drive signals generated by the drive circuit 20.

  With this configuration, the solid-state imaging device 10 according to Embodiment 2 can output the drive signal generated by the drive circuit 20 to the outside. The drive signal output externally is handled as an image in the test apparatus as in the first embodiment. The test apparatus stores in advance an expected value image obtained if the drive circuit 20 is functioning normally, and compares the stored expected value image with the actually output output image for each pixel. Thus, it can be determined whether or not the drive circuit 20 is functioning normally.

  The present invention can be used in, for example, a digital camera.

It is a perspective view which shows the external appearance of the solid-state imaging device which concerns on Embodiment 1 of this invention. It is a figure which shows the structure of the solid-state imaging device which concerns on Embodiment 1 of this invention. It is a figure which shows an example of a scan campus test. It is a figure which shows the detailed structure of the signal output circuit 17 which concerns on Embodiment 1 of this invention. FIG. 4 is a diagram illustrating a drive signal supplied to a signal output circuit 17 and an output signal output from the signal output circuit 17 during an image test period and a scan path test period. FIG. 6 is an enlarged view of a region A shown in FIG. 5. FIG. 6 is an enlarged view of a region B shown in FIG. 5. It is a figure for demonstrating the signal processing in a function test | inspection. It is a figure which shows the structure of the solid-state imaging device which concerns on Embodiment 2 of this invention. It is a figure which shows the structure of the solid-state imaging device concerning a prior art.

Explanation of symbols

1 pixel region 2 electrode 10, 50 solid-state imaging device 11, 51 imaging unit 12, 52 pixel 13, 53 load circuit 14, 54 row selection circuit 15, 55 signal processing circuit 16, 56 column selection circuit 17, 57 signal output circuit 18 , 58, 59 Electrode 20, 60 Drive circuit 21, 61 Scan campus test circuit 22 Mode control circuit 31 Input selection circuit 32 Buffer circuit 41 Pulse monitor circuit

Claims (6)

A solid-state imaging device formed on a semiconductor chip,
An imaging unit having a pixel region in which a plurality of pixels are two-dimensionally arranged;
A drive circuit that drives the imaging unit to generate an imaging signal based on a projection image projected on the pixel region;
A signal output circuit that selectively outputs an image signal generated by the imaging unit and an internal signal of the drive circuit to the outside of the semiconductor chip via a common electrode disposed on the surface of the semiconductor chip; A solid-state imaging device comprising: The solid-state imaging device according to claim 1, wherein the internal signal of the drive circuit is a signal that serves as a determination material for determining whether or not the drive circuit is functioning normally. The signal output circuit is
A buffer circuit that amplifies an input signal and outputs the signal externally using the electrode;
The solid-state imaging device according to claim 1, further comprising: an input selection circuit that selectively inputs either the image signal or the internal signal as the input signal to the buffer circuit. The buffer circuit is
A first MOS transistor, a second MOS transistor, and a load resistor are arranged in series in this order on a path connecting the positive electrode and the negative electrode of the power source, and a connection point between the second MOS transistor and the load resistor is the electrode. Having a configuration connected to
The input selection circuit includes:
In the first mode, the image signal is input to the gate of the second MOS transistor while the first MOS transistor is turned on. In the second mode, the second MOS transistor is turned on. The solid-state imaging device according to claim 3, wherein the internal signal is input to a gate of the first MOS transistor. The signal output circuit responds to a test signal given to a logic circuit subject to a scan path test when a scan path test is performed on all or a part of the logic circuits included in the drive circuit. The solid-state imaging device according to claim 1, wherein a response signal obtained from the logic circuit is externally output as an internal signal of the drive circuit. The signal output circuit externally outputs a drive signal supplied from the drive circuit to the imaging unit when the imaging unit is driven as an internal signal of the drive circuit. Solid-state imaging device.

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