JP2009005088A - Receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a receiver having a sampling filter and preventing the reception performance of the receiver from deteriorating due to an amplitude error or a quadrature error between an in-phase component and a quadrature component of a reception signal. <P>SOLUTION: The receiver comprises: a filter section 4 for filtering the reception signal; an I/Q error detecting section 7 provided in a demodulation path including a demodulating section 6 for detecting the amplitude error and the quadrature error between an I signal that is the in-phase component of the reception signal and a Q signal that is the quadrature component thereof; and a controlling section 8 for controlling the filter section 4 based on error information detected by the I/Q error detecting section 7. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a receiver applied to a wireless communication apparatus that can support multimode or multiband.

  In general, in order to support multimode or multiband in a wireless communication apparatus, it is necessary to prepare a plurality of wireless communication apparatuses having respective functions. However, since a plurality of wireless communication devices are prepared, there is a problem that the size of the device is increased and the cost is increased. In order to realize a wireless communication device that can support multimode or multiband, software wireless technology is used. It is necessary to develop the receiver used.

  An ideal software defined radio receiver can be configured by a combination of an AD converter directly connected to an antenna and a digital signal processing unit. However, in such a configuration, when a high-level interference wave is input from the antenna end, the input signal is saturated by the AD converter, so that the desired signal cannot be accurately reproduced. For this reason, it is necessary to provide the receiver with a blocking filter for attenuating the interference wave before the AD converter.

FIG. 6 is a block diagram showing a configuration of a general receiver.
In FIG. 6, the receiver includes an antenna 101 that receives a signal, a low noise amplification unit 102 that amplifies a reception signal via the antenna 101, and a frequency conversion that performs frequency conversion on an output signal of the low noise amplification unit 102. Unit 103, blocking filter 104 that performs interference wave removal processing on the output signal of frequency conversion unit 103, AD conversion unit 105 that performs AD conversion on the output signal of blocking filter 104, and AD conversion unit 105 And a demodulator 106 that performs demodulation processing on the output signal.

  In software defined radio, the band of the desired signal varies from system to system, and the frequency at which the jamming wave is located varies from system to system. Therefore, in the software defined radio receiver shown in FIG. 6, it is essential to vary the characteristics of the blocking filter 104.

  As a filter with variable characteristics, a filter composed of a voltage-current converter, a switch, and a capacitor can be considered. In this case, the characteristics of the filter are determined by the capacitance of the capacitor, the number of capacitors to be charged, or the clock frequency for controlling the switch. That is, the frequency response of the filter can be changed by changing the capacitance of the capacitor, the number of capacitors to be charged, and the clock frequency.

A sampling filter (hereinafter, also simply referred to as “filter”) has been known as a variable characteristic filter as described above (see, for example, Patent Document 1 and Non-Patent Document 1).
FIG. 7 is a block diagram schematically showing the configuration of the sampling filter described in Patent Document 1. In FIG.

In FIG. 7, the sampling filter includes a voltage / current conversion unit 201 that performs voltage / current conversion on an input voltage signal, a charge / discharge unit 202 that charges / discharges an electric charge with respect to an output current of the voltage / current conversion unit 201, and The capacitor 203 is configured to read out an output signal from the charging / discharging unit 202.
The charging / discharging unit 202 includes a plurality of switches and capacitors (see FIG. 8), and the transfer function H (z) of the filter is determined by the configuration of the capacitors and the control of the switches.

FIG. 8 is a circuit diagram showing a specific configuration example of the charging / discharging unit 202 in FIG.
The sampling filter shown in FIG. 8 is a filter that performs an averaging process and a thinning process on the input signal. When the clock frequency for the input signal is fs, the sampling process is performed on the input signal of 2 samples. The average value is output as the sample frequency fs / 2.

  In FIG. 8, the sampling filter has an input terminal 301 for taking in a voltage signal, a voltage-current conversion unit 201 that converts a voltage signal input from the input terminal 301 into a voltage-current, and an output current of the voltage-current conversion unit 201. , And capacitors 307 to 306 for selecting a capacitor to which the output current of the voltage / current conversion unit 201 is input is located between the voltage / current conversion unit 201 and the capacitors 303 to 306. And a capacitor 203 for sharing the charge together with the charge of the capacitors 303 to 306, and switches 312 to 315 for selecting a capacitor that is located between the capacitors 303 to 306 and the capacitor 203 and shares the charge with the capacitor 203, , By charging the capacitor 203 An output terminal 316 for the output signal Jill potential, and discharges the electric charge charged in the capacitor 303 to 306 and a switch 317-320 to allow the next charge.

  The charging / discharging unit 202 includes capacitors 303 to 306 and switches 307 to 310, 312 to 315, and 317 to 320. 7 and 8, for convenience, the capacitor 203 is illustrated with a configuration different from the charge / discharge unit 202, but the capacitor 203 is substantially included in the function of the charge / discharge unit 202.

In the charging / discharging unit 202, the capacitors 303 and 304 and the switches 307, 308, 312, 313, 317, and 318 constitute a first capacitor bank, and the capacitors 305 and 306 and the switches 309 and 310 are included. 314, 315, 319, and 320 constitute a second capacitor bank.
The first capacitor bank and the second capacitor bank are configured in parallel, and are alternately connected to the capacitor 203 for charge sharing.

Next, the operation of the conventional sampling filter shown in FIG. 8 will be described with reference to FIGS.
FIG. 9 is a timing chart showing the operation of the charging / discharging unit 202. The on / off state transition of the switches 307 to 310, 312 to 315, and 317 to 320 is represented by the on / off state of each switch and the sampling time (1, 2,..., 24). In FIG. 9, one sample time represents 1 / fs (= clock cycle).

FIG. 10 is an explanatory diagram showing the charges charged in the capacitors 303 to 306 and 203, and the charge Qk charged in each capacitor every sample time by the output current of the voltage-current converter 201 (k is the sample time). Represents.
In FIG. 10, C303 to C306 and C203 respectively correspond to the capacitors 303 to 306 and 203, the white frame represents discharge by charge sharing (signal readout), and the gray frame represents charging by charge sharing. Represents.

  In the expression representing the charge amount in FIG. 10, the coefficient A is A = (2Cr + Cout) / Cout, the coefficient Cr is Cr = C303 =... = C306, and the coefficient Cout is Cout = C203. It is.

  First, in the sample time 1 shown in FIG. 9, among the switches 307 to 310 connected to the voltage-current converter 201, only the switch 307 is in the on state, and the other switches 308 to 310 are in the off state. Therefore, the voltage signal input from the input terminal 301 is converted into an output current by the voltage / current converter 201, input to the capacitor 303 in the first capacitor bank, and the capacitor 303 is charged.

  Further, at the sample time 2, only the switch 308 is in the on state, and the other switches 307, 309, and 310 are in the off state. Therefore, the voltage signal input from the input terminal 301 is converted into an output current by the voltage / current converter 201, input to the capacitor 304 in the first capacitor bank, and the capacitor 304 is charged.

  Further, at the sample time 3, only the switch 309 is on, and the other switches 307, 308, 310 are off. Therefore, the voltage signal input from the input terminal 301 is converted into an output current by the voltage-current converter 201, input to the capacitor 305 in the second capacitor bank, and the capacitor 305 is charged.

On the other hand, in the first capacitor bank, when the switches 312 and 313 are turned on, the capacitors 303 and 304 that are charged are connected to the capacitor 203. The charge charged in the capacitor is shared with the capacitor 203.
At this time, when the capacitance of the capacitors 303 to 306 is Cr [F] and the capacitance of the capacitor 203 is Cout [F], the charge Q203 charged in the capacitor 203 is expressed as the following equation (1). Can do.

  Q203 = (Q1 + Q2) * α (1)

  However, (alpha) in Formula (1) can be represented by a fixed value like the following formula | equation (2).

  α = Cout / (2Cr + Cout) (2)

  As a result, the averaging process of the output current of the voltage-current converter 201 at the sample times 1 and 2 is performed, and the average value is charged as the charge in the capacitor 203, and the potential difference caused by the charging of the capacitor 203 is the sample time 3 Is output from the output terminal 316 as an output signal.

  After the charge sharing with the capacitor 203, the switches 317 and 318 are turned on, whereby the charges charged in the capacitors 303 and 304 are discharged, and the next charging is possible.

The above series of operations are alternately performed in the first capacitor bank and the second capacitor bank.
That is, while the capacitors 303 and 304 of the first capacitor bank and the capacitor 203 are connected and charge sharing is performed, the output current of the voltage-current converter 201 is sequentially applied to the capacitors 305 and 306 in the second capacitor bank. Charged.

On the contrary, while the output current of the voltage-current converter 201 is sequentially charged in the capacitors 303 and 304 in the first capacitor bank, the capacitors 305 and 306 and the capacitor 203 are connected in the second capacitor bank to charge. Sharing is done.
That is, it can be seen that the above-described filter is an filter that performs an averaging process on two samples of the input signal and outputs an average value every two samples.

In this case, the frequency response characteristic of the filter output signal has a steep attenuation null point for each sample frequency fs / 2, as shown in FIG.
It is possible to increase and change the number of samples to be subjected to the averaging process by increasing the number of capacitors in each capacitor bank. In addition, by setting the number of averaged samples large, the frequency response characteristic of the filter output signal becomes a narrow band low-pass characteristic (when attention is paid to a characteristic having a sampling frequency of fs / 2 or less).
That is, the sampling filter described above is a filter that can variably set the frequency response characteristics depending on the number of capacitors to be charged. Further, the transfer function H (z) of the filter shown in FIG. 8 can be expressed as the following equation (3).

  H (z) = 1 + 1 / z (3)

From the equation (3), the filter shown in FIG. 8 is called a real sampling filter in which the coefficient of the transfer function H (z) is a real number, and the filter characteristic is the same for each clock frequency fs.
Further, as is clear from FIG. 11, the filter characteristics of frequencies 0 to fs are line symmetric with respect to the sample frequency fs / 2.

  On the other hand, conventionally, a complex sampling filter in which the filter characteristics at frequencies 0 to fs are asymmetric with respect to the sampling frequency fs / 2 and the coefficient of the transfer function is a complex number is also known (for example, Non-Patent Document 2). reference).

FIG. 12 is a block diagram schematically showing the configuration of the complex sampling filter shown in Non-Patent Document 2.
In FIG. 12, the sampling filter includes a voltage / current converter 701 to which an in-phase component I signal is input, a voltage / current converter 702 to which a quadrature component Q signal is input, and output currents of the voltage / current converters 701 and 702. The charge / discharge circuit unit 703 charges and discharges the electric charge, the capacitor 710 for reading out the in-phase component output signal, and the capacitor 711 for reading out the quadrature component output signal. Note that the capacitors 710 and 711 are included in the function of the charge / discharge circuit portion 703.

  The charging / discharging circuit unit 703 includes charging / discharging units 704 and 705 for charging / discharging electric charges with respect to the output current of the voltage / current converting unit 701 and charging / discharging units for charging / discharging electric charges with respect to the output current of the voltage / current converting unit 702. 706, 707, a subtracting unit 708 for adding a signal weighted equivalently to the negative side to each output signal of the charging / discharging units 704, 706 and outputting it as a signal of the in-phase component, and charging / discharging unit 705 , 707, and an adder 709 for adding the output signals as orthogonal component signals.

The charging / discharging units 704 and 707 have the same circuit configuration in which the transfer function is represented by Hre (z), and the charging / discharging units 705 and 706 are the same circuit in which the transfer function is represented by Him (z). Consists of configuration.
Charging / discharging units 704 to 707 are configured by a plurality of switches and capacitors (see FIG. 13), and transfer functions Hre (z) and Him (z) are determined by the configuration of each capacitor and the control of each switch. .

The complex sampling filter shown in FIG. 12 has a configuration in which an in-phase component I signal and a quadrature component Q signal are added together.
Here, with respect to the transfer functions Hre (z) and Him (z) of the complex sampling filter, a case where the transfer function H (z) of the charge / discharge circuit unit 703 is expressed by the following equation (4) is taken as an example. explain.

  H (z) = 1 + (0.5 + 0.5 * j) / z (4)

  At this time, the transfer functions Hre (z) and Him (z) for the charge / discharge units 704 to 707 constituting the charge / discharge circuit unit 703 of the transfer function H (z) are expressed by the following equations (5) and (6). Can be expressed as:

Hre (z) = 1 + 0.5 / z (5)
Him (z) = 0.5 / z (6)

FIG. 13 is a circuit diagram showing a specific configuration example of the sampling filter of FIG.
The complex sampling filter shown in FIG. 13 is a filter that performs averaging processing and decimation processing with weighting on an input in-phase component I signal and a quadrature component Q signal. When fs is set, weighting is applied to the two samples of the input I signal and Q signal to perform averaging processing, and the average value is output at the sample frequency fs / 2.

  In FIG. 13, the complex sampling filter includes an input terminal 801 for capturing an in-phase component I signal, a voltage-current converter 701 that converts a voltage signal input from the input terminal 801 into a voltage-current, and a voltage-current converter 701. Capacitor 803 to 808 for charging the electric charge with the output current of, and a capacitor to which the output current of the voltage / current converter 701 is input between the voltage / current converter 701 and the capacitors 803 to 808 is selected. Switches 809 to 814.

  Further, the complex sampling filter includes an input terminal 815 for capturing a quadrature component Q signal, a voltage-current converter 702 that converts a voltage signal input from the input terminal 815 into a voltage-current, and an output of the voltage-current converter 702. Capacitors 817 to 822 for charging electric charges with current, and a voltage / current conversion unit 702 and a capacitor 817 to 822 for selecting a capacitor to which an output current of the voltage / current conversion unit 702 is input. Switches 823 to 828 are provided.

  In addition, the complex sampling filter includes a capacitor 710 for sharing the charge with the charge of the capacitors 803, 804, 806, 807, 819, and 822, and a charge with the charge of the capacitors 805, 808, 817, 818, 820, and 821. Capacitor 711 for sharing, and switches 831, 832, 834, and 835 for selecting a capacitor that is located between capacitors 803, 804, 806, 807, 819, 822, and capacitor 710 and that shares charge with capacitor 710 , 839, 842 and switches 833, 836, 837, 838, 84 for selecting a capacitor that is located between the capacitors 805, 808, 817, 818, 820, 821 and the capacitor 711 and shares charge with the capacitor 711. , And a 841.

  Further, the complex sampling filter is located between the capacitor 819 and the capacitor 710 and performs a negative weighting equivalently on the charge charged in the capacitor 819, a capacitor 822, a capacitor 710, And a converter 844 that is equivalently negatively weighted with respect to the charge charged in the capacitor 822, and outputs a potential difference generated by charging the capacitor 710 as a signal of the in-phase component. An output terminal 845 for output, an output terminal 846 for outputting a potential difference generated when the capacitor 711 is charged with charge as an orthogonal component signal, and the charges charged in the capacitors 803 to 808 and 817 to 822 are discharged. And switches 847 to 858 for enabling the next charging. That.

  The charging / discharging unit 704 includes capacitors 803, 804, 806, 807 and switches 809, 810, 812, 813, 831, 832, 834, 835, 847, 848, 850, 851, and the charging / discharging unit 705 , Capacitors 805 and 808, and switches 811, 814, 833, 836, 849, and 852.

The charging / discharging unit 706 includes capacitors 819 and 822 and switches 825, 828, 839, 842, 855, and 858. The charging / discharging unit 707 includes capacitors 817, 818, 820, and 821, switches 823, 824, 826, 827, 837, 838, 840, 841, 853, 854, 856, and 857.
The charge / discharge units 704 and 706 are shared with the capacitor 710, and the charge / discharge units 705 and 707 are shared with the capacitor 711.

Next, the operation of the conventional sampling filter shown in FIGS. 12 and 13 will be described with reference to FIGS.
FIG. 14 is a timing chart showing the operation of the charge / discharge circuit unit 703. Similarly to the above (see FIG. 9), the transition of the ON / OFF state of the switches 809 to 814, 823 to 828, 831 to 842, and 847 to 858 is performed. Is shown in association with the on / off state of each switch and the sample time (1, 2,..., 24).

  FIG. 15 is an explanatory diagram showing the charge charged in each capacitor, and the charge Qki (k is the sample time) charged in each capacitor 803 to 808 every sample time by the output current of the voltage-current converter 701, The charge charged in each capacitor 817 to 822 for each sample time by the output current of the voltage-current converter 702 indicates Qkq (k is the sample time) and the charge charged in the capacitors 710 and 711.

  In FIG. 15, C803 to C808, C817 to C822, C710, and C711 correspond to the capacitors 803 to 808, 817 to 822, 710, and 711, respectively, and the white frame indicates discharge (signal readout) due to charge sharing. The gray frame represents charging by charge sharing.

  15, the coefficient A is A = (3Cr + Cout) / Cout, the coefficient Cr is Cr = C803 =... = C817, and the coefficient Cout is Cout = C710. = C711.

By performing the switch control of FIG. 14 on the sampling filter of FIG. 13, it can be confirmed that the transfer function H (z) can be realized as shown in FIG.
In this case, as shown in FIG. 16, the filter characteristic is asymmetric with respect to the sample frequency fs / 2 at frequencies 0 to fs, and the coefficient of the transfer function is a complex number.
The software defined radio receiver is implemented by a receiver including the above-described variable characteristic filter.

US Patent Publication US2003 / 0083035A1 FIG. 9 R. B. Staszewski et al., "All-Digital Frequency Synthesizer and Discrete-Time Receiver for Bluetooth Radio in 130-nm CMOS", IEEE Journal of Solid-Solid. 39, no. 12, pp. 2278-2291, Dec. 2004 S. Karvonen et al., “A complex charge sampling scheme for complex IF receivers”, IEEE Circuits and Systems, 2003. ISCAS'03. Proceedings of the 2003 International Symposium, Vol. 2, pp. II-169-II-172, May 2003

When a receiver with a conventional sampling filter uses a quadrature mixer as a means for performing frequency conversion, the gain difference between the in-phase component and the quadrature component and the non-orthogonality of the local signal with respect to the in-phase component and the quadrature component , The imbalance between the in-phase component and the quadrature component in the quadrature mixer may occur, and an amplitude error or quadrature error may occur between the in-phase component and the quadrature component of the received signal. As a result, the received signal is distorted and received. There was a problem that the performance deteriorated.
In addition, in the case of a receiver equipped with a complex sampling filter, since the in-phase component and the quadrature component are added to each other in filtering, the influence of the amplitude error or quadrature error greatly affects the frequency characteristics of the filter. As a result, the desired characteristic cannot be realized, and as a result, there is a problem that the interference wave cannot be sufficiently attenuated.

The present invention has been made to solve the above-described problems. By providing a sampling filter with a function for correcting an amplitude error and a quadrature error, the amplitude error and the quadrature error between the in-phase component and the quadrature component of the received signal are provided. An object of the present invention is to obtain a receiver capable of preventing the reception performance deterioration due to the above.
It is another object of the present invention to provide a receiver capable of sufficiently attenuating an interference wave by preventing the deterioration of filter characteristics by providing a complex sampling filter with a function of correcting an amplitude error or a quadrature error.

  A receiver according to the present invention detects a magnitude error and a quadrature error between an in-phase component I signal and a quadrature component Q signal provided in a demodulation path including a filter unit that filters a received signal and a demodulation unit. An IQ error detection unit and a control unit that controls the filter unit based on error information detected by the IQ error detection unit are provided.

  According to the present invention, the receiver is provided with an IQ error detection unit that detects the amplitude error and the quadrature error of the in-phase component and the quadrature component, detects the amplitude error and the quadrature error of the in-phase component and the quadrature component of the received signal, and detects them. Based on the result, a sampling filter having a function of correcting the amplitude error and the quadrature error is controlled to correct the amplitude error and the quadrature error. By taking such means, the amplitude error and quadrature error of the in-phase component and the quadrature component of the received signal are reduced, and the reception performance is prevented from deteriorating. Further, when a complex sampling filter is used for the receiver, the interference wave can be sufficiently attenuated without deteriorating the filter characteristics, and good communication is possible.

Embodiment 1 FIG.
Embodiment 1 of the present invention will be described below with reference to the drawings.
1 is a block diagram schematically showing a basic configuration of a receiver according to Embodiment 1 of the present invention.
In FIG. 1, the receiver converts an antenna 1 for receiving a signal, a low noise amplification unit 2 for amplifying a reception signal via the antenna 1, and an output signal of the low noise amplification unit 2. The frequency conversion unit 3 that performs the filtering and the output signal of the frequency conversion unit 3 are filtered and the amplitude error and the quadrature error between the in-phase component (I signal) and the quadrature component (Q signal) of the received signal are corrected. The sampling filter unit with IQ error correction function (hereinafter simply referred to as “filter unit”) 4, the AD conversion unit 5 that converts the output signal of the filter unit 4 from an analog signal to a digital signal, and the output signal of the AD conversion unit 5 And a demodulator 6 that performs demodulation processing.

Of the above configuration, the elements (antenna 1, low noise amplification unit 2, frequency conversion unit 3, AD conversion unit 5 and demodulation unit 6) excluding the filter unit 4 are the same as the antenna 101 described above (see FIG. 6), low noise. This is the same as the amplification unit 102, the frequency conversion unit 103, the AD conversion unit 105, and the demodulation unit 106.
The filter unit 4 is obtained by adding an amplitude error and orthogonal error correction function to the real sampling filter described above (see FIG. 7).

The receiver according to the first embodiment of the present invention includes an IQ error detection unit 7 provided in a demodulation path including the demodulation unit 6 and a filter unit based on a detection result (error information) of the IQ error detection unit 7. 4 is provided.
The IQ error detector 7 detects an amplitude error or a quadrature error between the in-phase component I signal and the quadrature component Q signal of the received signal, using the output signal of the demodulator 6 or the signal in the process of the demodulator 6. .

FIG. 2 is a functional block diagram showing a specific example of the filter unit 4 having an IQ error correction function.
In FIG. 2, the filter unit 4 includes first and second voltage / current converters (hereinafter simply referred to as “voltage / current converters”) 41 and 42 to which an in-phase component I signal is input, and a quadrature component Q signal. Is input to a third voltage-current converter (hereinafter simply referred to as “voltage-current converter”) 43, an adder 44 for adding the output currents of the voltage-current converters 42, 43, and a voltage-current converter 41. The charging / discharging unit 45 outputs an in-phase component signal when the output current is input, and the charging / discharging unit 46 outputs an orthogonal component signal when the output signal of the addition unit 44 is input.

The charging / discharging unit 45 configures a first charging / discharging unit for charging / discharging the output current of the voltage / current conversion unit 41, and the charging / discharging unit 46 includes the voltage / current conversion units 42, 43. A second charging / discharging unit for charging / discharging the electric charge for each output current is configured.
Each charging / discharging unit 45, 46 is composed of a plurality of switches and capacitors in the same manner as described above (see FIG. 8), and each transfer function is H (z).
The output currents of the voltage / current converters 42 and 43 are controlled by the controller 8.

Next, the operation according to the first embodiment of the present invention will be described with reference to FIGS. Here, a case where the filter unit 4 is a real sampling filter unit with an IQ error correction function (see FIG. 2) will be described.
When communication is started, the IQ error detection unit 7 in the receiver detects an amplitude error and a quadrature error between the in-phase component and the quadrature component of the received signal using a known signal included in the received signal.

First, the received signal is received by the antenna 1 and amplified by the low noise amplification unit 2.
The received signal amplified by the low noise amplifying unit 2 is input to the frequency converting unit 3 to be frequency converted, converted to an IF signal or a baseband signal, and input to the filter unit 4.
In the filter unit 4, only the filtering process is performed without detecting the control from the control unit 8 with respect to the voltage / current conversion units 42 and 43 in order to detect an error at first.

  The signal filtered by the filter unit 4 is input to the AD conversion unit 5 and converted from an analog signal to a digital signal. The signal converted into the digital signal is input to the demodulator 6 and subjected to demodulation processing.

The IQ error detector 7 detects a preamble signal or a test signal whose signal pattern is known in advance using the output signal of the demodulator 6 or a signal in the process, and detects an amplitude error and a quadrature error of the received signal.
The control unit 8 controls the filter unit 4 so as to cancel the amplitude error and the quadrature error based on the error amount detected by the IQ error detection unit 7. That is, in the filter unit 4, the output currents of the voltage / current conversion units 42 and 43 are controlled in accordance with the control signal from the control unit 8.

  In FIG. 2, an in-phase component I signal and a quadrature component Q signal output from the frequency converter 3 are input to a filter unit 4 (real sampling filter with IQ error correction), and an in-phase component I signal (voltage signal). Are input to the voltage-current converters 41 and 42 and converted into current signals, and the quadrature component Q signal (voltage signal) is input into the voltage-current converter 43 and converted into current signals.

  The signal converted into the current signal by the voltage / current converter 41 is input to the charging / discharging unit 45, and the signals converted into the current signal by the voltage signal converters 42 and 43 are added by the adding unit 44 to be added to the charging / discharging unit. 46 is input.

  Each switch (see FIG. 8) of the charge / discharge units 45 and 46 is on / off controlled as described above (see FIG. 9). Thus, the in-phase component and the quadrature component are respectively subjected to the above-described filtering (see FIG. 11), and are output from the charging / discharging unit 45 as an in-phase component signal, and are output from the charging / discharging unit 46 as a quadrature component signal. Is done.

Next, a method of correcting the amplitude error and the orthogonal error by the control unit 8 will be described using mathematical expressions.
The control unit 8 controls the voltage / current conversion units 42 and 43 in the filter unit 4 based on the detected amplitude error and orthogonal error information obtained from the IQ error detection unit 7.

Here, a case where the amplitude error G and the quadrature error τ of the quadrature component Q signal with respect to the in-phase component I signal detected by the IQ error detection unit 7 will be described.
First, a signal input to the frequency conversion unit 3 is represented as the following expression (7).

  r (t) = A * cos (ωt + θ) (7)

  At this time, if an amplitude error and a quadrature error have not occurred, the frequency converter 3 down-converts the frequency to ω / (2π) and inputs the in-phase component I signal I (t) to the filter unit 4. The quadrature component Q signal Q (t) can be expressed by the following equations (8) and (9), respectively.

I (t) = (A / 2) * cos θ (8)
Q (t) = (A / 2) * sin θ (9)

  On the other hand, when the amplitude error G and the quadrature error τ have occurred, the in-phase component I signal I ′ (t) and the quadrature component Q signal Q ′ (t) input to the filter unit 4 are respectively It can represent like the following formula | equation (10) and (11).

I ′ (t) = (A / 2) * cos θ (10)
Q ′ (t) = (A * G / 2) * sin (θ−τ) = (A * G / 2) * (cosτ * sinθ−sinτ * cosθ) (11)

  Here, when the conversion coefficients of the voltage-current conversion units 41 to 43 are X1 [A / V], X2 [A / V], and X3 [A / V], respectively, the voltage-current conversion units 41 to 43 The output signals I1 ′ (t), I2 ′ (t), and Q3 ′ (t) are expressed as the following equations (12) to (14).

I1 ′ (t) = (A * X1 / 2) * cos θ (12)
I2 ′ (t) = (A * X2 / 2) * cos θ (13)
Q3 ′ (t) = (A * G * X3 / 2) * (cosτ * sinθ−sinτ * cosθ) (14)

  In order to correct the amplitude error and the quadrature error at the time of input of the charge / discharge units 45 and 46, the quadrature component Q signal Qin (t) input to the charge / discharge unit 46 is expressed by the following equation (15). It may be expressed in

  Qin (t) = (A * X1 / 2) * sinθ (15)

  That is, error correction can be performed by performing the following equation (16) on the in-phase component I signal I2 '(t) and the quadrature component Q signal Q3' (t).

  Qin (t) = Q3 ′ (t) * X1 / (G * X3 * cosτ) + I1 ′ (t) * X1 * sinτ / (X2 * cosτ) = (A * X1 / 2) * sinθ (16) )

  That is, the conversion coefficient X2 of the voltage / current conversion unit 41 is controlled so that the conversion coefficient X2 of the voltage / current conversion unit 42 is weighted by (sin τ / cos τ) times the conversion coefficient X1 of the voltage / current conversion unit 41. Is controlled to be 1 / (G * cosτ) times weighting. Thereby, the signals Iin (t) and Qin (t) input to the charging / discharging units 45 and 46 can be expressed as the following equations (17) and (18).

Iin (t) = (A * X1 / 2) * cos θ = I (t) * X1 (17)
Qin (t) = (A * X1 / 2) * sin θ = Q (t) * X1 (18)

  As a result, it is possible to correct the amplitude error and the orthogonal error of the received signal before being input to the charge / discharge units 45 and 46.

FIG. 3 is a circuit diagram showing a basic configuration of the voltage / current converters 42 and 43.
In FIG. 3, the voltage / current converters 42 and 43 are constituted by FET bridges having a resistance ro, and convert the input voltage signal Vdd into an output current Iout.
As shown in FIG. 3, by using the resistance ro as a variable resistance and controlling the resistance value of the resistance ro according to a control signal from the control unit 8, the conversion coefficients X2 and X3 can be controlled.

  As described above, the receiver according to Embodiment 1 of the present invention is provided in the demodulation path including the filter unit 4 (real sampling filter having an IQ error correction function) for filtering the received signal and the demodulation unit 6. The IQ error detector 7 detects the amplitude error and the quadrature error between the in-phase component I signal and the quadrature component Q signal of the received signal, and the filter unit 4 based on the error information detected by the IQ error detector 7. And a control unit 8 for controlling.

  In addition, the filter unit 4 charges and discharges the electric current with respect to the output current of the voltage-current converter 41, the voltage-current converters 41 and 42 to which the I signal is input, the voltage-current converter 43 to which the Q signal is input. A charge / discharge unit 45 for charging and discharging and a charge / discharge unit 46 for charging / discharging the output currents of the voltage / current conversion units 42 and 43. The control unit 8 includes a voltage / current conversion unit. Each output current of 42 and 43 is controlled.

As described above, by using the detection result of the IQ error detection unit 7 to control the voltage / current conversion units 42 and 43 in the filter unit 4, the signal at the input time of the charge / discharge units 45 and 46 in the filter 4 is converted into a signal. On the other hand, it is possible to correct the amplitude error and the orthogonal error.
As a result, it is possible to suppress the amplitude error and the quadrature error of the reception signal, and it is possible to prevent the reception performance from being deteriorated due to the amplitude error and the quadrature error of the reception signal.

Embodiment 2. FIG.
In the first embodiment, the amplitude error and the quadrature error are corrected in the receiver including the filter unit 4 including the real type sampling filter having the IQ error correction function. However, the complex sampling having the IQ error correction function is used. In a receiver provided with a filter, the amplitude error and the quadrature error may be corrected.

  4 is a functional block diagram showing a filter unit 4A (complex sampling filter having an IQ error correction function) according to Embodiment 2 of the present invention. The same components as those described above (see FIG. 2) are described above. The same reference numerals are given. The overall configuration of the receiver is as shown in FIG.

In FIG. 4, the filter unit 4A has a function of correcting an amplitude error and an orthogonal error, and includes a control unit 8A.
The filter 4A receives voltage / current converters 41 and 42 to which an in-phase component I signal is input, a voltage / current converter 43 to which a quadrature component Q signal is input, and an output current of the voltage / current converter 41. First and third charging / discharging units (hereinafter simply referred to as “charging / discharging units”) 45, 45A, an adding unit 44 for adding the output currents of the voltage-current conversion units 42, 43, and an output current of the adding unit 44 The second and fourth charging / discharging units (hereinafter simply referred to as “charging / discharging units”) 46, 46A and the output signals of the charging / discharging units 45, 46A are weighted equivalently on the negative side. The output signals of the first adder (hereinafter referred to as “subtractor”) 47 that outputs the signals of the in-phase components by adding the received signals and the charge / discharge units 45A and 46 are added to output the signals of the quadrature components Second adder (hereinafter simply referred to as “adder”) 4 It is equipped with a door.

The charging / discharging units 45 and 45A charge and discharge charges with respect to the output current of the voltage / current conversion unit 41, and the charging and discharging units 46 and 46A charge charges with respect to the output currents of the voltage / current conversion units 42 and 43, respectively. Discharge.
The charge / discharge units 45 and 46 have the same circuit configuration in which each transfer function is represented by Hre (z), and the charge / discharge units 45A and 46A have the same circuit in which each transfer function is represented by Him (z). Consists of configuration.

The charging / discharging units 45, 45A, 46A, 46 are configured by a plurality of switches and capacitors, like the charging / discharging units 704 to 707 described above (see FIG. 13), and the transfer function Hre ( z) and Him (z) are determined.
Further, the output currents of the voltage / current converters 42 and 43 are controlled by the controller 8A in the same manner as described above.

  In the receiver of FIG. 1, even when the filter unit 4A shown in FIG. 4 is used, the operations of the respective constituent elements 1 to 8 are the same as those of the first embodiment. In the filter unit 4A, the output currents of the voltage / current converters 42 and 43 are controlled in accordance with the control signal from the control unit 8A.

Next, the operation of the filter unit 4A shown in FIG. 4 will be described with reference to FIG.
The in-phase component I signal and the quadrature component Q signal output from the frequency conversion unit 3 are input to the filter unit 4A (complex sampling filter with IQ error correction function), and the in-phase component I signal (voltage signal) is a voltage current. The signals are input to the converters 41 and 42 and converted into current signals. Similarly, the quadrature component Q signal (voltage signal) is input to the voltage-current converter 43 and converted into a current signal.

The output signal converted into the current signal by the voltage / current converter 41 is input to the charge / discharge units 45 and 45A, and each output signal converted into the current signal by the voltage signal converters 42 and 43 is added by the adder 44. And input to the charge / discharge units 46A and 46.
Hereinafter, similarly to the above-described first embodiment, the control unit 8A controls the conversion coefficient (the output currents of the voltage / current conversion units 42 and 43) in accordance with the detection error from the IQ error detection unit 7. The amplitude error and the quadrature error between the in-phase component I signal input to the charge / discharge units 45 and 45A and the quadrature component Q signal input to the charge / discharge units 46A and 46 are corrected.

  The charge / discharge units 45, 45A, 46, and 46A are each configured as described above (see FIG. 13), and the switching control is performed as described above (see FIG. 14). As a result, the in-phase component and the quadrature component are respectively filtered based on the characteristics described above (see FIG. 16), and the in-phase component signal and the quadrature component signal are output.

  As described above, the filter unit 4A of the receiver according to the second embodiment of the present invention includes the voltage / current converters 41 and 42 to which the I signal is input, the voltage / current converter 43 to which the Q signal is input, Charge / discharge units 45 and 45A for charging and discharging charges with respect to the output current of the voltage / current conversion unit 41, and charge / discharge units for charging and discharging charges with respect to the output currents of the voltage / current conversion units 42 and 43 46, 46A and the subtractor 47 for adding the output signals of the charge / discharge units 45, 46A to output the in-phase component signal, and the output signals of the charge / discharge units 45A, 46 for adding the quadrature component signal. The control unit 8A controls each output current of the voltage / current converters 42 and 43.

  As described above, the amplitude error and the quadrature error between the in-phase component and the quadrature component of the received signal are detected, and the voltage-current conversion unit of the filter unit 4A (complex sampling filter having an IQ error correction function) is detected using the detection result. By controlling 42 and 43, it is possible to correct the amplitude error and the quadrature error for the signals at the time of input of the charge / discharge units 45, 45A, 46, and 46A in the sampling filter.

  As a result, it is possible to suppress the amplitude error and quadrature error of the received signal, and even for a complex sampling filter having a configuration in which an in-phase component I signal and a quadrature component Q signal are added together. Therefore, the interference wave can be sufficiently attenuated without deteriorating the filter characteristics, and the reception performance can be prevented from deteriorating.

Embodiment 3 FIG.
In the first and second embodiments, the control units 8 and 8A control only the filter units 4 and 4A (sampling filter with IQ error correction function) based on the detection result of the IQ error detection unit 7, and the in-phase component However, as shown in FIG. 5, the control unit 8B is configured to control the gain of not only the filter unit 4B but also the low noise amplification unit 2B. May be.

FIG. 5 is a block diagram showing a basic configuration of a receiver according to Embodiment 3 of the present invention. Components similar to those described above (see FIG. 1) are denoted by the same reference numerals.
In general, the amplitude error generated in the frequency converter 3 is caused by both an error for the in-phase component I signal and an error for the quadrature component Q signal. Therefore, when only the quadrature component Q signal is controlled, the input signal to the AD converter 5 may differ from the desired power.
For example, when the power of the input signal to the AD conversion unit 5 is excessive, the signal is saturated in the AD conversion unit 5 and the reception performance is deteriorated. Conversely, the power of the input signal to the AD conversion unit 5 is excessively small. Even in this case, the signal resolution in the AD conversion unit 5 is insufficient, and the reception performance is deteriorated.

  Therefore, in Embodiment 3 of the present invention, the control unit 8B controls the gain of the low noise amplification unit 2B as well as the filter unit 4B (sampling filter with IQ error correction function), thereby converting the AD conversion unit 5B. Set the input signal to the appropriate power level.

5, a receiver according to Embodiment 3 of the present invention includes an antenna 1 for receiving a signal, a low noise amplifying unit 2B for amplifying a received signal via antenna 1, and a low noise amplifying unit. The frequency conversion unit 3 that performs frequency conversion on the output signal of 2B, and performs filtering on the output signal of the frequency conversion unit 3, and corrects the amplitude error and the quadrature error between the in-phase component and the quadrature component of the received signal Filter unit 4B, an AD conversion unit 5 that converts the output signal of the filter unit 4B into a digital signal, a demodulation unit 6 that performs demodulation processing on the output signal of the AD conversion unit 5, and an output signal of the demodulation unit 6 Alternatively, an IQ error detection unit 7 that detects an amplitude error or a quadrature error between the in-phase component and the quadrature component of the received signal using the signal in the process, and the low noise amplification unit 2B based on the detection result of the IQ error detection unit 7 And a control unit 8B controls the gain and filter unit 4B.
Based on the error information detected by the IQ error detection unit 7, the control unit 8B adjusts the gain of the low noise amplification unit 2B so that the input signal to the AD conversion unit 5 has an appropriate power level.

  As described above, the control unit 8B of the receiver according to the third embodiment of the present invention controls the filter unit 4B and also controls the gain of the low noise amplification unit 2B that amplifies the received signal, thereby performing AD conversion. It is possible to adjust the input signal to the unit 5 to an appropriate power level, and it is possible to prevent the reception performance from deteriorating.

  Further, the control unit 8B performs the correction process of the amplitude error and the quadrature error on the quadrature component Q signal in the filter unit 4B, and also performs the same correction process on the in-phase component I signal. The correction process of the amplitude error and the orthogonal error can be performed more appropriately.

  In the first to third embodiments, the control unit 8, 8A, 8B controls the output current by changing the conversion coefficient of the voltage-current conversion unit 42, 43 in the filter unit 4, 4A, 4B. Alternatively, a current amplifier (not shown) may be provided on the output side of the voltage / current converters 42 and 43, and the output current may be controlled by controlling the current amplifier by the controller.

It is a block diagram which shows the whole structure of the receiver which concerns on Embodiment 1 of this invention. It is a functional block diagram which shows the filter part in FIG. 1 as a specific example. FIG. 3 is a circuit diagram showing a basic configuration of a voltage-current converter in FIG. 2. It is a functional block diagram which shows the filter part which concerns on Embodiment 2 of this invention. It is a block diagram which shows the receiver which concerns on Embodiment 3 of this invention. It is a block diagram which shows the whole structure of a general receiver. It is a block diagram which shows roughly the structure of the sampling filter used for the conventional receiver. It is a circuit diagram which shows the specific structural example of the charging / discharging part in FIG. It is a timing chart which shows operation | movement of the charging / discharging part of FIG. It is explanatory drawing which shows the electric charge charged to each capacitor in FIG. It is explanatory drawing which shows the frequency characteristic of the filter of FIG. It is a block diagram which shows schematically another structure of the sampling filter used for the conventional receiver. It is a circuit diagram which shows the specific example of the charging / discharging part in FIG. It is a timing chart which shows operation | movement of the charging / discharging part of FIG. It is explanatory drawing which shows the electric charge charged to each capacitor in FIG. It is explanatory drawing which shows the frequency characteristic of the filter of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Antenna 2, 2B Low noise amplification part 4, 4A, 4B filter part, 6 Demodulation part, 7 IQ error detection part, 8, 8A, 8B control part, 41 1st voltage-current conversion part, 42 2nd Voltage-current converter, 43 3rd voltage-current converter, 45 1st charging / discharging part, 46 2nd charging / discharging part, 45A 3rd charging / discharging part, 46A 4th charging / discharging part, 47 subtraction part ( First addition unit), 48 Second addition unit.

Claims (4)

A filter unit for filtering the received signal;
An IQ error detector provided in a demodulation path including a demodulator to detect an amplitude error and a quadrature error between the in-phase component I signal and the quadrature component Q signal of the received signal;
And a control unit that controls the filter unit based on error information detected by the IQ error detection unit. The filter unit is
First and second voltage-current converters to which the I signal is input;
A third voltage-current converter to which the Q signal is input;
A first charging / discharging unit for charging / discharging the output current of the first voltage-current conversion unit;
A second charging / discharging unit configured to charge / discharge electric charges with respect to each output current of the second and third voltage / current converters,
The receiver according to claim 1, wherein the control unit controls each output current of the second and third voltage-current converters. The filter unit is
First and second voltage-current converters to which the I signal is input;
A third voltage-current converter to which the Q signal is input;
First and third charging / discharging units for charging and discharging electric charges with respect to the output current of the first voltage-current conversion unit;
Second and fourth charging / discharging units for charging and discharging electric charges with respect to the respective output currents of the second and third voltage-current converters;
A first adder that adds the output signals of the first and fourth charging / discharging units and outputs a signal of an in-phase component;
A second adder that adds the output signals of the second and third charging / discharging units and outputs a signal of an orthogonal component;
The receiver according to claim 1, wherein the control unit controls each output current of the second and third voltage-current converters. A low noise amplification unit for amplifying the received signal;
The receiver according to any one of claims 1 to 3, wherein the control unit controls the filter unit and controls a gain of the low noise amplification unit.

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