JP2008515064A5 - - Google Patents

Download PDF

Info

Publication number
JP2008515064A5
JP2008515064A5 JP2007533793A JP2007533793A JP2008515064A5 JP 2008515064 A5 JP2008515064 A5 JP 2008515064A5 JP 2007533793 A JP2007533793 A JP 2007533793A JP 2007533793 A JP2007533793 A JP 2007533793A JP 2008515064 A5 JP2008515064 A5 JP 2008515064A5
Authority
JP
Japan
Prior art keywords
thread
instruction
checker
tracking
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007533793A
Other languages
English (en)
Japanese (ja)
Other versions
JP4691105B2 (ja
JP2008515064A (ja
Filing date
Publication date
Priority claimed from US10/953,887 external-priority patent/US7353365B2/en
Application filed filed Critical
Publication of JP2008515064A publication Critical patent/JP2008515064A/ja
Publication of JP2008515064A5 publication Critical patent/JP2008515064A5/ja
Application granted granted Critical
Publication of JP4691105B2 publication Critical patent/JP4691105B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP2007533793A 2004-09-29 2005-09-29 冗長マルチスレッド環境でのチェッカ命令の実行 Expired - Fee Related JP4691105B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/953,887 2004-09-29
US10/953,887 US7353365B2 (en) 2004-09-29 2004-09-29 Implementing check instructions in each thread within a redundant multithreading environments
PCT/US2005/035375 WO2006039595A2 (en) 2004-09-29 2005-09-29 Executing checker instructions in redundant multithreading environments

Publications (3)

Publication Number Publication Date
JP2008515064A JP2008515064A (ja) 2008-05-08
JP2008515064A5 true JP2008515064A5 (enExample) 2011-03-03
JP4691105B2 JP4691105B2 (ja) 2011-06-01

Family

ID=36001038

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007533793A Expired - Fee Related JP4691105B2 (ja) 2004-09-29 2005-09-29 冗長マルチスレッド環境でのチェッカ命令の実行

Country Status (7)

Country Link
US (1) US7353365B2 (enExample)
JP (1) JP4691105B2 (enExample)
CN (1) CN101031887B (enExample)
DE (1) DE112005002370T5 (enExample)
GB (1) GB2430520B (enExample)
TW (1) TWI317063B (enExample)
WO (1) WO2006039595A2 (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7581152B2 (en) * 2004-12-22 2009-08-25 Intel Corporation Fault free store data path for software implementation of redundant multithreading environments
US7321989B2 (en) * 2005-01-05 2008-01-22 The Aerospace Corporation Simultaneously multithreaded processing and single event failure detection method
US7818744B2 (en) * 2005-12-30 2010-10-19 Intel Corporation Apparatus and method for redundant software thread computation
GB0602641D0 (en) * 2006-02-09 2006-03-22 Eads Defence And Security Syst High speed data processing system
US7444544B2 (en) * 2006-07-14 2008-10-28 International Business Machines Corporation Write filter cache method and apparatus for protecting the microprocessor core from soft errors
US9594648B2 (en) * 2008-12-30 2017-03-14 Intel Corporation Controlling non-redundant execution in a redundant multithreading (RMT) processor
US9081688B2 (en) * 2008-12-30 2015-07-14 Intel Corporation Obtaining data for redundant multithreading (RMT) execution
CN101551764B (zh) * 2009-02-27 2010-11-10 北京时代民芯科技有限公司 基于同步冗余线程与编码技术的抗单粒子效应系统及方法
US9052887B2 (en) 2010-02-16 2015-06-09 Freescale Semiconductor, Inc. Fault tolerance of data processing steps operating in either a parallel operation mode or a non-synchronous redundant operation mode
US9361104B2 (en) * 2010-08-13 2016-06-07 Freescale Semiconductor, Inc. Systems and methods for determining instruction execution error by comparing an operand of a reference instruction to a result of a subsequent cross-check instruction
JP2012208662A (ja) * 2011-03-29 2012-10-25 Toyota Motor Corp マルチスレッド・プロセッサ
WO2014080245A1 (en) 2012-11-22 2014-05-30 Freescale Semiconductor, Inc. Data processing device, method of execution error detection and integrated circuit
AT515341B1 (de) * 2014-01-23 2015-12-15 Bernecker & Rainer Ind Elektronik Gmbh Verfahren zur Überprüfung der Abarbeitung von Software
US9823983B2 (en) 2014-09-25 2017-11-21 Nxp Usa, Inc. Electronic fault detection unit
US10013240B2 (en) * 2016-06-21 2018-07-03 Advanced Micro Devices, Inc. Fingerprinting of redundant threads using compiler-inserted transformation code
US10042687B2 (en) * 2016-08-08 2018-08-07 Advanced Micro Devices, Inc. Paired value comparison for redundant multi-threading operations

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19625195A1 (de) * 1996-06-24 1998-01-02 Siemens Ag Synchronisationsverfahren
JPH1115661A (ja) * 1997-06-26 1999-01-22 Toshiba Corp Ｃｐｕの自己診断方法
US6463579B1 (en) * 1999-02-17 2002-10-08 Intel Corporation System and method for generating recovery code
US6625749B1 (en) * 1999-12-21 2003-09-23 Intel Corporation Firmware mechanism for correcting soft errors
US6640313B1 (en) * 1999-12-21 2003-10-28 Intel Corporation Microprocessor with high-reliability operating mode
US6854051B2 (en) * 2000-04-19 2005-02-08 Hewlett-Packard Development Company, L.P. Cycle count replication in a simultaneous and redundantly threaded processor
US6854075B2 (en) * 2000-04-19 2005-02-08 Hewlett-Packard Development Company, L.P. Simultaneous and redundantly threaded processor store instruction comparator

Similar Documents

Publication Publication Date Title
US9965274B2 (en) Computer processor employing bypass network using result tags for routing result operands
JP2008515064A5 (enExample)
US9250901B2 (en) Execution context swap between heterogeneous functional hardware units
US9632825B2 (en) Method and apparatus for efficient scheduling for asymmetrical execution units
US8904153B2 (en) Vector loads with multiple vector elements from a same cache line in a scattered load operation
JP5799465B2 (ja) ループバッファ学習
US20120060016A1 (en) Vector Loads from Scattered Memory Locations
US20100332805A1 (en) Remapping source Registers to aid instruction scheduling within a processor
US20140181482A1 (en) Store-to-load forwarding
TW201037517A (en) Memory model for hardware attributes within a transactional memory system
US10049043B2 (en) Flushing control within a multi-threaded processor
US9904554B2 (en) Checkpoints for a simultaneous multithreading processor
KR20140113434A (ko) 바이패스 멀티플 인스턴스화 테이블을 갖는 이동 제거 시스템 및 방법
CN105094747B (zh) 基于smt的中央处理单元以及用于检测指令的数据相关性的装置
KR101952209B1 (ko) 벡터 레지스터 파일의 동적 재명명 기반의 레지스터 재구성
TW201606645A (zh) 在處理器管線中管理指令順序
US9361113B2 (en) Simultaneous finish of stores and dependent loads
WO2015017129A4 (en) Multi-threaded gpu pipeline
CN101371223B (zh) 运算数的提早有条件选择
CN1806226A (zh) 具有重放机制的加载存储单元
US9063855B2 (en) Fault handling at a transaction level by employing a token and a source-to-destination paradigm in a processor-based system
CA2657168A1 (en) Efficient interrupt return address save mechanism
US8117425B2 (en) Multithread processor and method of synchronization operations among threads to be used in same
CN104516726A (zh) 一种指令处理的方法及装置
US9442735B1 (en) Method and apparatus for processing speculative, out-of-order memory access instructions