JP2008312022A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for improving voltage comparison accuracy and reducing current consumption. <P>SOLUTION: A differential amplifier circuit 101 includes: a first transistor MP1 having a control electrode to which first input voltage is supplied; a second transistor MP2 having a control electrode to which second input voltage is supplied; a first switch MP3 connected between the first transistor MP1 and a first output node; a second switch MP4 connected between the second transistor MP2 and a second output node; a third switch MP5 connected between the first transistor MP1 and a second output node; a fourth switch MP6 connected between the second transistor MP2 and the first output node; a first capacitor CL1 coupled to the first output node; and a second capacitor CL2 coupled to the second output node. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device that performs a differential amplification operation.

  In recent years, analog / digital mixed integrated circuits that also integrate analog circuits are generally used in digital integrated circuits of CMOS (Complementary Metal Oxide Semiconductor) processes. The importance of an analog / digital converter (ADC) circuit as an interface unit for connecting between an analog circuit and a digital circuit is increasing.

  There are various types of ADC circuits such as a successive approximation type, a pipeline type, a flash type, a ΣΔ type, and a double integration type. Any of these types requires a comparator circuit for performing voltage comparison.

  In addition, a low consumption current operation of a CMOS analog / digital mixed integrated circuit is required for various reasons such as mobile compatibility and heat generation reduction. Such a requirement is no exception for the comparator circuit which is a key part of the analog part. .

  For example, Patent Document 1 discloses a comparator circuit that realizes a low current consumption operation. That is, a comparator circuit having a reset operation period and a comparison operation period as an operation state, receiving a predetermined differential input voltage and a differential input reference voltage, and comparing and collating voltage levels of these input voltages. The differential output output from the differential chopper type comparison means and the fully differential chopper type comparison means is received via capacitive coupling and operates as an offset compensated strobe latch means during the comparison operation period to operate a predetermined differential. And a fully differential amplification means for generating and outputting a digital voltage.

  Patent Document 2 also discloses a comparator circuit that realizes a low current consumption operation. That is, a chopper comparator that compares an input signal with a reference signal, the first P-channel transistor and the first N-channel transistor connected in series between the power supply potential and the reference potential, and the first A first capacitor connected between the gate of the P-channel transistor and the input node; a second capacitor connected between the gate of the first N-channel transistor and the input node; A first switch connected between the first input terminal receiving the input node and the input node; a second switch connected between the second input terminal receiving the input signal and the input node; A first gate bias voltage supplied to the gate of one P-channel transistor and a second gate via supplied to the gate of the first N-channel transistor And a gate bias voltage generation circuit for generating a voltage. The chopper-type comparator supplies the first and second gate bias voltages to the gates of the first P-channel transistor and the first N-channel transistor by turning on the first switch, respectively. Is provided. The control circuit, after precharging the first and second capacitors, stops supplying the first and second gate bias voltages, turns off the first switch, and turns on the second switch. Thus, a signal corresponding to the difference between the input signal and the reference signal is supplied to the gates of the first P-channel transistor and the first N-channel transistor by capacitive coupling of the first and second capacitors.

  Furthermore, due to the recent high accuracy of ADC circuits built in CMOS analog / digital mixed integrated circuits such as sensors, it is required to improve the voltage comparison accuracy of the comparator circuit mounted in the ADC circuit. Here, as one of the factors that lower the voltage comparison accuracy of the comparator circuit, an offset voltage is generated in the comparator circuit. That is, an offset voltage is generated due to manufacturing variations of MOS transistors and the like included in the amplifier circuit in the comparator circuit. In particular, the offset voltage generated in the MOS transistor in the input stage of the amplifier circuit becomes a problem. In order to remove such an offset voltage, the comparator circuit often employs an offset voltage external storage (OOS (Output Offset Storage) type) structure.

For example, Patent Document 3 discloses the following OOS type comparator circuit. That is, the OOS type comparator circuit includes an amplifier circuit, a latch circuit, and a capacitor. In the OOS type comparator circuit, the offset voltage correction operation of the amplifier circuit is performed before the voltage comparison operation. That is, charges corresponding to the gain times the offset voltage of the amplifier circuit are accumulated in the two capacitors respectively connected to the differential output of the amplifier circuit. In the voltage comparison operation, two input voltages to be compared are supplied to the amplifier circuit. The amplifier circuit amplifies and outputs two input voltages. At this time, the offset voltage is canceled from the output voltage of the amplifier circuit by the two capacitors, and a voltage not including the offset voltage can be obtained. The output voltage of the amplifier circuit is sent to a latch circuit, converted to a logic level of H level or L level, and output as a comparison result. With such a configuration, it is possible to prevent a decrease in voltage comparison accuracy.
JP-A-10-107600 JP 2001-94425 A JP-T 9-512684 Publication

  However, since the comparator circuit described in Patent Document 3 includes a plurality of stages of amplifier circuits that constantly consume current, it is difficult to reduce current consumption.

  Therefore, an object of the present invention is to provide a semiconductor device capable of improving voltage comparison accuracy and reducing current consumption.

  In order to solve the above problems, a semiconductor device according to an aspect of the present invention is supplied with a constant current source, a first conduction electrode coupled to the constant current source, a second conduction electrode, and a first input voltage. Supplied with a first transistor having a control electrode coupled to the first input node, a first conduction electrode coupled to the constant current source, a second conduction electrode, and a second input voltage. A second transistor having a control electrode coupled to the second input node; a first switch connected between the second conduction electrode of the first transistor and the first output node; A second switch connected between the second conduction electrode of the first transistor and the second output node; and a third switch connected between the second conduction electrode of the first transistor and the second output node. Switch, the second conductive electrode of the second transistor and the first A fourth switch connected to the output node; coupled to the first output node; charged according to a current flowing through the first transistor when the first switch is on; and a fourth switch The first capacitor is charged with a charge corresponding to the current flowing through the second transistor when the switch is on, and is coupled to the second output node, and flows through the second transistor when the second switch is on. And a second capacitor charged with a charge according to the current and charged with a charge according to the current flowing through the first transistor when the third switch is on.

  According to the present invention, it is possible to improve voltage comparison accuracy and reduce current consumption.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<First Embodiment>
[Configuration and basic operation]
FIG. 1 is a diagram showing a configuration of a differential amplifier circuit according to the first embodiment of the present invention.

  Referring to FIG. 1, differential amplifier circuit 101 has, for example, a non-inverting input terminal coupled to input node N1, an inverting input terminal coupled to input node N2, and a non-inverting output terminal coupled to output node N3. , An inverting output terminal is coupled to output node N4.

  Hereinafter, an offset voltage resulting from manufacturing variations of input transistors of the differential amplifier circuit 101, that is, P-channel MOS transistors MP1 and MP2 described later is referred to as Vos, and the offset voltage Vos is supplied to the non-inverting input terminal of the differential amplifier circuit 101. It shall be. The gain of the differential amplifier circuit 101 is A.

  Input voltages Vip and Vin to be compared are supplied to input nodes N1 and N2, respectively. Differential amplifier circuit 101 amplifies the voltage difference between input voltages Vip and Vin, and outputs output voltages Vop and Von representing the amplification results to output nodes N3 and N4, respectively.

FIG. 2 is a circuit diagram showing a configuration of the differential amplifier circuit according to the first embodiment of the present invention.
Referring to FIG. 2, differential amplifier circuit 101 includes a constant current source IBS, P channel MOS transistors MP1, MP2, MP3, MP4, MP5 and MP6, N channel MOS transistors MN1 and MN2, and capacitors CL1 and CL2. With. Each of P channel MOS transistors MP3, MP4, MP5 and MP6 and N channel MOS transistors MN1 and MN2 may be a complementary switch combining, for example, an N channel MOS transistor and a P channel MOS transistor.

  A first terminal of constant current source IBS is connected to a power supply node to which power supply voltage VDD is supplied. P channel MOS transistor MP1 has a source connected to the second terminal of constant current source IBS, a drain connected to the source of P channel MOS transistor MP3 and the source of P channel MOS transistor MP5, and a gate connected to input node N1. Connected. P channel MOS transistor MP2 has its source connected to the second terminal of constant current source IBS, its drain connected to the source of P channel MOS transistor MP4 and the source of P channel MOS transistor MP6, and its gate connected to input node N2. Connected. Control voltage Vp2 is supplied to the gate of P-channel MOS transistor MP3, and the drain is connected to output node N3. Control voltage Vp2 is supplied to the gate of P-channel MOS transistor MP4, and the drain is connected to output node N4. Control voltage Vp1 is supplied to the gate of P-channel MOS transistor MP5, and the drain is connected to output node N4. Control voltage Vp1 is supplied to the gate of P-channel MOS transistor MP6, and the drain is connected to output node N3. Capacitor CL1 has a first terminal connected to output node N3 and a second terminal connected to a ground node to which ground voltage VSS is supplied. N-channel MOS transistor MN1 is connected in parallel with capacitor CL1. That is, the N-channel MOS transistor MN1 has a drain connected to the first terminal of the capacitor CL1, and a source connected to the second terminal of the capacitor CL1. The N-channel MOS transistor MN1 is supplied with a control voltage Vp0 at its gate. Capacitor CL2 has a first terminal connected to output node N4 and a second terminal connected to a ground node supplied with ground voltage VSS. N-channel MOS transistor MN2 is connected in parallel with capacitor CL2. That is, the N-channel MOS transistor MN2 has a drain connected to the first terminal of the capacitor CL2 and a source connected to the second terminal of the capacitor CL2. The N-channel MOS transistor MN2 is supplied with a control voltage Vp0 at its gate.

[Operation]
Next, the operation of the differential amplifier circuit according to the first embodiment of the present invention will be described.

  FIG. 3A is a waveform diagram of a control voltage in the differential amplifier circuit according to the first embodiment of the present invention. (B) is a waveform diagram of the output voltage of the differential amplifier circuit according to the first embodiment of the present invention. (C) is a waveform diagram of current consumption of the differential amplifier circuit according to the first embodiment of the present invention.

  Referring to FIGS. 3A to 3C, capacitors CL1 and CL2 are discharged at time t1. That is, control voltage Vp0 is set to H level, control voltage Vp1 is set to H level, and control voltage Vp2 is set to H level (state ST1). At this time, P-channel MOS transistors MP3, MP4, MP5, and MP6 are in an off state, and N-channel MOS transistors MN1 and MN2 are in an on state. Thereby, the electric charge stored in capacitors CL1 and CL2 is discharged.

  In state ST1, since P-channel MOS transistors MP3, MP4, MP5, and MP6 are in an off state, no current flows from constant current source IBS to capacitors CL1 and CL2, so that no current is consumed in differential amplifier circuit 101. .

  Next, at time t2, capacitors CL1 and CL2 are charged with reference voltage VREF. That is, control voltage Vp0 is set to L level, control voltage Vp1 is set to L level, and control voltage Vp2 is set to H level (state ST2). At this time, P channel MOS transistors MP3 and MP4 are in an off state, P channel MOS transistors MP5 and MP6 are in an on state, and N channel MOS transistors MN1 and MN2 are in an off state.

  In state ST2, reference voltage VREF is supplied to the gates of P-channel MOS transistors MP1 and MP2. Then, P channel MOS transistor MP1 is turned on, and a current based on reference voltage VREF flows from constant current source IBS to capacitor CL2 via P channel MOS transistors MP1 and MP5. When P channel MOS transistor MP2 is turned on, a current based on reference voltage VREF flows from constant current source IBS to capacitor CL1 through P channel MOS transistors MP2 and MP6. Thereby, the capacitors CL1 and CL2 are charged, and the output voltage Vop and the output voltage Von satisfy the following expressions.

Vop−Von = −A × Vos (1)
Here, the reference voltage VREF is preferably a ground voltage in the analog circuit in the previous stage of the differential amplifier circuit 101. For example, when a circuit including the differential amplifier circuit 101 operates with only a single power supply, that is, the power supply voltage VDD, the reference voltage VREF is a voltage that is ½ of the power supply voltage VDD. For example, when the power supply voltage VDD is 5V, the reference voltage VREF is 2.5V.

  Next, at time t3, charging operation of capacitors CL1 and CL2 by input voltages Vip and Vin is performed. That is, control voltage Vp0 is set to L level, control voltage Vp1 is set to H level, and control voltage Vp2 is set to L level (state ST3). At this time, P-channel MOS transistors MP3 and MP4 are on, P-channel MOS transistors MP5 and MP6 are off, and N-channel MOS transistors MN1 and MN2 are off.

  In state ST3, input voltages Vip and Vin are supplied to the gates of P-channel MOS transistors MP1 and MP2, respectively. Then, P channel MOS transistor MP1 is turned on, and a current based on input voltage Vip flows from constant current source IBS to capacitor CL1 via P channel MOS transistors MP1 and MP3. When P channel MOS transistor MP2 is turned on, a current based on input voltage Vin flows from constant current source IBS to capacitor CL2 via P channel MOS transistors MP2 and MP4. Thereby, capacitors CL1 and CL2 are charged.

  As a result, voltages based on the amount of charge charged in capacitors CL1 and CL2 and the capacitance values of capacitors CL1 and CL2 are generated at output nodes N3 and N4, respectively. Each of these voltage values is a value corresponding to the voltage values of the input voltages Vip and Vin and the voltage value of the offset voltage Vos. Then, the output voltage Vop and the output voltage Von satisfy the following expression when the charges charged in the capacitors CL1 and CL2 in the state ST2 are not considered.

Vop−Von = A × (Vip−Vin + Vos) (2)
Here, the charges charged in capacitors CL1 and CL2 in state ST2 are opposite in polarity to the charges charged in capacitors CL1 and CL2 in state ST3. Therefore, the output voltage Vop and the output voltage Von actually satisfy the following expression.

Vop−Von = A × (Vip−Vin + Vos) −A × Vos = A × (Vip−Vin) (3)
Next, at time t4, control voltage Vp0 is set to L level, control voltage Vp1 is set to H level, and control voltage Vp2 is set to H level (state ST4). At this time, P-channel MOS transistors MP3, MP4, MP5 and MP6 and N-channel MOS transistors MN1 and MN2 are off. Thereby, the output voltages Vop and Von maintain the relationship of Formula (3).

  In state ST4, since P-channel MOS transistors MP3, MP4, MP5, and MP6 are in an off state, no current flows from constant current source IBS to capacitors CL1 and CL2, so that no current is consumed in differential amplifier circuit 101. .

  Therefore, in the differential amplifier circuit according to the first embodiment of the present invention, the offset voltage Vos can be canceled from the output voltages Vop and Von. In addition, since current is consumed only in states ST2 and ST3, a differential amplifier circuit that performs differential amplification operation with low current consumption can be realized. That is, in the differential amplifier circuit according to the first embodiment of the present invention, it is possible to improve voltage comparison accuracy and reduce current consumption.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Second Embodiment>
The present embodiment relates to a differential amplifier circuit corresponding to an input voltage in a range different from that of the differential amplifier circuit according to the first embodiment. The contents other than those described below are the same as those of the differential amplifier circuit according to the first embodiment.

[Configuration and basic operation]
FIG. 4 is a diagram showing a configuration of a differential amplifier circuit according to the second embodiment of the present invention.

  Referring to FIG. 4, differential amplifier circuit 102 includes constant current source IBS, N-channel MOS transistors MN21, MN22, MN23, MN24, MN25, MN26, P-channel MOS transistors MP21 and MP22, capacitor CL21, And a capacitor CL22. Each of N channel MOS transistors MN23, MN24, MN25, MN26, and P channel MOS transistors MP21, MP22 may be, for example, a complementary switch in which an N channel MOS transistor and a P channel MOS transistor are combined.

  A first terminal of constant current source IBS is connected to a ground node to which ground voltage VSS is supplied. N channel MOS transistor MN21 has a source connected to the second terminal of constant current source IBS, a drain connected to the source of N channel MOS transistor MN23 and the source of N channel MOS transistor MN25, and a gate connected to input node N1. Connected. N channel MOS transistor MN22 has a source connected to the second terminal of constant current source IBS, a drain connected to the source of N channel MOS transistor MN24 and the source of N channel MOS transistor MN26, and a gate connected to input node N2. Connected. Control voltage Vp2 is supplied to the gate of N-channel MOS transistor MN23, and the drain is connected to output node N3. Control voltage Vp2 is supplied to the gate of N-channel MOS transistor MN24, and the drain is connected to output node N4. Control voltage Vp1 is supplied to the gate of N-channel MOS transistor MN25, and the drain is connected to output node N4. Control voltage Vp1 is supplied to the gate of N-channel MOS transistor MN26, and the drain is connected to output node N3. Capacitor CL21 has a first terminal connected to output node N3 and a second terminal connected to a power supply node to which power supply voltage VDD is supplied. P-channel MOS transistor MP21 is connected in parallel with capacitor CL21. That is, P channel MOS transistor MP21 has a drain connected to the first terminal of capacitor CL21 and a source connected to the second terminal of capacitor CL21. The control voltage Vp0 is supplied to the gate of the P-channel MOS transistor MP21. Capacitor CL22 has a first terminal connected to output node N4 and a second terminal connected to a power supply node supplied with power supply voltage VDD. P-channel MOS transistor MP22 is connected in parallel with capacitor CL22. That is, P channel MOS transistor MP22 has a drain connected to the first terminal of capacitor CL22 and a source connected to the second terminal of capacitor CL22. The control voltage Vp0 is supplied to the gate of the P-channel MOS transistor MP22.

[Operation]
Next, the operation of the differential amplifier circuit according to the second embodiment of the present invention will be described.

  FIG. 5A is a waveform diagram of the control voltage in the differential amplifier circuit according to the second embodiment of the present invention. FIG. 6B is a waveform diagram of current consumption of the differential amplifier circuit according to the second embodiment of the present invention.

  Referring to FIGS. 5A and 5B, capacitors CL21 and CL22 are discharged at time t1. That is, control voltage Vp0 is set to L level, control voltage Vp1 is set to L level, and control voltage Vp2 is set to L level (state ST1). At this time, N-channel MOS transistors MN23, MN24, MN25, and MN26 are off, and P-channel MOS transistors MP21 and MP22 are on. Thereby, the electric charge stored in capacitors CL21 and CL22 is discharged.

  In state ST1, since N-channel MOS transistors MN23, MN24, MN25, and MN26 are off, no current flows from the power supply node to constant current source IBS via capacitors CL21 and CL22. In this case, no current is consumed.

  Next, at time t2, charging operation of capacitors CL21 and CL22 with reference voltage VREF is performed. That is, control voltage Vp0 is set to H level, control voltage Vp1 is set to H level, and control voltage Vp2 is set to L level (state ST2). At this time, N channel MOS transistors MN23 and MN24 are in an off state, N channel MOS transistors MN25 and MN26 are in an on state, and P channel MOS transistors MP21 and MP22 are in an off state.

  In state ST2, reference voltage VREF is supplied to the gates of N-channel MOS transistors MN21 and MN22, respectively. Then, N channel MOS transistor MN21 is turned on, and a current based on reference voltage VREF flows from power supply node to constant current source IBS via capacitor CL22, N channel MOS transistor MN25 and N channel MOS transistor MN21. Further, when N channel MOS transistor MN22 is turned on, a current based on reference voltage VREF flows from the power supply node to constant current source IBS via capacitor CL21, N channel MOS transistor MN26 and N channel MOS transistor MN22. Thereby, capacitors CL21 and CL22 are charged, and output voltage Vop and output voltage Von satisfy the following expressions.

Vop−Von = −A × Vos (4)
Here, the reference voltage VREF is preferably a ground voltage in the analog circuit in the previous stage of the differential amplifier circuit 102. For example, when a circuit including the differential amplifier circuit 102 operates with only a single power supply, that is, the power supply voltage VDD, the reference voltage VREF is a voltage that is ½ of the power supply voltage VDD. For example, when the power supply voltage VDD is 5V, the reference voltage VREF is 2.5V.

  Next, at time t3, capacitors CL21 and CL22 are charged by input voltages Vip and Vin. That is, control voltage Vp0 is set to H level, control voltage Vp1 is set to L level, and control voltage Vp2 is set to H level (state ST3). At this time, N channel MOS transistors MN23 and MN24 are in an on state, N channel MOS transistors MN25 and MN26 are in an off state, and P channel MOS transistors MP21 and MP22 are in an off state.

  In state ST3, input voltages Vip and Vin are supplied to the gates of N-channel MOS transistors MN21 and MN22, respectively. Then, N channel MOS transistor MN21 is turned on, so that a current based on input voltage Vip flows from power supply node to constant current source IBS via capacitor CL21, N channel MOS transistor MN23 and N channel MOS transistor MN21. Further, when N channel MOS transistor MN22 is turned on, a current based on input voltage Vin flows from power supply node to constant current source IBS via capacitor CL22, N channel MOS transistor MN24 and N channel MOS transistor MN22. Thereby, capacitors CL21 and CL22 are charged.

  As a result, voltages based on the amount of charge charged in capacitors CL21 and CL22 and the capacitance values of capacitors CL21 and CL22 are generated at output nodes N3 and N4, respectively. Each of these voltage values is a value corresponding to the voltage values of the input voltages Vip and Vin and the voltage value of the offset voltage Vos. Then, the output voltage Vop and the output voltage Von satisfy the following expression when the charges charged in the capacitors CL21 and CL22 in the state ST2 are not considered.

Vop−Von = A × (Vip−Vin + Vos) (5)
Here, the charges charged in capacitors CL21 and CL22 in state ST2 are opposite in polarity to the charges charged in capacitors CL21 and CL22 in state ST3. Therefore, the output voltage Vop and the output voltage Von actually satisfy the following expression.

Vop−Von = A × (Vip−Vin + Vos) −A × Vos = A × (Vip−Vin) (6)
Next, at time t4, control voltage Vp0 is set to H level, control voltage Vp1 is set to L level, and control voltage Vp2 is set to L level (state ST4). At this time, the N channel MOS transistors MN23, MN24, MN25, MN26 and the P channel MOS transistors MP21, MP22 are in the off state. Thereby, the output voltages Vop and Von maintain the relationship of Formula (6).

  In state ST4, since N-channel MOS transistors MN23, MN24, MN25, and MN26 are in an off state, no current flows from the power supply node to constant current source IBS via capacitors CL21 and CL22. In this case, no current is consumed.

  Therefore, in the differential amplifier circuit according to the second embodiment of the present invention, the offset voltage Vos can be canceled from the output voltages Vop and Von. In addition, since current is consumed only in states ST2 and ST3, a differential amplifier circuit that performs differential amplification operation with low current consumption can be realized. That is, in the differential amplifier circuit according to the second embodiment of the present invention, the voltage comparison accuracy can be improved and the current consumption can be reduced.

  Here, the input voltage range of the differential amplifier circuit 101 according to the first embodiment of the present invention is on the 0V side. That is, the voltage is from 0V to Vinr1. Here, the voltage Vinr1 is a voltage obtained by adding an overdrive voltage of the constant current source IBS and a voltage (threshold voltage + overdrive voltage) necessary for the P-channel MOS transistors MP1 and MP2 to operate in the saturation region. The voltage is subtracted from the voltage VDD.

  On the other hand, the input voltage range of the differential amplifier circuit 102 according to the second embodiment of the present invention is on the power supply voltage VDD side. That is, from the voltage Vinr2 to the power supply voltage VDD. Here, the voltage Vinr2 is a voltage obtained by adding the overdrive voltage of the constant current source IBS and a voltage (threshold voltage + overdrive voltage) necessary for the N-channel MOS transistors MN21 and MN22 to operate in the saturation region. .

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Third Embodiment>
The present embodiment relates to a differential amplifier circuit in which a specific configuration for realizing an input voltage reset function is added to the differential amplifier circuit according to the first embodiment. The contents other than those described below are the same as those of the differential amplifier circuit according to the first embodiment.

[Configuration and basic operation]
FIG. 6 is a diagram showing the configuration of the differential amplifier circuit according to the third embodiment of the present invention.

  Referring to FIG. 6, differential amplifier circuit 201 includes differential amplifier circuit 101 and switches S0P, S0N, S1P, and S1N.

  Switch S0P is connected between input node N1 and the non-inverting input terminal of differential amplifier circuit 101, that is, the gate of P-channel MOS transistor MP1. Switch S0N is connected between input node N2 and the inverting input terminal of differential amplifier circuit 101, that is, the gate of P-channel MOS transistor MP2. Switch S1P is connected between reference voltage node N5 to which reference voltage VREF is supplied and the non-inverting input terminal of differential amplifier circuit 101, that is, the gate of P channel MOS transistor MP1. Switch S1N is connected between reference voltage node N6 to which reference voltage VREF is supplied and the inverting input terminal of differential amplifier circuit 101, that is, the gate of P-channel MOS transistor MP2.

[Operation]
Next, the operation of the differential amplifier circuit according to the third embodiment of the present invention will be described.

  Referring again to FIGS. 3A to 3C, at time t1, control voltage Vp0 is set to H level, control voltage Vp1 is set to H level, and control voltage Vp2 is set to H level (state ST1). At this time, the switches S0P and S0N are in an off state, and the switches S1P and S1N are in an off state. P channel MOS transistors MP3, MP4, MP5 and MP6 are in an off state, and N channel MOS transistors MN1 and MN2 are in an on state. Thereby, the electric charge stored in capacitors CL1 and CL2 is discharged. That is, the charge accumulation state of capacitors CL1 and CL2 by input voltages Vip and Vin before time t1 is reset.

  Next, at time t2, control voltage Vp0 is set to L level, control voltage Vp1 is set to L level, and control voltage Vp2 is set to H level (state ST2). At this time, the switches S0P and S0N are in an off state, and the switches S1P and S1N are in an on state. As a result, the reference voltage VREF is supplied to the gate of the P-channel MOS transistor MP1 and the gate of the P-channel MOS transistor MP2 of the differential amplifier circuit 101, respectively. In differential amplifier circuit 101, capacitors CL1 and CL2 are charged by reference voltage VREF. Since this operation is the same as that of the differential amplifier circuit according to the first embodiment of the present invention, detailed description thereof will not be repeated here.

  Next, at time t3, control voltage Vp0 is set to L level, control voltage Vp1 is set to H level, and control voltage Vp2 is set to L level (state ST3). At this time, the switches S0P and S0N are on, and the switches S1P and S1N are off. Thereby, input voltages Vip and Vin are supplied to the gate of P channel MOS transistor MP1 and the gate of P channel MOS transistor MP2 of differential amplifier circuit 101, respectively. In differential amplifier circuit 101, capacitors CL1 and CL2 are charged by input voltages Vip and Vin. Since this operation is the same as that of the differential amplifier circuit according to the first embodiment of the present invention, detailed description thereof will not be repeated here.

  Next, at time t4, control voltage Vp0 is set to L level, control voltage Vp1 is set to H level, and control voltage Vp2 is set to H level (state ST4). At this time, the switches S0P and S0N are in an off state, and the switches S1P and S1N are in an off state. In the differential amplifier circuit 101, the output voltage Vop and the output voltage Von are maintained.

  Here, in the states ST1 and ST4, since the P-channel MOS transistors MP3, MP4, MP5, and MP6 in the differential amplifier circuit 101 are in the off state, the differential amplifier circuit by the switching operation of the switches S0P, S0N, S1P, and S1N. There is no influence on the differential amplification operation of 101.

  Since other configurations and operations are the same as those of the differential amplifier circuit according to the first embodiment, detailed description thereof will not be repeated here.

  Therefore, in the differential amplifier circuit according to the third embodiment of the present invention, the offset voltage Vos can be canceled from the output voltage. In addition, since current is consumed only in states ST2 and ST3, a differential amplifier circuit that performs differential amplification operation with low current consumption can be realized. That is, in the differential amplifier circuit according to the third embodiment of the present invention, the voltage comparison accuracy can be improved and the current consumption can be reduced.

  Each of switches S0P, S0N, S1P, and S1N may be an N-channel MOS transistor, a P-channel MOS transistor, or a combination of an N-channel MOS transistor and a P-channel MOS transistor. It may be a complementary switch. In this case, the level of the control voltage supplied to each switch may be set as appropriate so that the states ST1 to ST4 can be realized.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Fourth embodiment>
The present embodiment relates to a comparator circuit in which a latch circuit is added to the differential amplifier circuit according to the third embodiment. The contents other than those described below are the same as those of the differential amplifier circuit according to the third embodiment.

[Configuration and basic operation]
FIG. 7 is a diagram showing a configuration of a comparator circuit according to the fourth embodiment of the present invention.

  Referring to FIG. 7, the comparator circuit 301 includes a differential amplifier circuit 101, switches S0P, S0N, S1P, S1N, and a latch circuit 51.

  Latch circuit 51 compares output voltage Vop and output voltage Von received from differential amplifier circuit 101, holds an H-level or L-level digital signal representing the comparison result, and outputs it as output voltages VOUTP and VOUTN.

  FIG. 8 is a circuit diagram showing a configuration of the latch circuit 51 in the comparator circuit according to the fourth embodiment of the present invention.

  Referring to FIG. 8, latch circuit 51 includes a latch circuit body 21, a buffer circuit 22, and a reset set flip-flop circuit (RS flip-flop circuit) 23. The latch circuit body 21 includes P-channel MOS transistors MP11, MP12, MP13, MP14 and N-channel MOS transistors MN11, MN12, MN13, MN14, MN15, MN16, MN17, MN18. Buffer circuit 22 includes inverter circuits G1, G2, G3, and G4. Reset set flip-flop circuit 23 includes NAND circuits G5 and G6.

  The gate of the N-channel MOS transistor MN11 corresponds to the non-inverting input terminal of the latch circuit 51. The gate of the N-channel MOS transistor MN12 corresponds to the inverting input terminal of the latch circuit 51. That is, output voltages Vop and Von are supplied to the gates of N-channel MOS transistors MN11 and MN12, respectively.

  P-channel MOS transistors MP11 and MP12 and N-channel MOS transistors MN15 and MN16 start a latch operation based on control voltage VLATCH.

  P-channel MOS transistors MP13 and MP14 and N-channel MOS transistors MN13 and MN14 constitute a positive feedback circuit for rapidly determining the output voltage of latch circuit body 21.

  N-channel MOS transistors MN17 and MN18 keep the output voltage of latch circuit body 21 constant when latch circuit 51 is not performing a latch operation.

  The reset set flip-flop circuit 23 holds the output voltage of the latch circuit body 21 received via the buffer circuit 22 and outputs it to the outside as output voltages VOUTP and VOUTN.

  In the latch circuit 51, when the output voltage Vop is higher than the output voltage Von, the output voltage VOUTP is H level and the output voltage VOUTN is L level, and when the output voltage Vop is lower than the output voltage Von, the output voltage VOUTP is L level and output. The voltage VOUTN becomes H level. In the latch circuit 51, no current is consumed when the latch operation is not performed.

[Operation]
Next, the operation of the comparator circuit according to the fourth embodiment of the present invention will be described.

  FIG. 9A is a waveform diagram of the control voltage of the differential amplifier circuit in the comparator circuit according to the fourth embodiment of the present invention. (B) is a wave form chart of current consumption of a differential amplifier circuit in a comparator circuit concerning a 4th embodiment of the present invention.

  9A and 9B, at time t4, control voltage Vp0 is set to L level, control voltage Vp1 is set to H level, and control voltage Vp2 is set to H level. Then, after a predetermined time has elapsed from time t4, control voltage VLATCH is set from L level to H level (state ST4). When the control voltage VLATCH supplied to the latch circuit 51 changes from the L level to the H level, the latch circuit 51 compares the output voltage Vop and the output voltage Von received from the differential amplifier circuit 101, and outputs an H level representing the comparison result or An L level digital signal is held and output as output voltages VOUTP and VOUTN.

  Since other configurations and operations are the same as those of the differential amplifier circuit according to the third embodiment, detailed description thereof will not be repeated here.

  Therefore, in the comparator circuit according to the fourth embodiment of the present invention, the offset voltage Vos can be canceled from the output voltage of the differential amplifier circuit. In the differential amplifier circuit, current is consumed only in the states ST2 and ST3, and in the latch circuit, current is consumed only during the latch operation in the state ST4. A comparator circuit that performs a voltage comparison operation can be realized. That is, in the comparator circuit according to the fourth embodiment of the present invention, the voltage comparison accuracy can be improved and the current consumption can be reduced.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Fifth embodiment>
The present embodiment relates to a comparator circuit in which the differential amplifier circuit in the comparator circuit according to the fourth embodiment has a plurality of stages. The contents other than those described below are the same as those of the comparator circuit according to the fourth embodiment.

[Configuration and basic operation]
FIG. 10 is a diagram showing a configuration of a comparator circuit according to the fifth embodiment of the present invention.

  Referring to FIG. 10, comparator circuit 401 includes differential amplifier circuits 101A and 101B, switches S0P, S0N, S1P, S1N, S2P, S2N, S3P, and S3N, and latch circuit 51. The configurations of the differential amplifier circuits 101A and 101B are the same as those of the differential amplifier circuit 101 described above.

  Switch S0P is connected between input node N1A and the non-inverting input terminal of differential amplifier circuit 101A, that is, the gate of P-channel MOS transistor MP1. Switch S0N is connected between input node N2A and the inverting input terminal of differential amplifier circuit 101A, that is, the gate of P-channel MOS transistor MP2. Switch S1P is connected between reference voltage node N5A to which reference voltage VREF is supplied and the non-inverting input terminal of differential amplifier circuit 101A, that is, the gate of P-channel MOS transistor MP1. Switch S1N is connected between reference voltage node N6A to which reference voltage VREF is supplied and the inverting input terminal of differential amplifier circuit 101A, that is, the gate of P-channel MOS transistor MP2.

  The switch S2P is connected between the output node N3A, that is, the input node N1B, and the non-inverting input terminal of the differential amplifier circuit 101B. The switch S2N is connected between the output node N4A, that is, the input node N2B, and the inverting input terminal of the differential amplifier circuit 101B. The switch S3P is connected between the reference voltage node N5B to which the reference voltage VREF is supplied and the non-inverting input terminal of the differential amplifier circuit 101B. The switch S3N is connected between the reference voltage node N6B to which the reference voltage VREF is supplied and the inverting input terminal of the differential amplifier circuit 101B.

  Non-inverting input terminal of latch circuit 51 and output node N3B are connected. The inverting input terminal of latch circuit 51 is connected to output node N4B.

  Differential amplifier circuit 101A amplifies the voltage difference between input voltages Vip and Vin, and outputs output voltages Vop and Von representing the amplification results to output nodes N3A and N4A, respectively.

  Differential amplifier circuit 101B amplifies the difference in voltage received from differential amplifier circuit 101A, that is, output node N3A and output node N3B, and outputs output voltages Vop and Von representing the amplification results to output nodes N3B and N4B, respectively. .

[Operation]
Next, the operation of the comparator circuit according to the fifth embodiment of the present invention will be described.

  FIG. 11A is a waveform diagram of control voltages of the differential amplifier circuits 101A and 101B in the comparator circuit according to the fifth embodiment of the present invention. (B) is a wave form chart of current consumption of differential amplifier circuits 101A and 101B in a comparator circuit concerning a 5th embodiment of the present invention.

  Referring to FIGS. 11A and 11B, at time t1, control voltage Vp0 is set to H level, control voltage Vp1 is set to H level, and control voltage Vp2 is set to H level (state ST1). At this time, the switches S0P, S0N, S2P, and S2N are in an off state, and the switches S1P, S1N, S3P, and S3N are in an off state. In each of differential amplifier circuits 101A and 101B, capacitors CL1 and CL2 are discharged. Since this operation is the same as that of the differential amplifier circuit according to the first embodiment of the present invention, detailed description thereof will not be repeated here.

  Next, at time t2, control voltage Vp0 is set to L level, control voltage Vp1 is set to L level, and control voltage Vp2 is set to H level (state ST2). At this time, the switches S0P, S0N, S2P, and S2N are in an off state, and the switches S1P, S1N, S3P, and S3N are in an on state. Thus, reference voltage VREF is supplied to the gate of P channel MOS transistor MP1 and the gate of P channel MOS transistor MP2 of each of differential amplifier circuits 101A and 101B. In each of differential amplifier circuits 101A and 101B, charging operation of capacitors CL1 and CL2 by reference voltage VREF is performed. Since this operation is the same as that of the differential amplifier circuit according to the first embodiment of the present invention, detailed description thereof will not be repeated here.

  Next, at time t3, control voltage Vp0 is set to L level, control voltage Vp1 is set to H level, and control voltage Vp2 is set to L level (state ST3). At this time, the switches S0P, S0N, S2P, and S2N are on, and the switches S1P, S1N, S3P, and S3N are off. Thereby, input voltages Vip and Vin are supplied to the gate of P channel MOS transistor MP1 and the gate of P channel MOS transistor MP2 of differential amplifier circuit 101A, respectively. The output voltages Vop and Von of the differential amplifier circuit 101A are supplied to the gate of the P channel MOS transistor MP1 and the gate of the P channel MOS transistor MP2 of the differential amplifier circuit 101B, respectively. In each of differential amplifier circuits 101A and 101B, charging operation of capacitors CL1 and CL2 by input voltages Vip and Vin is performed. Since this operation is the same as that of the differential amplifier circuit according to the first embodiment of the present invention, detailed description thereof will not be repeated here.

  Next, at time t4, the control voltage Vp0 is set to the L level, the control voltage Vp1 is set to the H level, and the control voltage Vp2 is set to the H level. Then, after a predetermined time has elapsed from time t4, control voltage VLATCH is set from L level to H level (state ST4). At this time, the switches S0P, S0N, S2P, and S2N are in an off state, and the switches S1P, S1N, S3P, and S3N are in an off state. In each of differential amplifier circuits 101A and 101B, output voltage Vop and output voltage Von are maintained.

  Further, when the control voltage VLATCH supplied to the latch circuit 51 changes from the L level to the H level, the latch circuit 51 receives the output voltage Vop and the output voltage Von received from the differential amplifier circuit 101B, that is, the output node N3B and the output node N4B. Compares and holds a digital signal of H level or L level representing the comparison result and outputs it as output voltages VOUTP and VOUTN.

  Here, in the states ST1 and ST4, the P-channel MOS transistors MP3, MP4, MP5, and MP6 in each of the differential amplifier circuits 101A and 101B are in the off state, so that the switches S0P, S0N, S2P, S2N, S1P, and S1N , S3P and S3N have no effect on the differential amplification operation of the differential amplifier circuits 101A and 101B.

  Since other configurations and operations are the same as those of the comparator circuit according to the fourth embodiment, detailed description thereof will not be repeated here.

  Therefore, in the comparator circuit according to the fifth embodiment of the present invention, the offset voltage Vos can be canceled from the output voltage of the differential amplifier circuit. In the differential amplifier circuit, current is consumed only in the states ST2 and ST3, and in the latch circuit, current is consumed only during the latch operation in the state ST4. A comparator circuit that performs a voltage comparison operation can be realized. In other words, the comparator circuit according to the fifth embodiment of the present invention can improve the voltage comparison accuracy and reduce the current consumption.

  Further, in the comparator circuit according to the fifth embodiment of the present invention, the amplification capability is increased by the configuration including the differential amplifier circuits 101A and 101B, so that the time for obtaining the voltage comparison result exponentially is increased. Can do. Further, since the amplification capability is increased, it is possible to amplify a smaller difference between the input voltages Vip and Vin to a voltage that can be determined by the latch circuit 51, so that the voltage comparison accuracy can be further improved.

  In the comparator circuit according to the fifth embodiment of the present invention, the number of stages of the differential amplifier circuit is two, but the present invention is not limited to this. By further increasing the number of stages, a comparator circuit with higher speed and higher voltage comparison accuracy can be realized.

  Each of switches S0P, S0N, S2P, S2N, S1P, S1N, S3P, and S3N may be an N-channel MOS transistor, a P-channel MOS transistor, or an N-channel MOS transistor. Also, it may be a complementary switch combining a P-channel MOS transistor. In this case, the level of the control voltage supplied to each switch may be set as appropriate so that the states ST1 to ST4 can be realized.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Sixth Embodiment>
The present embodiment relates to an ADC circuit including the comparator circuit according to the fourth embodiment of the present invention. The contents other than those described below are the same as those of the comparator circuit according to the fourth embodiment.

[Configuration and basic operation]
FIG. 12 is a diagram showing a configuration of an ADC circuit according to the sixth embodiment of the present invention.

  Referring to FIG. 12, the ADC circuit 501 is a successive approximation ADC circuit, and includes a comparator circuit 301, a DAC (digital / analog converter) circuit 31, and a successive approximation register circuit 32. The DAC circuit 31 is a charge redistribution type, and includes capacitors C0 to C11, Cc, CA, and switches S0 to S11, S21, S22, SA. VAIN is an analog input voltage of the ADC circuit 501, VREF is a reference voltage of the comparator circuit 301 and the DAC circuit 31, and VDAC_OUT is an output voltage of the DAC circuit 31. The ADC circuit 501 is realized as one semiconductor integrated circuit, for example.

  The DAC circuit 31 generates the voltage VDAC_OUT by dividing the reference voltage VREF using the capacitors C0 to C11, Cc, and CA based on the 13-bit data received from the successive approximation register circuit 32. The capacitors C11 to C6 are set so that the capacitance is halved from the larger subscript to the smaller subscript. Similarly, the capacitors C5 to C0 are set so that the capacitance is halved from the larger subscript to the smaller subscript. Capacitor CA is set to the same capacity as capacitor C0. By disposing the capacitor Cc, the capacitor C5 can be set to the same capacitance value as the capacitor C11. For example, if the capacitance of the capacitor C11 is 64 × C, the capacitance of the capacitor C6 is 2 × C, the capacitance of the capacitor C5 is 64 × C, and the capacitances of the capacitors C0 and CA are 2 × C. The capacitance of the capacitor Cc is set to about 2 × C.

FIG. 13 is a waveform diagram of the output voltage of the DAC circuit 31 in the ADC circuit 501.
The operation of the ADC circuit 501 is divided into an initialization operation (timing a), an analog input voltage sampling operation (timing b), and a voltage comparison operation (after timing c).

  Referring to FIG. 13, at timing a, the successive approximation register circuit 32 is reset, and all 13-bit data output from the successive approximation register circuit 32 become zero. At this time, since the capacitors C0 to C11 and CA are connected to a node to which the reference voltage VREF is supplied, the DAC circuit 31 outputs the reference voltage VREF as the output voltage VDAC_OUT.

  At timing b, the analog input voltage VAIN is supplied to the DAC circuit 31 from the outside. The capacitors C0 to C11 and CA are connected to a node to which the analog input voltage VAIN is supplied. For this reason, the output voltage VDAC_OUT of the DAC circuit 31 becomes VREF−VAIN.

  At timing c, as the first comparison operation, the most significant bit B11 of the DAC circuit 31 is set to the initial value 1, and the bits B10 to B0 are set to 0. At this time, the capacitors C0 to C10 and CA are connected to a node to which the ground voltage VSS is supplied.

  Here, if the 12-bit data received from the successive approximation register circuit 32 by the DAC circuit 31 is b0 to b11, the output voltage VDAC_OUT of the DAC circuit 31 is expressed by the following equation.

  At timing c, since the most significant bit B11 is 1 and the bits B10 to B0 are 0, the output voltage VDAC_OUT of the DAC circuit 31 is expressed by the following equation.

VDAC_OUT = VREF−VAIN + VREF / 2
The comparator circuit 301 compares the output voltage VDAC_OUT with the reference voltage VREF and outputs the comparison result to the successive approximation register circuit 32.

  When the output voltage VDAC_OUT is smaller than the reference voltage VREF, the successive approximation register circuit 32 determines the most significant bit B11 of the output data as 1 and proceeds to the next comparison operation. On the other hand, when the output voltage VDAC_OUT is higher than the reference voltage VREF, the successive approximation register circuit 32 determines the most significant bit B11 of the output data as 0 and proceeds to the next comparison operation. Here, as shown in FIG. 13, since the output voltage VDAC_OUT is higher than the reference voltage VREF, the successive approximation register circuit 32 determines the most significant bit B11 of the output data as 0.

  The successive approximation register circuit 32 performs the comparison operation similarly after the timing d, and determines a value up to the least significant bit B0 of the output data. That is, bit B10 of the output data is determined to be 1 at timing d, and bit B9 of the output data is determined to be 0 at timing e. Therefore, the successive approximation operation ends in a state where the output voltage VDAC_OUT does not exceed the reference voltage VREF. The 12-bit data of bits B11 to B0 output from the successive approximation register circuit 32 when the least significant bit B0 is determined is a value obtained by converting the analog input voltage VAIN into a digital value.

  FIG. 14A is a waveform diagram of the control voltage of the differential amplifier circuit in the ADC circuit according to the sixth embodiment of the present invention. (B) is a wave form chart of current consumption of a differential amplifier circuit in an ADC circuit concerning a 6th embodiment of the present invention. FIGS. 14A and 14B show the control voltage and current consumption of the differential amplifier circuit at timing c in FIG. 13, respectively.

  Since the operation at times t1 to t4 is the same as that of the comparator circuit according to the fourth embodiment of the present invention, detailed description will not be repeated here.

  Therefore, in the comparator circuit according to the sixth embodiment of the present invention, the offset voltage Vos can be canceled from the output voltage of the differential amplifier circuit. In the differential amplifier circuit, the current is consumed only in the states ST2 and ST3. In the latch circuit, the current is consumed only during the latch operation in the state ST4. A comparator circuit that performs a voltage comparison operation can be realized. That is, the comparator circuit according to the sixth embodiment of the present invention can improve the voltage comparison accuracy and reduce the current consumption.

  Here, the current consumption of the successive approximation ADC circuit is generally reduced by using a charge redistribution DAC circuit. On the other hand, the comparator circuit often employs a configuration using a plurality of stages of amplifier circuits that constantly consume current. For this reason, the ratio of the consumption current of the comparator circuit to the consumption current of the entire successive approximation ADC circuit is high. Here, by applying the differential amplifier circuit according to the embodiment of the present invention, which is a charge storage type, to the comparator circuit, the consumption current of the comparator circuit can be reduced to a fraction of the conventional one. Further, since the offset voltage of the comparator circuit is canceled, it is possible to realize a successive approximation ADC circuit capable of significantly reducing current consumption while maintaining voltage comparison accuracy.

  Further, the comparator circuit according to the fifth embodiment of the present invention can be applied to the ADC circuit 501. As a result, the amplification capability of the comparator circuit can be increased, so that the non-linearity error or the like can be reduced in the successive approximation ADC circuit as a whole, and the conversion accuracy can be improved.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a figure which shows the structure of the differential amplifier circuit which concerns on the 1st Embodiment of this invention. 1 is a circuit diagram showing a configuration of a differential amplifier circuit according to a first embodiment of the present invention. FIG. 4A is a waveform diagram of a control voltage in the differential amplifier circuit according to the first embodiment of the present invention. (B) is a waveform diagram of the output voltage of the differential amplifier circuit according to the first embodiment of the present invention. (C) is a waveform diagram of current consumption of the differential amplifier circuit according to the first embodiment of the present invention. It is a figure which shows the structure of the differential amplifier circuit which concerns on the 2nd Embodiment of this invention. (A) is a wave form chart of a control voltage in a differential amplifier circuit concerning a 2nd embodiment of the present invention. FIG. 6B is a waveform diagram of current consumption of the differential amplifier circuit according to the second embodiment of the present invention. It is a figure which shows the structure of the differential amplifier circuit which concerns on the 3rd Embodiment of this invention. It is a figure which shows the structure of the comparator circuit which concerns on the 4th Embodiment of this invention. It is a circuit diagram which shows the structure of the latch circuit 51 in the comparator circuit which concerns on the 4th Embodiment of this invention. (A) is a wave form chart of a control voltage of a differential amplifier circuit in a comparator circuit concerning a 4th embodiment of the present invention. (B) is a wave form chart of current consumption of a differential amplifier circuit in a comparator circuit concerning a 4th embodiment of the present invention. It is a figure which shows the structure of the comparator circuit which concerns on the 5th Embodiment of this invention. (A) is a wave form chart of control voltage of differential amplifier circuits 101A and 101B in a comparator circuit concerning a 5th embodiment of the present invention. (B) is a wave form chart of current consumption of differential amplifier circuits 101A and 101B in a comparator circuit concerning a 5th embodiment of the present invention. It is a figure which shows the structure of the ADC circuit which concerns on the 6th Embodiment of this invention. 6 is a waveform diagram of an output voltage of a DAC circuit 31 in an ADC circuit 501. FIG. (A) is a wave form chart of a control voltage of a differential amplifier circuit in an ADC circuit concerning a 6th embodiment of the present invention. (B) is a wave form chart of current consumption of a differential amplifier circuit in an ADC circuit concerning a 6th embodiment of the present invention.

Explanation of symbols

  21 latch circuit body, 22 buffer circuit, 23 reset set flip-flop circuit (RS flip-flop circuit), 31 DAC (digital / analog converter) circuit, 32 successive approximation register circuit, 51 latch circuit, 101, 101A, 101B, 201 difference Dynamic amplifier circuit, 301, 402 comparator circuit, 501 ADC circuit, N1, N2 input node, N3, N4 output node, IBS constant current source, MP1, MP2, MP3, MP4, MP5, MP6, MP11, MP12, MP13, MP14 , MP21, MP22 P channel MOS transistors, MN1, MN11, MN12, MN13, MN14, MN15, MN16, MN17, MN18, MN2, MN21, MN22, MN23, MN24, MN25, MN26 N Channel MOS transistors, C0 to C11, Cc, CL1, CL2, CL21, CL22 capacitors, S0 to S11, S21, S22, S0P, S0N, S1P, S1N, S2P, S2N, S3P, S3N switches, G1, G2, G3 G4 inverter circuit, G5, G6 NAND circuit.

Claims (13)

A constant current source;
A first transistor having a first conduction electrode coupled to the constant current source, a second conduction electrode, and a control electrode coupled to a first input node to which a first input voltage is supplied;
A second transistor having a first conduction electrode coupled to the constant current source, a second conduction electrode, and a control electrode coupled to a second input node supplied with a second input voltage;
A first switch connected between a second conduction electrode of the first transistor and a first output node;
A second switch connected between a second conduction electrode of the second transistor and a second output node;
A third switch connected between a second conduction electrode of the first transistor and a second output node;
A fourth switch connected between a second conduction electrode of the second transistor and a first output node;
The second transistor coupled to the first output node is charged according to a current flowing through the first transistor when the first switch is turned on, and the second transistor is turned on when the fourth switch is turned on. A first capacitor that is charged with a charge in accordance with the current flowing through;
The first transistor coupled to the second output node is charged according to a current flowing through the second transistor when the second switch is turned on, and the first transistor is turned on when the third switch is turned on. And a second capacitor that is charged with a charge corresponding to the current flowing through the semiconductor device.   The semiconductor device according to claim 1, wherein each of the first switch to the fourth switch is a MOS transistor. In the first state, the first switch and the second switch are in an off state, and the third switch and the fourth switch are in an on state;
In a second state after the first state, the first switch and the second switch are in an on state, and the third switch and the fourth switch are in an off state;
2. The semiconductor device according to claim 1, wherein in the third state after the second state, the first switch to the fourth switch are in an off state. The semiconductor device further includes:
A fifth switch connected in parallel with the first capacitor and for discharging the first capacitor;
The semiconductor device according to claim 1, further comprising: a sixth switch connected in parallel with the second capacitor and discharging the second capacitor.   The semiconductor device according to claim 4, wherein each of the first to sixth switches is a MOS transistor. In the first state, the first switch to the fourth switch are in an off state, and the fifth switch and the sixth switch are in an on state;
In a second state after the first state, the first switch and the second switch are in an off state, the third switch and the fourth switch are in an on state, and The fifth switch and the sixth switch are in an off state;
In a third state after the second state, the first switch and the second switch are on, the third switch and the fourth switch are off, and The fifth switch and the sixth switch are in an off state;
5. The semiconductor device according to claim 4, wherein in the fourth state after the third state, the first switch to the sixth switch are in an off state. The semiconductor device further includes:
A seventh switch connected between the first input node and a control electrode of the first transistor;
An eighth switch connected between the second input node and a control electrode of the second transistor;
A ninth switch connected between a reference voltage node to which a reference voltage is supplied and a control electrode of the first transistor;
The semiconductor device according to claim 1, further comprising a tenth switch connected between the reference voltage node and a control electrode of the second transistor. In the first state, the first switch and the second switch are in an off state, the third switch and the fourth switch are in an on state, the seventh switch and the eighth switch The switch is in an off state, and the ninth switch and the tenth switch are in an on state;
In a second state after the first state, the first switch and the second switch are in an on state, the third switch and the fourth switch are in an off state, and the first switch 7 switch and the eighth switch are on, and the ninth switch and the tenth switch are off.
8. In a third state after the second state, the first switch to the fourth switch are in an off state, and the seventh switch to the tenth switch are in an off state. The semiconductor device described. The semiconductor device further includes:
A fifth switch connected in parallel with the first capacitor and for discharging the first capacitor;
A sixth switch connected in parallel with the second capacitor for discharging the second capacitor;
A seventh switch connected between the first input node and a control electrode of the first transistor;
An eighth switch connected between the second input node and a control electrode of the second transistor;
A ninth switch connected between a reference voltage node to which a reference voltage is supplied and a control electrode of the first transistor;
The semiconductor device according to claim 1, further comprising a tenth switch connected between the reference voltage node and a control electrode of the second transistor. In the first state, the first switch to the fourth switch are in an off state, and the fifth switch and the sixth switch are in an on state;
In a second state after the first state, the first switch and the second switch are in an off state, the third switch and the fourth switch are in an on state, and The fifth switch and the sixth switch are in an off state, the seventh switch and the eighth switch are in an off state, and the ninth switch and the tenth switch are in an on state. ,
In a third state after the second state, the first switch and the second switch are on, the third switch and the fourth switch are off, and The fifth switch and the sixth switch are in an off state, the seventh switch and the eighth switch are in an on state, and the ninth switch and the tenth switch are in an off state. ,
The semiconductor device according to claim 9, wherein in the fourth state after the third state, the first switch to the tenth switch are in an off state. The semiconductor device further includes:
A constant current source;
A third transistor having a first conduction electrode coupled to the constant current source, a second conduction electrode, and a control electrode coupled to the first output node;
A fourth transistor having a first conduction electrode coupled to the constant current source, a second conduction electrode, and a control electrode coupled to the second output node;
An eleventh switch connected between a second conduction electrode of the third transistor and a third output node;
A twelfth switch connected between a second conduction electrode of the fourth transistor and a fourth output node;
A thirteenth switch connected between a second conduction electrode of the third transistor and a fourth output node;
A fourteenth switch connected between a second conduction electrode of the fourth transistor and a third output node;
The fourth transistor coupled to the third output node is charged according to a current flowing through the third transistor when the eleventh switch is turned on, and the fourth transistor is turned on when the fourteenth switch is turned on. A third capacitor that is charged with a charge according to the current flowing through;
The third transistor coupled to the fourth output node is charged according to a current flowing through the fourth transistor when the twelfth switch is turned on, and the third transistor is turned on when the thirteenth switch is turned on. The semiconductor device according to claim 1, further comprising a fourth capacitor charged with electric charge according to a current flowing through the capacitor. The semiconductor device further includes:
The latch circuit which outputs the signal showing the comparison result of the said 1st input voltage and the said 2nd input voltage based on the voltage of the said 1st output node, and the voltage of the said 2nd output node. Semiconductor device. The semiconductor device further includes:
A successive approximation register circuit that outputs 1-bit or multiple-bit data;
A DAC circuit that generates a comparison target voltage based on an analog input voltage and output data of the successive approximation register circuit;
The comparison target voltage is supplied to the first input node, a reference voltage is supplied to the second input node,
13. The semiconductor device according to claim 12, wherein the successive approximation register circuit generates the data based on a signal received from the latch circuit and outputs the data as a digital conversion result of the analog input voltage.

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