JP2008311589A - Semiconductor integrated circuit, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device in which resistance to ESD can be secured without applying special customization to chips to be stored even when storing a plurality of chips in the same package. <P>SOLUTION: A protective circuit chip 13 where an ESD protective circuit 134 for attenuating the overvoltage applied to provided pad groups 131 and 132 is formed, an ASIC chip 14 where an internal circuit to be operated by receiving power supply to provided power supply system pads 141a and 141b is formed, and a general purpose chip 15 where an internal circuit to be operated by receiving the power supply to provided power supply system pads 151a and 151b is formed are stored in one package. Then, power is supplied to the power supply system pads of the ASIC chip 14 and the general purpose chip 15 through the pad groups 131 and 132 of the protective circuit chip 13, and the ESD protection of the power supply system pads is secured in the ESD protective circuit 134. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit in which a plurality of semiconductor integrated circuit chips are stored in one package and a method for manufacturing the same.

In an SIP (System in Package) that stores ASIC chips designed for each product type and general-purpose chips such as memories and analog circuits in one package, each power supply pad and I / O pad of the ASIC chip has an ESD function. It is necessary to provide a protection circuit. Of these, the I / O pads can be designed based on the specifications of the ASIC chip itself, including the ESD protection circuit, but the power supply pads also take into consideration general-purpose chips combined with the ASIC chip. Need to design. For example, in FIG. 11 and FIG. 14 of Patent Document 1 in which a SIP is configured by a first chip 1110 (equivalent to a general-purpose chip) and a second chip 1120 (equivalent to an ASIC chip), ESD protection arranged in the second chip 1120 The circuit ensures the ESD resistance of the power supply system of the first chip 1110 as well as the second chip 1120.
Japanese Patent Laid-Open No. 2004-282058

  However, in order to use this method, it is necessary that the pad arrangement of a plurality of chips to be combined as SIP is determined in advance, and in a chip incorporating an ESD protection circuit, the chip is customized according to the power supply system. There is a need.

  For example, when a general-purpose chip with a low cost is selected in accordance with market trends and a SIP is configured by combining this with an ASIC chip, it is necessary to change the design of the ASIC chip according to the pad position of the general-purpose chip. The design period becomes longer. For example, when this ESD protection circuit is incorporated in a high-function ASIC chip using a wiring of 6 layers or more and using a more expensive manufacturing process, an arrangement area and a wiring area for the ESD protection circuit are specially required. Therefore, there is a possibility that a demerit occurs in cost.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit and a method for manufacturing the same, in which when a plurality of chips are stored in the same package, the ESD resistance of the power supply system can be secured without special customization of the stored chips. It is to be.

In order to achieve the above object, a semiconductor integrated circuit according to a first aspect of the present invention includes a first semiconductor integrated circuit chip on which an ESD protection circuit for attenuating an overvoltage applied to a pad provided, and a power supply system pad provided In the semiconductor integrated circuit having the required functions, the second and third semiconductor integrated circuit chips in which the internal circuits that operate upon receiving power supply are formed are stored in the same package. The power supply to the power supply system pads of the three semiconductor integrated circuit chips is performed through the pads of the first semiconductor integrated circuit chip, and the internal circuits of the second and third semiconductor integrated circuit chips All the required functions are realized.
According to a second aspect of the present invention, there is provided the semiconductor integrated circuit according to the first aspect, wherein the power supply system pads of the second and third semiconductor integrated circuit chips are supplied with power having a relatively high potential. Supply of power to the first power supply pads of the second and third semiconductor integrated circuit chips, including a first power supply pad and a second power supply pad to which power of a relatively low potential is supplied, Alternatively, power is supplied to the second power supply pad via different pads of the first semiconductor integrated circuit chip, and the ESD protection circuit attenuates overvoltage generated between the different pads. It is characterized by that.
According to a third aspect of the present invention, there is provided a method for manufacturing a semiconductor integrated circuit, comprising: a first semiconductor integrated circuit chip on which an ESD protection circuit that attenuates an overvoltage applied to a provided pad; The second semiconductor integrated circuit chip in which the internal circuit that operates upon receipt is formed and the third semiconductor integrated circuit chip in which the internal circuit that operates upon receipt of power supply from the power supply system pad provided are identical to each other. Manufacturing of a semiconductor integrated circuit that is housed in a package and connected so that power is supplied to the power supply pads of the second and third semiconductor integrated circuit chips via the pads of the first semiconductor integrated circuit In the method, the first semiconductor integrated circuit chip is prepared on a semiconductor substrate on which an element for forming the ESD protection circuit is prepared. Characterized by prepared by performing wiring process in accordance with the specifications of the conductor integrated circuit chip and the third semiconductor integrated circuit chip.
According to a fourth aspect of the present invention, in the semiconductor integrated circuit manufacturing method according to the third aspect, the semiconductor integrated circuit has at least one specification of the first semiconductor integrated circuit chip and the second semiconductor integrated circuit chip. The first semiconductor integrated circuit chip, which includes a plurality of different types of semiconductor integrated circuits and is stored in each of the plurality of types of semiconductor integrated circuits, is wired using the same type of semiconductor substrate prepared in advance. It is characterized by being manufactured as a semiconductor integrated circuit chip having different specifications by customizing the process.

  According to the present invention, since the power is supplied to the second and third semiconductor integrated circuit chips via the first semiconductor integrated circuit chip incorporating the ESD protection circuit, the second and third semiconductor integrated circuits are provided. It is not necessary to incorporate an ESD protection circuit for the power supply system in the chip. For this reason, the ESD tolerance of the power supply system can be ensured without prolonging the design period and increasing the cost.

<First embodiment>
FIG. 1 is a plan view showing a configuration of a semiconductor integrated circuit 10 according to a first embodiment of the present invention. 11 is an assembly substrate, 12 is a package lead group as external connection terminals arranged on the substrate 11, 13 is a protection circuit chip (first semiconductor integrated circuit chip), and 14 is an ASIC chip (third semiconductor integrated circuit chip). , 15 is a general-purpose chip (second semiconductor integrated circuit chip) such as a memory. All of the logic functions of the semiconductor integrated circuit 10 are performed by internal circuits of the ASIC chip 14 and the general-purpose chip 15. The protection circuit chip 13 performs a power feeding and signal transmission function, but does not contribute to a logic function.

  The protection circuit chip 13 includes a pad group 131 for connecting to each lead of the package lead group 12 by a wire 16 and a pad group 132 for connecting to the ASIC chip 14 by a wire 17 or to a general-purpose chip 15 by a wire 18. And is disposed on the substrate 11. Each pad of the pad group 131 and each pad of the pad group 132 are connected to each other by a wiring 133, and an ESD protection circuit 134 is disposed between each side of the wiring 133. ing. The ESD protection circuit 134 includes a GGNMOS transistor, a clamp-type NMOS transistor, a bidirectional diode, and the like. The ASIC chip 14 includes a power supply system (power supply VDD and ground GND) and a signal pad group 141 and is disposed on the substrate 11. The general-purpose chip 15 also includes a power supply system and a signal pad group 151 and is disposed on the ASIC chip 14.

  Here, the power supply voltage 141a of VDD1 in the pad group 141 of the ASIC chip 14 and the power supply pad 151a of VDD2 in the pad group 151 of the general-purpose chip 15 have different power supply voltages, or Even if the voltages are the same, it is assumed that VDD power supply potentials need to be supplied from different package leads in order to prevent droughts between them. For this reason, these power supply pads 141a and 151a are connected to different pads 132a and 132b of the protection circuit chip 13 by wires 17a and 18a, respectively. The pads 131 in which these pads 132 a and 132 b are connected by the wiring 133 are connected to different leads in the package lead group 12 by the wires 16. Further, the ESD protection circuit 134a of the protection circuit chip 13 is connected between the pads 132a and 132b by the wiring 135a. Thereby, the overvoltage applied between the power supply pad 141a of the ASIC chip 14 and the power supply pad 151a of the general-purpose chip 15 is attenuated by the ESD protection circuit 134a.

  Further, in order to prevent mutual interference between the ground pad 141b of GND1 in the pad group 141 of the ASIC chip 14 and the ground pad 151b of GND2 in the pad group 151 of the general-purpose chip 15, different packages are used. Assume that a ground potential needs to be supplied from the lead. For this reason, the ground pads 141b and 151b are connected to different pads 132c and 132d of the protection circuit chip 13 by wires 17b and 18b, respectively.

  The pads 131 in which these pads 132 c and 132 d are connected by the wiring 133 are connected to different leads in the package lead group 12 by the wires 16. Further, the ESD protection circuit 134b of the protection circuit chip 13 is connected between the pads 132c and 132d by the wiring 135b. Thereby, the overvoltage applied between the ground pad 141b of the ASIC chip 14 and the ground pad 151a of the general-purpose chip 15 is attenuated by the ESD transfer circuit 134b.

  Here, at least between the power supply pad 151a and the ground pad 151b of the general-purpose chip 15, there is provided an ESD transfer circuit that attenuates an overvoltage applied between the power supply pad 151a and the ground pad 151b. An ESD childcare circuit that attenuates an overvoltage applied between the power supply pad 141a and the ground pad 141b may also be provided between the power supply pad 141a and the ground pad 141b of the ASIC chip 14. However, as shown in FIG. 1, since the power supply pad 141a of the ASIC chip 14 and the power supply pad 151a of the general-purpose chip 15 are connected to different package leads, an overvoltage is applied between these different package leads. In such a case, the overvoltage cannot be attenuated by the ESD protection circuit provided in the general-purpose chip 15 or the ASIC chip 14. Further, since the ground pad 141b of the ASIC chip 14 and the ground pad 151b of the general-purpose chip 15 are connected to different package leads, when an overvoltage is applied between these different package leads, the general-purpose chip 15 or the ASIC chip. The overvoltage can not be attenuated by the ESD conserving circuit provided in FIG. This is because a path for discharging the overvoltage cannot be formed between the different package leads to which the overvoltage is applied through any of the ESD protection circuits of the ASIC chip 14 and the general-purpose chip 15.

  In contrast, in the semiconductor integrated circuit 10 of the present invention shown in FIG. 1, the ESD protection circuit 134a of the protection circuit chip 13 is connected between the power supply pad 141a of the ASIC chip 14 and the power supply pad 151a of the general-purpose chip 15. ing. Therefore, even if an overvoltage is applied between package leads for supplying a power supply potential to the power supply pads of these different chips, it can be attenuated by the ESD protection circuit 134a. Further, the ESD protection circuit 134 b of the protection circuit chip 13 is connected between the ground pad 141 b of the ASIC chip 14 and the ground pad 151 b of the general-purpose chip 15. Therefore, even if an overvoltage is applied between package leads for supplying a ground potential to the ground pads of these different chips, the ESD protection circuit 134b can attenuate the overvoltage. Further, for example, when an overvoltage is applied between a package lead for supplying a power supply potential to the power supply pad of the ASIC chip 14 and a package lead for supplying a ground potential to the ground pad of the general-purpose chip 15. The overvoltage is attenuated by the ESD transfer circuit 134a connected between the pad 132a and the pad 132b and the ESD protection circuit (not shown) connected between the power supply pad 151a and the ground pad 151b of the general-purpose chip 15. The

  The semiconductor integrated circuit 10 of the first embodiment is manufactured as follows, for example. First, the protection circuit chip 13 is prepared. However, at this stage, a process up to forming elements such as a MOS transistor and a diode necessary for forming an ESD protection circuit on the surface of the semiconductor substrate is performed, and a wiring process is not performed. That is, it is manufactured as a master slice that can be customized by wiring.

  Further, a general-purpose chip 15 formed with a pad group 151 including power supply pads (151a, 151b, etc.) and an internal circuit (not shown) that operates when the power supply pads receive power supply. prepare. Specifically, for example, when the general-purpose chip is a memory chip, a chip that can be easily procured in the market is selected and purchased within a range that satisfies the required storage capacity, bit configuration, access time, and the like. Accordingly, chips having different specifications such as chip dimensions and pad arrangements may be prepared depending on the ease of procurement from time to time.

  In addition, the ASIC chip 14 in which a pad group 141 including power supply pads (141a, 141b, etc.) and an internal circuit (not shown) that operates when the power supply pads receive power supply is formed. prepare. The ASIC chip 14 is designed to have a necessary function by operating using a general-purpose chip, and is manufactured, for example, using an advanced process having six or more wiring layers.

  Then, when the specifications of the general-purpose chip and the ASIC chip become clear, a protection circuit chip wiring process prepared in advance is performed. At this time, a pad for connecting to the lead of the package and a pad for connecting to the pad of the general-purpose chip or the ASIC chip are determined in accordance with the chip size and the pad arrangement of the general-purpose chip and the ASIC chip. Then, the wiring is customized so that an ESD protection circuit necessary for obtaining a necessary protection characteristic is connected to these pads. That is, elements for forming an ESD protection circuit, which have been formed on the surface of the semiconductor substrate in advance, are connected to each other, wiring for forming an ESD protection circuit having necessary protection performance, a pad, and ESD protection A mask of one layer or a plurality of layers necessary for forming a wiring for connecting a circuit to a pad is prepared, and a wiring process is performed using the mask. Thereby, the protection circuit chip 13 in which the pad, the ESD protection circuit, and the wiring for connecting the ESD protection circuit to the pad are formed is manufactured.

  Here, the protection circuit chip 13 has a large minimum dimension and a small number of wiring layers (usually 2 to 3 layers) as long as it can form an element constituting the ESD protection circuit and a wiring connecting between the elements. It is sufficient) and can be manufactured by an inexpensive manufacturing process.

  Then, the protection circuit chip 13 and the ASIC chip 14 are mounted on the substrate 11 having the package lead group 12, and the general-purpose chip 15 is mounted on the ASIC chip 14, and the power supply system pad of the ASIC chip 14 is mounted. The power supply to 141a and 141b and the power supply to the power supply pads 151a and 151b of the general-purpose chip 15 are performed via the pad groups 131 and 132 of the protection circuit chip 13, respectively, and further signal transmission is performed as necessary. As shown, wires (in addition to 17a, 17b, 18a, and 18b shown in the figure) connect the signal pads of the ASIC chip 14 to the corresponding package leads, and the signal pads of the general-purpose chip 15 to the corresponding signal pads of the ASIC chip 14. Connecting wires, etc.), then connect the whole into one package Stores.

  As described above, in this embodiment, the protection circuit chip 13 having the ESD protection circuit 134 is provided, and the pad group 141 of the ASIC chip 14 and the general-purpose chip 15 are connected via the pad groups 131 and 132 of the protection circuit chip 13. At least a power supply system pad of the pad group 151 is connected to the package lead 12. For this reason, it is not necessary to mount an ESD protection circuit on the power supply system pad of the ASIC chip 14, and design restrictions on the ASIC chip 14 are reduced. That is, there is no need to design an ESD protection circuit for the power supply system pad, or even when an ESD protection circuit for the power supply system pad is provided, the design is performed in consideration of only the specifications of the ASIC chip 14. be able to.

  When the ESD protection circuit for the power supply system pad is not provided on the ASIC chip 14, the arrangement area for providing the protection circuit and the wiring area for connecting the protection circuit to the pad become unnecessary, and the chip size and cost Can be reduced. The protection circuit chip 13 needs an area for providing an ESD protection circuit and wiring. However, as described above, the protection circuit chip 13 can be manufactured by an inexpensive process as compared with the ASIC chip 14, and thus the cost of the semiconductor integrated circuit 10 as a whole can be reduced. Further, the customization process of the protection circuit chip 13 can only be performed after the specifications of both the ASIC chip 14 and the general-purpose chip 15 (arrangement of power supply pads, etc.) are determined. However, since the customization process has a small number of processes and can be performed in a short period, the customization process of the protection circuit chip 13 does not extend the delivery time of the entire semiconductor integrated circuit 10.

  Note that VDD power supply potentials are supplied from different package leads to the electric wire pad 141a of the ASIC chip 14 and the power supply pad 151a of the general-purpose chip 15, and the ground pad 141b of the ASIC chip 14 and the ground pad 151b of the general-purpose chip 15 are supplied to When supplying a ground potential from different package leads, an ESD protection circuit for attenuating an overvoltage applied between the different package leads is provided on the protection circuit chip 13 as in the semiconductor integrated circuit 10 shown in FIG. It is necessary to provide it. On the other hand, for example, when the VDD power supply potential is supplied from the same package lead to the power supply pad 141a of the ASIC chip 14 and the power supply pad 151a of the general-purpose chip 15, the power supply potential of the ASIC chip 14 to which the power supply potential is supplied from the same package lead. No overvoltage is applied between the power supply pad 141a and the power supply pad 151a of the general-purpose chip 15. Therefore, it is not necessary to connect an ESD protection circuit provided on the protection circuit chip 13 between these power supply pads. In this case, for example, the overvoltage applied between the package lead for supplying the power supply potential and the package lead for supplying the ground potential is provided at least in the general-purpose chip 15 (or, further, in the ASIC chip). It can be attenuated by an ESD transfer circuit (provided) connected between the wire pad and the ground pad.

  Note that the power supply pads supplied from the same package lead of the ASIC chip 14 and the general-purpose chip 15 can be directly connected to the package lead without being relayed by the pads of the protection circuit chip 13. However, even when supplying from the same package lead, the ESD protection circuit provided on the protection circuit chip is relayed by the pad of the protection circuit chip 13 and connected to the power supply pad of the ASIC chip 14 or the general-purpose chip 15. It is also possible to connect between the pad and a pad connected to the ground pad. As a result, it is possible to improve the ESD resistance between the power supply pad and the ground pad.

  For the signal pads other than the power supply system pads, the overvoltage is attenuated by the ESD protection circuit provided in each of the ASIC chip 14 and the general-purpose chip 15. Therefore, it is not necessary to connect by relaying the pads of the protection circuit chip 13 or to connect an ESD protection circuit provided on the protection circuit chip 13. What is necessary is just to connect directly to the package lead or between the signal pad of the ASIC chip 14 and the signal pad of the general-purpose chip 15. Of course, depending on the pad arrangement of each chip, if it is easier to connect with the pads of the protection circuit chip 13, it is possible to relay with the protection circuit chip 13. Also in this case, it is not necessary to connect the ESD protection circuit provided in the protection circuit chip to the pad of the protection circuit chip 13 that relays the connection to the signal pad.

  In the example shown in FIG. 1, the pad 132a of the protection circuit chip 13 connected to the power supply pad 141a of the ASIC chip 14 and the pad 132b of the protection circuit chip 13 connected to the power supply pad 151a of the general-purpose chip 15 are used. In the meantime, an ESD protection circuit 134a provided in the protection circuit chip 13 is connected, and the protection circuit chip 13 connected to the ground pad 141b of the ASIC chip 14 and the protection connected to the ground pad 151b of the general-purpose chip 15 are connected. An ESD protection circuit 134b provided on the protection circuit chip 13 is connected between the pads 132d of the circuit chip 13. However, between the pad 132a of the protection circuit chip 13 connected to the power supply pad 141a of the ASIC chip 14 and the pad 132d of the protection circuit chip 13 connected to the ground pad 151b of the general-purpose chip 15, and between the pad 132d of the ASIC chip 14 ESD protection provided on the protection circuit chip 13 between the pad 132c of the protection circuit chip 13 connected to the ground pad 141b and the pad 132b of the protection circuit chip 13 connected to the power supply pad 151a of the general-purpose chip 15, respectively. It is also possible to connect circuits.

  In any case, for example, the protection circuit chip 13, the ASIC chip 14, and the general-purpose chip 15 stored in the same package are not limited to one each, and may be two or more. It is.

<Second embodiment>
FIG. 2 is a plan view showing a configuration of a semiconductor integrated circuit 10A according to the second embodiment of the present invention. Here, an example in which another general-purpose chip 15A having a pad arrangement different from that of the general-purpose chip 15 shown in FIG. 1 is used will be described.

  In the general-purpose chip 15A, the power supply pad 151c of VDD2 is arranged on the right end, and the ground pad 151d of GND2 is arranged on the left side thereof. Therefore, as in the first embodiment, when the power supply pad 151c is connected to the pad 132b of the protection circuit chip 13 and the ground pad 151d of the GND 2 is connected to the pad 134a of the protection circuit chip 13, the wires are crossed. To do.

  Therefore, in this embodiment, the VDD2 power pad 151c of the general-purpose chip 15A is connected to the right end pad 132e of the protection circuit chip 13A by the wire 18c, and the GND2 ground pad 151d is connected to the pad 132f of the protection circuit chip 13A by the wire 18d. Connect each one. In the protection circuit chip 13A, the pad 132e is connected to the ESD protection circuit 134a by the wiring 136, and the pad 132f is connected to the ESD protection circuit 134b by the wiring 137. Others are the same as FIG.

  Therefore, also in this embodiment, the ESD protection circuit 134a performs ESD between the VDD1 power supply pad 141a in the pad group 141 of the ASIC chip 14 and the VDD2 power supply pad 151c in the pad group 151 of the general-purpose chip 15A. Protected. Further, the ESD protection circuit 134b protects the ESD between the ground pad 141b of GND1 in the pad group 141 of the ASIC chip 14 and the ground pad 151d of GND2 in the pad group 151 of the general-purpose chip 15A.

  Here, the protection circuit chip 13A is different from the protection circuit chip 13 in the first embodiment in that the pads used for connecting to the power supply system pads of the general-purpose chip 15A and the ESD protection circuits 134a and 134b are connected to these. It is a chip with different specifications, with different wiring connected to the pad. However, it can be manufactured by using the same master slice as that for manufacturing the protection circuit chip 13 in the first embodiment and customizing only the wiring. In the second embodiment, the ASIC chip 14 having the same specifications (same chip dimensions and pad arrangement) as the first embodiment and the general-purpose chip 15A having different specifications (different pad arrangements) are the same. The case where the integrated circuit 10A is configured by being stored in a package has been described. The same applies to the case where general-purpose chips having the same specifications as ASIC chips having different specifications are stored in the same package. That is, the protection circuit chip can be manufactured by customizing the same master slice.

  Thus, when a plurality of chips are stored in the same package to constitute a semiconductor integrated circuit, by supplying power and ESD protection via a protection circuit chip (different from the plurality of chips), Even when the specifications of at least one of the plurality of chips are different, the protection circuit chip can be manufactured inexpensively and in a short period of time by using the same type of master slice prepared in advance. As a result, it is possible to reduce the cost and shorten the delivery time of the entire semiconductor integrated circuit.

  In the first and second embodiments, the general-purpose chip 15 or 15A is stacked on the ASIC chip 14 and stored in the same package. However, depending on the dimensions of these chips, the ASIC chip is stacked on the general-purpose chip. Is also possible. Moreover, it is possible to mount each chip on the package substrate without stacking the chips. At least in this case, it is also possible to use a wiring formed on the package substrate instead of using a wire for connection between chips or between a chip and a package lead.

1 is a plan view of a semiconductor integrated circuit according to a first embodiment of the present invention. It is a top view of the semiconductor integrated circuit of the 2nd Example of this invention.

Explanation of symbols

10, 10A: Semiconductor integrated circuit 11: Substrate 12: Package lead group 13, 13A: Protection circuit chip, 131, 132: Pad group, 133: Wiring, 134, 134a, 134b: ESD protection circuit, 135a, 135b, 136, 137: Wiring 14: ASIC chip, 141: Pad group, 141a, 141b: Pad 15, 15A: General-purpose chip, 151: Pad group, 151a-151d: Pad 16: Wire 17, 17a, 17b: Wire 18, 18a, 18d : Wire

Claims (4)

A first semiconductor integrated circuit chip formed with an ESD protection circuit for attenuating an overvoltage applied to the pad provided; and second and third elements formed with internal circuits that operate upon receiving power from the power supply system pad provided. In the semiconductor integrated circuit having the required function, the semiconductor integrated circuit chip is stored in the same package.
Power is supplied to the power supply system pads of the second and third semiconductor integrated circuit chips through the pads of the first semiconductor integrated circuit chip, and the second and third semiconductor integrated circuit chips are supplied. All of the required functions are realized by the internal circuit. Each of the power supply system pads of the second and third semiconductor integrated circuit chips has a first power supply pad to which a relatively high potential power is supplied and a first power supply pad to which a relatively low potential power is supplied. 2 power pads,
Pads for supplying power to the first power supply pads of the second and third semiconductor integrated circuit chips or for supplying power to the second power supply pads are different from each other in the first semiconductor integrated circuit chip. Made through
The semiconductor integrated circuit according to claim 1, wherein the ESD protection circuit attenuates an overvoltage generated between the different pads. A first semiconductor integrated circuit chip formed with an ESD protection circuit for attenuating an overvoltage applied to the pad provided; and a second semiconductor integrated circuit formed with an internal circuit that operates upon receiving power from the power supply pad provided. A circuit chip and a third semiconductor integrated circuit chip in which an internal circuit that operates by receiving power supply is supplied to a power supply system pad provided in the same package, and the second and third semiconductor integrated circuits In the method of manufacturing a semiconductor integrated circuit, the connection is performed so that the power supply to the power supply system pad of the chip is performed through the pad of the first semiconductor integrated circuit.
The second semiconductor integrated circuit chip and the third semiconductor integrated circuit chip are prepared on a semiconductor substrate prepared in advance, on which an element for forming the ESD protection circuit is formed. A method of manufacturing a semiconductor integrated circuit, wherein the manufacturing process is performed by performing a wiring process according to the specifications. The semiconductor integrated circuit includes a plurality of types of semiconductor integrated circuits having different specifications of at least one of the first semiconductor integrated circuit chip and the second semiconductor integrated circuit chip,
By customizing the wiring process of the first semiconductor integrated circuit chip stored in each of the plurality of types of semiconductor integrated circuits using the same type of semiconductor substrate prepared in advance, semiconductors having different specifications 4. The method of manufacturing a semiconductor integrated circuit according to claim 3, wherein the semiconductor integrated circuit is manufactured as an integrated circuit chip.

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