JP2008310491A - Constant voltage power circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a constant voltage power circuit improving a transitional response lag of an output transistor without increasing current consumption and having small fluctuated output voltage. <P>SOLUTION: When output current Io is rapidly changed and a response lag occurs in a power transistor 7 and a difference between the output voltage Vp1 at a first driver stage 102 and the output voltage Vp2 at a second driver stage 103 satisfies an expression (Vp1-Vp2)>¾Vtp¾ if a threshold value of a P-channel MOS type field-effect transistor 15 for a control circuit is assumed to be Vtp, the P-channel MOS type field-effect transistor 15 for a control circuit turns on, a route where a gate of the power transistor 7 is connected with the ground is formed via the P-channel MOS type field-effect transistor 15 for a control circuit, and a parasitic capacity of the power transistor 7 is rapidly discharged, and consequently, the transitional response lag is dissolved. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a constant voltage power supply circuit, and more particularly to a circuit for improving a delay of a transient response characteristic caused by a parasitic capacitance of a power transistor used in an output stage.

Conventionally, as this type of constant voltage power supply circuit, for example, the one shown in FIG. 5 is generally well known.
Hereinafter, the conventional constant voltage power supply circuit will be described with reference to FIG. 5. The constant voltage power supply circuit includes an error amplifier 101A for detecting a difference between the output voltage and the reference voltage Vref, and the error amplifier 101A. The driver stage 102A for amplifying the output and the final stage part 104A driven by the driver stage 102A are roughly divided.
The final stage section 104A includes a power transistor M9 formed of a MOS field effect transistor (MOS FET) and two feedback resistors R1 and R2 provided in series between the drain of the power transistor M9 and the ground. It is configured as follows.

The voltage obtained by dividing the output voltage V0 by the feedback resistors R1 and R2 is fed back to the input stage of the error amplifier 101A, and the output voltage V0 is feedback-controlled so that there is no difference from the reference voltage Vref. It is configured to be stabilized.
In the constant voltage power supply circuit having such a configuration, the maximum output current is determined by the transistor size of the power transistor M9, and the current flowing through the error amplifier 101A and the driver stage 102A becomes a consumption current. Lowering current consumption tends to be an increasingly serious technical issue in the future.
An example of this type of constant voltage power supply circuit is disclosed in Patent Document 1 and the like.

JP-A-5-324104 (page 2-3, FIG. 1)

However, when the transistor size of the power transistor is increased as the output current increases, the parasitic capacitance increases, resulting in a problem that the transient response is delayed.
This transient response delay can be explained as follows.
First, in the conventional circuit, the output voltage V0 of the power transistor M9 is controlled by the output voltage Vp1 of the driver stage 102A.
That is, when the load fluctuates rapidly, the gate-source voltage Vgs9 (= VIN−Vp1), which is the drive voltage of the power transistor M9, also stabilizes the output voltage V0 via the output voltage Vp1 of the driver stage 102A. It is necessary to fluctuate.
Such fluctuation of Vgs9 is accompanied by charging / discharging of the parasitic capacitance Cg (see FIG. 5) of the power transistor M9.

For example, when the load is light and the drive voltage Vgs9 of the power transistor M9 is reduced, that is, when the output voltage Vp1 of the driver stage 102A is increased, the input element M1 (P-channel MOS FET) of the driver stage 102A is transiently changed. The parasitic capacitance of the power transistor M9 is charged.
On the other hand, when the load becomes heavy and the drive voltage Vgs9 of the power transistor M9 is increased, that is, when the output voltage Vp1 of the driver stage 102A is lowered, the current source load M2 (N-channel MOS FET) of the driver stage 102A is The charge of the parasitic capacitance of the power transistor M9 is discharged transiently.
At this time, the current source load M2 functions as a constant current source and performs a constant current discharge, so that a certain amount of time is required for the discharge.

  In the conventional circuit shown in FIG. 5, for example, it is assumed that a sudden load fluctuation occurs and the output current changes from Io1 to Io2 (Io1 <Io2). Since the constant voltage power supply circuit operates to supply a large amount of current to the load and keep the output voltage V0 constant, the gate-source voltage Vgs9 of the power transistor M9 follows the load variation from Vgs1 to Vgs2 ( | Vgs1 | <| Vgs2 |). Then, while the gate-source voltage Vgs9 is changed from Vgs1 to Vgs2, constant current discharge by the current load M2 is performed as described above.

On the other hand, since the input element M1 of the driver stage 102A connected to the output of the error amplifier 101A is a MOS FET having a normal size gate, it does not have the influence of parasitic capacitance and responds at high speed. In comparison, the output of the driver stage 102A is connected to the gate of the power transistor M9, which is equivalent to connecting a large output capacity.
As described above, since this capacity is discharged at a constant current by the current source load M2, the discharge takes time.

  Here, for the sake of simplicity, assuming a simple constant current discharge circuit assuming that the drain-source voltage VDS of the power transistor M9 does not change, the time td required for the above-described discharge can be estimated as follows.

  First, the drive voltage Vgs1 necessary for flowing the output current Io1 and the drive voltage Vgs2 necessary for flowing the output current Io2 are expressed by the following formulas 1 and 2.

Vgs1 = {(2 × Io1) / β} ^1/2 + Vth Equation 1

Vgs2 = {(2 × Io2) / β} ^1/2 + Vth Expression 2

  Here, Vth is a threshold value of the MOS transistor, and β is expressed by Equation 3 below.

  β = μ · Cox · (W / L) Equation 3

  In Equation 3, μ is the carrier mobility, Cox is the gate capacitance per unit area, W is the channel width, and L is the channel length.

  In general, when the capacitor C is charged and discharged with the constant current I, the time t required for the voltage V to be generated between the capacitor electrodes can be expressed by the following equation (4).

  t = V · C / I Equation 4

  Considering charging / discharging of the parasitic capacitance of the power transistor M9 in the same manner, the time td required for constant current discharge while the drive voltage Vgs9 of the power transistor M9 is changed from Vgs1 to Vgs2 is expressed by the following equation (5). Is done.

  td = {(| Vgs2 | − | Vgs1 |) · Cg} / Id Formula 5

Here, Cg is the gate terminal capacitance of the power transistor M9, and Id is a constant current value output from the current source load M2.
Accordingly, the time required for constant current discharge while the output current is changed from Io1 to Io2 is expressed by the following equation (6).

td = {(2 / β) ^1/2 (Io2 ^1/2 −Io1 ^1/2 ) · Cg} / Id Equation 6

For example, if β = 1 (A / V ² ), Cg = 100 (pF), Io1 = 10 (mA), Io2 = 500 (mA), Id = 5 (μA), from Equation 6, td = 17 .2 (μs).
During this time td, the output voltage V0 falls without being able to pursue the load fluctuation. Therefore, the output voltage V0 greatly decreases as the discharge takes a longer time.

In such a constant voltage power supply circuit, when the aspect ratio W / L of the power transistor M9 of the output stage 104A is increased in order to obtain output current capability, β increases in proportion to the aspect ratio according to Equation 3. In the case of a general MOS transistor, the gate terminal capacitance Cg is also considered to increase in proportion to the aspect ratio, and as a result, the discharge time td is proportional to the square root of the aspect ratio. Therefore, a trade-off occurs between the size of the power transistor and the discharge time.
That is, if the constant current value Id is increased, the discharge time is shortened and the degree of decrease in the output voltage V0 is improved. However, since the bias state of the driver stage 102A changes, the main loop, that is, the feedback loop needs to be readjusted. In addition, the current consumption increases as the constant current value Id increases. There is a problem of hindering power consumption.

  The present invention has been made in view of the above circumstances, and provides a constant voltage power supply circuit that can improve the transient response delay of the output transistor without increasing the current consumption, and has a small output voltage fluctuation. It is.

In order to achieve the above object of the present invention, a constant voltage power supply circuit according to the present invention comprises:
An error amplifier configured to output a difference between a reference voltage and a feedback voltage corresponding to the output voltage;
A first driver stage for amplifying and outputting the output voltage of the error amplifier;
An output stage comprising a power transistor driven by the first driver stage and a voltage dividing resistor connected in series to the power transistor;
Comprising
The output voltage divided by the voltage dividing resistor is fed back to the error amplifier as the feedback voltage, and is a constant voltage power supply circuit configured to be able to make the output voltage constant,
A second driver stage is provided together with the first driver stage;
The first driver stage includes a first driver stage field effect transistor that is grounded to amplify the output of the error amplifier, and a current source load of the first driver stage field effect transistor, While the output voltage is configured to be applied to the gate of the power transistor,
The second driver stage includes a second driver stage field effect transistor that is grounded to amplify the output of the error amplifier, and a current source load of the second driver stage field effect transistor. Become
Provided with a control circuit configured to be able to form a discharge path of the parasitic capacitance of the power transistor based on the difference between the output voltage of the first driver stage and the output voltage of the second driver stage It is.
In such a configuration, the control circuit uses a P-channel MOS field effect transistor, the output voltage of the second driver stage is the gate, the output voltage of the first driver stage is the source, On the other hand, it is preferable that the drain is connected to the ground and the input voltage is applied to the substrate.

  According to the present invention, the response delay of the power transistor constituting the output stage can be detected during a transient response with a simple configuration, and the detection result can form a path that promotes the discharge of the parasitic capacitance of the power transistor. This is advantageous in that a delay in response during the transient response of the transistor can be eliminated and a constant voltage power supply circuit with small fluctuations in output voltage can be provided.

Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 4.
The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.
First, a basic configuration example of a constant voltage power supply circuit according to an embodiment of the present invention will be described with reference to FIG.
The constant voltage power supply circuit according to the embodiment of the present invention includes an error amplifier 101, first and second driver stages (indicated as “D1” and “D2” in FIG. 1) 102 and 103, and a control circuit, respectively. (Indicated as “A” in FIG. 1) 105 and the output stage 104 are roughly divided.
Such a constant voltage power supply circuit has basically the same configuration as this type of conventional constant voltage power supply circuit except for the second driver stage 103 and the control circuit 105.

The error amplifier 101 includes first and second error amplifier first and second MOS field effect transistors (represented as “M5” and “M6” in FIG. 1, respectively) 1 and 2 provided to perform a differential amplification operation. A differential amplifier is formed at the center. Hereinafter, the MOS field effect transistor is referred to as a “MOS transistor”.
In the embodiment of the present invention, N-channel MOS transistors are used as the error amplifier first and second MOS transistors 1 and 2.

In the error amplifier 101, the reference voltage Vref is applied to the gate of the first MOS transistor 1 for error amplifier, while the stabilized output voltage V0 is applied to the gate of the second MOS transistor 2 for error amplifier. A divided voltage is applied as a feedback voltage.
A difference between the reference voltage Vref and the feedback voltage is obtained at the drain of the second MOS transistor 2 for error amplifier.
In the error amplifier 101, the current mirror circuit is configured by the error amplifier first and second P-channel MOS transistors 23 and 24. The error amplifier first and second MOSs for error amplifier which are differentially connected are used. The third NMOS transistor 25 for error amplifier functions as a current source for the first and second MOS transistors 1 and 2 for error amplifier. It has become a thing.

The first driver stage 102 includes a first driver stage P-channel MOS transistor (indicated as “M1” in FIG. 1) 3 and a first driver stage N-channel MOS transistor (in FIG. 1, “M2”). And 4). In the following description, for convenience, the P-channel MOS transistor is referred to as a “PMOS transistor” and the N-channel MOS transistor is referred to as an “NMOS transistor”.
In the first driver stage 102, the first driver stage PMOS transistor 3 and the first driver stage NMOS transistor 4 are connected in series between the input voltage terminal 21 and the ground. One driver stage NMOS transistor 4 functions as a current source load of the first driver stage PMOS transistor 3.

In other words, the first driver stage PMOS transistor 3 has a source connected to the input voltage terminal 21 and a drain connected to the drain of the first driver stage NMOS transistor 4. The source of the NMOS transistor 4 is connected to the ground.
The gate of the first driver stage PMOS transistor 3 is connected to the drain of the error amplifier second MOS transistor 2 which is the single-ended output terminal of the error amplifier 101. The gate of the first driver stage NMOS transistor 4 is connected to the constant current source 11.
With this connection, the first driver stage PMOS transistor 3 and the first driver stage NMOS transistor 4 function as a driver of the common source circuit.

  The constant current source 11 has one end connected to the input voltage terminal 21 and the other end connected to the drain and gate of a constant current source NMOS transistor (denoted as “M8” in FIG. 1) 12. Yes. The gate of the first driver stage NMOS transistor 4 is connected to the connection point between the constant current source 11 and the drain and gate of the constant current source NMOS transistor 12.

  The second driver stage 103 includes a second driver stage PMOS transistor (denoted as “M10” in FIG. 1) 5 and a second driver stage NMOS transistor (denoted as “M11” in FIG. 1) 6. The configuration is basically the same as that of the first driver stage 102 described above.

In other words, the second driver stage PMOS transistor 5 has a source connected to the input voltage terminal 21, and a drain connected to the drain of the second driver stage NMOS transistor 6. The source of the NMOS transistor 6 is connected to the ground.
The gate of the second driver stage PMOS transistor 5 is connected to the drain of the error amplifier second MOS transistor 2 which is the single-ended output terminal of the error amplifier 101, while the second driver stage NMOS transistor is connected. 6 is connected to a connection point between the constant current source 11 and the constant current source NMOS transistor 12.

With this connection, the second driver stage PMOS transistor 5 and the second driver stage NMOS transistor 6 function as drivers of the source ground circuit, and the second driver stage NMOS transistor 6 The second driver stage PMOS transistor 5 functions as a current source load.
In the second driver stage 103, the bias is adjusted so that the output voltage Vp2 is equal to the input voltage VIN applied from the outside to the input voltage terminal 21 in the steady state.

The output stage 104 includes a power transistor 7 (denoted as “M9” in FIG. 1) 7 and a first and second feedback resistors 8 and 9 as main components.
The power transistor 7 has a source connected to the input voltage terminal 21 and a first feedback resistor 8 and a second feedback resistor 9 connected in series from the drain side between the drain and the ground. A stabilized output voltage V0 is obtained at a connection point between the power transistor 7 and the first feedback resistor 8.

The gate of the power transistor 7 is connected to the connection point between the drain of the first driver stage PMOS transistor 3 and the drain of the first driver stage NMOS transistor 4.
On the other hand, the connection point between the first and second feedback resistors 8 and 9 is connected to the gate of the second MOS transistor 2 for error amplifier constituting the error amplifier 101. With this configuration, the stabilized output voltage V0 is divided by the first and second feedback resistors 8 and 9, and the divided voltage as the voltage drop of the second feedback resistor 9 is divided into the stabilized output voltage V0. The voltage is fed back to the error amplifier 101 as a voltage corresponding to.
In FIG. 1, the part denoted by A represents a control circuit for improving the charge / discharge of the power transistor 7 in accordance with the difference between the output signals of the first and second driver stages 102 and 103. (Details will be described later).

Next, in this configuration, the operation and function of the first and second driver stages 102 and 103 will be described with reference to FIGS.
First, for convenience of explanation, the circuit shown in FIG. 2 is the same as FIG. 1 except that the block denoted by A in FIG. 1 is omitted.
FIG. 3 also shows a waveform diagram (FIG. 3A) schematically showing a change in output current in the operating state described below, and output voltages Vp1,1 of the first and second driver stages 102 and 103. Waveform diagrams (FIG. 3B) schematically showing changes in Vp2 are shown.

First, it is assumed that the load suddenly increases, that is, the case where the output current suddenly increases from Io1 to Io2 (Io1 <Io2) (see the location at time t1 in FIG. 3A). In this case, the output voltage Vp3 of the error amplifier 101 increases rapidly, and the output voltage Vp1 of the first driver stage 102 must decrease rapidly with the rapid change. If the electric charge of the capacitor is not discharged, the output voltage Vp1 of the first driver stage 102 cannot be decreased rapidly but gradually decreases (see FIG. 3B).
That is, the discharge of the parasitic capacitance takes time because it is performed at a constant current, and therefore, a transient response delay td (see FIG. 3B) occurs.

On the other hand, the circuit constant is set so that the output voltage Vp2 of the second driver stage 103 whose output is not connected to the power transistor 7 becomes the input voltage VIN in a steady state. Unlike the output voltage Vp1 of the first driver stage 102, the output voltage Vp2 drops rapidly as Vp3 rises rapidly (see FIG. 3B).
Therefore, in this state, the difference between the output voltage Vp1 of the first driver stage 102 and the output voltage Vp2 of the second driver stage 103 is (Vp1−Vp2). That is, the state in which the operation delay due to the parasitic capacitance of the power transistor 7 occurs can be expressed as (Vp1−Vp2)> 0.

Therefore, in addition to the first driver stage 102, by providing the second driver stage 103 using a source grounded circuit, the state where the operation delay due to the parasitic capacitance is generated occurs in the two driver stages 102, 103. It can be detected as a difference in output voltage.
Then, by providing a control circuit that promotes charging / discharging of the parasitic capacitance of the power transistor 7, it is possible to improve the delay of the transient response as described above. For example, the block 105 indicated by the symbol A in FIG. 1 assumes such a control circuit.

Next, a more specific circuit configuration example will be described with reference to FIG.
The same components as those in the configuration example shown in FIGS. 1 and 2 are denoted by the same reference numerals, detailed description thereof is omitted, and different points will be mainly described below.
This circuit configuration example particularly shows a specific circuit configuration of the control circuit 105 for promoting charging / discharging of the parasitic capacitance of the power transistor 7.
More specifically, the control circuit 105 in this configuration example is configured using a control circuit PMOS transistor (indicated as “M12” in FIG. 4) 15.

That is, the source of the control circuit PMOS transistor 15 is the output terminal of the first driver stage 102, that is, the connection between the drain of the first driver stage PMOS transistor 3 and the drain of the first driver stage NMOS transistor 4. Connected to a point, the output voltage Vp1 is applied.
The control circuit PMOS transistor 15 has a drain connected to the ground and a substrate connected to the input voltage terminal 21.
Further, the gate of the control circuit PMOS transistor 15 is the connection point between the output terminal of the second driver stage 103, that is, the drain of the second driver stage PMOS transistor 5 and the drain of the second driver stage NMOS transistor 6. And the output voltage Vp2 is applied.

Next, the operation of the control circuit 105 in such a configuration will be described.
First, since (Vp1−Vp2) <0 in the steady state, the control circuit PMOS transistor 15 is cut off, and functions and operates as a constant voltage power supply circuit that is basically the same as the conventional circuit. Is realized.

On the other hand, assuming that the load suddenly becomes a heavy load, as described above, the output of the first driver stage 102 in which the output change is delayed due to the parasitic capacitance of the power transistor 7. The potential difference between the voltage Vp1 and the output voltage Vp2 of the second driver stage 103 without delay in output change is (Vp1−Vp2)> 0.
Here, assuming that the threshold of the control circuit PMOS transistor 15 is Vtp, the control circuit PMOS transistor 15 operates when the stabilized output voltage V0 is stabilized under the condition of | Vtp |>(Vp1-Vp2)> 0. The control circuit PMOS transistor 15 is turned on when the transient response is delayed enough to satisfy (Vp1−Vp2)> | Vtp |.

As a result, as a discharge path of the parasitic capacitance of the power transistor 7, the output node of the first driver stage 102, that is, the drain of the first driver stage PMOS transistor 3 and the first driver stage NMOS transistor 4 A path from the connection point to the ground via the control circuit PMOS transistor 15 in the on state is formed, and the output voltage Vp1 of the first driver stage 102 is rapidly lowered.
This rapid decrease in the output voltage Vp1 of the first driver stage 102 prompts the rapid supply of the current necessary for the load, and the stabilized output voltage V0 is restored to and maintained at a desired voltage without greatly decreasing. It will be.

  The potential difference (Vp1−Vp2) between the output voltages of the first and second driver stages 102 and 103 becomes smaller in the process in which the stabilized output voltage V0 returns to the desired voltage, and finally (Vp1−Vp1−Vp2). When Vp2) <| Vtp |, the PMOS transistor 15 for control circuit returns to the cutoff state again. That is, when the stabilized output voltage V0 returns to a desired voltage, the output voltage of the second driver stage 103 without delay returns rapidly to VIN (see FIG. 3B), and (Vp1-Vp2) < In order to satisfy | Vtp |, the PMOS transistor 15 for control circuit is cut off at high speed.

  In this way, when the charging and discharging of the parasitic capacitance of the power transistor 7 is completed, the control circuit PMOS transistor 15 is immediately cut off, and the overshoot of the stabilized output voltage V0 does not significantly increase as compared with the conventional circuit. The normal constant voltage power supply operation is not affected at all.

It is a circuit diagram which shows the structural example of the constant voltage power supply circuit in embodiment of this invention. FIG. 2 is a circuit diagram illustrating a configuration example of a constant voltage power supply circuit in a state in which a block indicated by a symbol A in the configuration example illustrated in FIG. 1 is excluded. FIG. 3 is a waveform diagram illustrating a schematic waveform of a main part of the constant voltage power supply circuit according to the embodiment of the present invention. FIG. 3A is a waveform diagram schematically illustrating a change in output current, and FIG. It is a wave form diagram showing roughly change of output voltage of the 1st and 2nd driver stages. FIG. 2 is a circuit diagram illustrating a configuration example of a constant voltage power supply circuit according to an embodiment of the present invention including a specific circuit configuration example of a block indicated by a symbol A in the configuration example illustrated in FIG. 1. It is a circuit diagram which shows one structural example of a conventional circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 ... Error amplifier 102 ... 1st driver stage 103 ... 2nd driver stage 104 ... Output stage 105 ... Control circuit

Claims (2)

An error amplifier configured to output a difference between a reference voltage and a feedback voltage corresponding to the output voltage;
A first driver stage for amplifying and outputting the output voltage of the error amplifier;
An output stage comprising a power transistor driven by the first driver stage and a voltage dividing resistor connected in series to the power transistor;
Comprising
The output voltage divided by the voltage dividing resistor is fed back to the error amplifier as the feedback voltage, and is a constant voltage power supply circuit configured to be able to make the output voltage constant,
A second driver stage is provided together with the first driver stage;
The first driver stage includes a first driver stage field effect transistor that is grounded to amplify the output of the error amplifier, and a current source load of the first driver stage field effect transistor, While the output voltage is configured to be applied to the gate of the power transistor,
The second driver stage includes a second driver stage field effect transistor that is grounded to amplify the output of the error amplifier, and a current source load of the second driver stage field effect transistor. Become
And a control circuit configured to form a discharge path of a parasitic capacitance of the power transistor based on a difference between an output voltage of the first driver stage and an output voltage of the second driver stage. Constant voltage power supply circuit.   The control circuit uses a P-channel MOS field effect transistor, and the output voltage of the second driver stage is applied to the gate, and the output voltage of the first driver stage is applied to the source. 2. The constant voltage power supply circuit according to claim 1, wherein the drain is connected to the ground and an input voltage is applied to the substrate.

Images