JP2008310355A - Display device and control method of display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device in which a method of high-speed transmission of display data signal is improved, defect or constraint accompanying the conventional high-speed signal transmission is removed and low cost and high reliability is achieved. <P>SOLUTION: The display device comprises: a division means that divides display data to be displayed on a display means and generates the divided display data as a plurality (N) of serial signals; a means that multiplies marks different from one another of the serial signals; a combination means that combines output signals of the multiplying means and combines the output signals into serial signals fewer than the N; a means that converts the signals output from the combination means into electromagnetic signals and transmits the electromagnetic signals; a means that receives and demodulates the electromagnetic signals; and a restoring means that calculates correlation with the marks from the output signals of the demodulation means and restores the output signals into the display data, wherein the display means is driven on the basis of the signals restored by the restoring means. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a display device, and is suitable for application to a display device that requires high-speed large-capacity data transfer for driving a large display element such as a high-definition television.

In recent years, functions of televisions, notebook computers and the like have been remarkably improved, screens have become larger, and resolution and resolution have been increasing. In particular, in digital high-vision using a flat panel display, the display device is large in size and has a very large number of pixels, and the frequency band of the drive signal is very wide.
FIG. 9 is a block diagram showing a typical configuration of a display device using an active matrix liquid crystal display as a display element, and FIG. 10 is a time chart thereof.

  As illustrated in FIG. 9, the CPU 1701 generates image data to be displayed in accordance with an instruction from the main body unit 1719 and writes the image data in the video memory 1702. Note that the main body portion 1719 means a main body portion including an input / output device of a computer such as a main body circuit including a tuner and a demodulating portion in a television and a DVD player reproducing portion. The CPU 1701 receives a signal from the main body 1719, generates image data to be displayed by decompression or calculation from the image signal, a compressed image such as JPEG or MPEG, or moving image data, stores the image data in the video memory 1702, and stores it as necessary. To rewrite and update sequentially. The liquid crystal controller 1703 generates various timings necessary for liquid crystal display, that is, the X clock signal 1715, the horizontal synchronization signal 1714, and the vertical synchronization signal 1718 of the X driver 1713, and the image data in the order to be displayed from the video memory 1702. Is sent to the drivers (X driver 1713 and Y driver 1707) of the liquid crystal display 1708. Here, when the pixels of the liquid crystal display 1708 are composed of n rows and m columns, the X driver 1713 is composed of m stages of X shift registers 1704, m words of latches 1705, and m DA converters 1706. . The m-stage X shift register 1704, m-word latches 1705, and m DA converters 1706 are usually divided into a plurality of sets, integrated on a semiconductor integrated circuit, and arranged around the liquid crystal display 1708.

  When the liquid crystal controller 1703 reads the top pixel of the display frame, it generates a vertical synchronization signal 1718 and sends it to the Y driver 1707. At the same time, the liquid crystal controller 1703 reads data to be displayed on the pixel in the first row and first column of the liquid crystal display 1708 from the video memory 1702 and sends the data as a display data signal 1716 to the data terminal of the latch 1705. Here, the display data signal 1716 has, for example, 8 bits for each of R, G, and B for each pixel, and they are transmitted in parallel as 24 bits of parallel data using 24 transmission lines, or after the parallel-to-parallel conversion, 24 It is transmitted at twice the transmission rate.

As shown in FIG. 10, the X shift register 1704 reads the horizontal synchronization signal 1714 generated by the liquid crystal controller 703 in synchronization with the X clock signal 1715, and latches the signal X1 latch ( FIG. 10 (c)) is generated. With this signal, data displayed on the pixel in the first row and first column is latched in the first column of the latch 1705. Subsequently, the liquid crystal controller 1703 reads out data to be displayed on the next pixel from the video memory 1702 and outputs the data. The X shift register 1704 of the X driver 1713 shifts the horizontal synchronizing signal 1714 by one and generates a signal X2 latch (FIG. 10 (d)) for latching the image data in the second column. Latch eye image data.

  Thereafter, the X shift register 1704 sequentially shifts the horizontal synchronization signal 1714 and sequentially latches data to be displayed on the first row. In such an operation, when the display data signal 1716 is sent as parallel data for each pixel through a plurality of transmission lines, the display data is read into the latch 1705 in parallel every X clock, and serial When it is sent as data, it will not be necessary to explain that it is read into the latch 1705 in parallel after the serial-to-parallel conversion. When the latch 1705 finishes storing the data for one row, the next horizontal synchronizing signal 1714 (FIGS. 10A and 10H, FIG. 10A to FIG. 10F and FIG. 10G to FIG. 10K). )), The horizontal time scale of the horizontal axis is changed, so that the horizontal sync signal 714, which is the same signal, is re-displayed in addition to (a).) Is output, and the DA converter 1706 is output. D / A converts the data held in the latch 1705 and outputs it to the Xi-th (1 ≦ i ≦ m) of the column electrode 1710. At the same time, the Y driver 1707 outputs a selection signal to the first row electrode Y1.

Similarly, the Y driver 1707 sequentially shifts the selection signal to the Yj-th (1 ≦ j ≦ n) of the row electrode 1709 every time the horizontal synchronization signal 1714 is output.
The one-dot chain line 1718 in FIG. 9 is an enlarged view of one pixel portion of the liquid crystal display 1708 arranged in a matrix. When the Yj-th row electrode 1709 is selected, the active switch element 1711 transmits the output of the DA converter 1706 output to the Xi-th column electrode 1710 to the pixel electrode 1712. Note that one DA converter 1706 may be placed on the liquid crystal controller side, and the data 1716 may be transmitted as an analog signal. In this case, the latch 1705 is an analog sample and hold circuit. This method can reduce the number of DA converters and has been used in the past. However, even if it is a DA converter, the voltage value finally applied to the pixel electrode 1712 only needs to be a predetermined value. Since digital circuits such as pulse width modulation can be used and an analog sample-and-hold circuit is not required, the method described here has become mainstream as the density of LSIs increases.

However, in this method, since data is sent as a digital signal, the number of signal lines is very large, and for example, a total of 24 bits of 8 bits × 3 primary colors are required. Further, the amount of image data necessary for displaying one frame is multiplied by this resolution (number of pixels).
Note that after the display signal at the right end of the row is output from the liquid crystal controller 1703, the time until the display signal at the left end of the next row is output, or after the image data of the bottom row on the screen has been output, The time until image data of the first row of the frame is output is called a (horizontal, vertical) blanking period or blanking period, and cannot be set to 0 in the CRT, but may be 0 in the liquid crystal display. FIG. 10 illustrates a case where a horizontal blanking period for one pixel and a vertical blanking period for one row are taken.

  With the recent increase in display size and resolution, image data to be transferred from the liquid crystal controller 1703 exceeds gigabit per second. For example, if a high-definition class screen with a resolution of 1920 × 1080 pixels is displayed for 60 frames per second, a data transfer rate of 1920 × 1080 × 24 × 60≈2.986 Gbps (bits per second) is required. .

  In addition, the displayed data often includes various functions in the main body portion 1719 with the era of multimedia, and it is desirable that the liquid crystal display body 1708 and the main body portion 1719 be separable. Due to such a requirement, the mounting substrate is separated into a plurality of cases, and in that case, the mounting substrate is often divided by the one-dot chain lines 1717-1717 'in FIG. Inevitably, the connection between the main body 1719 and the liquid crystal display 1708 becomes long.

  Further, as the resolution of the liquid crystal display body 1708 is increased, the signal frequencies of those lines are increased, making connection difficult. Also, the display screen itself becomes large, and it is practically impossible to distribute data exceeding gigabits per second to a liquid crystal driver (especially the X driver 1713) arranged around the screen exceeding 100 inches. A method of reducing the transmission speed of each line by providing a large number of lines in parallel is adopted. However, in the high-definition class, the number of tracks becomes very large, exceeding 100.

In order to solve this problem, for example, LVDS (Low
It has been proposed to use (Voltage Differential Signaling) for connection of a display driver (Patent Document 1 and Patent Document 2). In Patent Document 3 and Patent Document 4 and the like, a new method is also proposed because sufficient resolution cannot be obtained even with this method.

Japanese Patent No. 3086456 (column 44) Japanese Patent No. 3330359 (column 46) Japanese Patent No. 3349426 Japanese Patent No. 3349490

However, recent progress in the enlargement of display bodies is remarkable, and sufficient performance cannot be obtained even with these technologies. In order to obtain sufficient anti-noise characteristics (interference resistance and coherence), careful design and adjustment are required. Further, in LVDS, since the signal level is small, an analog signal is inevitably handled by a digital IC, and there is a problem that power consumption increases.
In addition, in order to transmit a signal with high accuracy, matched impedance termination is required. However, since the number of lines that need impedance termination is large and the transmission impedance is about 100 ohms at most, the termination resistance is not limited. There was also a problem that the power consumed was unacceptably large.

  Furthermore, when the mounting substrate is divided by the one-dot chain line 1717-1717 'in FIG. 9, it is necessary to transmit a large amount of data at high speed through a line routed by a long wiring. For this reason, the radiation electromagnetic field from a track | line increases, and becomes a factor of the electromagnetic wave interference to another electronic device or an own apparatus. In the conventional signal transmission through the signal line, the amplitude level at the power receiving end is defined, and even if sufficient quality is ensured at the power receiving end, the amplitude level of the signal cannot be lowered. In other words, EMI countermeasures become difficult, resulting in restrictions on equipment design and cost increase. On the transmission side, in addition to the load at the power receiving end, the stray capacitance of the line is simultaneously driven, so that extra energy is required for signal transmission. That is, the result is an increase in power consumption.

Further, the increase in the number of wirings accompanying the increase in the transfer data requires a physical space for wiring, which naturally imposes great restrictions on the device design.
In particular, when the wiring passes through a movable part such as a hinge part, the characteristic impedance changes depending on the bending state of the movable part. Therefore, impedance mismatch occurs depending on the situation, and signal degradation is caused by reflection at the bent part. For this reason, there are problems that the speed of data to be transmitted is limited and that the mounting method and the arrangement of parts are restricted. Further, since the number of signals to be exchanged exceeds 100, there is a disadvantage that the cost of the flexible substrate and connector for performing this connection is high and the connection reliability is low.

  Therefore, the present invention improves the method of high-speed transmission of data having various problems and restrictions as described above by a completely new method that has not existed in the past, eliminates these conventional defects and restrictions, and is reliable at low cost. An object is to realize a display device with high performance.

  The display device according to the present invention includes display means for displaying display data, dividing means for dividing the display data displayed on the display means to generate a plurality of N (N is an integer of 1 or more) serial signals, A plurality of multiplication means for multiplying each serial signal by a different code; a transmission means for converting the signal output from the multiplication means into an electromagnetic wave signal; and a reception means for receiving the electromagnetic wave signal; and A restoration unit that restores the display data by calculating a correlation between the received signal received and the code, and a driving unit that drives the display unit based on the signal restored by the restoration unit. It is characterized by that.

  According to this configuration of the present invention, display data transmitted to the display means is code-division multiplexed and transmitted as an electromagnetic wave signal, so that various problems associated with conventional high-speed mass data transmission by wire can be eliminated at once. In addition, since codes are spread and multiplexed, the number of transmission paths can be reduced. By appropriately selecting the spread codes, the signal energy spectrum can be concentrated near the radio frequency, and radio transmission using electromagnetic waves can be easily realized. It becomes. Furthermore, transmission with a small number of transmission lines and relaxation of the restriction on the frequency band required for each transmission line can be achieved. Therefore, the above configuration enables wireless transmission using electromagnetic waves for signal transmission / reception, and signals propagate through space, so there is no need for wiring such as flexible boards and connectors, resulting in high cost and reliability problems due to them. Disappears. In addition, it is possible to avoid the problem of power consumption that rises due to termination for impedance matching and an increase in data transmission speed. Further, there are no restrictions on wiring routing and component placement, and the design and usability of the electronic device can be improved. In addition, since signal transmission by this electromagnetic wave is performed at a close distance in the same device, it is only necessary to ensure communication within this distance, and the intensity of the radiated electromagnetic wave can be reduced to the limit, so that the EMI characteristics are improved. Essentially improved and countermeasures become easier.

The transmission means of the display device according to the present invention comprises a combining means for combining the output signals of the multiplying means and combining them into a serial signal less than N, and modulating a signal output from the combining means to a predetermined radio frequency. And a transmitting antenna that receives an output from the modulating means and radiates an electromagnetic wave.
According to the above configuration of the present invention, the display data signal is multiplexed and transmitted by a smaller number of modulation means and antenna means than N, so that the number of modulation means and antenna means can be reduced and multiplexed. It becomes possible to suppress the level of signal variation of each channel to be small, thereby facilitating the realization of the device.

The transmission means of the display device according to the present invention modulates an output signal of each of the multiplication means and modulates it to a predetermined radio frequency, and receives an output of each of the plurality of modulation means to emit an electromagnetic wave. And a plurality of transmitting antennas.
According to the above configuration of the present invention, the divided display data signal is directly modulated for each divided signal without being combined after being multiplied by a code, and is radiated as an electromagnetic wave signal from different antennas. Therefore, a circuit for synthesizing that requires analog addition becomes unnecessary, and realization by a semiconductor integrated circuit becomes easy.

The signal output from the multiplication means of the display device according to the present invention has a radio frequency component sufficient to radiate electromagnetic energy, and a plurality of transmission antennas that receive electromagnetic signals and emit electromagnetic waves. It is characterized by providing.
According to the above-described configuration of the present invention, since the code multiplied by the multiplying unit includes sufficient radio frequency energy, the multiplying unit can also function as the modulating unit, and the signal is converted to the radio frequency. The modulation means for modulating becomes unnecessary, and the circuit configuration can be simplified.

The display means of the display device according to the present invention has pixels arranged in a matrix and is displayed by line sequential scanning.
According to the configuration of the present invention, it can be implemented in a large-sized and large-capacity display device such as a flat-screen television or a notebook computer.
The dividing means of the display device according to the present invention is characterized in that pixel data of each pixel is divided for each bit and serially output for each pixel.

According to the above configuration of the present invention, it is possible to transmit pixel data that has been output and transmitted in parallel in the past or transmitted as high-speed serial data by parallel-to-parallel conversion by code division multiplexing for each pixel. The transfer speed for each bit can be reduced, and the conditions required for the electromagnetic wave transmission path can be relaxed.
The dividing means of the display device according to the present invention is characterized in that the column of the display means is divided into N sets and the pixel signals of each set are output in parallel.

  With the above-described configuration of the present invention, the display columns are grouped into N, so control for each group is possible. In particular, since the driving circuit of the display means is often divided into several groups for each column or row and mounted on a semiconductor integrated circuit, this configuration according to the present invention is convenient. In addition, transmission by code division multiplexing using electromagnetic waves is possible, the transfer rate for each bit can be reduced, and the conditions required for the transmission path of electromagnetic waves can be relaxed.

  A display device according to the present invention divides display data having pixels arranged in a matrix and display data displayed on the display means into a plurality of N (N is an integer of 1 or more) sets of serial signals. Output from the synthesizing unit, a dividing unit that multiplies each of the serial signals by a different code, a synthesizing unit that synthesizes the output signals of the multiplying unit and synthesizes the serial signal into fewer than N serial signals. Transmitting means for converting the signal to be converted into an electromagnetic wave signal and transmitting, demodulating means for receiving and demodulating the electromagnetic wave signal, and restoring the display data by calculating the correlation between the output of the demodulating means and the code Means, storage means for temporarily storing the output signal of the restoration means, and drive means for driving the display means for each column based on the signal stored by the storage means. Characterized in that it.

  According to the above configuration of the present invention, since the display means side has the storage means for temporarily storing the display data restored by the restoration means, when the display data previously sent by the storage means is the same, By using the display data that has been sent out and stored in the storage means, it is possible to stop sending the display data and reduce the power consumption of the apparatus.

The display device according to the present invention is characterized in that the dividing means outputs display data only to a set that needs to be rewritten.
According to the above configuration of the present invention, the pixel data transmitted to the display means can be performed only on a portion that needs to be rewritten. Therefore, even if the display image is stationary, the image data is always displayed for each frame. Compared with the conventional method of transferring and updating data, the power consumption can be significantly reduced.

The display device according to the present invention includes a first code generation circuit for generating a code supplied to the multiplication means, and a second code for generating the same code as the code supplied to the restoration means and supplied to the multiplication means. The first code generation circuit and the second code generation circuit are synchronized by the same clock signal.
According to the above configuration of the present invention, it is possible to directly acquire a signal for synchronization of spreading code generation on the receiving side from the transmitting side. This eliminates the need for a special circuit for synchronizing the spread code generation on the receiving side, and simplifies synchronization acquisition.

  The display device according to the present invention includes display means having pixels arranged in a matrix and driven by line sequential scanning, display data generating means for generating display data for each scanning line of the display means, and the display Transmitting means for converting the signal output from the data generating means into an electromagnetic wave signal and transmitting it, demodulating means for receiving and demodulating the electromagnetic wave signal, and display data demodulated by the demodulating means to drive data to each predetermined pixel Driving means divided into N groups (N is an integer equal to or greater than 1) and detection means for detecting pixels having different display data between adjacent scanning lines, and displayed on the nearest scanning line Display data is sent from the display data generating means to the driving means only for a set including one or more pixels on which display data different from display data is displayed.

  According to the above configuration of the present invention, if there is no difference in display data between the image displayed by the scanning line immediately above displayed on the display device and the scanning line to be displayed this time, transmission of the display data is stopped. The operation of the transmission line and the circuit for driving the display body can be stopped, and the power consumption of the device can be significantly reduced. In particular, the correlation of display data between scan lines is strong, and a structure in which one scan line is separated into several sets has a significant effect compared to the control for each frame.

In the display device according to the present invention, a code for code multiplexing is assigned to each set of the driving means, and transmission of display data from the display data generating means to the driving means is performed by the code. It is characterized by designating which set of means is sent.
According to the above configuration of the present invention, addressing for display data distribution is performed by codes, so that it can be realized with a simple circuit, and the transmission rate can be reduced. Even against it, it can be more resistant. The frequency component of the transmitted signal is spread and has a great effect on EMI countermeasures.

The code of the display device according to the present invention is an orthogonal code, the same PN code whose phase is shifted, or the same PN code whose phase is shifted and offset is added.
According to the above configuration of the present invention, when the code used for code division multiplexing is an orthogonal code, the correlation between the codes can be made completely zero, so that each data is completely separated and restored from the multiplexed image signal. I can do it. Also, if the code used for code division multiplexing is a PN sequence, even if the same code is used, if the code phase is different, the correlation can be very small, so that multiplexing using one code is possible, Each data can be separated and restored from the converted image signal.

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a main part of an embodiment of a display device according to the present invention. FIG. 1 illustrates a typical block diagram of a display device using an active matrix liquid crystal display as a display element.
As shown in FIG. 1, the CPU 101 generates image data to be displayed in accordance with an instruction from the main body 131 and writes it in the video memory 102. Here, the main body 131 means a main body including an input / output device of a computer such as a main circuit including a tuner and a demodulator in a television and a DVD player reproducing unit. The CPU 101 receives the signal from the main unit 131, generates the image signal, image data to be displayed by decompression or calculation from a compressed image or moving image data such as JPEG or MPEG, and stores it in the video memory 102, and stores it as necessary. To rewrite and update sequentially. The liquid crystal controller 103 generates various timings necessary for liquid crystal display, that is, the X clock signal 115, the horizontal synchronizing signal 114, and the vertical synchronizing signal 118 of the X driver 113, and the display data in the order to be displayed from the video memory 102. Is read. At this time, the display data is read from the video memory 102 as bit-parallel serial data for each pixel and output as a display data signal 116.

Here, multiplication circuits 119-1, 119-2,..., 119 -N corresponding to the respective bits of the display data are provided on the main body 131 side, and the multiplication circuits 119-1, 119-2 are provided. ,..., 119 -N are supplied with spreading codes C _k (k = 1, 2,..., N), respectively. Then, each bit of the display data signal 116 is respectively transmitted by the spreading code C _k (k = 1, 2,... N) and the multiplication circuits 119-1, 119-2,. The signals are multiplied and analog-added by the adder circuit 120, modulated by the modulation circuit 123 as a multiplexed signal 122, and transmitted from the transmission antenna 125 to the liquid crystal display 108 side as an electromagnetic wave (radio wave) signal.

Here, on the liquid crystal display 108 side, correlation circuits 121-1, 121-2,..., 121-N corresponding to the respective bits of the display data are provided, and the correlation circuits 121-1, 121-N are provided. 2,..., 121-N are supplied with spreading codes C _k (k = 1, 2,..., N), respectively. On the liquid crystal display 108 side, the electromagnetic wave signal received by the receiving antenna 126 is demodulated into the multiplexed signal 122 by the demodulation circuit 124. The demodulated multiplexed signal 122 has a correlation of the same spreading code C _k (k = 1, 2,... N) as the spreading code multiplied on the transmission side. .., 121-N respectively, restored to bit-parallel serial data for each pixel, and sent to the latch 105. The restoration of the multiplexed signal 122 can also be realized by a method using a matched filter. When the matched filter is used, the synchronization procedure with the spreading code can be simplified.

Here, the spread code C _k (k = 1, 2,... N) is a time function that changes in units of time called a chip period t _c, and is a code that has a low correlation between different spread codes. Select and use. That is, when the value of the i-th C _k is written as C _k (i) with t _c as a unit, two arbitrary spreading codes C _k and C _{k ′} are taken, and the following calculation is executed:
R = ΣC _k (i) C _{k ′} (i)
That is, when correlation calculation is performed (the sum is calculated over one symbol interval), when k and k ′ are different, the spreading code C so that the absolute value of R takes a value close to zero. _k and C _{k ′} are set. When R = 0, it is said that these two types of spreading codes C _k and C _{k ′} are orthogonal. When the orthogonal spreading codes C _k and C _{k ′} are used, the multiplexed signal 122 can be completely separated on the receiving side.

The X driver 113 includes an m-stage X shift register 104, an m-word latch 105, and m DA converters 106 when the pixels of the liquid crystal display 108 are configured by n rows and m columns. The m-stage X shift register 104, m-word latch 105, and m DA converters 106 are usually divided into a plurality of sets, integrated on a semiconductor integrated circuit, and arranged around the liquid crystal display 108. When the liquid crystal controller 103 reads the first pixel of the display frame, the liquid crystal controller 103 generates a vertical synchronization signal 118 and sends it to the Y driver 107. At the same time, the data to be displayed on the pixel in the first row and the first column is restored as parallel data for each pixel by the correlation circuits 121-1, 121-2,. Thereafter, each time the X clock signal 115 is sequentially input, the read clock of the latch 105 generated by the X shift register 104 is shifted in the column direction and latched. (The method for generating the X clock signal 115 will be described later.)
Conventionally, the display data signal 116 has 8 bits for each RGB, for example, for each pixel, and they are transmitted in parallel as 24 bits of parallel data using 24 transmission lines, or 24 times after parallel conversion. It was transmitted with the transmission rate.

  On the other hand, according to the present embodiment, the display data signal 116 is code-multiplexed as a multiplexed signal 122 and propagates in space as an electromagnetic wave signal. Of course, in this example, all 24 bits are multiplexed into one. However, for example, 8 bits may be multiplexed to form 3 channels and transmitted using different frequencies, for example. Even in such a case, the circuit for generating / restoring the electromagnetic wave signal can be realized without increasing the size. Even if all 24 bits are multiplexed into one, the transmission rate per bit line of the display data data signal 116 is the same as when the conventional 24 signal lines are drawn. Note that it is not 24 times higher.

FIG. 2 is a diagram for explaining in more detail an example of multiplexing of the display data signal 116 of the display device according to the present invention and its restoration, that is, examples of the parts of the multiplier circuit 119, the adder circuit 120, and the correlation circuit 121 of FIG. A method for generating the X clock signal 115 will also be described.
In FIG. 2, the display data signal 116 read by the liquid crystal controller 103 is bit-parallelized for each pixel and is output to the terminal 209. Each bit of the display data signal 116 includes each of the spread codes C _k (k = 1, 2,... N) generated by the spread code generation circuit 201 and the multiplication circuits 202-1, 202-2, 202. Multiplied by −N, added in an analog manner by the adder circuit 203, sent as a multiplexed signal 214 to the modulation circuit 216, and sent as an electromagnetic wave signal from the transmitting antenna 218 to the liquid crystal display 108 side. If the input of the multiplication circuit 202 is a digital binary value and the spreading code C _k is also a binary value, the multiplication circuit 202 can be constituted by an exclusive OR circuit. Since the output of the adder circuit 203 is multivalued, analog addition is necessary. When the output logic of the multiplication circuit 202 is 1, -1V, and when the logic is 0, 1V is associated and analog addition is performed.

On the liquid crystal display 108 side, the multiplexed signal 122 due to the electromagnetic wave transmitted from the transmitting antenna 218 is received by the receiving antenna 219, and the multiplexed signal is restored by the demodulation circuit 217. The reconstructed multiplexed signal includes the same spreading code C _k (k = 1, 2,... N) as the spreading code used on the transmission side generated by the spreading code generation circuit 204 and each multiplication circuit 206-. 1, 206-2, 206-N. These signals are integrated over one symbol section by integrating circuits 207-1, 207-2, and 207-N, respectively, and bit 1 or 0 is determined by determining circuits 208-1, 208-2, and 208-N, respectively. Then, it is output as display data 210 and sent to the latch 105 in FIG.

Since one input is a multi-value signal for the multiplication circuits 206-1, 206-2, and 206-N, the exclusive OR circuit can no longer be used, and an analog multiplication circuit such as a balanced modulation circuit is used. In this part, all the processes after AD conversion may be digitized and processed.
In this embodiment, the spread code C _k used on the transmission side cannot be correctly restored on the reception side unless the same spread code C _k is used in synchronization on the reception side. In conventional multiplex communication using spread codes, a special circuit is required on the receiving side to synchronize the generation of spread codes. However, as in this example, when the transmitting and receiving ends are at a close distance, The signal for this purpose may be obtained directly from the transmission side. For this reason, in this embodiment, the same chip clock 211 is used, and the spread code generation circuits 201 and 204 are reset by the horizontal synchronization signal 213 to achieve synchronization. By taking such a configuration, synchronization acquisition can be significantly simplified. The frequency dividing circuit 205 divides the chip clock 211 to generate a signal for each symbol period, and integrate circuits 207-1, 207-2, 207-N and determination circuits 208-1, 208-2, 208-. Reset N. In this case, since the output 212 of the frequency dividing circuit 205 is one symbol period, it has the same period and phase as the X clock signal 105, and this signal can be used as the X clock signal 115. The chip clock 211 is a clock signal having a period corresponding to one chip of a spread code, and the frequency of the normal chip clock 211 is high. For example, the horizontal synchronization signal 213 is transmitted on the liquid crystal display 108 side without sending the chip clock 211. May be multiplied and reproduced by means such as PLL, or a clock signal for each pixel such as the X clock signal 115 may be sent and multiplied and reproduced on the receiving side.

  An alternate long and short dash line 215-215 ′ is a boundary that separates the main body 131 side and the liquid crystal display body 108 side, and a transmission line that passes through this boundary requires a physical length and requires good transmission characteristics. It was difficult to implement with technology. In the present embodiment, there are three lines that are transmitted through the boundary, that is, the chip clock signal 211, the horizontal synchronizing signal 213, and the vertical synchronizing signal 216, and each line does not require high speed and wide bandwidth. In addition, since the display data signal 116 requiring the highest speed and wide band is transmitted by electromagnetic waves, various difficulties in conventional high-speed data transmission can be eliminated. Furthermore, it is possible to perform transmission without increasing the transmission rate by multiplexing with spreading codes.

FIG. 3 is a time chart for briefly explaining the operation of the present invention. FIG. 4A illustrates the multiplexing process on the transmission side, and FIG. 4B illustrates the restoration process on the reception side. Here, for the sake of simplicity, the number of multiplexing is described as 3, but in practice, the spreading code length is increased and the number of multiplexing is made much larger. In the figure, time t _b is a symbol period in which one symbol is transmitted, time t _c is a chip period, and t _b / t _c is called a spreading factor (SF). 1 / t _c is the chip frequency.

In FIG. 3A, b ₁ , b ₂ , and b ₃ are display data read from the video memory 102 by the liquid crystal controller 103. C ₁ , C ₂ , and C ₃ are spreading codes generated by the spreading code generation circuit 201, and b ₁ , b ₂ , and b ₃ are respectively multiplied by the multiplication circuit 202, and b ₁ C ₁ , b ₂ C ₂ , B ₃ C ₃ is generated. Here, C ₁ , C ₂ , C ₃ and b ₁ , b ₂ , b ₃ are illustrated as logic binary signals with logic 1 and 0. Further, b ₁ C ₁ , b ₂ C ₂ , and b ₃ C ₃ are the results of multiplication by making analog value -1 correspond to logic 1 and analog value 1 correspond to logic 0. It may be considered that an exclusive OR of b _k and C _k is taken, and that the analog value −1 is associated when the output is logic 1, and the analog value 1 is associated when the output is logic 0. b ₁ C ₁ , b ₂ C ₂ , and b ₃ C ₃ are added in an analog manner by the adder circuit 203 to output S. That is, S = b ₁ C ₁ + b ₂ C ₂ + b ₃ C ₃ , and this signal is modulated by the modulation circuit 216 as a multiplexed signal 214 and then transmitted to the liquid crystal display 108 side through the transmission antenna 218.

On the liquid crystal display 108 side, as shown in FIG. 3B, the signal received by the receiving antenna 219 is demodulated by the demodulating circuit 217, and the demodulated multiplexed signal S has the same spreading code C _{1 as} that on the transmitting side. , C ₂ , C ₃ are multiplied by multiplication circuits 206-1, 206-2, 206-N, respectively, to generate SC ₁ , SC ₂ , SC ₃ , and integration circuits 207-1, 207-2, 207-N To integrate over time t _b . Each integration result is also shown in FIG. Decision circuit 208-1,208-2,208-N by determining logical 1 if the logical 0, V _t or less if the integration result is the threshold level V _t above, can restore the original display data signal 116. Since this figure is a schematic in an environment with no noise at all, the integration result is ± 4. However, in the environment where the orthogonality of spreading codes is bad or noisy, this is clear. so it can not discriminate, do the discrimination and appropriately determine the threshold level V _t.

Meanwhile, the signal 1 bit multiplexed with a spread code is transmitted in the time of 1 symbol interval t _b. This is the same speed as the transmission per signal line when the display data signal 116 is transmitted in parallel using a plurality of conventional transmission lines. In the case of transmitting a total of 24 bits of 8 bits for each of R, G, and B in the 1920 × 1080 pixel liquid crystal display 108 used in the description of the conventional example as an example, when 24 bits are multiplexed, each bit is 1920 × 1080. Although it is transmitted at a speed of × 60≈124.4 Mbps, it is actually spread to SF times for multiplexing. In order to multiplex and send 24 bits and completely separate them on the receiving side, at least 24 SFs are required. In consideration of this, the chip rate of diffusion becomes the above-mentioned SF times, that is, about 3 Gcps (chip per second) which is the same value as the conventional one, and it may be considered that there is no effect. Considering the orthogonality and accuracy of the spread code, it is necessary to transmit at higher cps. However, this is advantageous when the display data signal 116 is transmitted by electromagnetic waves as in this embodiment. The degree of freedom in selecting the chip rate can be increased, and the frequency of the radiated electromagnetic wave can be increased to some extent, and transmission as an electromagnetic wave becomes easier. Furthermore, in comparison with the case where everything is transmitted as serial data as in the prior art, in this embodiment, the bandwidth required for the transmission path may be narrow, so the design is easier. That is, in the conventional example, the display data signal 116 is in a very wide frequency band from DC in the case of full screen black or white to the highest frequency in the case of a checkered pattern for each dot (about 1.5 GHz in the above example). On the other hand, while uniform transmission characteristics are required, the band required in the present embodiment is such that most of the energy required for transmission is at most up to the symbol frequency band around the chip frequency. Because it concentrates, it does not require a large bandwidth in the transmission line. This significantly relaxes the characteristics required for the transmission line and facilitates its realization.
Further, in the conventional example, since one bit is transmitted within one period of about 3 GHz, it is easy to receive interference between symbols, and further, resistance to reflection due to a bend or mismatch of the transmission path is weak. . On the other hand, in this embodiment, since the time for sending 1 bit is longer than that of the conventional example by SF compared to the conventional example, the intersymbol interference is remarkably mitigated even if there is a disturbance due to the same amount of reflection as the conventional example. The Further, as a characteristic of code multiplexing, distortion due to multipath when propagating in space can be removed by a RAKE method or the like.
As described above, even if the chip rate of the code in the transmission line is higher than the transfer clock frequency in the case of conventional all serial transmission, the specifications required for the transmission line are remarkably relaxed and easy to implement. It is. Furthermore, in the conventional example, when the display content to be displayed is a specific pattern, the display data signal 1716 may have a very strong spectrum at a specific frequency. This is very disadvantageous from the viewpoint of unnecessary radiation generated from equipment, that is, EMI regulation. However, according to the present embodiment, the display data signal is always spread by the spread code, and therefore, a strong spectrum at a specific frequency. There is also an effect that it is very advantageous in terms of EMI countermeasures.
In addition, when a signal is transmitted through a wired line as in the past, the signal needs to be driven together with the stray capacitance of the line, and there is an essential problem that power consumption increases as the signal frequency increases. . On the other hand, in this embodiment, since the signal propagates through the space by electromagnetic waves, the higher the frequency, the easier it is to radiate as electromagnetic waves, and the power on the transmitting side can be reduced to a level that can be received on the receiving side, thus significantly reducing power consumption. effective.

FIG. 4 is a diagram showing a main part of another embodiment according to the present invention. An example in which another method is adopted as the configuration of the adder circuit 203, the modulation circuit 216, and the demodulation circuit 217 shown in FIG. Show. Another example of a method for generating a chip clock or an X clock signal is also shown. 4, components having the same functions as those in the block shown in FIG. 2 are denoted by the same reference numerals, and description thereof is omitted unless particularly described.
In FIG. 4, transmission antennas 418-1, 418-2, and 418 -N are provided corresponding to the respective bits of the display data signal 116. The transmission antennas 418-1, 418-2, and 418 -N are connected to multiplication circuits 202-1, 202-2, and 202 -N via amplifiers 416-1, 416-2, and 416 -N, respectively. Has been.
The amplifiers 416-1, 416-2, and 416-N receive and amplify the signals of the multiplication circuits 202-1, 202-2, and 202-N, respectively, and transmit antennas 418-1, 418-2, and 418-. Each N is powered. Note that the amplifiers 416-1, 416-2, and 416-N can be provided with a function of reducing transmission power to a minimum level that can ensure a required SN ratio on the receiving side. Transmission level control may be performed based on the reception result from the reception side. If the output drive capability of the multiplier circuits 202-1, 202-2, 202-N is sufficient, the amplifiers 416-1, 416-2, 416-N are omitted, and the transmitting antennas 418-1, 418-2 are omitted. 418-N may be directly fed.
In this embodiment, amplifiers 416-1, 416-2, and 416-N are arranged at the position of the modulation circuit 216 in the first embodiment. In this way, by adjusting the code length of the spread code and setting and using the chip frequency in a desired frequency band, the multiplying circuits 202-1, 202-2, and 202 -N also function as the modulation circuit 216. It is possible. When such a circuit configuration is adopted, the frequency spectrum of the output signals of the multiplication circuits 202-1, 202-2, and 202-N is a convolution integral of the display data input to the terminal 209 and the frequency spectrum of the spread code. . If the spreading code is selected properly, it is possible to generate an electromagnetic wave signal whose spectrum is concentrated in the range of ± symbol rate centering on 1/2 of the chip frequency, and the circuit can be simplified.
Furthermore, compared with the first embodiment, the adder circuit 120 is omitted, but the addition of signals is performed in space and becomes a multiplexed signal 403 by electromagnetic waves. In this case, each transmitting antenna 418-1, 418-2, 418-N needs to be sufficiently close to the wavelength of the chip frequency. When antennas having the same constant number are located at a short distance, they have an influence on each other, but not so much as to hinder communication with the short distance. The electromagnetic wave signals transmitted from the respective transmission antennas 418-1, 418-2, and 418 -N are added in space to become a multiplexed signal 403 and received by the reception antenna 219. The amplifier 417 amplifies the signal received by the receiving antenna 219 to a necessary level, transmits it to the multiplication circuits 206-1, 206-2, 206-N, and restores the display data signal 116 by the same operation as in the first embodiment. Output to terminal 210.

The chip clock 211 supplies a clock to the code generation circuit 201 to generate a spread code. The frequency dividing circuit 403 divides the chip clock 211 to generate a horizontal synchronizing signal 213, and this signal is transmitted to the liquid crystal display 108 side by wire. The horizontal synchronization signal 213 has a sufficiently lower frequency than the display data signal 116 and the like, and since it is only for one line, wiring is easy. On the liquid crystal display 108 side, the horizontal synchronizing signal 213 is multiplied by the PLL 404 to generate a chip clock having the same homologous frequency as the chip clock 211 used on the transmission side, and is sent to the code generation circuit 204, and the spread code on the reception side is generated. appear. The chip clock 405 is also frequency-divided by the frequency dividing circuit 205 to generate the X clock signal 212. The X clock signal 212 is also used for resetting the integration circuit 207.
By adopting such a configuration, it is possible to reduce the number of lines connecting the liquid crystal display 108 side and the main body 131 side, and the signal transmitted through the wired path is low in frequency, and thus easy to implement. In addition, various problems in high-speed mass data transmission, which has been a problem in the past, can be solved at once.

FIG. 5 is a block diagram showing a main part of still another embodiment of the display device according to the present invention. Note that the functions of the blocks assigned the same numbers as in FIG.
In FIG. 5, the X driver 513 is divided into N groups, and X shift registers 543-1,... 543-N, latches 544-1,. ,... 545-N. Usually, the X driver 513 and the Y driver 107 are divided into a plurality of parts, housed in an integrated circuit, and used in cascade connection. The grouping into N groups may be considered as a unit of this driver integrated circuit, or a plurality of groups may exist in one driver integrated circuit. Each pair of X drivers 513 includes a correlation circuit 541-1,..., 541-N and a spread code generation circuit 542-1,. Each set of the X driver 513 is assigned a unique spreading code set S _p = [C _pk ] (p = 1, 2,... N), and each spreading code generating circuit 542-, ... 542-N generate this allocated spreading code set. That is, the spreading code generation circuit 542-p of the p-th set generates a respective code of the code set S _p. The correlation between each set of spreading code sets is designed to be small. It goes without saying that the correlation between codes in the code set is designed to be small. In both cases, it is ideal to use a completely zero correlation, that is, an orthogonal code system.

For the sake of explanation, the display data of the q-th column (q = 1, 2,... N / N) of the p-th group (p = 1, 2,... N) is Dpq. Dpq has information on color and gradation, that is, it is composed of a plurality of bits such as 8 bits for each of RGB. _Let the kth bit of each D _{pq be} b _k .
.., 542 -N on the X driver 513 side generate only the code set assigned to itself, whereas the code generator circuit 501 on the transmission side uses it as necessary. Generate all spreading code sets The liquid crystal controller 103 reads display data to be displayed from the video memory 102 and outputs it to the multiplexing circuit 503. The multiplexing circuit 503 selects a spread code set based on which set of X drivers 513 drives the pixel on which the display data is displayed, multiplexes the display data signal 116 with the spread code set, and Multiple signals 122 are generated. That is, the display data signal 116 sent to the X driver 513 of p-th set are multiplexed by code set S _p. In each set of the signal receiving side, that is, the X driver 513, only the spreading code of its own set is generated as the spreading code, and the display data signal 116 sent to the other set cannot be restored. Is determined. The multiplexed signal 122 generated by the multiplexing circuit 503 is modulated by the modulation circuit 123 and transmitted as an electromagnetic wave signal from the transmission antenna 125 to the liquid crystal display 108 side. On the liquid crystal display 108 side, the electromagnetic wave signal is received by the receiving antenna 126, the multiplexed signal is restored by the demodulation circuit 124, and is distributed to the correlation circuits 541-1,... 541-N. As will be described later with reference to FIG. 6, the reception antenna 126 and the demodulation circuit 124 may be used in common for each group, or a dedicated reception antenna and demodulation circuit may be provided for each group.

  In displaying an image, the correlation between scanning lines and frames is large, and it is often unnecessary to update the display data transmitted last time. The liquid crystal controller 103 compares the display data on the previous scanning line with the display data to be sent this time, and sends the display data only to a group having a different portion of the display data. On the liquid crystal display 108 side, if the correlation circuits 541-1,..., 541-N cannot detect the display data, it is determined that there is no need to change the display data, and the X shift register 543-1, ..., 543-N, latches 544, ..., 544-N and DA converters 545-1, ..., 545-N are stopped, and the output is not changed.

  In this way, the display data sending operation to the group that does not need to be updated can be stopped, so that the power consumption of the device can be greatly reduced. That is, by adopting the configuration as described above, the destination of display data is addressed by a spreading code for each group. Therefore, the destination of display data can be specified by changing the spreading code. For this reason, data transmission can be stopped for a set that does not require rewriting of display data, and power consumption can be reduced. As the number of sets (that is, N) increases, the display data transmission / stop control can be finely executed, and the effect of power consumption increases. When N is maximized, N = n (the number of pixels in the horizontal direction). However, if N is increased too much, there is a trade-off that the code length becomes longer and the amount of multiplexing / decompression increases.

Transmission order of the display data _{D 11, D 12, ··· D} 1N, D 21, D 22, ··· D 2N, each bit for each pixel from left to right as ··· b _{k (k} = 1, 2, · · w, w is may be multiplexed bit number) of pixels, D _11, D _21, each b ₁ of · · · D _N1 multiplexed, followed by the b ₂ is multiplexed After the first pixel is completed after being multiplexed bit by bit and transmitted, the second pixel, ie, b ₁ of D ₂₂ , D ₂₂ ,... DN ₂ is multiplexed, and then b ₂ is multiplexed. You may make it do.

In this case, in the former method, the spreading code set used when transmitting D ₁₁ , D ₁₂ ,... D _1N is S ₁ = [C _1k ] (k = 1, 2,... W). _{Yes, the} spread code set used when D ₂₁ , D ₂₂ ,... D _2N is transmitted is different because S ₂ = [C _2k ] (k = 1, 2,... W). The spreading code set is not used at the same time. On the other hand, in the latter method, since it is transmitted in a bit-serial in parallel, a plurality of different spreading code sets are used simultaneously. In the latter case, in many cases, the number of codes in each code set may be 1 or 2 (when sending 2 bits of each pixel in parallel). Thus, since each set and each bit can be addressed by a spreading code, the sending order can be arbitrarily changed. The former method has the advantage that the display data read from the video memory can be sent without rearrangement, but there is a period of no signal for a set that does not require data update, the bit transfer rate is high, and many The number of spreading codes is required. In the latter method, the liquid crystal controller 103 has to read and store the pixel data for each set, and then rearrange the data for each bit to output. However, the transfer rate per bit can be reduced, and the necessary spreading code can be reduced. The number may be small, and the code design is easy. The latter method is described in more detail in Example 5.

FIG. 6 is a diagram for explaining still another embodiment of the present invention. In FIG. 5, an X driver 513, correlation circuits 541-1,... 541-N, a spread code generation circuit 542-1,. .. 542-N, a portion corresponding to each set of the reception antenna 126 and the demodulation circuit 124 can be replaced with the configuration of FIG. FIG. 6 shows only one set.
In this embodiment, in order to reduce the transfer of the display data signal 116 using the correlation between the frames of the display image, the frame memory 643 is placed for each set on the liquid crystal display 108 side, and the display is stationary. The display data signal 116 is not transferred, and the data stored in the frame memory 643 is used.

In the following description, the X driver 513 and the like in FIG. 5 are replaced with the configuration in FIG.
When the video memory 102 is rewritten, the liquid crystal controller 103 multiplexes the multiplexed signal 122 using the spread code set assigned to the group having the pixels for displaying the rewritten data, and modulates the multiplexed signal 122 to change the liquid crystal. An electromagnetic wave signal is transmitted to the display body 108 side. The liquid crystal controller 103 can detect that the video memory 102 has been rewritten by the CPU 101 by monitoring control of the video memory 102 from the CPU 101 (write pulse or address bus of the video memory 102). In addition, the CPU 101 can detect a portion that needs to be rewritten for each frame from the compression / decompression algorithm in MPEG decompression or the like. The CPU 101 may directly notify the liquid crystal controller 103 of the rewritten portion detected in this way. (In FIG. 5, the signal path for this is omitted.) In synchronization with the vertical synchronizing signal 118 and the horizontal synchronizing signal 114 generated by the liquid crystal controller 103, only the display data of the rewritten pixel is transmitted. Display data may be sent each time the video memory 102 is rewritten, but the rewriting of the CPU 101 to the video memory 102 is usually much faster than the timing at which the liquid crystal display 108 needs display data. For this reason, it is better to send the data in synchronization with the horizontal synchronizing signal 114 and the vertical synchronizing signal 118 immediately before the liquid crystal display 108 needs display data. In addition, in order to address all pixels by addressing with a spreading code, a very long spreading code is required. For this reason, data is transmitted in synchronization with the synchronization signal. For example, the row address, the pixel address in the X direction in the set, etc. are calculated from the timing from the synchronization signal, thereby reducing the number of address bits to be specified and short diffusion. It is good to be able to operate with a sign.

  The reception antenna 126 built in the liquid crystal display 108 receives the multiplexed signal 122 transmitted by the electromagnetic wave, demodulates it by the demodulation circuit 124, and sends it to the correlation circuit 641. The correlation circuit 641 calculates the correlation with the spreading code set assigned to the set, restores the display data signal 116 sent to the set, and stores it in the frame memory 643. If such a display data signal 116 generated by the liquid crystal controller 103 is not sent, the previous data is stored without updating the display data used in the display of the previous frame stored in the frame memory 643. Has been. The controller 602 synchronizes the spread code generating circuit 642 and controls the timing in synchronization with the chip clock 505 input to the terminal 603 and the horizontal synchronization signal 114 and the vertical synchronization signal 118 input to the terminals 604 and 605, respectively. Then, the latch 644 and the DA converter 645 are controlled in accordance with the display body operation.

  That is, the latch 644 reads display data on the scanning line to be displayed next from the frame memory 643 in accordance with the timing output from the controller 602 and holds it. When the next horizontal synchronizing signal 114 is input, the controller 602 activates the DA converter 645 and outputs and displays the driving voltage on the liquid crystal display 108 according to the data held in the latch 644.

In the above embodiment, the frame memory 643 is used to hold the data displayed in the previous frame. However, if the pixel itself has a holding function due to the capacitance of each pixel of the display body, the frame memory 643 is used. It can be omitted.
Further, the receiving antenna 126 and the demodulation circuit 124 may be provided for each set instead of each one. With such a configuration, it is not necessary to distribute the output of the demodulation circuit 124 to each set by wiring, and the mounting can be performed more efficiently.

  According to the above configuration of the present invention, since the display data signal 116 is addressed to a spread code, the display data signal 116 can be easily transmitted only to a set that needs to be rewritten. This has a significant effect on reducing power consumption.

FIG. 7 is a diagram showing still another embodiment according to the present invention, and illustrates the transmission order of display data signals in more detail. The display data signal transmission sequence corresponds to the case of the latter method in the third embodiment, and FIG. 7 is a diagram showing the configuration of the transmission side in more detail.
The liquid crystal controller 103 first reads from the video memory 102 the data of the pixel D _{11 in} the row to which the display data of the liquid crystal display 108 is to be sent. Data read from the video memory 102 is multi-bit information having color and gradation information. This information is sent to the parallel-serial conversion circuit 701-1, after being converted into a serial signal by the parallel-serial conversion is multiplied by the spread codes C ₁ to generate the PN code generating circuit 704 at multiplier circuit 702-1, the modulation Modulated by the circuit 703-1 and transmitted as an electromagnetic wave signal from the transmission antenna 705-1.

Next, the liquid crystal controller 103 reads the data of the pixel row of D ₂₁ to be sent to the display data of the liquid crystal display element 108 with a delay 1t _c from the video memory 102, and sends the parallel-serial conversion circuit 701-2. The parallel-to-serial conversion circuit 701-2 converts the display data of the pixel of D ₂₁ into a serial signal, which is then multiplied by the spreading code C ₂ generated by the PN code generation circuit 704 by the multiplication circuit 702-2 and modulated. The signal is modulated by the circuit 703-2 and transmitted as an electromagnetic wave signal from the transmission antenna 705-2.

Similarly, the same operation is continued up to the pixel of D _N1 , and further, D ₁₂ , D ₂₂ ,..., D _N2, and then data transmission for one line is completed with D _NM (where M = n / N). Then, the display data transmission of the next line is continued.
The PN code generation circuit 704 includes a shift register and a feedback circuit 706. The feedback circuit 706 takes an exclusive OR of outputs (taps) of appropriate stages of the shift register and feeds back to the first stage of the shift register. Depending on how the taps are taken, the combination of data held in the shift register can take the maximum number excluding all zeros (that is, 2 ^s -1 when an s-stage shift register is used).

In the embodiment of FIG. 7, since each spreading code is taken from the same shift register, these spreading codes have the same pattern of only by an integer multiple shift t _c to each other. The codes generated in this way are called M-sequences or PN sequences, and are 2 ^s -1 when the autocorrelation function is in-phase (τ = 0), and -1 in all other cases. It is known that According to the configuration of the present embodiment, since the spreading codes used use code sets having the same pattern but different phases, only one code generating circuit is required. In addition, since the PN code is generated by the shift register, if the code is extracted from each stage of the shift register, a code set having a different phase can be extracted, and the circuit can be simplified.

Next, an outline of the operation will be described with reference to the time chart of FIG. In the bottom row of the figure, a chip clock number is assigned for ease of the following description.
Hereinafter, when referring to the time, using the chip clock number, for example, when representing the leading edge of the time chip clock number 5, it is referred to as the leading edge of t _c 5. As in the case of FIG. 3, t _b in the figure is one symbol period, and t _c is a chip clock period. For ease of explanation, the case where the code length of the spreading code is 7 and the multiplexing number is 3 will be described as an example. However, in actual implementation, a longer code should be used and the multiplexing number should be larger. C ₁ , C ₂ , and C ₃ are PN sequences of length 7 used as spreading codes, and are out of phase by t _c . Here, t _b = 7t _c .

Liquid crystal controller 103 reads the D ₁₁ until t _c1 begins, and sends the data to the parallel-serial conversion circuit 701-1. Parallel-serial conversion circuit 701-1, and outputs it as serial data from bit 1 of D ₁₁ in sequence. D _{11 in} FIG. 8 shows a state of outputting every bit b ₁ to t _b . That is, b ₁ (b ₁ = 1 in this example) from t _c1 to t _c 7, b ₂ (b ₂ = 0 in this example) from t _c8 to t _c14 (b ₂ = 0 in this example), and send data every 7 t _{c in} the following order. Update.

Between t _c1 and t _c7 , that is, while the parallel-to-serial conversion circuit 701-1 sends b ₁ , the liquid crystal controller 103 reads D ₂₁ and sends data to the parallel-to-serial conversion circuit 701-2. Convert to serial data. D ₂₁ is, b ₁ (in this example b ₁ = 1) from t _c8 that is, from the second symbol in each 7t _c, b ₂ (in this example b ₂ = 0), signals are outputted in the ... Similarly, transmission of D ₃₁ starts from the third symbol, that is, t _c15 . One symbol section before the D ₂₁ parallel conversion is started and two symbol sections before the D ₃₁ parallel conversion are null periods in which nothing is transmitted.

These signals are multiplied by spreading codes C ₁ , C ₂ , and C ₃ by multiplication circuits 702-1, 702-2, and 702-3, respectively, and C ₁ D ₁₁ , C ₂ D ₂₁ , and C ₃ D ₃₁ are output. The As described above, the multiplication at this time is performed by making the analog value −1 correspond to the logic 1 of the spread code and the display data and the analog value 1 corresponding to the logic 0.
In FIG. 8, the line above the line D ₂₁ is displayed as a logical value, and the line below the line C ₁ D ₁₁ is displayed as an analog value. In addition, an analog value 0 is multiplied during a null period in which there is no transmission data. S is a multiplexed signal obtained by adding C ₁ D ₁₁ , C ₂ D ₂₁ , and C ₃ D ₃₁ , and in FIG. 7, since the addition of signals is performed in space, it can be considered as the strength of electromagnetic waves in space.

c ₁ , c ₂ , and c ₃ are obtained by converting the logical value representations of C ₁ , C ₂ , and C ₃ into analog value representations, respectively. The multiplexed signal S is multiplied by c ₁ , c ₂ , and c ₃ to calculate correlations with C ₁ , C ₂ , and C _3, and Sc ₁ , Sc ₂ , and Sc ₃ are calculated. ΣSc _1, ΣSc _2, ΣSc ₃ is an integrated value of up to 7t _c before that time. Strong correlation is shown at the end of each t _b period (hatched in FIG. 8), and received bits can be determined. That is, the logical value is 0 for a large positive value, and the logical value is 1 for a large negative value. When the signal is not null, the value is almost zero. For example, in the null 801 portion, the integrated value 802 is 0. When a PN sequence is used as such a spreading code, since the correlation does not become completely zero when the chip phase is shifted, some error is included. Therefore, it is necessary to take measures such as increasing the code length and increasing the spreading factor. There is also a method of ensuring orthogonality by offsetting the PN code slightly and keeping balance. In this case, it is necessary that the adder circuit, the reception-side correlation circuit, and the multiplier circuit be capable of correctly calculating the offset. It is also possible to use a code set having completely orthogonality instead of the PN code.

  The liquid crystal controller 103 sends the display data signal 116 only to the group that needs to update the display data signal 116. A null is transmitted for a group that does not require transmission of the display data signal 116. On the receiving side, if null can be received, it is understood that it is not necessary to update the display data signal 116 of the set. Therefore, the necessity of updating can be determined by receiving the head portion of each set. If there is no need for updating, the display data used is the previous one, and unnecessary circuit operations are stopped. This can significantly reduce the power consumption of the display device.

  In the present embodiment, the video memory 102 is described on the assumption that a frame memory, that is, one screen or more is stored. However, a television memory such as NTSC does not necessarily require a frame memory. Even in such a case, if the video memory has a line buffer memory for one or two scanning lines and a portion that needs to be updated is detected, the scanning order is not necessarily left to right as in this embodiment. A non-compliant transfer operation is possible, and in this case, unnecessary transfer can be omitted using the correlation between the scanning lines, which is effective in reducing the power consumption of the display device.

  As described above, according to these configurations according to the present invention, various difficulties in transmission of display data that includes a very high frequency component and requires high-speed data transfer can be reduced. Since signals can be multiplexed by spreading codes, the number of lines required for transmission can be reduced. In addition, the frequency band included in the display data can be narrowed to facilitate line design. Furthermore, even in the display of an image pattern in which a strong spectral peak appears in the spatial frequency of the image to be displayed, the display data is frequency-spread by the spreading code, so that a strong spectral peak does not appear at a specific frequency, and EMI There is a remarkable effect in countermeasures. Furthermore, since data addressing can be performed using a spread code, a data destination can be designated without any special addressing means. As a result, data transfer from the video memory to the display body can be performed only when the display changes, which has a significant effect on reducing the power consumption of the display device.

  The present invention has been described by taking a large-sized television display device as an example. However, the present invention is not limited to the above-described embodiment, and can be used in a wide range of applications such as connection with a display in electronic devices such as notebook computers and mobile phones. Applicable to.

The block diagram which shows the principal part of one Example of this invention. The block diagram which shows the multiplexing of one Example of this invention, and its decompression | restoration circuit part. The time chart which shows operation | movement of one Example of this invention. The block diagram which shows the principal part of the other Example of this invention. The block diagram which shows the principal part of the further another Example of this invention. The block diagram which shows the principal part of the further another Example of this invention. The block diagram which shows the principal part of the further another Example of this invention. The time chart which shows further operation | movement of one Example of this invention. FIG. 10 is a block diagram illustrating a display device having a conventional liquid crystal display body. The time chart explaining operation | movement of the display apparatus with the conventional liquid crystal display body.

Explanation of symbols

  131 ... Main body, 101 ... CPU, 102 ... Video memory, 103 ... Liquid crystal controller, 104, 543-1, 543-N ... X shift register, 105, 544-1, 544-N, 644 ... Latch, 106, 545 1,545-N, 645 ... DA converter, 107 ... Y driver, 108 ... liquid crystal display, 109 ... row electrode, 110 ... column electrode, 113,513 ... X driver, 119-1, 119-2, 119- N, 202-1, 202-2, 202-N, 206-1, 206-2, 206-N, 702-1, 702-2, 702-N ... multiplier circuit, 120, 203 ... adder circuit, 121- 1, 121-2, 121-N, 541-1, 541-N, 641 ... correlation circuit, 123, 216, 703-1, 703-2, 703-N ... modulation circuit, 124, 217 ... recovery Circuit, 125, 218, 418-1, 418-2, 418-N, 705-1, 705-2, 705-N ... transmitting antenna, 126, 219 ... receiving antenna, 205, 403 ... frequency dividing circuit, 207- 1, 207-2, 207-N: integration circuit, 208-1, 208-2, 208-N: determination circuit, 108, 708 ... liquid crystal display, 201, 204, 501, 542-1, 542-N, 642... Spreading code generation circuit, 503... Multiplexing circuit, 416-1, 416-2, 416-N, 417... Amplifier, 404... PLL, 602 ... Controller, 643 ... Frame memory, 701-1 and 701-2 701-N: Parallel-to-parallel conversion circuit, 704 ... PN code generation circuit, 706 ... Feedback circuit.

Claims (13)

Display means for displaying display data;
Dividing means for dividing display data displayed on the display means and generating a plurality of N (N is an integer of 1 or more) serial signals;
A plurality of multiplication means for multiplying each serial signal by a different code;
Transmitting means for converting the signal output from the multiplying means into an electromagnetic wave signal and transmitting the electromagnetic wave signal;
Receiving means for receiving the electromagnetic wave signal;
Restoring means for restoring the display data by calculating a correlation between the received signal received by the receiving means and the code;
A display device comprising: drive means for driving the display means based on the signal restored by the restoration means. The transmission means includes
Synthesizing means for synthesizing the output signals of the multiplying means and synthesizing them into serial signals less than the N;
Modulation means for modulating the signal output from the synthesizing means and modulating the signal to a predetermined radio frequency;
The display device according to claim 1, further comprising a transmission antenna that receives an output from the modulation unit and radiates an electromagnetic wave. The transmission means includes
A plurality of modulation means for modulating an output signal of each of the multiplication means and modulating the output signal to a predetermined radio frequency;
The display device according to claim 1, further comprising: a plurality of transmitting antennas that receive outputs of the plurality of modulation units and emit electromagnetic waves.   The signal output from the multiplication unit has a radio frequency component sufficient to radiate electromagnetic energy, and includes a plurality of transmission antennas that receive electromagnetic signals and emit electromagnetic waves. The display device according to claim 1.   5. The display device according to claim 1, wherein the display unit includes pixels arranged in a matrix and is displayed by line-sequential scanning.   6. The display device according to claim 1, wherein the dividing unit divides pixel data of each pixel into bits and serially outputs the data for each pixel. 6. The display device according to claim 1, wherein the dividing unit divides the column of the display unit into N sets and outputs the pixel signals of the sets in parallel. . Display means having pixels arranged in a matrix;
Dividing means for dividing the display data displayed on the display means into a plurality of N (N is an integer of 1 or more) sets and generating a serial signal;
Multiplying means for multiplying each serial signal by a different code;
Synthesizing means for synthesizing the output signals of the multiplying means and synthesizing them into serial signals less than the N;
Transmitting means for converting the signal output from the combining means into an electromagnetic wave signal and transmitting the electromagnetic wave signal;
Demodulation means for receiving and demodulating the electromagnetic wave signal;
Restoring means for restoring the display data by calculating a correlation between the output of the demodulating means and the code;
Storage means for temporarily storing an output signal of the restoration means;
A display device comprising: drive means for driving the display means for each column based on the signal stored by the storage means.   The display device according to claim 8, wherein the dividing unit outputs display data only to a set that needs to be rewritten. A first code generation circuit for generating a code supplied to the multiplication means;
A second code generation circuit for generating the same code as the code supplied to the restoration means and supplied to the multiplication means;
The display device according to claim 1, wherein the first code generation circuit and the second code generation circuit are synchronized by the same clock signal. Display means having pixels arranged in a matrix and driven by line sequential scanning;
Display data generating means for generating display data for each scanning line of the display means;
Transmitting means for converting the signal output from the display data generating means into an electromagnetic wave signal and transmitting it;
Demodulation means for receiving and demodulating the electromagnetic wave signal;
Drive means grouped into N (N is an integer of 1 or more) that distributes display data demodulated by the demodulation means as drive data to each predetermined pixel;
Comprising detection means for detecting pixels having different display data between adjacent scanning lines;
Display data is sent from the display data generating means to the driving means only for a set including one or more pixels on which display data different from the display data displayed on the latest scanning line is displayed. Display device.   Each set of the driving means is assigned a code for code multiplexing, and the transmission of display data from the display data generating means to the driving means is sent to any set of the driving means by the code. 12. The display device according to claim 11, wherein the display device is designated.   13. The code according to claim 1, wherein the code is an orthogonal code, the same PN code whose phase is shifted, or the same PN code whose phase is shifted and added with an offset. The display device described.

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