JP2008293044A - Display device and method for controlling display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve a method for high-speed transmission of display data signals in a display device, to eliminate drawbacks or restrictions accompanying conventional high-speed transmission of signals and to inexpensively achieve a device with high reliability. <P>SOLUTION: The display device is equipped with: a dividing means dividing the display data to display an image on a display means to generate a plurality N of serial signals; a means of multiplying each of the serial signals by a different code; and a synthesizing means synthesizing the output signal of the multiplication means to obtain serial signals in a number smaller than N; a restoration means receiving an output signal of the synthesizing means and calculating the correlation with the above codes to restore to the display data; and a driving means driving the display means based on the signal restored by the restoration means. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a display device that requires high-speed and large-capacity data transfer to drive a large display element such as a high-definition television.

In recent years, functions of televisions, notebook computers and the like have been remarkably improved, screens have become larger, and resolution and resolution have been increasing. In particular, in digital high-vision using a flat panel display, the display device is large in size and has a very large number of pixels, and the frequency band of the drive signal is very wide.
FIG. 7 is a block diagram showing a typical configuration of a display device using an active matrix liquid crystal display as a display element, and FIG. 8 is a time chart thereof.

  As illustrated in FIG. 7, the CPU 701 generates image data to be displayed in accordance with an instruction from the main body 719 and writes the image data in the video memory 702. Note that the main body portion 719 means a main body portion including an input / output device of a computer such as a main body circuit including a tuner and a demodulating portion in a television and a DVD player reproducing portion. The CPU 701 receives the signal from the main body 719, generates image data to be displayed by decompressing or calculating the image signal, compressed image such as JPEG or MPEG, or moving image data, stores the image data in the video memory 702, and stores it as necessary. To rewrite and update sequentially.

  The liquid crystal controller 703 generates various timings necessary for liquid crystal display, that is, the X clock signal 715, the horizontal synchronization signal 714, and the vertical synchronization signal 718 of the X driver 713, and the image data in the order to be displayed from the video memory 702. Is sent to the drivers (the X driver 713 and the Y driver 707) of the liquid crystal display body 708. Here, the X driver 713 includes an m-stage X shift register 704, an m-word latch 705, and m DA converters 706 when the pixels of the liquid crystal display 708 are configured by n rows and m columns. . The m-stage X shift register 704, m-word latch 705, and m DA converters 706 are usually divided into a plurality of sets, integrated on a semiconductor integrated circuit, and arranged around the liquid crystal display 708.

  When the liquid crystal controller 703 reads the top pixel of the display frame, it generates a vertical synchronization signal 718 and sends it to the Y driver 707. At the same time, the liquid crystal controller 703 reads data to be displayed on the pixel in the first row and first column of the liquid crystal display body 708 from the video memory 702 and sends it as a display data signal 716 to the data terminal of the latch 705. Here, the display data signal 716 has, for example, 8 bits for each of RGB for each pixel, and they are transmitted in parallel as 24 bits of parallel data using 24 transmission lines, or after the parallel-to-parallel conversion, 24 It is transmitted at twice the transmission rate.

  As shown in FIG. 8, the X shift register 704 reads the horizontal synchronization signal 714 generated by the liquid crystal controller 703 in synchronization with the X clock signal 715, and latches the signal X1 latch ( FIG. 8 (c)) is generated. With this signal, data displayed on the pixel in the first row and first column is latched in the first column of the latch 705. Subsequently, the liquid crystal controller 703 reads out and outputs data to be displayed on the next pixel from the video memory 702. The X shift register 704 of the X driver 713 shifts the horizontal synchronization signal 714 by one and generates a signal X2 latch (FIG. 8D) for latching the image data in the second column, thereby generating 1 row × 2 columns. Latch eye image data.

  Thereafter, the X shift register 704 sequentially shifts the horizontal synchronizing signal 714 and sequentially latches data to be displayed on the first row. In such an operation, when the display data signal 716 is sent as parallel data for each pixel through a plurality of transmission lines, the display data is read into the latch 705 in parallel every X clock, and serial When it is sent as data, it will not be necessary to explain that it is read into the latch 705 in parallel after the serial-to-parallel conversion.

  When the latch 705 finishes storing the data for one row, the next horizontal synchronizing signal 714 (FIGS. 8A and 8H, FIG. 8A to FIG. 8F and FIG. 8G to FIG. Note that the time scale of the horizontal axis is changed at (), so that the horizontal sync signal 714, which is the same signal, is re-displayed in (h) in addition to (a), and the DA converter 706 is output. D / A converts the data held in the latch 705 and outputs it to the Xi th (1 ≦ i ≦ m) of the column electrode 710. At the same time, the Y driver 707 outputs a selection signal to the first row electrode Y1.

Similarly, the Y driver 707 sequentially shifts the selection signal to the Yj-th (1 ≦ j ≦ n) of the row electrode 709 every time the horizontal synchronization signal 714 is output.
7 is an enlarged view of one pixel portion of the liquid crystal display 708 arranged in a matrix. When the Yj-th row electrode 709 is selected, the active switch element 711 transmits the output of the DA converter 706 output to the Xi-th column electrode 710 to the pixel electrode 712. Note that one DA converter 706 can be placed on the liquid crystal controller side and data 716 can be transmitted as an analog signal. In this case, the latch 705 is an analog sample and hold circuit. This method can reduce the number of DA converters and has been used in the past. However, even if it is a DA converter, the voltage value finally applied to the pixel electrode 712 may be a predetermined value. Since digital circuits such as pulse width modulation can be used and an analog sample-and-hold circuit is not required, the method described here has become mainstream as the density of LSIs increases.

However, in this method, since data is sent as a digital signal, the number of signal lines is very large, and for example, a total of 24 bits of 8 bits × 3 primary colors are required. Further, the amount of image data necessary for displaying one frame is multiplied by this resolution (number of pixels).
Note that after the display signal at the right end of the row is output from the liquid crystal controller 703, the time until the display signal at the left end of the next row is output, or after the image data of the bottom row on the screen has been output, The time until image data of the first row of the frame is output is called a (horizontal, vertical) blanking period or blanking period, and cannot be set to 0 in the CRT, but may be 0 in the liquid crystal display. FIG. 8 illustrates a case where a horizontal blanking period for one pixel and a vertical blanking period for one row are taken.

  With the recent increase in display size and resolution, the image data to be transferred from the liquid crystal controller 703 exceeds gigabit per second. For example, if a high-definition class screen with a resolution of 1920 × 1080 pixels is displayed for 60 frames per second, a data transfer rate of 1920 × 1080 × 24 × 60≈2.986 Gbps (bits per second) is required. .

  In addition, the displayed data often includes various functions in the main body 719 with the era of multimedia, and it is desirable that the liquid crystal display body 708 and the main body 719 can be separated into a removable state. Due to such a demand, the mounting substrate is separated into a plurality of cases, and in that case, the mounting substrates are often separated by the one-dot chain lines 717-717 in FIG. Inevitably, the connection between the main body 719 and the liquid crystal display body 708 becomes long.

  Further, as the resolution of the liquid crystal display body 708 is increased, the signal frequencies of those lines are increased, making connection difficult. In addition, the display screen itself becomes large. For example, it is practically impossible to distribute data exceeding gigabit per second to a liquid crystal driver (especially the X driver 713) arranged around the screen exceeding 100 inches. A method of reducing the transmission speed of each line by providing a large number of lines in parallel is adopted. However, in the high-definition class, the number of tracks becomes very large, exceeding 100.

  In order to solve this problem, as a high-speed data transmission system, for example, LVDS (Low Voltage Differential Signaling) is used for connection of a display driver (Patent Document 1 and Patent Document 2). In Patent Document 3 and Patent Document 4 and the like, a new method is also proposed because sufficient resolution cannot be obtained even with this method.

Japanese Patent No. 3086456 (column 44) Japanese Patent No. 3330359 (column 46) Japanese Patent No. 3349426 Japanese Patent No. 3349490

However, recent progress in the enlargement of display bodies is remarkable, and sufficient performance cannot be obtained even with these technologies. In order to obtain sufficient anti-noise characteristics (interference resistance and coherence), careful design and adjustment are required. Further, in LVDS, since the signal level is small, an analog signal is inevitably handled by a digital IC, and there is a problem that power consumption increases.
In addition, in order to transmit a signal with high accuracy, matched impedance termination is required. However, since the number of lines that need impedance termination is large and the transmission impedance is about 100 ohms at most, the termination resistance is not limited. There was also a problem that the power consumed was unacceptably large.

  Furthermore, when the mounting substrate is divided by the one-dot chain line 717-717 'in FIG. 7, it is necessary to transmit a large amount of data at high speed through a line routed by a long wiring. For this reason, the radiation electromagnetic field from a track | line increases, and becomes a factor of the electromagnetic wave interference to another electronic device or an own apparatus. In the conventional signal transmission through the signal line, the amplitude level at the power receiving end is defined, and even if sufficient quality is ensured at the power receiving end, the amplitude level of the signal cannot be lowered. In other words, EMI countermeasures become difficult, resulting in restrictions on equipment design and cost increase. On the transmission side, in addition to the load at the power receiving end, the stray capacitance of the line is simultaneously driven, so that extra energy is required for signal transmission. That is, the result is an increase in power consumption.

Further, the increase in the number of wirings accompanying the increase in the transfer data requires a physical space for wiring, which naturally imposes great restrictions on the device design.
In particular, when the wiring passes through a movable part such as a hinge part, the characteristic impedance changes depending on the bending state of the movable part. Therefore, impedance mismatch occurs depending on the situation, and signal degradation is caused by reflection at the bent part. For this reason, there are problems that the speed of data to be transmitted is limited and that the mounting method and the arrangement of parts are restricted. Further, since the number of signals to be exchanged exceeds 100, there is a disadvantage that the cost of the flexible substrate and connector for performing this connection is high and the connection reliability is low.

  Therefore, the present invention improves the method of high-speed transmission of data having various problems and restrictions as described above by a completely new method that has not existed in the past, eliminates these conventional defects and restrictions, and is reliable at low cost. An object is to realize a display device with high performance.

  The display device according to the present invention includes display means for displaying display data, dividing means for dividing the display data displayed on the display means to generate a plurality of N (N is an integer of 2 or more) serial signals, Multiplication means for multiplying each serial signal by a different code, synthesis means for synthesizing the output signal of the multiplication means to synthesize a serial signal of less than N, and calculating the correlation between the output signal of the synthesis means and the code By doing so, it is provided with a restoring means for restoring the display data, and a driving means for driving the display means based on the signal restored by the restoring means.

With this configuration of the present invention, the display data transmitted to the display means is code-division multiplexed and transmitted, so that the bandwidth required for the line can be reduced, transmission can be easily realized, and the number of transmission lines is small. And the restriction on the frequency band required for each transmission path can be relaxed.
The display means of the display device according to the present invention has pixels arranged in a matrix and is displayed by line sequential scanning.

According to the configuration of the present invention, it can be implemented in a large-sized and large-capacity display device such as a flat-screen television or a notebook computer.
The dividing means of the display device according to the present invention is characterized in that pixel data of each pixel is divided for each bit and serially output for each pixel.
According to the above configuration of the present invention, it is possible to transmit pixel data that has been conventionally output and transmitted in parallel, or parallel-to-parallel and transmitted as high-speed serial data by code-division multiplexing for each pixel, and there is little Transmission according to the number of transmission lines is possible, the transfer rate for each bit can be lowered, and the conditions required for the transmission lines can be relaxed.

The display device according to the present invention is characterized in that the dividing means divides the column of the display means into N sets and serially outputs pixel signals for each set.
According to the above configuration of the present invention, pixel data that has been transmitted as high-speed serial data in the past can be transmitted by code division multiplexing, can be transmitted with a small number of transmission lines, and the transfer rate for each bit can be reduced. This can alleviate the conditions required for the transmission line.

  A display device according to the present invention divides display data having pixels arranged in a matrix and display data displayed on the display unit into a plurality of N (N is an integer of 2 or more) sets of serial signals. Dividing means to generate, multiplication means for multiplying each of the serial signals by different codes, combining means for combining the output signals of the multiplying means and combining them into serial signals less than N, and output signals of the combining means By calculating the correlation between the display and the code, the storage means for restoring the display data, the storage means for temporarily storing the output signal of the restoration means, and the display based on the signal stored by the storage means Drive means for driving the means for each column.

According to the above configuration of the present invention, the display information can be temporarily stored on the display data receiving side. Therefore, if there is no change in the display data already sent, the display data stored in the storage means is stored. Therefore, the display data can be stopped and the power consumption of the circuit can be reduced.
The display device according to the present invention is characterized in that the dividing means outputs display data only to a set that needs to be rewritten.

According to the above-described configuration of the present invention, the pixel data transmitted to the display means can be performed only on a portion that needs to be rewritten. Therefore, even if the display image is stationary every frame, the image data is always displayed. Compared with the conventional method of transferring and updating data, the power consumption can be significantly reduced.
The display device according to the present invention includes a first spreading code generating circuit for generating a code supplied to the multiplying means, and a second code for generating the same code as the code supplied to the restoring means and supplied to the multiplying means. A spread code generating circuit, wherein the first spread code generating circuit and the second spread code generating circuit are synchronized by the same clock signal.

According to the above configuration of the present invention, it is possible to directly acquire a signal for synchronization of spreading code generation on the receiving side from the transmitting side. This eliminates the need for a special circuit for synchronizing the spread code generation on the receiving side, and simplifies synchronization acquisition.
The display device according to the present invention includes display means having pixels arranged in a matrix and driven by line sequential scanning, display data generating means for generating display data for each scanning line of the display means, and the display The display data is different between the driving means divided into N (N is an integer of 2 or more) groups for distributing the display data generated by the data generating means to the predetermined pixels as drive data, and adjacent scanning lines. The display data generating means to the driving means only for a set including one or more pixels on which display data different from the display data displayed on the latest scanning line is displayed. Display data is transmitted to

  According to the above configuration of the present invention, if there is no difference in display data between the image displayed by the scanning line immediately above displayed on the display device and the scanning line to be displayed this time, transmission of the display data is stopped. The operation of the transmission line and the circuit for driving the display body can be stopped, and the power consumption of the device can be significantly reduced. In particular, the correlation of display data between scan lines is strong, and a structure in which one scan line is separated into several sets has a significant effect compared to control for each frame.

In the display device according to the present invention, a code for code multiplexing is assigned to each set of the driving means, and transmission of display data from the display data generating means to the driving means is performed by the code. It is characterized by designating which set of means is sent.
According to the above configuration of the present invention, addressing for display data distribution is performed by codes, so that it can be realized with a simple circuit, and the transmission rate can be reduced. Even against it, it can be more resistant. The frequency component of the transmitted signal is spread, and there is a great effect on EMI countermeasures.

The display device according to the present invention is characterized in that the code is an orthogonal code.
According to the above configuration of the present invention, since the code used for code division multiplexing is an orthogonal code, the correlation between the codes can be made completely zero, and each data can be completely separated and restored from the multiplexed image signal. it can.

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a main part of an embodiment of a display device according to the present invention. FIG. 1 illustrates a typical block diagram of a display device using an active matrix liquid crystal display as a display element.
As shown in FIG. 1, the CPU 101 generates image data to be displayed in accordance with an instruction from the main body 131 and writes it in the video memory 102. Here, the main body 131 means a main body including an input / output device of a computer such as a main circuit including a tuner and a demodulator in a television and a DVD player reproducing unit. The CPU 101 receives the signal from the main unit 131, generates the image signal, image data to be displayed by decompression or calculation from a compressed image or moving image data such as JPEG or MPEG, and stores it in the video memory 102, and stores it as necessary. To rewrite and update sequentially.

  The liquid crystal controller 103 generates various timings necessary for liquid crystal display, that is, the X clock signal 115, the horizontal synchronizing signal 114, and the vertical synchronizing signal 118 of the X driver 113, and the display data in the order to be displayed from the video memory 102. Is read. At this time, the display data is read from the video memory 102 as bit-parallel serial data for each pixel and output as a display data signal 116.

Here, multiplication circuits 119-1, 119-2,..., 119 -N corresponding to the respective bits of the display data are provided on the main body 131 side, and the multiplication circuits 119-1, 119-2 are provided. ,..., 119 -N are supplied with spreading codes C _k (k = 1, 2,..., N), respectively. Each bit of the display data signal 116 is multiplied by the spread code C _k (k = 1, 2,... N) and the multiplication circuits 119-1, 119-2,. Then, analog addition is performed by the adder circuit 120 and sent to the liquid crystal display 108 side as a multiplexed signal 122.

Here, on the liquid crystal display 108 side, correlation circuits 121-1, 121-2,..., 121-N corresponding to the respective bits of the display data are provided, and the correlation circuits 121-1, 121-N are provided. 2,..., 121-N are supplied with spreading codes C _k (k = 1, 2,..., N), respectively. On the liquid crystal display 108 side, the correlation of the same spread code C _k (k = 1, 2,..., N) as the spread code multiplied by the multiplexed signal 122 on the transmission side is correlated with the correlation circuits 121-1, 121. -2,..., 121-N, respectively, restored to bit-parallel serial data for each pixel and sent to the latch 105. The restoration of the multiplexed signal 122 can also be realized by a method using a matched filter. When the matched filter is used, the synchronization procedure with the spreading code can be simplified.

  The X driver 113 includes an m-stage X shift register 104, an m word latch 105, and m DA converters 106 when the pixels of the liquid crystal display 108 are configured by n rows and m columns. The m-stage X shift register 104, m-word latch 105 and m DA converters 106 are usually divided into a plurality of sets, integrated on a semiconductor integrated circuit, and arranged around the liquid crystal display 108.

  When the liquid crystal controller 103 reads the first pixel of the display frame, it generates a vertical synchronization signal 118 and sends it to the Y driver 107. At the same time, the data to be displayed on the pixel in the first row and the first column is restored as parallel data for each pixel by the correlation circuits 121-1, 121-2,. Thereafter, every time the X clock signal 115 is input, the read clock of the latch 105 generated by the X shift register 104 is shifted in the column direction and latched.

  Conventionally, the display data signal 116 is 8 bits for each RGB, for example, for each pixel, and they are transmitted in parallel as 24 bits of parallel data using 24 transmission lines, or 24 times after parallel conversion. However, according to the embodiment of FIG. 1, since this signal is code-multiplexed as the multiplexed signal 122, only one transmission path is required. Of course, in this example, all 24 bits of the display data signal 116 are multiplexed into one. However, for example, the display data signal 116 may be multiplexed every 8 bits and transmitted through three transmission lines. Even in such a case, the number of signal transmission paths can be greatly reduced. Further, the transmission rate per bit line of the display data signal 116 is the same as that of the conventional case where 24 signal lines are drawn, and is not 24 times higher than the multiplexing by the parallel conversion. Please be careful.

FIG. 2 shows multiplexing of display data signals of the display device according to the present invention and its restoration, that is, multiplication circuits 119-1, 119-2,..., 119-N, addition circuit 120 and correlation circuit 121-1 in FIG. , 121-2,..., 121 -N is a diagram illustrating an example of the portion in more detail.
In FIG. 2, the display data signal 116 read by the liquid crystal controller 103 in FIG. 1 is bit-parallelized for each pixel and is output to the terminal 209. Each bit of the display data is a spreading code C _k (k = 1, 2,...) Generated by the spreading code generation circuit 201 by the multiplication circuits 202-1, 202-2,. N), is added in an analog manner by the adder circuit 203, and is sent to the liquid crystal display 108 side of FIG. If the inputs of the multiplication circuits 202-1, 202-2,..., 202-N are digital binary and the spreading code C _k is also binary, the multiplication circuits 202-1, 202-2,. .., 202-N can be constituted by an exclusive OR circuit. Since the output of the adder circuit 203 is multivalued, analog addition is necessary. In the adder circuit 203, the output logic 1 of the multiplier circuits 202-1, 202-2,...

The multiplexed signal 214 transmitted to the liquid crystal display 108 side is the same spreading code C _k (k = 1, 2,..., N) as the spreading code used on the transmission side generated by the spreading code generation circuit 204. Are multiplied by multiplication circuits 206-1, 206-2, and 206-N. These multiplication signals are integrated over one symbol section by integrating circuits 207-1, 207-2, and 207-N, respectively, and bit 1 or 0 is set by determination circuits 208-1, 208-2, and 208-N, respectively. It is determined, output as display data 210, and sent to the latch 105 of FIG.

Since one input of the multiplying circuits 206-1, 206-2, and 206-N is a multilevel signal, the exclusive OR circuit can no longer be used, and an analog multiplying circuit such as a balanced modulation circuit is used. In this part, all processes after AD conversion can be digitized, which will be described later.
In this embodiment, the spread code C _k used on the transmission side cannot be correctly restored on the reception side unless the same spread code C _k is used in synchronization on the reception side. In conventional multiplex communication using spreading codes, a special circuit for synchronizing spreading code generation is required on the receiving side. However, when the transmitting and receiving ends are at a close distance as in this embodiment, synchronization is required. The signal may be obtained directly from the transmission side. In this embodiment, the same chip clock 211 is used, and the spread code generation circuits 201 and 204 are reset by the horizontal synchronization signal 213 to achieve synchronization. By taking such a configuration, synchronization acquisition can be significantly simplified. The frequency dividing circuit 205 divides the chip clock 211 to generate a signal for each symbol period, and integrates circuit 207-1, 207-2, 207-N and determination circuit 208-1, 208-2, 208-N. To reset. The chip clock 211 is a clock signal having a cycle corresponding to one chip of a spread code, and the frequency of the normal chip clock 211 is increased. Therefore, without sending the chip clock 211, for example, the horizontal synchronizing signal 213 is multiplied on the liquid crystal display 108 side in FIG. 1 and reproduced by means such as PLL, or a clock for each pixel such as the X clock signal 115 is obtained. A signal may be sent, multiplied at the receiving side, and reproduced.

  2 is a boundary separating the main body 131 side and the liquid crystal display 108 side, and the transmission line passing through this boundary requires a physical length, and good transmission characteristics are required. If the number is large, implementation becomes difficult. In this embodiment, there are four lines that are transmitted through this boundary, ie, the multiplexed signal 214, the chip clock signal 211, the horizontal synchronizing signal 213, and the vertical synchronizing signal 216, and each line does not require a wide band. . Therefore, the difficulty in implementation is eliminated, and it can be easily realized at a low cost.

FIG. 3 is a time chart for briefly explaining the operation of the present invention. FIG. 4A illustrates the multiplexing process on the transmission side, and FIG. 4B illustrates the restoration process on the reception side. Here, for the sake of simplicity, the multiplex number is described as 3, but in practice, the spreading code length is made longer and the multiplex number is made much larger. In the figure, t _b is a symbol period in which one symbol is transmitted, t _c is a chip period, and t _b / t _c is called a spreading factor (SF). 1 / t _c is the chip frequency.

In FIG. 3A, b ₁ , b ₂ , and b ₃ are display data read from the video memory 102 by the liquid crystal controller 103. C ₁ , C ₂ , and C ₃ are spreading codes generated by the spreading code generation circuit 201, and b ₁ , b ₂ , and b ₃ are multiplied by multiplication circuits 202-1, 201-2, and 202 -N, respectively, and b ₁ C ₁ , b ₂ C ₂ , b ₃ C ₃ are generated. Here, C ₁ , C ₂ , C ₃ and b ₁ , b ₂ , b ₃ are shown as logic binary signals with logic 1 and 0. Further, b ₁ C ₁ , b ₂ C ₂ , and b ₃ C ₃ are the results of multiplication by associating −1 when logic 1 and 1 when logic 0. It may be considered that an exclusive OR of b _k and C _k is taken, and that the analog value −1 is associated when the output is logic 1, and the analog value 1 is associated when the output is logic 0. b ₁ C ₁ , b ₂ C ₂ , and b ₃ C ₃ are added in an analog manner by the adder circuit 203 to output a multiplexed signal S. That is, S = b ₁ C ₁ + b ₂ C ₂ + b ₃ C ₃ , and this signal is transmitted to the liquid crystal display 108 side as a multiplexed signal 214.

On the liquid crystal display 108 side, as shown in FIG. 3B, the multiplexed signals S ₁ , C ₂ , and C ₃ are multiplied to the multiplexed signal S by multiplication circuits 206-1, 206-2, and 206 -N. Are respectively multiplied to generate SC ₁ , SC ₂ , SC _3, and are integrated over time t _b by integrating circuits 207-1, 207-2, 207-N, respectively. Each integration result is also shown in FIG. Decision circuit 208-1,208-2,208-N by determining logical 1 if the logical 0, V _t or less if the integration result is the threshold level V _t above, can restore the original display data signal 116. In this figure, the integration result is ± 4 because it is a schematic in an environment with no noise at all. However, in the environment where the orthogonality of the spreading code is bad or noisy, it is clear as above. so it can not discriminate, do the discrimination and appropriately determine the V _t.

Meanwhile, the signal 1 bit multiplexed is transmitted in time of one symbol interval t _b by the spread code. This is the same speed as transmission per signal line when display data is transmitted in parallel using a plurality of conventional transmission lines. In the case of a 1920 × 1080 pixel display used in the description of the conventional example, for example, a case where a total of 24 bits of RGB are transmitted by a total of 24 bits for 60 frames per second is taken.
Although it is transmitted at a speed of 1920 × 1080 × 60≈124.4 Mbps, it is actually spread by SF times for multiplexing.
In order to multiplex and send 24 bits and completely separate them on the receiving side, at least 24 SFs are required. In consideration of this, the chip rate of the diffusion is the above-mentioned SF times, that is, about 3 Gcps which is the same value as the conventional one, and it may seem that there is no effect.

  However, compared to the case where everything is transmitted as serial data as in the prior art, in this embodiment, the bandwidth required for the transmission path may be narrow and the design is easy. That is, in the conventional example, the display data signal covers a very wide frequency band from DC in the case of full screen black or white to the highest frequency in the case of a checkered pattern for each dot (about 1.5 GHz in the above example). While uniform transmission characteristics are required, in the case of the present embodiment, most of the energy required for transmission is concentrated in a band about the symbol frequency up and down centering on the chip frequency. Therefore, a large specific bandwidth is not required for the transmission line. This remarkably relaxes the characteristics required for the transmission line and facilitates the realization. In the conventional example, since one bit is transmitted within one period of about 3 GHz, it is easy to receive interference between symbols. Further, in the conventional example, the resistance to reflection due to bending or mismatch of the transmission path is weak.

  On the other hand, in this embodiment, since the time for sending 1 bit is longer than that of the conventional example by SF compared to the conventional example, the intersymbol interference is remarkably mitigated even if there is a disturbance due to the same amount of reflection as the conventional example. The Further, as a characteristic of code multiplexing, such distortion due to multipath can be removed by a RAKE method or the like.

As described above, even if the chip rate of the code in the transmission line is the same as the transfer clock frequency in the case of conventional all serial transmission, the specifications required for the transmission line are remarkably relaxed and easy to implement. It becomes.
Furthermore, in the conventional example, when the display content to be displayed is a specific pattern, the display data signal 716 may have a very strong spectrum at a specific frequency. This is very disadvantageous from the viewpoint of unnecessary radiation generated from equipment, that is, EMI regulation. However, according to the present embodiment, the display data signal 116 is always spread by a spread code, and therefore, a strong spectrum at a specific frequency. There is also an effect that it is very advantageous in terms of EMI countermeasures. Also, for example, if the number of multiplexed signal lines is 3 and each of R, G, and B is multiplexed by 8 bits, 24 display data signal lines can be reduced to 3, and the chip frequency of each line is not much. It may be more realistic without being expensive.

  FIG. 4 is a diagram showing a main part of another embodiment according to the present invention, and shows another method for restoring the original display data signal 116 from the multiplexed signal 122 in the first embodiment. In FIG. 4, a multiplexed signal 122 input to a terminal 301 is AD converted by an AD converter 302 and converted into a digital signal. The spread code generation circuit 304 receives the chip clock input to the terminal 306 and generates the same spread code as that on the transmission side. The CPU 303 calculates the correlation between the multiplexed signal 122 converted into a digital signal by the AD converter 302 and the spreading code generated by the spreading code generation circuit 304, restores the display data signal 116 from the multiplexed signal 122, and supplies it to the terminal 308. Output. The CPU and the spread code generation circuit 304 are synchronized by a horizontal synchronization signal 309. Further, the frequency dividing circuit 305 divides the chip clock signal into 1 / SF to generate the clock signal 305 (X clock signal) of the X shift register.

  By adopting such a configuration, an analog circuit can be minimized and mounting on an integrated circuit is facilitated. The AD conversion circuit 302 needs only to have a resolution of 5 bits at most even if it is 24 multiplexed, and is easy to implement.

FIG. 5 is a block diagram showing a main part of still another embodiment of the display device according to the present invention. Note that the functions of the blocks assigned the same numbers as in FIG.
In FIG. 5, the X driver 513 is divided into N groups, and each of them is an X shift register 543-1,... 543-N, a latch 544-1, ... 544-N, and a DA converter 545-1. ,... 545-N. Usually, the X driver 513 and the Y driver 107 are divided into a plurality of parts, housed in an integrated circuit, and used in cascade connection. The grouping into N groups may be considered as a unit of this driver integrated circuit, or a plurality of groups may exist in one driver integrated circuit. Conversely, one set can be constituted by a plurality of integrated circuits. Each pair of X drivers 513 includes a correlation circuit 541-1,..., 541-N and a spread code generation circuit 542-1,. Each set of the X driver 513 is assigned a unique spreading code set S _p = [C _pk ] (p = 1, 2,..., N), and the spreading code generation circuit 542-is assigned. 1,... 542-N generate this allocated spreading code set. That is, the code generation circuit 542-p of the p-th set generates a respective code of the code set S _p. The correlation between each set of spreading code sets is designed to be small. It goes without saying that the correlation between codes in the code set is designed to be small. In both cases, it is ideal to use a completely zero correlation, that is, an orthogonal code system.

For the sake of explanation, the display data of the q-th column (q = 1, 2,..., N / N) of the p-th group (p = 1, 2,..., N) is represented by D _pq . D _pq has information about color and gradation, that is, it is composed of a plurality of bits such as 8 bits for each of RGB. _Let the kth bit of each D _{pq be} b _k .
.., 542 -N on the X driver 513 side generate only the code set assigned to the set, whereas the transmission side spread code generation circuit 501 generates the code as needed. Generate all spreading code sets used. The liquid crystal controller 103 reads display data to be displayed from the video memory 102 and outputs it to the multiplexing circuit 503. Multiplex circuit 503 selects a spread code set based on which set of X drivers 513 drives a pixel on which the display data is displayed, and multiplexes display data signal 116 with the spread code set. Multiple signals 122 are generated. That is, the display data signal 116 sent to the X driver 513 of p-th set are multiplexed by code set S _P. In each set of the signal receiving side, that is, the X driver 513, only the spreading code of its own set is generated as the spreading code, and the display data signal 116 sent to the other set cannot be restored. Determined correctly. In displaying an image, the correlation between scanning lines and frames is large, and it is often unnecessary to update the display data signal 116 transmitted last time. The liquid crystal controller 103 compares the display data on the previous scanning line with the display data to be sent this time, and sends the display data only to a group having a different portion of the display data. On the liquid crystal display 108 side, it is determined that the group in which the correlation circuits 541-1,..., 541-N cannot detect the display data signal 116 need not be changed to the display data signal 116. , 543-N, latches 544-1,... 544-N and DA converters 545-1,. The display data of the previous scanning line is continuously output without changing the output. In this way, the display data sending operation to the group that does not need to be updated can be stopped, so that the power consumption of the device can be greatly reduced.

  That is, by adopting the above configuration, the destination of the display data signal 116 is addressed by a spreading code for each group, so that the destination of the display data signal 116 can be specified by changing the spreading code. Become. For this reason, with this configuration according to the present embodiment, data transmission is stopped and power consumption can be reduced for a group in which the display data signal 116 does not need to be rewritten.

Further, as the number of sets of X drivers 513 (that is, N) is increased, the transmission / stop control of the display data signal 116 can be executed more finely, and the effect of power consumption is increased. When N is maximized, N = n (the number of pixels in the horizontal direction). However, if N is increased too much, there is a trade-off that the code length becomes longer and the amount of multiplexing / decompression increases.
Transmission order of the display data signal _{116, D 11, D 12, ···} , D 1N, D 21, D 22, ···, D 2N, as ..., each for each pixel from the left to the right Bits b _k (k = 1, 2,...) May be multiplexed, and each b ₁ of D ₁₁ , D ₂₁ ,..., D _N1 is multiplexed, and then each b ₂ is multiplexed. After the first pixel is completed after being multiplexed for each bit, the second pixel, that is, b ₁ of D ₂₂ , D ₂₂ ,... DN ₂ is multiplexed, and then b ₂ is multiplexed. You may do it. Since each set and each bit can be addressed by a spreading code, the transmission order can be arbitrarily changed. The former method has an advantage that the display data signal 116 read from the video memory 102 can be transmitted without rearrangement. However, since there is a non-signal period for a set that does not require data update, the bit transfer rate is high. high. In the latter method, the liquid crystal controller 103 has to read out the pixel data for each group, store them once, rearrange them for each bit, and output them, but the transfer rate per bit can be reduced.

6 is a diagram for explaining still another embodiment of the present invention. In FIG. 5, an X driver 513, correlation circuits 541-1,... 541-N, a spread code generation circuit 542-1,. , 542-N are replaced as shown in FIG. In FIG. 6, only one set is shown.
In this embodiment, in order to reduce the transfer of the display data signal 116 using the correlation between the frames of the display image, the frame memory 643 is placed on the liquid crystal display 108 side, and the display data is displayed when the display is stationary. The data stored in the frame memory 643 is used without transferring the signal 116.

In the following description, the X driver 513 and the like in FIG. 5 are replaced with the configuration in FIG.
In FIG. 5, when the contents of the video memory 102 are rewritten, the liquid crystal controller 103 multiplexes the multiplexed signal in the multiplexing circuit 503 using the spreading code set assigned to the group having the pixel for displaying the rewritten data. 122 is sent to the liquid crystal display 108 side (terminal 603 in FIG. 6).

  The liquid crystal controller 103 can detect that the video memory 102 has been rewritten by the CPU 101 by monitoring control of the video memory 102 from the CPU 101 (write pulse or address bus of the video memory 102). In addition, the CPU 101 can detect a portion that needs to be rewritten for each frame from the compression / decompression algorithm in MPEG decompression or the like.

The CPU 101 may directly notify the liquid crystal controller 103 of the rewritten portion detected in this way. In FIG. 5, a signal path for this purpose is omitted. Then, in synchronization with the vertical synchronizing signal 118 and the horizontal synchronizing signal 114 generated by the liquid crystal controller 103, only the display data signal 116 of the rewritten pixel is sent out.
Here, the display data signal 116 may be sent each time the video memory 102 is rewritten, but normally, the timing at which the rewriting of the CPU 101 to the video memory 102 requires display data on the liquid crystal display 108 side. Therefore, it is better to send the data immediately before the liquid crystal display 108 needs display data in synchronization with the horizontal synchronizing signal 114 and the vertical synchronizing signal 118.

  In addition, in order to address all pixels by addressing with a spreading code, a very long spreading code is required. For this reason, by sending data in synchronization with the synchronization signal, for example, the row address, the pixel address in the X direction within the set, etc. are calculated from the timing from the synchronization signal, thereby reducing the number of address bits to be specified. It is preferable to enable operation with a short spreading code.

  A correlation circuit 641 incorporated in each set of the X driver 513 on the liquid crystal display 108 side calculates a correlation with the spreading code set assigned to the set, restores the display data signal 116 sent to the set, and Store in memory 643. If such display data generated by the liquid crystal controller 103 is not sent, the previous data is stored without updating the display data used in the display of the previous frame stored in the frame memory 643. Yes.

  The controller 602 synchronizes the spread code generation circuit 642 and synchronizes with the chip clock 505 input to the terminal 606 and the horizontal synchronization signal 114 and the vertical synchronization signal 118 input to the terminals 604 and 605, respectively. And the latch 644 and the DA converter 645 are controlled in accordance with the operation of the liquid crystal display 108. That is, the latch 644 reads display data on the scanning line to be displayed next from the frame memory 643 and holds it in accordance with the timing output by the controller 602. When the next horizontal synchronizing signal 114 is input, the controller 602 activates the DA converter 645 to output and display the driving voltage on the liquid crystal display 108 according to the data held in the latch 644.

In the above embodiment, the method of using the frame memory 643 to hold the data displayed in the previous frame has been described. However, when the pixel itself has a holding function due to the capacitance of each pixel of the liquid crystal display 108 or the like. The frame memory 643 can be omitted.
According to the above-described configuration according to the present embodiment, various difficulties in transmission of display data including a very high frequency component and requiring high-speed data transfer can be reduced in the display device. Since signals can be multiplexed by spreading codes, the number of lines required for transmission can be reduced. In addition, the frequency band included in the display data can be narrowed to facilitate line design. Furthermore, even in the display of an image pattern in which a strong spectrum peak appears at the spatial frequency, the display data is frequency-spread by the spreading code, so that a strong spectrum peak does not appear at a specific frequency. This has a significant effect on EMI countermeasures. Furthermore, since the data can be addressed by the spread code, the data destination can be designated without any special addressing means. As a result, data transfer from the video memory 102 to the liquid crystal display 108 can be performed only when the display content changes, which has a significant effect on reducing the power consumption of the display device.

  The present invention has been described by taking a large-sized television display device as an example. However, the present invention is not limited to the above-described embodiment, and can be used in a wide range of applications such as connection with a display in electronic devices such as notebook computers and mobile phones. Applicable to.

The block diagram which shows the principal part of one Example of this invention. The block diagram which shows the multiplexing of one Example of this invention, and its decompression | restoration circuit part. The time chart which shows operation | movement of one Example of this invention. The block diagram explaining the restoration circuit part of the other Example of this invention in detail. The block diagram which shows the further another Example of this invention. The block diagram which shows the further another Example of this invention. FIG. 10 is a block diagram illustrating a display device having a conventional liquid crystal display body. The time chart explaining operation | movement of the display apparatus with the conventional liquid crystal display body.

Explanation of symbols

131 ... Main body, 101, 303 ... CPU, 102 ... Video memory, 103 ... Liquid crystal controller, 104, 543-1, 543-N ... X shift register, 105, 544-1, 5
44-N, 644 ... Latch, 106,545-1, 545-N, 645 ... DA converter, 1
07: Y driver, 108: Liquid crystal display, 109: Row electrode, 110: Column electrode, 113, 5
13... X driver, 119-1, 119-2, 119-N, 202-1, 202-2, 2
02-N, 206-1, 206-2, 206-N... Multiplier circuit, 120, 203... Adder circuit, 121-1, 121-2, 121-N, 541-1, 541-N, 641. ,
205, 305 ... frequency divider circuit, 207-1, 207-2, 207-N ... integrator circuit, 208-
1, 208-2, 208-N: determination circuit, 108, 708: liquid crystal display, 201, 204
, 304, 501, 542-1, 542 -N, 642... Spread code generation circuit, 203, 50
3 ... multiplexing circuit, 302 ... AD converter, 602 ... controller, 643 ... frame memory.

Claims (10)

Display means for displaying display data;
Dividing means for dividing display data displayed on the display means and generating a plurality of N (N is an integer of 2 or more) serial signals;
Multiplying means for multiplying each serial signal by a different code;
Synthesizing means for synthesizing the output signals of the multiplying means and synthesizing them into serial signals less than the N;
Restoring means for restoring the display data by calculating a correlation between the output signal of the combining means and the code;
A display device comprising: drive means for driving the display means based on the signal restored by the restoration means.   2. The display device according to claim 1, wherein the display means has pixels arranged in a matrix and is displayed by line sequential scanning.   3. The display device according to claim 1, wherein the dividing unit divides pixel data of each pixel into bits and outputs serially for each pixel.   3. The display device according to claim 1, wherein the dividing unit divides the column of the display unit into N groups and serially outputs a pixel signal for each group. Display means having pixels arranged in a matrix;
Dividing means for dividing the display data displayed on the display means into a plurality of N (N is an integer of 2 or more) sets and generating a serial signal;
Multiplying means for multiplying each serial signal by a different code;
Synthesizing means for synthesizing the output signals of the multiplying means and synthesizing them into serial signals less than the N;
Restoring means for restoring the display data by calculating a correlation between the output signal of the combining means and the code;
Storage means for temporarily storing an output signal of the restoration means;
A display device comprising: drive means for driving the display means for each column based on the signal stored by the storage means.   6. The display device according to claim 5, wherein the dividing unit outputs display data only to a set that needs to be rewritten. A first spreading code generating circuit for generating a code supplied to the multiplication means;
A second spreading code generating circuit for generating the same code as that supplied to the restoring means and supplied to the multiplying means;
7. The display device according to claim 1, wherein the first spreading code generation circuit and the second spreading code generation circuit are synchronized by the same clock signal. Display means having pixels arranged in a matrix and driven by line sequential scanning;
Display data generating means for generating display data for each scanning line of the display means;
Driving means that is divided into N (N is an integer of 2 or more) groups that distribute display data generated by the display data generating means to predetermined pixels as drive data;
Detecting means for detecting pixels having different display data between adjacent scanning lines,
Display data is sent from the display data generating means to the driving means only for a set including one or more pixels on which display data different from the display data displayed on the latest scanning line is displayed. Display device.   Each set of the driving means is assigned a code for code multiplexing, and the transmission of display data from the display data generating means to the driving means is sent to any set of the driving means by the code. 9. The display device according to claim 8, wherein the display device is designated.   The display device according to claim 1, wherein the code is an orthogonal code.

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