JP2008306576A - Decoding method and decoding apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accurately decode a reception signal even if a quadrature amplitude modulation (QAM) signal contains phase noise. <P>SOLUTION: A soft determination decoding apparatus uses the viterbi method for determining a metric for each digit respectively between a reception data stream connecting reception symbols in the order of reception and a binary signal stream determined for each transition path and for estimating a binary signal stream with a minimum cumulative metric among accumulated metrics as an encoded signal. The soft determination decoding apparatus comprises: a metric calculation circuit 52 for calculating a metric for each digit, respectively at a plurality of points preset on an IQ coordinate, between a reference symbol representing a transition path connecting states before and after the reception of the reception symbol and a reception symbol contained in the reception data stream and for determining a correction metric by multiplying the metric by a weight coefficient; an ACS circuit 54 for determining a cumulative metric by accumulating the correction metrics; and a correction table 26 for storing weight coefficients each having a positive correlation with a magnitude of phase noise in the reference symbol. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a decoding method and a decoding apparatus for accurately decoding a quadrature amplitude modulation (QAM (Quadrature Amplitude Modulation)) signal with reduced influence of phase noise.

  Quadrature amplitude modulation, that is, QAM is one of digital modulation methods, and amplitude modulation is performed on each of the carrier waves whose phases are orthogonal. As a result, data can be efficiently transferred with a limited bandwidth.

  By the way, in a communication system using QAM, phase noise may occur due to an influence of a residual carrier frequency error in a carrier frequency synchronization unit or frequency conversion in a transmitter and a receiver. When phase noise is present, a received signal to be given as a reference symbol on the IQ coordinate may deviate from the reference symbol.

In order to reduce the influence of the deviation of the received signal from the reference symbol, a technique for rearranging QAM signal points so as to reduce the influence of phase noise when transmitting a signal by QAM is disclosed (for example, Patent Document 1).
JP 2005-333545 A

  However, the technique disclosed in Patent Document 1 is a technique that is applied to the transmission side of QAM, and is not applied to the reception side. Therefore, the advent of a technique capable of reducing the influence of phase noise on the receiving side has been desired.

  The present invention has been made under such a technical background. Accordingly, an object of the present invention is to provide a decoding method and a decoding apparatus capable of removing an error due to noise from a received signal even if the QAM received signal includes phase noise.

  In order to achieve the above-described object, the decoding method of the present invention performs quadrature amplitude modulation on a transmission unit obtained by cutting out a convolutionally encoded signal from a higher-order bit side for every fixed number of digits, and transmits the signals in the order of extraction. The received transmission unit is received as a received symbol on the IQ coordinate, and is determined for each transition path between the received data string in which the received symbols are connected in order of reception from the upper bit side to the lower bit side. A metric for each digit is obtained from the binary signal sequence, and soft decision decoding is performed using the Viterbi method for estimating a binary signal sequence that minimizes the accumulated metric obtained by accumulating the metrics as the encoded signal. is there.

  In this decoding method, between a plurality of points set in advance on the IQ coordinate, each representing a transition path connecting states before and after reception of a received symbol, and a received symbol included in the received data string Then, the metric for each digit is calculated, the correction metric is calculated by multiplying the metric by a weight coefficient having a positive correlation with the magnitude of the phase noise in the reference symbol, and the accumulated metric is obtained as the accumulated correction metric.

  In this decoding method, the quadrature amplitude modulation is preferably 16QAM.

  In this decoding method, it is preferable that the weighting factor is set to 0.8, 1.0, and 1.2 according to the distance between the reference symbol and the origin of the IQ coordinate.

  The decoding device according to the present invention performs quadrature amplitude modulation on a transmission unit obtained by cutting out a convolutionally encoded signal from a higher-order bit side for every fixed number of digits, transmits the transmission unit in the order of extraction, and sets the transmitted transmission unit as an IQ coordinate. A digit is received between the received data string that is received as the upper received symbol and the received symbol is connected in order of reception from the upper bit side to the lower bit side, and the binary signal string determined for each transition path between states. Each metric is obtained, and soft decision decoding is performed using a Viterbi method in which a binary signal sequence having a minimum accumulated metric is estimated as an encoded signal.

  This decoding apparatus includes a plurality of points set in advance on IQ coordinates, each of which is between a reference symbol representing a transition path connecting states before and after reception of a received symbol and a received symbol included in the received data sequence. The metric calculation circuit that calculates the metric for each digit and multiplies the metric by the weighting factor to obtain the correction metric, the addition comparison selection circuit that accumulates the correction metric to obtain the accumulated metric, and the phase noise of the reference symbol And a correction table having a positive correlation with the magnitude and storing a weighting factor to be multiplied by the metric.

  The decoding apparatus and decoding method of the present invention are configured as described above. Therefore, the decoding apparatus and decoding method of the present invention can remove errors due to noise from the received signal even if the QAM received signal includes phase noise, for example.

  Embodiments of the present invention will be described below with reference to the drawings. Each drawing is merely a schematic representation of the shape, size, and arrangement relationship of each component to the extent that the present invention can be understood. Moreover, although the preferable structural example of this invention is demonstrated hereafter, the material of each component, a numerical condition, etc. are only a suitable example. Therefore, the present invention is not limited to the following embodiments. Moreover, in each figure, the same code | symbol is attached | subjected to a common component and the description may be abbreviate | omitted.

(Transmission / reception system)
First, a transmission / reception system to which the present invention is applied will be outlined with reference to FIG. FIG. 1 is a functional block diagram showing the configuration of the transmission / reception system.

  The transmission / reception system 10 includes a transmitter 12 and a receiver 14.

  The transmitter 12 includes an encoder 16 and a modulator 18. The encoder 16 convolutionally encodes the input original signal to generate an encoded signal. The modulator 18 performs quadrature amplitude modulation on the encoded signal and transmits it as a reference symbol on IQ coordinates.

  The receiver 14 includes a demodulator 20 and a Viterbi decoder 22. The demodulator 20 receives the signal transmitted from the transmitter 12 as a reception symbol that is one point on the IQ coordinate. The Viterbi decoder 22 performs soft decision decoding of the original signal based on the Viterbi method from the received received symbols.

  As will be described later, the present invention relates to a Viterbi decoder 22 and a decoding method in the Viterbi decoder 22.

(Explanation of basic matters)
First, in order to better understand the present invention, the following three items will be described among the basic matters related to the present invention.
(1) Encoder 16
(2) Modulator 18 and demodulator 20
(3) Viterbi decoding.

(1) Encoder 16
FIG. 2 is a schematic diagram showing the configuration of the conventional encoder 16.

  The encoder 16 performs convolutional coding on the input original signal (binary signal) and outputs a coded signal (binary signal).

  More specifically, the encoder 16 includes an encoder 24 and a parallel-serial converter 25 as shown in FIG. In FIG. 2, A1 and A2 are shift registers. P1 and P2 are adders. The encoder 24 receives the input signal I bit by bit. By inputting this input signal I, the parallel output signals V1 and V2 of 1 bit from the encoder 24 are aligned in the form of the serial output signal “V1V2” by the parallel-serial converter 25. Is output.

  The encoder 24 can take four states determined by values (0 or 1) held in the shift registers A1 and A2. Specifically, a “11” state with A1 = 1 and A2 = 1, a “01” state with A1 = 0 and A2 = 1, a “10” state with A1 = 1 and A2 = 0, and A1 = 0 and This is the “00” state with A2 = 0. Hereinafter, the “11” state is referred to as S11, the “01” state as S01, the “10” state as S10, and the “00” state as S00.

  The encoder 24 outputs the output signals V1 and V2 depending on the current state of the encoder 24 itself and the input signal I, and makes a transition between the states.

  FIG. 3 is a state transition diagram of the encoder 24 for explaining the state transition described above. An arrow connecting the four states is a path permitted by the encoder 24. Hereinafter, a path connecting a transition source state and a transition destination state in one transition is particularly referred to as a “branch”. Further, a movement path between states by a plurality of transitions, that is, a path obtained by combining a plurality of branches is referred to as a “transition path”.

  Further, symbols (for example, 0/11 etc.) attached to each of these arrows indicate an input signal I and output signals V1 and V2 corresponding to the branch. Specifically, the numerator of the symbol indicates the input signal I, and the denominator of the symbol indicates the output signals V1 and V2. That is, this symbol is written according to the rule (I / V1V2).

  For example, the symbol 1/11 attached to the branch (arrow) connecting S00 and S01 needs to input the input signal I = 1 to the encoder 24 in the transition from S00 to S01. In this case, output signals V1 = 1 and V2 = 1 are output.

  Here, it is assumed that an n-bit original signal is encoded by the encoder 24 to generate an encoded signal. Here, the “encoded signal” indicates a binary signal obtained by performing parallel-serial conversion after convolutional encoding of the original signal by the encoder 24.

  The original signal is cut out bit by bit from the upper bit side and input to the encoder 24 as the input signal I. The state of the encoder 24 changes according to both the input signal I and the state of the encoder 24 before the input signal I is input, and outputs the output signals V1 and V2 determined by the branch. As a result, the encoder 24 convolutionally encodes the n-bit original signal, and the encoded output signals V1 and V2 are parallel-serialized by the parallel-serial converter 25 to output a 2n-bit encoded signal. .

  Consider the encoded signal H obtained when “0110” is input as the original signal G to the encoder 24 and the initial state of the encoder 24 is S00.

  The encoded signal H can be obtained from the state transition diagram of FIG. That is, the signal “0” → “1” → “1” → “0” obtained by cutting out the original signal G one bit at a time from the high-order bit side is set as the input signal I, and the initial state is set to the encoder 24 with S00 Enter in order. Then, the encoded signal H may be obtained by serially connecting the output signals V1 and V2 obtained for each of the extracted input signals I. The encoded signal H obtained in this way is “00110111”.

  The process of obtaining the encoded signal H from the original signal G can also be expressed as a transition path of a trellis diagram.

  FIG. 4 is a diagram showing a trellis diagram. Here, the “trellis diagram” is a time series of branches connecting the states of the encoder 24 shown in the state transition diagram (FIG. 3).

  In FIG. 4, each arrow is a branch connecting the two states of the encoder 24. The symbol attached to each arrow represents (I / V1V2) as in FIG. A thick line indicates a transition path when the original signal G is “0110”.

  At time t = 0, the first bit signal “0” from the higher bit side of the original signal G “0110” is input to the encoder 24 as the input signal I. Then, the encoder 24 outputs “00” as the output signal V1V2, and transitions from the initial state S00 to S00.

  At time t = 1, “1” of the second bit from the upper bit side of the original signal G is input to the encoder 24 as the input signal I. Then, the encoder 24 outputs “11” as the output signal V1V2, and transits from S00 to S01.

  At time t = 2, the third bit “1” from the higher-order bit side of the original signal G is input to the encoder 24 as the input signal I. Then, the encoder 24 outputs “01” as the output signal V1V2, and transitions from S01 to S10.

  At time t = 3, the fourth bit “0” from the upper bit side of the original signal G is input to the encoder 24 as the input signal I. Then, the encoder 24 outputs “11” as the output signal V1V2, and transits from S10 to S00.

  The encoded signals H (“00110111”) are obtained by arranging the output signals V1 and V2 thus obtained in time series along t = 0 to 3.

(2) Modulator 18 and demodulator 20
Next, the modulator 18 and the demodulator 20 will be described with reference to FIGS. Note that the configurations of the modulator 18 and the demodulator 20 are well known in the art and will not be described. Therefore, in this section, transmission / reception of signals by QAM between the modulator 18 and the demodulator 20 will be mainly described.

  FIG. 5 is a schematic diagram showing reference symbols in 16QAM on IQ coordinates. FIG. 6 is a schematic diagram showing the state of deviation due to phase noise of received symbols in 16QAM on IQ coordinates.

  The modulator 18 performs quadrature amplitude modulation on the encoded signal output from the encoder 16 and transmits the modulated signal to the demodulator 20. Thus, the encoded signal is transmitted as one point (reference symbol) on the IQ coordinate (FIG. 5).

  Here, the outline of quadrature amplitude modulation (QAM) will be described. Quadrature amplitude modulation is one of digital modulation methods. QAM is a modulation method in which amplitude modulation is performed on carriers whose phases are orthogonal, and transmission is performed by combining these carriers.

  For example, in QAM, if four values are given according to the amplitude of the in-phase carrier wave and four values are given according to the amplitude of the quadrature carrier wave, a 4-bit (16 types) digital signal is sent in one transmission. Can do.

  A QAM that can send a 4-bit digital signal in one transmission is referred to as “16QAM”. In this embodiment, a case of 16QAM will be described in particular.

  FIG. 5 shows the arrangement of reference symbols on IQ coordinates in 16QAM together with digital signals corresponding to the respective reference symbols. In FIG. 5, the horizontal axis represents the amplitude of the in-phase component, and the vertical axis represents the amplitude of the quadrature component.

  The 16 reference symbols shown in FIG. 5 have preset positions on the IQ coordinates. In FIG. 5, for convenience, 16 reference symbols are shown at the same time. However, in actual transmission, only one point among these reference symbols is transmitted for each transmission.

  Here, transmission of the coded signal H (“00110111”) described above will be considered. In this case, the modulator 18 generates the transmission units U1 (“0011”) and U2 (“0111”) by cutting out the encoded signal H from the upper bit side every fixed number of digits (4 digits in the case of 16QAM). To do.

  Then, the modulator 18 performs quadrature amplitude modulation on each of the transmission units U1 and U2, and in the cutout order (U1 → U2), the reference symbol on the IQ coordinate (indicated by a double circle surrounded by a circle in FIG. 5). As a reference symbol).

  The transmission units U1 and U2 transmitted in this way are received by the demodulator 20 as reception symbols that are one point on the IQ coordinate. However, as already described, the received symbol is deviated from the reference symbol at the time of transmission due to phase noise generated in the process of transmission / reception in the transmission unit.

  FIG. 6 shows how the received symbols are shifted due to phase noise. Due to the occurrence of phase noise, each received symbol varies in the circumferential direction of the IQ coordinate. That is, the received symbol deviates from the reference symbol and is detected as one point within the curved thick line range shown in FIG. In general, the amount of deviation due to phase noise introduced into a received symbol and the distance from the origin of the IQ coordinate have a positive correlation.

  Here, it is assumed that the above-described transmission unit U1 (“0011”) is received as a reception symbol R1 (“0.2, 0.3, 0.7, 0.6”) on the IQ coordinate due to the influence of phase noise. Assume. Similarly, it is assumed that the transmission unit U2 (“0111”) is received as a reception symbol R2 (“0.8, 0.5, 0.6, 0.5”) on the IQ coordinate due to the influence of phase noise. (To be described later with reference to FIG. 8).

(3) Viterbi Decoding In this section, soft-decision Viterbi decoding performed by a general decoder will be described in order to help understand the Viterbi decoder 22 and the decoding method of the present invention.

  FIG. 7 is a functional block diagram showing a configuration of a general decoder. FIG. 8 is a trellis diagram for explaining the decoding process of general Viterbi decoding.

  Referring to FIG. 7, the decoder 50 includes a metric calculation circuit 52, an addition comparison selection circuit 54 (hereinafter also referred to as “ACS circuit 54”), a cumulative metric storage circuit 56, a transition path storage circuit 58, And a maximum likelihood decoding determination circuit 60.

  The decoder 50 can be configured using a CPU (Central Processing Unit). In that case, the metric calculation circuit 52, the ACS circuit 54, and the maximum likelihood decoding determination circuit 60 are obtained as functional means when the program is executed. Therefore, the metric calculation circuit 52 functions as a metric calculation unit. The ACS circuit 54 functions as cumulative metric calculation means, determination means for determining the magnitude of the cumulative metric, and transition path selection means for selecting the next transition path from the determination result. The maximum likelihood decoding determination circuit 60 functions as maximum likelihood determination means. Further, the cumulative metric storage circuit 56 and the transition path storage circuit 58 can be configured by a RAM (Random Access Memory).

  The decoder 50 obtains a signal (hereinafter referred to as “decoded signal”) that is considered to be closest to the original encoded signal H from the received data sequence including the received symbols R1 and R2 received by the demodulator 20. Obtained by soft decision decoding using the Viterbi method.

  Here, the “Viterbi method” is one of convolutional code decoding methods, and using a received received symbol, a binary signal sequence having the maximum likelihood of giving this received symbol is transmitted and encoded. The signal is estimated. Further, “soft decision decoding” refers to a decoding method for decoding an encoded signal using a multi-value data string (not a binary data string) as a received data string.

In other words, the Viterbi method, from the trellis diagram (FIG. 8) all transition paths possible in (which is 2 ⁿ present when the number of bits of the original signal G and n.), Received It can also be said to be a decoding method for obtaining a transition path (hereinafter referred to as “maximum likelihood path”) that gives a decoded signal that seems to be closest to the original encoded signal H by using the symbols R1 and R2.

  The received symbol input to the decoder 50 is output to the metric calculation circuit 52 as 2-bit data cut out by 2 bits from the upper bit side. Calculation formulas to be described later used in the metric calculation circuit 52 are stored in advance in a storage unit (not shown) so as to be readable, and the calculation results are also stored in the storage unit.

  The metric calculation circuit 52 receives the input 2-bit data (for example, “0.2, 0.3” which is the upper 2 bits of the reception symbol R1) and a binary signal sequence (“00”) that can be taken by the 2-bit data. ”,“ 01 ”,“ 10 ”, and“ 11 ”).

  Here, the metric is, for example, an absolute value of “difference for each digit” between input 2-bit data and a binary signal sequence that can be taken by the 2-bit data.

More specifically, in the metric M, 2-bit data is “ab” (where 0 ≦ a, b ≦ 1), and the binary signal string is “AB” (where A, B = 0 or 1). Is obtained by the following formula (1).
M = | A−a | + | B−b | (1)
That is, the smaller the value of the metric M, the higher the similarity between the 2-bit data “ab” and the binary signal sequence “AB”. That is, when the metrics of the 2-bit data “ab” and the binary signal sequence “AB” are minimum, it can be said that “ab” is most likely output from the branch that outputs “AB”.

  According to equation (1), the metric calculation circuit 52 processes the 2-bit data in the order of input to obtain a metric and outputs it to the ACS circuit 54.

  The cumulative metric calculation means of the ACS circuit 54 calculates a cumulative metric obtained by accumulating the metric M for every branch on the trellis diagram, and stores the cumulative metric in the cumulative metric storage circuit 56 in association with the transition path. And the transition path is stored in the transition path storage circuit 58.

  Here, the cumulative metric is the sum of the metrics M for each branch of the trellis diagram. In other words, the cumulative metric represents the similarity between an arbitrary binary signal sequence having the same number of bits as the received data sequence and the received data sequence. That is, the smaller the cumulative metric value is, the more similar the binary signal sequence and the received data sequence are.

  The ACS circuit 54 reads the accumulated metric (hereinafter referred to as “old accumulated metric”) obtained so far from the accumulated metric storage circuit 56. Then, the metric M newly input to the ACS circuit is added to the old cumulative metric to calculate a new cumulative metric.

  Further, the determination means of the ACS circuit 54 compares the new cumulative metric for each transition path in order to reduce the subsequent calculation amount. Furthermore, as a result of the comparison, the transition path selection unit excludes a transition path having a large new cumulative metric, that is, a transition path that gives a binary signal having a low similarity to the received data string, from the subsequent calculations.

  In other words, the ACS circuit 54 compares the new cumulative metrics of the two transition paths that enter an arbitrary state of the trellis diagram. Then, only the smaller one of the new cumulative metrics is adopted as the selected route, that is, the “surviving route”, and only the new cumulative metric related to the surviving route is stored in the cumulative metric storage circuit 56. The “surviving route” will be described in detail in a specific example described later. Further, the ACS circuit 54 stores the surviving path in the transition path storage circuit 58.

  When the processing of all the received data sequences is completed, the maximum likelihood determination means of the maximum likelihood decoding determination circuit 60 compares the cumulative metrics of the surviving paths stored in the transition path storage circuit 58, and determines the smallest among the surviving paths. The value of the received signal is estimated from the transition path that gives the cumulative metric, and the binary signal sequence output when passing through this maximum likelihood path is used as the decoded signal.

  Next, referring to FIG. 8, received symbols R1 (“0.2, 0.3, 0.7, 0.6”) and R2 (“0.8, 0.5, 0.6, 0. The soft decision decoding process by the general Viterbi decoder 50 will be described by taking the case of 5 ″) as an example.

  In FIG. 8, the numerical value with parentheses attached to each branch is a metric for each branch. Also, the circled numbers attached to each branch indicate the route number of the branch. Further, a symbol such as (0/00) attached to each arrow represents (I / V1V2) as in FIG.

  The reception symbol R1 received by the demodulator 20 is cut out by 2 bits from the upper bit side and input to the metric calculation circuit 52 in time series. That is, as shown by t = 1 in FIG. 8, the metric calculation circuit 52 has 2 bits that are the upper 2 bits of the received symbol R1 (“0.2, 0.3, 0.7, 0.6”). Data “0.2, 0.3” is input. That is, in this case, a = 0.2 and b = 0.3.

  The metric calculation means of the metric calculation circuit 52 to which the 2-bit data “0.2, 0.3” is input calculates the metric M for each branch. That is, a branch that transitions from the initial state S00 (t = 0) to S00 (t = 1) (hereinafter referred to as “first branch”), and the initial state S00 (t = 0) to S01 (t = 1). Metrics M1 and M2 in the branch that transitions to (hereinafter referred to as “second branch”) are respectively calculated.

  When it is assumed that a transition has occurred along the first branch (S00 → S00), the output signal V1V2 is “00”. That is, A = 0 and B = 0. Therefore, the metric M1 related to the first branch is | 0−0.2 | + | 0−0.3 | = 0.5 in accordance with the above-described equation (1). The metric M1 is stored in the cumulative metric storage circuit 56 via the ACS circuit 54. Further, the ACS circuit 54 stores the first branch in the transition path storage circuit 58.

  Similarly, when it is assumed that a transition has occurred along the second branch (S00 → S01), the output signal V1V2 is “11”. That is, A = 1 and B = 1. Accordingly, the metric M2 related to the second branch is | 1-0.2 | + | 1-0.3 | = 1.5 in the same manner. The metric M2 is stored in the cumulative metric storage circuit 56 via the ACS circuit 54. Further, the ACS circuit 54 stores the second branch in the transition path storage circuit 58.

  At t = 2, 2-bit data “0.7, 0.6” (that is, a = 0.7 and b = 0.6) which is the lower 2 bits of the received symbol R1 is input to the metric calculation circuit 52. The

Based on this signal, the metric calculation means of the metric calculation circuit 52 calculates a metric for each branch in the same manner as described above. That is, the metric calculation circuit 52 obtains the following four branch metrics M3 to M6.
(Third branch): S00 (t = 1) → S00 (t = 2)
(Fourth branch): S00 (t = 1) → S01 (t = 2)
(Fifth branch): S01 (t = 1) → S10 (t = 2)
(Sixth branch): S01 (t = 1) → S11 (t = 2)
Then, the following metrics M3 to M6 obtained using the equation (1) for each branch are input to the ACS circuit 54.
(3rd branch metric M3) = | 0−0.7 | + | 0−0.6 | = 1.3
(4th branch metric M4) = | 1-0.7 | + | 1-0.6 | = 0.7
(5th branch metric M5) = | 0−0.7 | + | 1−0.6 | = 1.1
(6th branch metric M6) = | 1−0.7 | + | 0−0.6 | = 0.9
Then, the cumulative metric calculation means of the ACS circuit 54 reads the first and second branches stored in the transition path storage circuit 58. Further, the cumulative metric calculation means of the ACS circuit 54 reads the cumulative metrics M1 and M2 corresponding to the read first and second branches from the cumulative metric storage circuit 56.

  Then, the ACS circuit 54 individually accumulates the metrics M3 and M4 of the third and fourth branches in the read cumulative metric M1 of the first branch. Similarly, the ACS circuit 54 individually accumulates the metrics M5 and M6 of the fifth and sixth branches in the read accumulated metric M2 of the second branch.

  After that, the ACS circuit 54 stores the individual transition paths from the first transition (t = 0) to the previous transition (t = 2) in the transition path storage circuit 58 and the transition paths associated with the individual transition paths. Each accumulated metric is stored in the accumulated metric storage circuit 56.

That is, at the stage where t = 2 is finished, the cumulative metric storage circuit 56 stores the following cumulative metrics.
(1) Cumulative metric of the first → third branch = Σ (1,3) = 0.5 + 1.3 = 1.8
(2) Cumulative metric of first → fourth branch = Σ (1,4) = 0.5 + 0.7 = 1.2
(3) Cumulative metric of 2nd → 5th branch = Σ (2,5) = 1.5 + 1.1 = 2.6
(4) Cumulative metric of 2nd → 6th branch = Σ (2,6) = 1.5 + 0.9 = 2.4
At t = 3, 2-bit data “0.8, 0.5” (ie, a) that is the upper 2 bits of the received symbol R2 (“0.8, 0.5, 0.6, 0.5”). = 0.8 and b = 0.5) are cut out and input to the metric calculation circuit 52. Then, the metrics M7 to M14 of the seventh to fourteenth branches are calculated and input to the ACS circuit 54 as described above.

  At t = 3, the survival route is selected by the determination unit and the transition route selection unit of the ACS circuit 54. That is, for example, when focusing on S00 at t = 3, it is possible to transition to S00 (t = 3) from both S00 (seventh branch) and S10 (11th branch) at t = 2. The ACS circuit 54 selects, as a surviving path, one of these branches (seventh and eleventh branches) having a smaller cumulative metric so far. Then, the transition path with the larger cumulative metric is excluded from the subsequent calculations (in FIG. 8, it is indicated with an X mark).

Specifically, the ACS circuit 54 calculates the cumulative metric shown below.
(Cumulative metric of 7th branch) = total of 1st → 3rd → 7th branch metric = Σ (1, 3, 7) = 0.5 + 1.3 + 1.3 = 3.1
(11th branch cumulative metric) = 2nd → 5th → 11th branch metric sum = Σ (2,5,11) = 1.5 + 1.1 + 0.7 = 3.3
From the result of this calculation, the determination means determines that Σ (1, 3, 7) <Σ (2, 5, 11), so the transition path selection means of the ACS circuit 54 selects the seventh branch with a small cumulative metric. This is selected as a surviving path and stored in the transition path storage circuit 58. Further, the transition path selection means of the ACS circuit 54 stores the accumulated metric Σ (1, 3, 7) in the accumulated metric storage circuit 56 in association with the elapsed transition path up to the seventh path.

  Similarly, the ACS circuit 54 can transition to the eighth and twelfth branches that may transition to S01 and the ninth and thirteenth branches that may transition to S10 and t11 at t = 3. Surviving paths are also obtained for the tenth and fourteenth branches. Then, the transition path storage circuit 58 stores the eighth, ninth, and tenth branches that are survival paths. At the same time, the cumulative metrics Σ (1, 3, 8), Σ (1, 4, 9) and Σ (1, 4, 10) are stored in the cumulative metric storage circuit 56 in association with the progress transition paths of these paths. .

  At t = 4, the same processing as t = 3 is performed. That is, the ACS circuit 54 calculates the metrics M15 to M22 of the 15th to 22nd branches in the same manner as described above. Then, the ACS circuit 54 reads the surviving paths (seventh to tenth branches) from the transition path storing circuit 58, and the accumulated metrics Σ (1, 3, 7), Σ (1, 3) corresponding to these surviving paths. , 8), Σ (1, 4, 9) and Σ (1, 4, 10) are read from the cumulative metric storage circuit 56. Then, each metric M15 to M22 of the 15th to 22nd branches is added to the accumulated metric of the read survival path.

  Further, in the same manner as described above, the ACS circuit 54 selects a survival path from the fifteenth to twenty-second branches in the same manner as described above. As a result, the selected 19th to 22nd branches are stored in the transition path storage circuit 58 as surviving paths. At the same time, the cumulative metric calculation circuit 56 stores the cumulative metric of the surviving path. In this case, the cumulative metrics of the surviving paths 1 to 4 are Σ (1,4,9,19), Σ (1,4,9,20), Σ (1,4,10,21) and Σ (1, 4, 10, 22).

  Finally, the maximum likelihood determination means of the maximum likelihood decoding determination circuit 60 reads the surviving paths from the transition path storage circuit 58 and reads the cumulative metrics corresponding to these surviving paths from the cumulative metric storage circuit 56. Then, these are compared with each other, the path with the smallest cumulative metric is set as the maximum likelihood path, and the demodulated signal is estimated.

That is, the maximum likelihood decoding determination circuit 60 reads the following four transition paths as survival paths.
(Surviving path 1): 1st → 4th → 9th → 19th branch (cumulative metric: 3.4)
(Surviving path 2): 1st → 4th → 9th → 20th branch (cumulative metric: 3.6)
(Surviving path 3): 1st → 4th → 10th → 21st branch (cumulative metric: 2.8)
(Surviving path 4): 1st → 4th → 10th → 22nd branch (cumulative metric: 3.0)
The maximum likelihood decoding determination circuit 60 compares the accumulated metrics of these surviving paths, selects the “surviving path 3” that is the smallest as the maximum likelihood path, and outputs it.

  By the way, the maximum likelihood path (surviving path 3) selected by the maximum likelihood decoding determination circuit 60 performs a transition from S00 → S00 → S01 → S11 → S10 on the trellis diagram. The series of output signals V1V2 obtained from this transition path, that is, the decoded signal is “00111010”. However, this decoded signal is different from the encoded signal H “00110111” transmitted by the transmitter 12.

  As described above, the reason why the encoded signal H and the decoded signal are different, that is, the reason why the encoded signal H is decoded erroneously is that the received symbols R1 and R2 are affected by phase noise and the like. Therefore, in the next section, it will be described that the decoder of the present invention can decode the encoded signal H with improved decoding accuracy even when there is phase noise.

(Viterbi decoder of the present invention)
Next, the Viterbi decoder and decoding method of the present invention will be described with reference to FIGS. FIG. 9 is a functional block diagram showing the configuration of the decoder of the present invention. In FIG. 9, the same components as those in FIG. 7 are denoted by the same reference numerals, and redundant description is omitted. FIG. 10 is a schematic diagram of IQ coordinates for explaining the weighting factors stored in the correction table.

  Referring to FIG. 9, the Viterbi decoder 22 is different from the decoder 50 in that it includes a correction table 26. Therefore, although not particularly illustrated, a storage unit is provided, and the correction table 26 is stored in a freely readable manner. Among the data generated by the processing in the Viterbi decoder 22, the cumulative metric storage circuit 56 and Data that is not stored in the transition path storage circuit 58 is temporarily stored in the storage unit in a readable manner.

  The correction table 26 stores a weighting coefficient W for correcting phase noise included in the received symbol. Specifically, when obtaining a metric between a received symbol and a reference symbol on IQ coordinates, a weighting factor W to be multiplied by the metric is stored in association with the reference symbol.

  More specifically, in the correction table 26, the weighting factor W is determined for every 16 reference symbols. This weight coefficient W is set so as to have a positive correlation with the magnitude of the phase noise (see FIG. 6) introduced into the reference symbol. According to experience, the influence of phase noise tends to increase as the distance from the origin of the IQ coordinate increases.

  Therefore, in this embodiment, as shown in FIG. 10, the weighting factor W is set to 0.8, 1.0, and 1.2 according to the magnitude of the influence of the phase noise in the reference symbol. ing. For the four reference symbols that are less affected by the phase noise, the weighting factor W is set to 0.8. For the eight reference symbols that are moderately affected by phase noise, the weighting factor W is set to 1.0. For the four reference symbols that are greatly affected by the phase noise, the weighting factor W is set to 1.2.

  Table 1 below shows the value of the weighting factor for each reference symbol.

  The specific values (0.8, 1.0, and 1.2) of the weighting factor W are subjected to decoding simulation for various encoded signals H by changing the weighting factor W in an environment where phase noise exists. Can be determined. That is, the weighting factor W is a value that increases the probability that the encoded signal H can be accurately decoded even if phase noise exists.

  Next, the operation of the Viterbi decoder 22, that is, the decoding method of the present invention will be described.

  The Viterbi decoder 22 is different from the general decoder 50 in that decoding is performed for each received symbol. More specifically, in the general decoder 50, as described above, 2-bit data obtained by cutting out received symbols by 2 bits from the upper side is used for decoding. However, the Viterbi decoder 22 of the present invention performs decoding using the 4-bit received symbols as they are in order to reduce the influence of phase noise.

  Hereinafter, the reception symbols R1 (“0.2, 0.3, 0.7, 0.6”) and R2 (“0.8, 0.5, 0.6, 0. The case of 5 ″) will be described as an example.

  The reception symbol R 1 received by the demodulator 20 is input to the metric calculation circuit 52. Then, the metric is calculated for each received symbol as described above. As is apparent from the trellis diagram (FIG. 8), it can be seen that there are only four transition paths to which the received symbol R1 can be attributed. Hereinafter, a transition path that may give a received symbol of 4 bits length on the trellis diagram, that is, a transition path composed of two consecutive branches is referred to as a “meta branch”.

  That is, in FIG. 8, at t = 0, the state located at S00 transitions to any of the states S00, S01, S10, and S11 at t = 2 when the output of the 4-bit transmission unit U1 ends. To do.

That is, between t = 0 and 2, only four meta branches listed below are possible (meta branch 1): S00 (t = 0) → S00 (t = 1) → S00 (t = 2) The transmission unit “0000” is output from this meta branch. This occupies [0000] reference symbols on IQ coordinates.
(Meta branch 2): Meta branch of S00 (t = 0) → S00 (t = 1) → S01 (t = 2), and the transmission unit “0011” is output from this meta branch. This occupies [0011] reference symbols on IQ coordinates.
(Meta branch 3): Meta branch of S00 (t = 0) → S01 (t = 1) → S10 (t = 2), and a transmission unit “1101” is output from this meta branch. This occupies a reference symbol of [1101] on the IQ coordinate.
(Meta branch 4): Meta branch of S00 (t = 0) → S01 (t = 1) → S11 (t = 2), and the transmission unit “1110” is output from this meta branch. This occupies [1110] reference symbols on IQ coordinates.

  This indicates that the reference symbols to which the received symbol R1 may belong on the IQ coordinate are limited to the above-described four points. These four reference symbols represent transition paths (metabranches) between states before and after reception of received symbols.

Based on the above points, the metric calculation circuit 52 calculates a metric for each of these four meta branches. Specifically, the received symbol is (“a, b, c, d”) (where a, b, c, and d are real numbers of 0 or more and 1 or less), and the transmission unit is (“A, B, C, D ″) (where A, B, C, and D are 0 or 1), the metric MM given by the following equation (2) is obtained for each meta branch.
MM = | A−a | + | B−b | + | C−c | + | D−d | (2)
By the way, if the transmission unit is (“A, B, C, D”), the reference symbol is [A, B, C, D]. Therefore, the metric MM described above is based on the received symbol and the reference on the IQ coordinate. It can also be said to be the sum of the absolute values of the differences between the symbols.

  Next, the metric calculation circuit 52 is further provided with a weighting unit, and by using this unit, the metric MM obtained by the above-described procedure is corrected with reference to the correction table 26. Specifically, the weighting unit multiplies the metric for each reference symbol corresponding to each of the meta branches 1 to 4 by the weighting coefficient shown in Table 1 to obtain a corrected metric HMM.

  That is, for example, the reference symbol [0000] corresponding to the meta branch 1 is greatly affected by the phase noise as can be seen from FIG. As a result, even if the distance between the received symbol and [0000] is close on the IQ coordinate, it is not known whether the received symbol can simply be assigned to [0000]. This is because the vicinity of [0000] is a region that is greatly affected by the phase noise, so that a transmission unit transmitted with a reference symbol other than [0000] may be received by chance near [0000] due to phase noise. Because there is.

  Thus, in order to avoid erroneous assignment of the received symbol to the reference symbol, the value of the metric MM is corrected according to the influence of the phase noise. That is, a corrected metric HMM (= W × MM) obtained by multiplying the metric MM by the weight coefficient W for each reference symbol is used.

  The metric MM, correction metric HMM, and weight coefficient W of the meta branches 1 to 4 obtained in this way are summarized in Table 2 below. Note that the metric MM described in the following table is equal to the metric added to the arrow between t = 0 and t = 2 in FIG.

  The correction metrics shown in Table 2 are stored in the cumulative metric storage circuit 56 via the ACS circuit 54. Further, the ACS circuit 54 stores the meta branches 1 to 4 in the transition path storage circuit 58.

  Subsequently, the reception symbol R 2 (“0.8, 0.5, 0.6, 0.5”) is input to the metric calculation circuit 52. Then, a metric MM related to the received symbol R2 is calculated. As can be seen from the trellis diagram (FIG. 4) when the encoded signal H is created, it can be seen that there are 16 meta branches that give the received symbol R2. That is, the received symbol R2 may be attributed to all the reference symbols of the IQ coordinate at the time point t = 4.

  Therefore, the metric calculation means of the metric calculation circuit 52 calculates the metric MM with the received symbol R2 for all meta branches (16) in the same manner as described above. Then, the weighting means multiplies the calculated metric MM by the weight coefficient W for each reference symbol to obtain a corrected metric HMM in the same manner as described above.

  The metric MM and the corrected metric HMM thus obtained are shown in Table 3 below. Note that the metric MM described in the following table is equal to the metric added to the arrow between t = 2 to t = 4 in FIG.

  The corrected metric HMM shown in Table 3 is input to the ACS circuit 54. The ACS circuit 54 reads the meta branch (Table 2) derived from the received symbol R1 and the correction metric from the transition path storage circuit 58 and the cumulative metric storage circuit 56, respectively.

  Then, the ACS circuit 54 calculates a cumulative metric obtained by accumulating the correction metrics HMMs in Tables 2 and 3. The cumulative metric for each transition path calculated in this way is shown in Table 4 below.

  Finally, the maximum likelihood determination means of the maximum likelihood decoding determination circuit 60 estimates the maximum likelihood path based on the cumulative metric shown in Table 4. That is, as is clear from Table 4, the maximum likelihood decoding determination circuit 60 has the No. with the smallest cumulative metric. Route 3 is estimated as the maximum likelihood route (indicated by “」 ”in Table 4).

  By the way, this No. The decoded signal obtained from the three transition paths becomes “001110111” by following the trellis diagram of FIG. This decoded signal matches the encoded signal H “00110111” transmitted by the transmitter 12. This is in contrast to the fact that the above-described general decoder 50 performs erroneous decoding.

  That is, according to the decoder 22 and the decoding method of the present invention, the encoded signal H can be decoded more accurately even if there is phase noise.

  In the description of the operation of the Viterbi decoder 22 described above, the Viterbi decoder 22 of the present invention did not select a survival path. This is because there are only two received symbols R1 and R2 decoded by the decoder 22. That is, when the Viterbi decoder 22 continuously receives three received symbols, for example, R1 → R2 → R3, the branch that transitions to each state after calculating the cumulative metric up to R2 The process of narrowing down to one survival path is performed.

  Although the case of 16QAM has been described in this embodiment, the present invention can also be applied to other quadrature amplitude modulation such as 64QAM and 256QAM.

It is a functional block diagram which shows the structure of a transmission / reception system. It is a schematic diagram which shows the structure of an encoder. It is a state transition diagram of an encoder. It is a trellis diagram used for description of a process for obtaining an encoded signal from an original signal. It is a schematic diagram which shows the reference symbol in 16QAM on IQ coordinate. It is a schematic diagram which shows the mode of the shift | offset | difference by the phase noise of the received symbol in 16QAM on IQ coordinate. It is a functional block diagram which shows the structure of a general decoder. It is a trellis diagram used for description of a decoding process of general Viterbi decoding. It is a functional block diagram which shows the structure of the decoder of this invention. It is a schematic diagram of IQ coordinate used for description of the weight coefficient memorize | stored in the correction table.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Transmission / reception system 12 Transmitter 14 Receiver 16 Encoder 18 Modulator 20 Demodulator 22 Viterbi decoder 24 Encoder 25 Parallel-serial converter 26 Correction table 50 Decoder 52 Metric calculation circuit 54 ACS circuit 56 Cumulative metric storage circuit 58 Transition path memory circuit 60 Maximum likelihood decoding determination circuit

Claims (4)

A transmission unit obtained by cutting out the convolutionally encoded signal from the upper bit side for each fixed number of digits is subjected to quadrature amplitude modulation, and transmitted in the cutout order. The transmitted transmission unit is used as a received symbol on the IQ coordinate. Each received
A metric for each digit is obtained between a received data sequence in which the received symbols are connected in order of reception from the upper bit side to the lower bit side and a binary signal sequence determined for every transition path between states, In the soft decision decoding method using the Viterbi method for estimating the binary signal sequence that minimizes the accumulated metric obtained by accumulating metrics as the encoded signal,
A plurality of points set in advance on the IQ coordinates, each of the reference symbols representing the transition path connecting the states before and after reception of the received symbol, and the received symbol included in the received data sequence Between each of the above metrics for each digit,
A decoding method, wherein a correction metric is calculated by multiplying the metric by a weighting factor having a positive correlation with the magnitude of the influence of phase noise on the reference symbol, and the accumulated metric is obtained as an accumulation of the correction metric.   The decoding method according to claim 1, wherein the quadrature amplitude modulation is 16QAM.   The decoding method according to claim 2, wherein the weighting factor is set to 0.8, 1.0, and 1.2 according to a distance between the reference symbol and an origin of the IQ coordinate. A transmission unit obtained by cutting out the convolutionally encoded signal from the upper bit side for each fixed number of digits is subjected to quadrature amplitude modulation, and transmitted in the cutout order. The transmitted transmission unit is used as a received symbol on the IQ coordinate. Each received
A metric for each digit is obtained between a received data sequence in which the received symbols are connected in order of reception from the upper bit side to the lower bit side and a binary signal sequence determined for every transition path between states, In the soft decision decoding apparatus using the Viterbi method for estimating the binary signal sequence having a minimum accumulated metric obtained by accumulating metrics as the encoded signal,
A plurality of points set in advance on the IQ coordinates, each of the reference symbols representing the transition path connecting the states before and after reception of the received symbol, and the received symbol included in the received data sequence A metric calculation circuit that calculates the metric for each digit and obtains a correction metric by multiplying the metric by a weighting factor;
An addition comparison selection circuit for accumulating the correction metric to obtain an accumulated metric;
A decoding apparatus comprising: a correction table that has a positive correlation with the magnitude of phase noise in the reference symbol and stores the weighting coefficient multiplied by the metric.

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