JP2008306574A - Encoding method, encoder and decoder for image data - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an encoder and decoder of compressed image data in which a real-time decoding process can be carried out. <P>SOLUTION: When a sign amount per frame of a mid code just before a variable-length encoding is A, a conversion amount into the intermediate code per frame by a piece of variable-length decoding means is K, and an upper-limit value of the sign amount per slice of the intermediate code, immediately prior to the variable length encoding, if N (N: an integer of two or larger) pieces of variable-length decoding means are parallel-operated in slice units is X, the upper limit value X of the sign amount per slice of the intermediate code is set by formula: X≤(N×K-A)/(N-1). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an apparatus and method for encoding and decoding image data, and more particularly to an apparatus and method for realizing real-time decoding of compressed image data with a low compression rate.

  Since commercial / broadcast equipment requires editing in units of one frame, a method of recording input image data by compressing it to a fixed length in units of one frame has become mainstream. For example, in the DVCPRO compression, the input video signal is compressed to 1/5 and recorded.

  However, due to the demand for higher image quality due to the larger screen of TV, the broadcasting system is shifting from the SD system to the HD system in which the horizontal resolution and the vertical resolution are doubled. In the HD method, the amount of input image data is four times that of the SD method, so if the current compression technology is used as it is, the storage capacity and communication bandwidth will also be four times, which is economically difficult. Therefore, a compression method that is more efficient than the conventional compression method is desired.

One of the currently proposed image compression methods is H.264. There are H.264 systems. H. When H.264 is applied to frame fixed length compression, it is possible to realize high compression about twice that of the prior art. H. The following is a newly adopted technology effective for intra-frame compression in H.264.
1) Intraframe predictive encoding: A target compressed block is predicted from adjacent blocks and encoded.
2) Adaptive arithmetic coding: The generation probability of a signal to be coded is updated in accordance with the status of surrounding blocks.

  However, both 1) intra-frame predictive coding and 2) adaptive arithmetic coding are computationally intensive, and large-scale hardware is required to perform real-time processing. In particular, since adaptive arithmetic coding requires bit processing, real-time processing is very difficult.

  As a method for realizing the real-time decoding process, for example, as shown in FIG. 8, two arithmetic decoders (decoders) 22-1 and 22-2 are mounted, and the arithmetic decoders 22-1 and 22 for each frame. -2 is used to perform parallel processing. In this case, since the decoding process for one frame may be performed with a throughput of 15 Hz, the processing capability required for the arithmetic decoder is halved. However, in the frame parallel method, the latency for the compression decoding process increases, so that when the screen is searched with a JOG dial such as a VTR, there is a problem that the responsiveness deteriorates.

In Patent Document 1, H. Although H.264 is not touched directly, high-speed decoding processing is realized by dividing one screen into a plurality of slices, mounting a plurality of slice decoders, and performing the following sequential processing.
1) A plurality of slice decoders are operated in parallel.
2) The next slice decoding process is assigned to the slice decoder that has completed the process.

  Considering the case where decoding is performed in real time by operating the decoder in parallel as shown in FIG.

  FIG. 2 shows a general configuration of an intra-frame fixed-length compressed image using H.264. FIG. 9 is a conceptual diagram of a slice obtained by dividing a television screen. An HD video signal of one frame composed of 1920 pixels in the horizontal direction and 1088 pixels in the vertical direction is equally divided into four. The unit divided in this way is called a “slice”.

  A slice is composed of a plurality of macroblocks. A macroblock is a group of four DCT blocks each consisting of 8 horizontal pixels and 8 vertical pixels. Since one frame is composed of {(1920/8) × (1088/8)} / 4 = 8160 macroblocks, one slice is composed of 2040 (= 8160/4) macroblocks.

  Next, the binary code amount and the compressed image data amount will be considered in detail. As described above, since the adaptive arithmetic code has a large variation in encoding efficiency, the correlation between the compressed image data amount in the frame and the binary code amount in the frame varies depending on the characteristics of the image data.

  10, 11, and 12 are diagrams for explaining the correlation between the binary code amount and the compressed image data amount after arithmetic coding. 10, 11, and 12, (a) shows the binary code amount of each slice constituting the frame, and (b) shows the compressed image data amount after arithmetic coding of each slice constituting the frame. . As shown in these figures, even if the amount of compressed image data per slice is constant, the amount of binary code per slice before encoding may vary greatly.

  The operation when the binary codes shown in FIGS. 10A, 11A, and 12A are input to the arithmetic decoders 22-1 and 22-2 shown in FIG. 8 will be described. FIG. 13 is a diagram showing the timing when each compressed image data shown in FIG. 10 is binary coded by the two arithmetic decoders 22-1 and 22-2. FIG. 13A shows the output of one arithmetic decoder (decoder) 22-1 and FIG. 13B shows the output of another arithmetic decoder 22-2.

  In general, when an arithmetic decoder performs bit processing and performs one bit processing in one clock, the binary code amount after arithmetic decoding and the decoding processing time are in a proportional relationship.

  In the example of FIG. 13, the slice 0 is simultaneously decoded by the arithmetic decoder 22-1 and the slice 1 is simultaneously decoded by the arithmetic decoder 22-2. Slice 1 with a small binary code amount finishes arithmetic decoding first. Therefore, slice 2 is supplied to the arithmetic decoder 22b. When the arithmetic decoder 22-1 finishes decoding slice 0, slice 3 is supplied to the arithmetic decoder 22-1.

  In this way, by sequentially supplying slices to the arithmetic decoder for which the decoding process has been completed first, parallel processing is executed to achieve high speed. In the figure, since the arithmetic decoding process for slice 3 is completed within one frame, a video signal can be output after one frame.

JP 2002-57986 A

  Consider a case where compressed image data with more variation in the binary code amount of a slice is arithmetically decoded in parallel. FIG. 14 is a diagram showing output timing when each compressed image data shown in FIG. 12 is binary coded by an arithmetic decoder. FIG. 14A shows the output of the arithmetic decoder 22-1 and FIG. 14B shows the output of the arithmetic decoder 22-2. In the same figure, since the arithmetic decoding process of slice 3 is not completed within one frame, the video signal cannot be output after one frame, and thus the output video signal is interrupted.

  In this way, H.C. In the decoding processing of H.264 compressed image data, when two arithmetic decoders having a large processing load are provided in parallel and arithmetic decoding processing is performed in units of slices, the processing speed becomes high on average, but real-time reproduction cannot be guaranteed. There was a problem.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a compressed image data encoding device and decoding device capable of real-time decoding processing.

In a first aspect of the present invention, there is provided an encoding method for dividing one-screen data into a plurality of slices and compressing intra frames. The encoding method includes the upper limit value of the code amount per frame of the compressed image data after the variable length code, the upper limit value of the code amount per frame of the intermediate code immediately before the variable length encoding, and the intermediate code immediately before the variable length encoding. The upper limit value of the code amount per slice is defined. The code amount per frame of the intermediate code immediately before variable length coding is A, the conversion amount to one intermediate code per frame by one variable length decoding means is K, and the variable length decoding means is N (in slice units). N is an integer greater than or equal to 2) When the code amount upper limit value per slice of the intermediate code immediately before variable length coding is X, when X is operated in parallel, The code amount upper limit value X is set.
X ≦ (N × KA) / (N−1)

  In a second aspect of the present invention, there is provided an encoding device that divides one screen into a plurality of slices and compresses intra frames. The encoding device includes a quantization unit that quantizes image data according to a quantization parameter, a quantization control unit that controls the quantization parameter of the quantization unit, and encodes the quantized image data using a variable length code. Encoding means for generating compressed image data, first detection means for detecting the amount of code per frame of compressed image data after variable length coding, and 1 of intermediate code immediately before variable length coding Second detection means for detecting the code amount per frame and third detection means for detecting the code amount per slice of the intermediate code immediately before variable length coding are provided.

  The quantization control means refers to the detection results from the first to third detection means, and defines a predetermined upper limit value of the code amount per frame of the compressed image data after the variable length code and the variable length code. The amount of code by changing the quantization parameter so as to satisfy the upper limit value of the code amount per frame of the intermediate code immediately before encoding and the upper limit value of the code amount per slice of the intermediate code immediately before variable length encoding Take control.

In a third aspect of the present invention, there is provided a decoding device for receiving and decoding compressed image data encoded by a variable length code by an encoding device. The decoding apparatus includes N variable-length decoding units that decode the compressed image data and convert it into an intermediate code (N is an integer of 2 or more). When the upper limit value of the code amount per slice of the intermediate code immediately before variable length coding in the encoding device is X, and the upper limit value of the code amount per frame of the intermediate code immediately before variable length coding is A, In each variable length decoding means, the lower limit value K of the intermediate code amount that can be converted from the image data per frame satisfies the following equation.
K = X + (A−X) / N

  According to the encoding method of the present invention, in addition to the upper limit value of the code amount per frame of the compressed image data after the variable length code and the upper limit value of the code amount per frame of the intermediate code immediately before the variable length encoding, the variable length code The upper limit value of the code amount per slice of the intermediate code immediately before conversion is defined. Therefore, when the compressed image data encoded by the encoding device is decoded, the number of variable length decoding units that are operated in parallel in slice units and the lower limit value of the throughput per frame of the variable length decoding unit can be defined. .

  In addition, if the number of parallel operations is set in accordance with the throughput per frame of the variable length decoding means, it is possible to provide a low-delay decoding device that suppresses the throughput of the variable length decoding means to a practical rate. is there.

  Furthermore, in a system that handles two modes, the basic code amount of compressed image data (for example, 25 Mbps) and a high-definition mode (for example, 50 Mbps), it is assumed that two variable-length decoding units are mounted in parallel in the high-definition mode. In addition, by defining the throughput per frame of the variable length decoding means and the upper limit value of the code amount per slice of the intermediate code immediately before the variable length coding, it becomes effective in a system that handles different compression rates. .

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a compressed image data encoding device and decoding device according to the present invention will be described below with reference to the accompanying drawings.

1. Configuration of Encoding Device FIG. 1 is a diagram showing the configuration of an image data encoding device according to the present invention.
The blocking unit 1 divides the input video signal into macro blocks. The computing unit 2 computes a difference between each pixel of the input macroblock and a pixel created by an intra prediction unit described later. The DCT unit 3 performs DCT conversion on the output of the computing unit 2. The quantizer 4 quantizes the output from the DCT unit 3 according to a quantization parameter determined by a quantization control unit 14 described later. The inverse quantizer 5 inversely quantizes the output from the quantizer 4. The inverse DCT unit 6 performs inverse DCT on the output of the inverse quantizer 5 and converts it into pixel data. The intra prediction unit 7 predicts and creates the next macroblock pixel from the macroblock pixel data restored by the inverse DCT unit 6. The syntax creation unit 8 outputs the output of the quantizer 4 to H.264. H.264 is converted into syntax. The binary encoding unit 9 converts the syntax into a binary code (intermediate code). The arithmetic encoder 10 arithmetically encodes the binary code to generate compressed image data.

  The in-frame compressed image data amount detection unit 11 observes the history of the compressed image data amount in the frame. The intra-frame binary code amount detection unit 12 observes the history of the binary code amount within the frame. The intra-slice binary code amount detection unit 13 observes the history of the binary code amount in the slice.

  The quantization control unit 14 compresses one frame while referring to the observation results of the intra-frame compressed image data amount detection unit 11, the intra-frame binary code amount detection unit 12, and the intra-slice binary code amount detection unit 13. From the image data amount and the compressed image data amount per frame, the maximum value of the binary code amount per frame specified by the format, and the maximum value of the binary code amount per slice specified by the method described later The quantization parameter in the quantizer 4 is controlled so as to satisfy

  That is, the quantization control unit 14 controls the quantization parameter based on the observation result from the intra-frame compressed image data amount detection unit 11 so that the compressed image data amount per frame falls within the upper limit value. . Further, the quantization control unit 14 controls the quantization parameter based on the observation result from the intra-frame binary code amount detection unit 12 so that the compressed image data amount per frame falls within the upper limit value. Further, the quantization control unit 14 determines the upper limit of the binary code amount per slice of the binary code generated by the binary code unit 9 based on the observation result from the intra-slice binary code amount detection unit 13. The quantization parameter is controlled so as to be within the value.

  FIG. 2 is a diagram for explaining the operation of the quantization control unit 14. FIG. 2 is a diagram illustrating a relationship between a block position in a frame and a code amount when the block is encoded. When the quantization parameter is increased, the code amount decreases, and when the quantization parameter is decreased, the code amount increases. Using this characteristic, the quantization parameter is controlled so as to be within the target code amount in the frame. The curve (a) in the figure shows a case where the code amount is larger than expected, and therefore the control is performed so that the quantization parameter is sequentially increased so as to be within the target code amount. Since the code amount is smaller, a case is shown in which the quantization parameter is sequentially decreased to control to approach the target code amount.

2. Configuration of Decoding Device A decoding device that decodes compressed image data generated by the encoding device 100 will be described. FIG. 3 is a configuration diagram of a decoding apparatus for compressed image data. The decoding apparatus 200 includes an arithmetic decoder in parallel, thereby speeding up the decoding process.

  The slice detection unit 20 detects the head position of the slice by detecting the reserved three consecutive bytes (000000, 000001, 000002, or 000003) in the input compressed image data. The slice memory 21 temporarily records the compressed image data for each slice.

  Arithmetic decoders 22a and 22b are provided in parallel, and these arithmetic decoders 22a and 22b convert the compressed image data read from the slice memory 21 into a binary code. Thus, the arithmetic decoding process is parallelized in units of slices.

  The syntax generators 23a and 23b convert the binary code output from the arithmetic decoders 22a and 22b to the H.264 format. The parallelizing unit 24 that converts to the syntax defined by H.264 controls the read operation of the slice memory 21 and supplies compressed image data to the two arithmetic decoders 22a and 22b in units of slices. The frame memory 25 temporarily records the syntax data. The inverse quantizer 26 interprets the syntax of the syntax data read from the frame memory 25 and performs an inverse quantization process. The inverse DCT unit 27 performs inverse DCT transform on the output of the inverse quantizer 26. The deblocking unit 27 generates a video signal from the output of the inverse DCT unit 27.

3. Upper limit value of binary code amount in one slice and processing capability of arithmetic decoder One of the characteristics of the encoding process in this embodiment is that an upper limit value is set for the binary code amount per slice in the binary code. It is provided. That is, in the encoding apparatus 100, the intra-slice binary code amount detection unit 13 detects the binary code amount per slice of the binary code generated by the binary code unit 9. Based on the detection result, the quantization control unit 14 controls the quantization parameter so that the binary code amount per slice of the binary code generated by the binary code unit 9 falls within the upper limit value. To do.

  Hereinafter, a method for setting the upper limit value of the binary code amount per slice in the encoding apparatus 100 of the present embodiment will be described. In the following description, an example in which one frame includes four slices will be described. The following setting method is premised on decoding by a decoding apparatus 200 including two arithmetic decoders 22a and 22b provided in parallel as shown in FIG.

H. According to the H.264 format, the total of binary codes of 4 slices is restricted to about 1.6 times that of compressed image data. When the binary code amount of slice N is B (N) (N = 0, 1, 2, 3), and the upper limit of the sum of binary codes of one frame, that is, four slices is A, the following equation is established.
B (0) + B (1) + B (2) + B (3) ≦ A (1)

Further, when the binary code amount that can be decoded per frame of the arithmetic decoders 22a and 22b is K, and the upper limit value of the binary code amount of one slice is X, the following equation is established.
AK ≤ X ≤ K (2)

  For example, if K = A / 2, then X = A / 2. This means that if the upper limit value X of a binary code for one slice is set to half of the upper limit value A of a binary code for one frame, an arithmetic process capable of processing half the data amount of the binary code amount for one frame. It is shown that the decoding process is completed within one frame period by operating two decoders in parallel.

  However, the above considerations may not be sufficient. This will be described below. For example, consider a case where decoding processing is performed by two parallel arithmetic decoders in the order of B (0), B (1), B (2), and B (3).

  When B (0) or B (1) is 2 / A (see FIG. 4A), 2 of the data amount of A / 2 is obtained in one of the two arithmetic decoders 22a and 22b. The value code is decoded and the remaining three slices are decoded. In this case, the above consideration is appropriate.

Next, consider the case where B (2) is A / 2 (see FIG. 4B). At the time of decoding of slice 2, the two arithmetic decoders 22a and 22b have already decoded the binary code for slices 0 and 1, and the decoding of slice 2 is assigned to the one that finished earlier. When B (2) is A / 2, the sum of the binary code values of the remaining slices 0, 1, and 3 is A / 2. Then, considering that slices 0, 1, 3 are processed by at least two arithmetic decoders, it is considered that the size of slice 0 can be a maximum of A / 4. Therefore, when B (2) is A / 2, the processable binary code amount K of the arithmetic decoder that decodes slice 2 needs to satisfy the following equation.
K ≧ A / 4 + A / 2 = (3/4) × A (3)

  The above equation (3) indicates that the decoding process is not completed within one frame even if two arithmetic decoders capable of decoding with a processing capacity half the upper limit A of the binary code of one frame are operated in parallel. ing. In this case, the capability K of the arithmetic decoder is required to be at least (3/4) × A.

  Consider the case where B (3) is A / 2. At the start of the arithmetic decoding of slice 3, the amount of binary code processing of the arithmetic decoder whose decoding has ended first is equal to that at the same time, and is A / 4. Therefore, in this case as well, as described above, the binary code amount K to be processed by the arithmetic decoder that decodes the slice 3 needs to satisfy Expression (3).

  FIG. 5 is a diagram illustrating the output timing of the encoding apparatus 100 according to the present embodiment. According to the conventional encoding apparatus, the encoding according to the present embodiment is applied to one frame of image data having the binary code amount shown in FIG. 12A and the compressed image data amount shown in FIG. The binary code amount (FIG. 4 (a)) and the compressed image data amount (FIG. 4 (b)) when the apparatus is adapted are shown. The shaded area shown in FIG. 4 indicates the amount of data reduced by this embodiment. In this example, the quantization parameter is controlled by the quantization controller 14 so that the binary code amount of slice 3 is half the upper limit of the code amount of one frame.

  FIG. 6 is a diagram illustrating output timings of the arithmetic decoders 22a and 22b in the decoding device 200 according to the present embodiment. The timing is as shown in FIG. 14 by the conventional decoding device. FIG. 6A shows the binary code amount output from the arithmetic decoder 22a, and FIG. 6B shows the binary code amount output from the arithmetic decoder 22b. The shaded area in the figure is the amount of data reduced by this embodiment. As a result of the control by the quantization control unit 14 so that the binary code amount of the slice 3 is half of the upper limit value of the code amount of one frame, the arithmetic decoding process is completed within one frame period.

  As described above, the upper limit value of the binary code amount per slice is limited to half of the upper limit value of the binary code amount per frame, and further, the guaranteed performance of the binary code processing amount of the two arithmetic decoders is improved. If (3/4) × A, the arithmetic decoding process can be accommodated within one frame, and a real-time decoding process can be realized.

  In this embodiment, for the sake of simplicity, one frame is described as four slices, but the present invention is not limited to four slices. If the number of other slices is 2 in parallel, Expression (3) holds.

Furthermore, although the number of arithmetic decoders provided in parallel is two, the number of parallel decoders can be increased. For example, if the upper limit value of the binary code amount of a slice is 3/2 in parallel, the remaining half code amount is equally divided into three. Therefore, when the parallel number of arithmetic decoders is 3, the guaranteed value K of the binary code amount processed by the arithmetic decoder is expressed by the following equation.
K = (1/2) × (1/3) × A + A / 2 = (2/3) × A (4)

  Finally, consider the case where the parallel number of arithmetic decoders is generalized to N in the decoding device.

As shown in FIG. 7 (a), the number of arithmetic decoders to be converted into intermediate codes in the decoding device is N (N is an integer equal to or greater than 2), and the intermediate code per slice immediately before arithmetic encoding in the encoding device. Assuming that the upper limit value of the code amount is X and the upper limit value of the code amount per frame of the intermediate code immediately before arithmetic coding is A, the guaranteed value of the binary code amount to be processed by the arithmetic decoder per frame K is expressed by the following equation (see FIG. 7B).
K = X + (A−X) / N (5)

Also, from the above equation (5), the upper limit value X of the code amount per slice of the binary code (intermediate code) immediately before the arithmetic coding in the encoding device is obtained by the following equation.
X = (N × K−A) / (N−1) (6)

  In other words, the above equation expresses the binary code amount to be processed per frame if the upper limit value of the code amount per slice of the binary code (intermediate code) immediately before arithmetic coding is defined as the value shown in equation (5). It is shown that when N arithmetic decoders having a guaranteed value of K are installed and N slices are decoded in parallel, an image data encoding / decoding device capable of real-time decoding with low delay can be provided.

The stream generated by the encoding apparatus 100 may include the following information.
Information indicating the maximum value of the code amount of the binary code per slice Information indicating that the stream is encoded in a predetermined method in which the maximum value of the code amount of the binary code per slice is limited

  Further, the idea of the present invention is applied to a system that handles two modes of a high-definition mode (for example, 50 Mbps) together with a mode of a basic code amount (for example, 25 Mbps) of compressed image data. Assuming that two decoders are mounted in parallel, if the throughput per frame of the variable-length decoder and the upper limit value of the code amount per slice of the intermediate code immediately before variable-length coding are defined, It goes without saying that effective operation is possible in a system that handles different compression rates.

  As described above, although the arithmetic code has been described in the present embodiment, it goes without saying that the present invention can also be applied to other variable-length codes.

  The image data encoding device according to the present invention is effective for searching for edit points because it can perform low-delay decoding by parallel processing during decoding. Therefore, the present invention is useful for video equipment related to the manufacture of image data encoding / decoding devices for broadcasting and business equipment that require one frame editing.

The figure which shows the structure of the encoding apparatus of the image data which concerns on this invention. Explanatory drawing of the quantization control unit of the encoding device The figure which shows the structure of the decoding apparatus of the compressed image data which concerns on this invention The figure for demonstrating the upper limit of the amount of binary codes per slice The figure explaining the output timing of the encoding apparatus of embodiment of this invention The figure explaining the output timing of the arithmetic decoder of the decoding apparatus of embodiment of this invention (A) The figure which shows N arithmetic decoders connected in parallel, (b) The figure for demonstrating the upper limit of the binary code amount per slice in the decoding apparatus provided with N arithmetic decoders Diagram showing two arithmetic decoders connected in parallel Diagram explaining the slice (A) The figure which shows the data amount of the compressed image data before arithmetic coding, (b) The figure which shows the data amount of the compressed image data after arithmetic coding (A) The figure which shows the data amount of the compressed image data before arithmetic coding, (b) The figure which shows the data amount of the compressed image data after arithmetic coding (A) The figure which shows the data amount of the compressed image data before arithmetic coding, (b) The figure which shows the data amount of the compressed image data after arithmetic coding Diagram explaining the output timing of the arithmetic decoder Diagram explaining the output timing of the arithmetic decoder

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Blockizer 3 DCT means 4 Quantizer 9 Binary encoding part 10 Arithmetic encoder 11 Intra-frame compressed image data amount detection part 12 In-frame binary code quantity detection part 13 In-slice binary code quantity detection part 14 Quantization control units 22a, 22b, 22-1 to 22-N arithmetic decoder 100 encoding device 200 decoding device

Claims (6)

An encoding method for dividing one-screen data into a plurality of slices and compressing intra-frame data,
Upper limit value of code amount per frame of compressed image data after variable length coding, upper limit value of code amount per frame of intermediate code immediately before variable length coding, and code per slice of intermediate code immediately before variable length coding The upper limit of the amount is defined,
The code amount per frame of the intermediate code immediately before variable length coding is A, the conversion amount to one intermediate code per frame by one variable length decoding means is K, and the variable length decoding means is N (in slice units). When N is an integer of 2 or more) and the code amount upper limit value per slice of the intermediate code immediately before variable-length coding when operated in parallel is X,
Set the code amount upper limit value X per slice of the intermediate code so as to satisfy the following equation:
An image data encoding method characterized by the above.
X ≦ (N × KA) / (N−1)   2. The image data encoding method according to claim 1, wherein the variable length code is an arithmetic code. An encoding device that divides one screen into a plurality of slices and compresses intra frames,
A quantization means for quantizing the image data according to the quantization parameter;
Quantization control means for controlling the quantization parameter of the quantization means;
Encoding means for generating compressed image data by encoding the quantized image data with a variable length code;
First detection means for detecting a code amount per frame of the compressed image data after the variable length code;
Second detection means for detecting a code amount per frame of the intermediate code immediately before the variable length encoding;
Third detection means for detecting a code amount per slice of the intermediate code immediately before variable length coding;
The quantization control means refers to the detection results from the first to third detection means, and defines a predetermined upper limit value of the code amount per frame of the compressed image data after the variable length code, and a variable The quantization parameter is changed so as to satisfy the upper limit value of the code amount per frame of the intermediate code immediately before long coding and the upper limit value of the code amount per slice of the intermediate code immediately before variable length coding. An image data encoding device that performs code amount control.   5. The image data encoding apparatus according to claim 4, wherein the variable length code is an arithmetic code. A decoding device that receives and decodes compressed image data encoded by a variable-length code by an encoding device,
N variable-length decoding means for decoding compressed image data and converting it into an intermediate code (N is an integer of 2 or more)
When the upper limit value of the code amount per slice of the intermediate code immediately before variable length coding in the encoding device is X, and the upper limit value of the code amount per frame of the intermediate code immediately before variable length coding is A. A decoding apparatus for compressed image data, wherein the lower limit value K of the amount of intermediate code that can be converted from image data per frame in each of the variable length decoding means satisfies the following equation.
K = X + (A−X) / N   6. The image data encoding apparatus according to claim 5, wherein the variable length code is an arithmetic code.

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