JP2008306103A - Semiconductor device and method of designing conductive pattern - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that prevents a conductive pattern from being cracked. <P>SOLUTION: The semiconductor device of this invention includes a first straight line conductive pattern 12 mounted on an insulating film 10, a second straight line conductive pattern 14 which is disposed on the insulating film 10 and bonded to an end portion of the first conductive pattern 12 in a direction of 90° to the first conductive pattern 12, a right triangle auxiliary pattern 16 which is disposed on the insulating film 10 positioned at an inner angle side of the bonded portion of the first conductive pattern 12 and second conductive pattern 14 and connected to each of the first conductive pattern 12 and second conductive pattern 14, and a passivation film 20. Two sides between right angle portions of the auxiliary pattern 16 are in line contact with each of the first conductive pattern 12 and second conductive pattern 14. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a conductive pattern design method. In particular, the present invention relates to a semiconductor device and a conductive pattern design method capable of suppressing cracks in a conductive pattern.

  FIG. 5A is a plan view for explaining a conductive pattern included in a conventional semiconductor device, and FIG. 5B is a cross-sectional view taken along the line AA ′ of FIG. The conductive patterns 112 and 114 shown in this drawing belong to the uppermost wiring layer and are formed on the uppermost interlayer insulating film 110. The conductive patterns 112 and 114 are linear patterns, and their ends are joined. The angle of the conductive pattern 114 with respect to the conductive pattern 112 is 90 °. A passivation film 120 is formed on the conductive patterns 112 and 114 and the interlayer insulating film 110. The passivation film 120 has a structure in which a silicon oxide film 120b and a silicon nitride film 120a are stacked in this order (see, for example, Patent Document 1).

  Since the passivation film 120 includes the silicon nitride film 120 a, stress is applied from the passivation film 120 to the conductive patterns 112 and 114. For this reason, the crack 112a may arise in the junction part of the conductive patterns 112 and 114. FIG.

Japanese Patent Laying-Open No. 2006-24685 (FIG. 4, sixth paragraph)

  As described above, in the uppermost wiring layer, when the ends of the two linear conductive patterns are bonded so as to form an angle of 90 °, the bonded portion is cracked due to the stress applied from the passivation film. May occur.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device and a conductive pattern design method capable of suppressing cracks in the conductive pattern.

In order to solve the above problems, a semiconductor device according to the present invention includes a linear first conductive pattern provided on an insulating film,
A linear second conductive pattern provided on the insulating film and bonded to an end of the first conductive pattern in an orientation of 90 ° with respect to the first conductive pattern;
A right triangle shape provided on the insulating film located on the inner corner side of the joint portion of the first conductive pattern and the second conductive pattern and connected to the first conductive pattern and the second conductive pattern, respectively. Auxiliary patterns,
A passivation film formed on the insulating film, on the first conductive pattern, and on the auxiliary pattern;
Comprising
In the auxiliary pattern, two sides sandwiching a right angle portion are in line contact with the first conductive pattern and the second conductive pattern, respectively.

  According to this semiconductor device, the auxiliary pattern is formed on the inner corner side of the joint portion between the first conductive pattern and the second conductive pattern. For this reason, even if stress is applied to the joint portion from the passivation film, the stress is dispersed, and cracks are suppressed from entering the joint portion.

A semiconductor device according to the present invention includes a linear first conductive pattern provided on an insulating film,
A linear second conductive pattern provided on the insulating film and bonded to an end of the first conductive pattern in an orientation of 90 ° with respect to the first conductive pattern;
Auxiliary provided on the insulating film located on the inner corner side of the joint portion of the first conductive pattern and the second conductive pattern, and connected to the first conductive pattern and the second conductive pattern, respectively. With patterns,
A passivation film formed on the insulating film, on the first conductive pattern, and on the auxiliary pattern;
Comprising
The auxiliary pattern is
A first side that is in line contact with the first conductive pattern and one end of which is located at an inner corner of the joint portion;
A second side that is in line contact with the second conductive pattern and one end of which is located at an inner corner of the joint portion;
A third side that connects the other end of the first side and the other end of the second side and is concave inward.
The first side and the second side are preferably substantially equal in length.

  The first conductive pattern and the second conductive pattern have a length of 2 μm or more, and the auxiliary pattern, the first conductive pattern, and the second conductive pattern have a thickness of 4 μm or more. Since the stress resulting from the passivation film is larger than the reference value, the present invention is particularly effective.

The conductive pattern design method according to the present invention is a conductive pattern design method for designing a conductive pattern on an insulating film,
Using a computer, a linear first conductive pattern and a linear second conductive pattern joined to an end of the first conductive pattern at an angle of 90 ° to the first conductive pattern. Generating pattern data indicating a conductive pattern;
An auxiliary pattern in the shape of a right triangle that the computer is located on the inner corner side of the joint portion of the first conductive pattern and the second conductive pattern and is connected to each of the first conductive pattern and the second conductive pattern A step of generating
Comprising
In the auxiliary pattern, two sides sandwiching a right angle portion are in line contact with the first conductive pattern and the second conductive pattern, respectively.

Another conductive pattern design method according to the present invention is a conductive pattern design method for designing a conductive pattern on an insulating film,
Using a computer, a linear first conductive pattern and a linear second conductive pattern joined to an end of the first conductive pattern at an angle of 90 ° to the first conductive pattern. Generating pattern data indicating a conductive pattern;
An auxiliary pattern in the shape of a right triangle that the computer is located on the inner corner side of the joint portion of the first conductive pattern and the second conductive pattern and is connected to each of the first conductive pattern and the second conductive pattern A step of generating
Comprising
The auxiliary pattern is
A first side that is in line contact with the first conductive pattern and one end of which is located at an inner corner of the joint portion;
A first side that is in line contact with the second conductive pattern and one end of which is located at an inner corner of the joint portion;
A third side that connects the other end of the first side and the other end of the second side and is concave inward.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1A is a plan view for explaining a semiconductor device according to the first embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along line AA ′ of FIG. This semiconductor device has Al alloy wirings 12 and 14 on the uppermost interlayer insulating film 10. The Al alloy wirings 12 and 14 are linear wirings, and their ends are joined. The angle formed between the Al alloy wires 12 and 14 is 90 °. A passivation film 20 as a protective film is formed on the interlayer insulating film 10 and the Al alloy wirings 12 and 14. The passivation film 20 has a structure in which a silicon oxide film 20b and a silicon nitride film 20a are stacked in this order. The thickness of the silicon oxide film 20b is, for example, 1500 nm or less, and the thickness of the silicon nitride film 20a is, for example, not less than 300 nm and not more than 1000 nm.

  A semiconductor substrate (not shown) and a transistor (not shown) formed on the semiconductor substrate are located below the interlayer insulating film 10. This transistor is electrically connected to the Al alloy wires 12 and 14.

  On the interlayer insulating film 10, an auxiliary pattern 16 is formed which is located on the inner corner side of the joined portion of the Al alloy wirings 12 and 14. The planar shape of the auxiliary pattern 16 is a right-angled isosceles triangle, and two sides 16a and 16b sandwiching the right-angled portion are in line contact with the Al alloy wirings 12 and 14, respectively.

  Since the passivation film 20 includes the silicon nitride film 20 a, stress caused by the passivation film 20 is applied to the side walls of the Al alloy wirings 12 and 14. Since the Al alloy wirings 12 and 14 extend in a direction perpendicular to each other, a stress in a direction of cutting the joint portion is applied to the joint portion of the Al alloy wirings 12 and 14.

  On the other hand, in this embodiment, as described above, the auxiliary pattern 16 is formed on the inner corner side of the joint portion of the Al alloy wirings 12 and 14. For this reason, the stress caused by the passivation film 20 is distributed and applied to the two portions of the auxiliary pattern 16 and the joint portions 16c and 16d of the Al alloy wirings 12 and 14. Therefore, it is possible to suppress the occurrence of cracks at the joint portions of the Al alloy wirings 12 and 14 as compared with the conventional case. Such an effect becomes particularly remarkable when the length of the Al alloy wirings 12 and 14 is 2 μm or more and the thickness of the Al alloy wirings 12 and 14 is 4 μm or more, respectively.

  Such a semiconductor device is formed as follows. First, an Al alloy film is formed on the interlayer insulating film 10 by a sputtering method. Next, a photoresist film (not shown) is formed on the Al alloy film, this photoresist film is exposed using a reticle, and then developed. Thereby, a resist pattern located on the Al alloy film is formed. Next, the Al alloy film is etched using this resist pattern as a mask. Thereby, the Al alloy wirings 12 and 14 and the auxiliary pattern 16 are formed. Thereafter, the resist pattern is removed. Next, the silicon oxide film 20b and the silicon nitride film 20a are stacked in this order.

  FIG. 2 is a flowchart for explaining a pattern design method of the Al alloy wirings 12 and 14 and the auxiliary pattern 16 shown in FIG. First, the designer generates pattern data indicating the pattern of the Al alloy wirings 12 and 14 using a computer (S2). Next, the computer detects that the Al alloy wirings 12 and 14 are linear to each other, the ends are joined to each other, and the angle formed by each other is 90 °, and the length of the Al alloy wirings 12 and 14 is When it is detected that the thickness and thickness are equal to or greater than the reference value, pattern data indicating the auxiliary pattern 16 is generated, and this pattern data is combined with pattern data indicating the Al alloy wirings 12 and 14 (S4). For this reason, the labor demanded by the designer can be reduced.

  As described above, according to the first embodiment, the auxiliary pattern 16 is formed on the inner corner side of the joint portion of the Al alloy wirings 12 and 14. For this reason, it is suppressed that a crack arises in the joined part of Al alloy wiring 12 and 14 compared with the past. At the stage of designing the wiring pattern, the computer automatically generates pattern data corresponding to the auxiliary pattern 16 and synthesizes the pattern data corresponding to the Al alloy wirings 12 and 14. Therefore, the labor required for the designer is small.

  FIG. 3A is a plan view for explaining the configuration of the semiconductor device according to the second embodiment. The semiconductor device according to this embodiment has the same configuration as that of the first embodiment except for the planar shape of the auxiliary pattern 16. Hereinafter, the same components as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

In the present embodiment, the auxiliary pattern 16 has a shape in which the hypotenuse 16e of the auxiliary pattern 16 shown in the first embodiment is gently concaved inward. The other two sides 16a and 16b have one end located at the inner corner of the joint portion of the Al alloy wirings 12 and 14 as in the first embodiment.
The manufacturing method of the semiconductor device according to the present embodiment and the pattern design method of the Al alloy wirings 12 and 14 and the auxiliary pattern 16 are the same as those in the first embodiment.

FIG. 3B is a plan view for explaining an opening pattern of a reticle used in the present embodiment. In the present embodiment, the opening pattern of the reticle has a shape in which the opening pattern 36 corresponding to the auxiliary pattern 16 is combined with the linear opening patterns 32 and 34 corresponding to the Al alloy wirings 12 and 14. A portion of the opening pattern 36 corresponding to the oblique side 16e has a staircase shape. In this way, the step shape becomes a substantially arc shape during exposure and development, and the hypotenuse 16e shown in FIG. 3A is formed.
As described above, the present embodiment can provide the same effects as those of the first embodiment.

  FIG. 4 is a plan view for explaining the configuration of the semiconductor device according to the third embodiment. In the semiconductor device according to this embodiment, the Al alloy wiring 14 is a coil, and the inner peripheral end of the Al alloy wiring 14 belongs to a wiring layer below the Al alloy wiring 14. The configuration is the same as that of the semiconductor device according to the first embodiment except that the Al alloy wiring 18 is connected to the Al alloy wiring 18 located in the same layer as the Al alloy wiring 14.

  The Al alloy wiring 18 is located outside the Al alloy wiring 14 that is a coil. The Al alloy wiring 40 and the Al alloy wirings 14 and 18 are connected to each other through a tungsten plug 11 embedded in the interlayer insulating film 10. Hereinafter, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  Also according to this embodiment, the same effect as that of the first embodiment can be obtained. In the present embodiment, even if the auxiliary pattern 16 has the same shape as that of the second embodiment, the same effect as that of the first embodiment can be obtained.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

(A) is a top view for demonstrating the semiconductor device which concerns on 1st Embodiment, (B) is AA 'sectional drawing of (A). 3 is a flowchart for explaining a pattern design method for the Al alloy wirings 12 and 14 and the auxiliary pattern 16 shown in FIG. 1. (A) is a plan view for explaining the configuration of the semiconductor device according to the second embodiment, and (B) is a plan view for explaining an opening pattern of a reticle used in this embodiment. FIG. 6 is a plan view for explaining a configuration of a semiconductor device according to a third embodiment. (A) is a top view for demonstrating the conventional semiconductor device, (B) is AA 'sectional drawing of (A).

Explanation of symbols

DESCRIPTION OF SYMBOLS 10,110 ... Interlayer insulation film, 11 ... Tungsten plug, 12, 14, 18, 40 ... Al alloy wiring, 16a, 16b ... Side, 16c, 16d ... Joint part, 16e ... Oblique side, 20, 120 ... Passivation film, 20a 120a ... silicon nitride film, 20b, 120b ... silicon oxide film, 32, 34, 36 ... opening pattern, 112, 114 ... conductive pattern, 112a ... crack

Claims (6)

A linear first conductive pattern provided on the insulating film;
A linear second conductive pattern provided on the insulating film and bonded to an end of the first conductive pattern in an orientation of 90 ° with respect to the first conductive pattern;
A right triangle shape provided on the insulating film located on the inner corner side of the joint portion of the first conductive pattern and the second conductive pattern and connected to the first conductive pattern and the second conductive pattern, respectively. Auxiliary patterns,
A passivation film formed on the insulating film, on the first conductive pattern, and on the auxiliary pattern;
Comprising
The auxiliary pattern is a semiconductor device in which two sides sandwiching a right angle portion are in line contact with the first conductive pattern and the second conductive pattern, respectively. A linear first conductive pattern provided on the insulating film;
A linear second conductive pattern provided on the insulating film and bonded to an end of the first conductive pattern in an orientation of 90 ° with respect to the first conductive pattern;
Auxiliary provided on the insulating film located on the inner corner side of the joint portion of the first conductive pattern and the second conductive pattern, and connected to the first conductive pattern and the second conductive pattern, respectively. With patterns,
A passivation film formed on the insulating film, on the first conductive pattern, and on the auxiliary pattern;
Comprising
The auxiliary pattern is
A first side that is in line contact with the first conductive pattern and one end of which is located at an inner corner of the joint portion;
A second side that is in line contact with the second conductive pattern and one end of which is located at an inner corner of the joint portion;
A third side that connects the other end of the first side and the other end of the second side and is concave toward the inside;
A semiconductor device comprising:   The semiconductor device according to claim 2, wherein the first side and the second side have substantially the same length. The first conductive pattern and the second conductive pattern have a length of 2 μm or more,
The semiconductor device according to claim 1, wherein the auxiliary pattern, the first conductive pattern, and the second conductive pattern have a thickness of 4 μm or more. A conductive pattern design method for designing a conductive pattern on an insulating film,
Using a computer, a linear first conductive pattern and a linear second conductive pattern joined to an end of the first conductive pattern at an angle of 90 ° to the first conductive pattern. Generating pattern data indicating a conductive pattern;
An auxiliary pattern in the shape of a right triangle that the computer is located on the inner corner side of the joint portion of the first conductive pattern and the second conductive pattern and is connected to each of the first conductive pattern and the second conductive pattern A step of generating
Comprising
The auxiliary pattern is a conductive pattern design method in which two sides sandwiching a right angle portion are in line contact with the first conductive pattern and the second conductive pattern, respectively. A conductive pattern design method for designing a conductive pattern on an insulating film,
Using a computer, a linear first conductive pattern and a linear second conductive pattern joined to an end of the first conductive pattern at an angle of 90 ° to the first conductive pattern. Generating pattern data indicating a conductive pattern;
An auxiliary pattern in the shape of a right triangle that the computer is located on the inner corner side of the joint portion of the first conductive pattern and the second conductive pattern and is connected to each of the first conductive pattern and the second conductive pattern A step of generating
Comprising
The auxiliary pattern is
A first side that is in line contact with the first conductive pattern and one end of which is located at an inner corner of the joint portion;
A first side that is in line contact with the second conductive pattern and one end of which is located at an inner corner of the joint portion;
A third side that connects the other end of the first side and the other end of the second side and is concave toward the inside;
A conductive pattern design method comprising:

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