JP2008306047A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which compensates the irregularity of characteristics of a surface side structure of a semiconductor device in processing of the back side. <P>SOLUTION: A measurement of a gate threshold voltage is made for each unit of FET structure after forming a plurality of units of FET structure on a wafer 26. When heating the back of the wafer 26 to activate an impurity, the laser irradiation 44 at a lowered heating temperature is carried out for an unit of FET structure 40 whose gate threshold voltage is low, and the laser irradiation 54 at an elevated temperature is carried out for an unit of FET structure 50 whose gate threshold voltage is high. The heating condition of impurity activation is set on the result of measurement of the gate threshold voltage, whereby, the irregularity of characteristics of an unit of FET structure is compensated, and the characteristics of semiconductor device can be made uniform. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a FET structure on the front surface side and a second conductivity type semiconductor layer on the back surface side, such as an IGBT, and a manufacturing method thereof. In particular, a heating step of activating the second conductivity type impurity implanted into the back surface side by injecting the second conductivity type impurity into the back surface side of the first conductivity type semiconductor wafer and applying heat to the back surface of the semiconductor wafer is provided. The present invention relates to a semiconductor device manufacturing method and a semiconductor device manufactured by the manufacturing method. More specifically, a method of manufacturing a semiconductor device having stable characteristics by locally adjusting the activation rate of the second conductivity type impurity using a heating method capable of locally controlling the temperature applied to the back surface of the semiconductor wafer. About.

Usually, a plurality of semiconductor devices of the above type are manufactured from a single wafer. That is, a plurality of semiconductor devices are manufactured in one wafer, and a plurality of semiconductor devices are manufactured by dicing along a boundary line between adjacent semiconductor devices. In this specification, an FET structure corresponding to one semiconductor device is defined as a unit FET structure. A plurality of unit FET structures are manufactured in one wafer, and a plurality of semiconductor devices can be manufactured from one wafer by dicing along a boundary line between adjacent unit FET structures.
In many cases, a plurality of cell blocks are formed in one semiconductor device. That is, in many cases, the unit FET structure constituting one semiconductor device is divided into a plurality of parts. In the present specification, each of the FET structures obtained by dividing the unit FET structure into a plurality is referred to as a divided FET structure. One unit FET structure is composed of a plurality of divided FET structures.
When a plurality of semiconductor devices in which one unit FET structure is composed of a plurality of divided FET structures are manufactured from one wafer, a plurality of divided FET structures are formed in one wafer. A plurality of unit FET structures to be configured are manufactured, and dicing is performed along a boundary line between adjacent unit FET structures.

Patent Documents 1 and 2 propose a technique in which a unit FET structure is composed of a plurality of divided FET structures.
In the technique of Patent Document 1, a gate pad is prepared for each divided FET structure. Then, the characteristics are measured for each divided FET structure. The gate pad of the divided FET structure whose normal characteristics are determined is connected to the gate voltage source. The gate pad of the split FET structure for which the abnormal characteristic is determined is connected to the ground voltage. As a result, it is possible to manufacture a semiconductor device that uses only a split FET structure with normal characteristics.
In the technique of Patent Document 2, the wiring connecting the gate voltage source and each divided FET structure is made independent from the other divided FET structures, and a fuse function that blows when an excessive current flows in each wiring is incorporated. In the split FET structure in which the gate insulating film is abnormal and the insulation is broken, an excessive gate current flows, so the fuse is blown. As a result, a semiconductor device in which only a normal divided FET structure is connected to the gate voltage source can be manufactured.

  As illustrated in FIG. 9, a plurality of semiconductor devices 72, 74, and 76 may be connected in parallel and used. In this case, if the ON voltages or the gate threshold voltages of the plurality of semiconductor devices 72, 74, and 76 are not uniform, there is a problem that current concentrates on the specific semiconductor device and the specific semiconductor device is overheated. For example, if the ON voltage or the gate threshold voltage of the semiconductor device 76 among the plurality of semiconductor devices 72, 74, 76 is lower than that of the other semiconductor devices 72, 74, an excessive current 66 is generated in the semiconductor device 76. A phenomenon occurs in which the semiconductor device 76 generates excessive heat. The gate threshold voltage of the semiconductor device has a negative temperature dependency. When the temperature of the semiconductor device 76 increases, the gate threshold voltage of the semiconductor device 76 further decreases. As a result, the current further concentrates on the semiconductor device 76, and eventually the semiconductor device 76 is overheated and destroyed. In order to avoid the occurrence of such a phenomenon, the semiconductor devices 72, 74, and 76 are required to have characteristics such as an ON voltage and a gate threshold voltage. There is a need for a technique for mass-producing a plurality of semiconductor devices having uniform characteristics.

  In the current mass production technology, the manufacturing process is strictly controlled to prevent the characteristics from changing in one wafer, and the characteristics from changing from wafer to wafer. Then, the characteristics are measured after manufacturing, and only the semiconductor device having the uniform characteristics is screened. With the current mass production technology, semiconductor devices with uneven characteristics are manufactured with a certain probability, and the problem remains that the yield is reduced by that amount.

  The same kind of problem also occurs when the unit FET structure is composed of a plurality of divided FET structures. In this case, the parallel circuit illustrated in FIG. 9 is configured in one semiconductor device. That is, in one semiconductor device, three divided FET structures 72, 74, and 76 are connected in parallel. Also in this case, if the ON voltages or the gate threshold voltages of the plurality of divided FET structures 72, 74, and 76 are not uniform, current flows in a specific divided FET structure and the specific divided FET structure is overheated. Problems arise. For example, if the ON voltage of the divided FET structure 76 is lower than the ON voltages of the other divided FET structures 72 and 74 among the plurality of divided FET structures 72, 74, and 76, an excessive current 66 is generated in the divided FET structure 76. Flows and the split FET structure 76 generates excessive heat. The gate threshold voltage has a negative temperature dependency, and when the temperature of the split FET structure 76 rises, the gate threshold voltage of the split FET structure 76 further decreases. As a result, the current further concentrates on the split FET structure 76, and eventually the split FET structure 76 is overheated and destroyed. The split FET structures 72, 74, and 76 are required to have characteristics such as an ON voltage and a gate threshold voltage. There is a need for a technique for mass-producing a plurality of divided FET structures with uniform characteristics.

  According to the techniques of Patent Documents 1 and 2 described above, a semiconductor device using only a divided FET structure with uniform characteristics can be realized. However, even with this technique, it is inevitable that divided FET structures with irregular characteristics are manufactured at a constant ratio, and the divided FET structure corresponding to that amount is wasted.

Japanese Patent Application No. 11-288250 Japanese Patent Application No. 11-230534

  The present invention was created to solve the above-described problems. One object of the present invention is to provide a manufacturing method for mass-producing a plurality of semiconductor devices with uniform characteristics from a single semiconductor wafer with a high yield. Another object is to provide a manufacturing method for mass-producing a semiconductor device having the characteristics of the split FET structure with a high yield when manufacturing a semiconductor device having a plurality of split FET structures. is there. The present invention can also realize both the above-mentioned objects at the same time.

One invention of this application is provided with an FET structure (referring to a semiconductor structure constituting a field effect transistor) on the front surface side from one first conductive semiconductor wafer and on the back surface side. The present invention relates to a method of manufacturing a plurality of semiconductor devices including a second conductivity type semiconductor layer.
The manufacturing method of the present invention includes the following steps.
(1) A surface side manufacturing process for manufacturing a plurality of unit FET structures constituting one semiconductor device on the surface side of a semiconductor wafer;
(2) an implantation step of implanting a second conductivity type impurity on the back surface side of the semiconductor wafer;
(3) A measurement process for measuring at least one of on-voltage, on-resistance, and gate threshold voltage for each unit FET structure,
(4) A heating step of activating the second conductivity type impurities implanted in the implantation step by applying heat to the back surface of the semiconductor wafer.
In the present invention, in the heating step (4), the heating temperature was raised in the range corresponding to the unit FET structure where the measurement result obtained in the measurement step (3) was high, and the heating step was obtained in the measurement step (3). The heating temperature is lowered in the range corresponding to the unit FET structure having a low measurement result.
Moreover, among the above steps, the surface side manufacturing step (1), the measurement step (3), and the heating step (4) need to be performed in the order of description, whereas (2) the injection step ( What is necessary is just to be implemented before the heating process of 4). That is, impurities may be implanted before the measurement step (3), or impurities may be implanted after the measurement step (3). When measurement is performed before the impurity implantation step, the characteristics of the unipolar transistor formed of the FET structure formed on the surface side are measured, and the on-resistance or the gate threshold voltage can be measured. When measurement is performed after the bipolar transistor is formed by implanting impurities, the on-voltage or the gate threshold voltage can be measured.
Further, in the impurity implantation process, as a result, the impurity may be implanted into the back side of the semiconductor wafer, and the implantation direction is not limited. By controlling the implantation depth, impurities can be implanted from the front surface of the semiconductor wafer to the vicinity of the back surface of the semiconductor wafer.

In the above method, at least one of the on-voltage, the on-resistance, and the gate threshold voltage is measured for each unit FET structure before performing the heating step for activating the impurities. Therefore, the heating temperature applied in the heating process can be determined based on the measurement result, and the unevenness of the characteristics of the unit FET structure can be compensated. For example, in a unit FET structure with a high gate threshold voltage measurement result, current does not flow easily. Therefore, in the range corresponding to the unit FET structure, the activation rate of impurities is increased by raising the heating temperature. The characteristic that the gate threshold voltage of the FET structure is high and the current does not easily flow can be compensated by the phenomenon that the current easily flows by increasing the activation rate of the impurity. Conversely, in a unit FET structure with a low gate threshold voltage measurement result, the activation rate of impurities is lowered by lowering the heating temperature in a range corresponding to the unit FET structure. The characteristic that the gate threshold voltage of the FET structure is low and the current easily flows can be compensated by the phenomenon that the current does not easily flow by decreasing the impurity activation rate.
According to the method of the present invention, it is possible to mass-produce a plurality of semiconductor devices having uniform characteristics from a single semiconductor wafer with a high yield.

The present invention is also useful in the case of manufacturing a semiconductor device in which a unit FET structure constituting one semiconductor device is divided into a plurality of divided FET structures.
Another invention of the present application includes an FET structure on the front surface side from the first conductivity type semiconductor wafer (more precisely, an FET structure divided into a plurality of divided FET structures) and a second back surface side. The present invention relates to a method for manufacturing a semiconductor device including a conductive semiconductor layer.
The manufacturing method of the present invention includes the following steps.
(1) On the surface side of a semiconductor wafer, a surface side manufacturing process for manufacturing an FET structure that constitutes a semiconductor device by dividing it into a plurality of divided FET structures;
(2) an implantation step of implanting a second conductivity type impurity on the back surface side of the semiconductor wafer;
(3) A measurement process for measuring at least one of an on-voltage, an on-resistance, and a gate threshold voltage for each divided FET structure;
(4) A heating step for activating the second conductivity type impurities implanted in the implantation step by applying heat to the back surface of the semiconductor wafer.
In the present invention, in the heating step (4), the heating temperature was increased in the range corresponding to the high split FET structure in which the measurement result obtained in the measurement step (3) was high, and the heating step was obtained in the measurement step (3). The heating temperature is lowered in the range corresponding to the divided FET structure having a low measurement result.
In the present invention, the surface side manufacturing process (1), the measurement process (3), and the heating process (4) need to be performed in the order of description, whereas the (2) injection process is the heating process (4). It may be performed before the process. That is, impurities may be implanted before the measurement step (3), or impurities may be implanted after the measurement step (3). When measurement is performed before the impurity implantation step, the characteristics of the unipolar transistor formed of the FET structure formed on the surface side are measured, and the on-resistance or the gate threshold voltage can be measured. When measurement is performed after the bipolar transistor is formed by implanting impurities, the on-voltage or the gate threshold voltage can be measured. Similar to the first invention, in the impurity implantation step, the impurity may be implanted from the surface of the semiconductor wafer or from the back surface of the semiconductor wafer.

In the above method, at least one of the on-voltage, the on-resistance, and the gate threshold voltage is measured for each divided FET structure before performing the heating step for activating the impurities. Therefore, the heating temperature applied in the heating process can be determined based on the measurement result, and the unevenness of the characteristics of the divided FET structure can be compensated. For example, in a split FET structure with a high gate threshold voltage measurement result, current does not flow easily. Therefore, in the range corresponding to the divided FET structure, the activation rate of impurities is increased by raising the heating temperature. The characteristic that the gate threshold voltage of the FET structure is high and the current does not easily flow can be compensated by the phenomenon that the current easily flows by increasing the activation rate of the impurity. Conversely, in a split FET structure with a low gate threshold voltage measurement result, the impurity activation rate is lowered by lowering the heating temperature in a range corresponding to the split FET structure. The characteristic that the gate threshold voltage of the FET structure is low and the current easily flows can be compensated by the phenomenon that the current does not easily flow by decreasing the impurity activation rate.
According to the method of the present invention, it is possible to mass-produce semiconductor devices having the characteristics of the divided FET structure with a high yield.
In some cases, a plurality of semiconductor devices in which one unit FET structure is composed of a plurality of divided FET structures are manufactured from one wafer. In this case, by increasing the heating temperature in the range corresponding to the divided FET structure where the measurement result is high in a unit of one semiconductor wafer, and lowering the heating temperature in the range corresponding to the divided FET structure where the measurement result is low, A plurality of semiconductor devices having the characteristics of the divided FET structure and the characteristics of each semiconductor device can be manufactured with high yield. However, it is not indispensable to adjust the heating temperature in units of one semiconductor wafer. In one semiconductor device unit, the heating temperature is increased in the range corresponding to the divided FET structure in which the measurement results are high. By reducing the heating temperature in a range corresponding to a low split FET structure, a semiconductor device having the same split FET structure characteristics can be manufactured with high yield.

  In order to be able to measure the on-voltage or on-resistance for each divided FET structure, it is preferable to divide at least one of the front-side electrode and the back-side electrode corresponding to the divided FET structure. Then, by using the divided electrode, it becomes possible to measure the on-voltage or on-resistance for each divided FET structure.

  In order to be able to measure the gate threshold voltage for each divided FET structure, it is preferable to form a divided gate pad divided into a plurality of parts corresponding to the divided FET structure. Then, by using the divided gate pad, the gate threshold voltage can be measured for each divided FET structure.

  When dividing into a plurality of divided gate pads, when the semiconductor device is actually used, the same gate voltage is often applied to the plurality of divided gate pads. Therefore, it is preferable to arrange a plurality of divided gate pads densely so that a plurality of divided gate pads can be simultaneously connected to one wire. The mounting operation of the semiconductor device is facilitated.

The semiconductor device manufactured by the present invention also has a novel feature. The semiconductor device realized by the invention is a semiconductor device having a FET structure on the front surface side and a second conductivity type semiconductor layer on the back surface side, and the FET structure is divided into a plurality of divided FET structures. ing.
In the semiconductor device realized by the invention, the impurity conductivity of the second conductivity type semiconductor layer is high in the range corresponding to the divided FET structure in which at least one of the on-voltage, the on-resistance, and the gate threshold voltage is high. The impurity conductivity of the second conductivity type semiconductor layer is low in a range corresponding to a divided FET structure in which at least one of on-resistance and gate threshold voltage is low.

  The semiconductor device of the present invention has the characteristics of the divided FET structure. For example, when the method shown in FIG. 9 is used, the degree of current concentration in a specific divided FET structure can be reduced.

  According to the method of the present invention, unevenness of characteristics for each unit FET structure or divided FET structure can be compensated for in the manufacturing process. As a result, a semiconductor device having a unit FET structure or a divided FET structure with uniform characteristics can be manufactured with high yield.

The main features of the embodiments described below are first organized.
(Feature 1) The semiconductor device of the present invention is a vertical IGBT in which an emitter electrode is formed on the front surface and a collector electrode is formed on the back surface.
(Feature 2) In the heating step, the back surface of the semiconductor wafer is scanned with a laser beam. At least one of the intensity of the laser beam and the scanning speed is adjusted in conjunction with the irradiation position of the laser beam.

(First embodiment)
In the first embodiment, a plurality of semiconductor devices having uniform characteristics are manufactured from a single semiconductor wafer.
In FIG. 4, reference numeral 26 indicates a semiconductor wafer containing n-type impurities, and 34 semiconductor devices 80 are manufactured from one wafer 26. In this embodiment, 34 semiconductor devices 80 with uniform characteristics can be manufactured.
FIG. 1 schematically shows a longitudinal sectional structure of one semiconductor device 80. The semiconductor device 80 manufactured in the first embodiment is an IGBT (Insulated Gate Bipolar Transistor). As shown in FIG. 1, the semiconductor device 80 is manufactured from a semiconductor wafer 26 containing n-type impurities, includes a FET structure 20 on the front surface side, and a collector layer 14 in which p-type impurities are implanted on the back surface side. It has.

On the surface side of the semiconductor wafer 26, a body layer 8 containing p-type impurities is formed. At a position facing the surface of the body layer 8, an emitter region 6 (in the case of FIG. 1, divided into six parts) containing an n-type impurity in a high concentration is formed. Each emitter region 6 is separated from the drift layer 12 (the region remaining without being processed by the semiconductor wafer 26 functions as a drift layer) by the body layer 8. A trench 10 a is formed from the surface of each emitter region 6 to penetrate the emitter region 6 and the body layer 8 and reach the drift layer 12. The wall surface of each trench 10a is covered with a gate insulating film 10, and the gate electrode 4 is filled inside each trench 10a. The upper surface of the gate electrode 4 is covered with a gate insulating film 10. The gate insulating film 10 is shown thicker than it actually is. The emitter region 6, the body layer 8, the drift layer 12, the gate insulating film 10, and the gate electrode 4 form a structure 20 that realizes a field effect transistor (FET). That is, an FET structure 20 is formed that changes between a state in which the emitter region 6 and the drift layer 12 are conductive and a state in which the emitter region 6 and the drift layer 12 are not conductive, depending on the voltage applied to the gate electrode 4.
On the back side of the drift layer 12, a collector layer 14 activated by implanting p-type impurities is formed. A back electrode 16 is laminated on the lower surface of the collector layer 14. The back surface side electrode 16 is electrically connected to the collector layer 14 and operates as a collector electrode.

  As shown in FIG. 1, the FET structure 20 is divided into three divided FET structures 20a, 20b, and 20c. As shown in FIGS. 1 and 2, the gate electrode 4 of the split FET structure 20a is connected to the gate pad 22 by a gate wiring 18a. The gate electrode 4 of the split FET structure 20b is connected to the gate pad 22 by a gate wiring 18b. The gate electrode 4 of the split FET structure 20c is connected to the gate pad 22 by a gate wiring 18c. This embodiment is not intended to make the characteristics of the three divided FET structures 20a, 20b, and 20c uniform, but aims to make the characteristics of the 34 semiconductor devices 80 shown in FIG. 4 uniform. Three split FET structures 20a, 20b, and 20c are commonly connected to the gate pad 22.

  In the present embodiment, 34 FET structures 20 are formed on the surface side of the semiconductor wafer 26. In each gate electrode 4, in a cross section (not shown), a portion exposed to the surface without being covered with the surface-side electrode 2 is formed. Next, the surface side electrode 2 and the gate pad 20 are formed. Then, gate wirings 18a, 18b and 18c are formed. The gate wirings 18 a, 18 b, and 18 c are in contact with the gate wiring 4 and are in contact with the gate pad 22 at portions exposed on the surface. Next, p-type impurities are implanted from the back surface of the semiconductor wafer 26.

In this embodiment, after the implantation of the p-type impurity and prior to the application of heat to activate it, the gate threshold voltage of the semiconductor device 80 being manufactured is set to each of the 34 semiconductor devices 80. Measure about.
In the measurement process, the measurement probe is brought into contact with the front surface of the front surface side electrode 2 of each semiconductor device 80 and the back surface of the collector layer 14 (the back surface side electrode 16 is not yet formed) to complete the circuit of FIG. That is, the measurement probe to be brought into contact with the surface of the surface side electrode 2 is grounded. The measurement probe brought into contact with the surface of the collector layer 14 is connected to the positive electrode of the DC power supply 34 via the ammeter 32.
In this state, the measurement probe connected to the power source 30 capable of changing the voltage is brought into contact with the gate pad 22 of the semiconductor device 80 whose gate threshold voltage is to be measured. Initially, the voltage of the variable power supply 30 is lowered. Thereafter, the current flowing between the collector layer 14 and the surface side electrode 2 is measured by the ammeter 32, and the voltage of the variable voltage 30 is gradually increased. The voltage value of the variable voltage 30 is measured when the current detected by the ammeter 32 reaches a certain value Io. The voltage value becomes the gate threshold voltage of the semiconductor device 80.
The measurement probe to be brought into contact with the gate pad 22 is moved so as to make a round of the 34 semiconductor devices 80, and the above measurement is performed each time, whereby the gate threshold voltage is set for each of the 34 semiconductor devices 80. Can be measured.
In the measurement process, the surface-side electrodes 2 of the 34 semiconductor devices 80 may be continuous, or the collector layers 14 of the 34 semiconductor devices 80 may be continuous. Since only the semiconductor device 80 to which a voltage is applied to the gate pad 22 conducts in the measurement process, even if the surface side electrode 2 or the collector layer 14 is continuous, the gate threshold voltage of each semiconductor device 80 is continuous. Can be measured.

  In the measurement process, the p-type impurity implanted into the collector layer 14 is not activated, and the semiconductor device 80 being manufactured operates as a MOS. In the measurement process, the gate threshold voltage of the semiconductor device 80 operating as a MOS is measured.

In this embodiment, the temperature applied to the back surface for activating the impurities implanted into the collector layer 14 is determined for each semiconductor device 80 from the gate threshold voltage measured for each semiconductor device 80.
The semiconductor device 80 having a high gate threshold voltage has a characteristic that the collector-emitter current hardly flows. In this case, if the activation rate of the impurities implanted into the collector layer 14 is increased, the conductivity modulation phenomenon is activated and the collector-emitter current is likely to flow. On the other hand, the semiconductor device 80 having a low gate threshold voltage has a characteristic that a collector-emitter current easily flows. In this case, the conductivity modulation phenomenon that lowers the activation rate of the impurity implanted into the collector layer 14 becomes inactive, and it becomes difficult for the collector-emitter current to flow. If the conductivity of the FET structure on the front surface side is smaller than the design value, the conductivity modulation phenomenon that occurs on the back surface side is activated, whereby the current conduction characteristics of the entire semiconductor device 80 can be brought close to the design value. If the conductivity of the FET structure on the front surface side is larger than the design value, the current conduction characteristics of the entire semiconductor device 80 can be brought close to the design value by inactivating the conductivity modulation phenomenon that occurs on the back surface side. . As a result, the characteristics of 34 semiconductor devices 80 manufactured on one semiconductor wafer 26 can be made uniform.

In this embodiment, the back surface is irradiated with a laser beam to heat and activate the impurities implanted into the collector layer 14. FIG. 5 shows a process of irradiating the back surface of the semiconductor wafer 26 with a laser beam, and 49 indicates the size of the laser beam. The size of the laser beam 49 is smaller than that of the semiconductor wafer 26 and is approximately the same size as each semiconductor device 80. By scanning the laser beam along the scanning line 24, the entire back surface of the semiconductor wafer 26 can be heated. At this time, the intensity and / or scanning speed of the laser beam can be changed according to the position where the laser beam is irradiated. If the laser beam intensity is increased, the heating temperature in the range irradiated with the laser beam is raised. If the scanning speed is reduced, the heating temperature in the range irradiated with the laser beam is raised.
When irradiating the back surface of the semiconductor device 80 with the conductivity of the FET structure on the front surface side as designed, a standard design value laser beam intensity and a standard scanning speed are adopted. When irradiating the back surface of the semiconductor device 80 in which the gate threshold voltage lower than the design value is measured, a laser beam having a lower intensity than the standard design value or a scanning speed higher than the standard scanning speed is adopted. . FIG. 9 shows that the low-intensity or high-speed laser scan 44 is employed because the gate threshold voltage of the semiconductor device 80 manufactured at the position shown in FIG. 40 is low. When irradiating the back surface of the semiconductor device 80 in which the gate threshold voltage higher than the design value is measured, a laser beam having a higher intensity than the standard design value or a scan speed lower than the standard scan speed is adopted. . FIG. 9 shows that a laser scan 54 with high intensity or low speed is employed because the gate threshold voltage of the semiconductor device 80 manufactured at the position shown in FIG. 50 is high.
In this embodiment, the back surface side electrode 16 is formed after irradiating the back surface of the semiconductor wafer 26 with a laser beam to activate the impurities implanted into the collector layer 14. Thereafter, dicing is performed along a line passing between the unit FET structures 20 constituted by the three divided FET structures 20a, 20b, and 20c. Thus, 34 semiconductor devices 80 can be manufactured from one semiconductor wafer 26.

(Second embodiment)
In the second embodiment, a semiconductor device is manufactured in which the characteristics of the IGBT composed of the split FET structure on the front surface side and the collector layer on the back surface side are the same for the split FET structure divided into a plurality of parts. That is, the semiconductor device 90 whose characteristics do not change depending on the location in one semiconductor device is manufactured.
Also in this embodiment, as shown in FIG. 4, 34 semiconductor devices are manufactured from one semiconductor wafer 26. As shown in FIG. 1, one semiconductor device includes divided FET structures 20a, 20b, and 20c divided into three. A duplicate description of the events common to the first embodiment is omitted.
As shown in FIG. 6, the semiconductor device 90 of the present embodiment includes divided gate pads 20a, 20b, and 20c divided into three pieces. The divided gate pad 22a is connected to the divided FET structure 20a by a gate wiring 18a. The divided gate pad 22b is connected to the divided FET structure 20b by the gate wiring 18b. The divided gate pad 22c is connected to the divided FET structure 20c by the gate wiring 18c.

When the FET structure 20 constituting one semiconductor device 90 is divided into a plurality of FET structures, and the gate pad 22 is divided into a plurality of divided gate pads correspondingly, the first embodiment Similarly, the gate threshold voltage can be measured for each divided FET structure.
The threshold voltage of the divided FET structure 20a can be measured by measuring the threshold voltage by realizing the circuit of FIG. 3 by bringing the measurement probe brought into contact with the gate pad into contact with the divided gate pad 22a. Similarly, the threshold voltage of the split FET structure 20b can be measured by bringing the measurement probe into contact with the split gate pad 22b. The threshold voltage of the split FET structure 20c can be measured by bringing the measurement probe into contact with the split gate pad 22c.

Also in this embodiment, after measuring the threshold voltage for each divided FET structure, the back surface of the semiconductor wafer 26 is irradiated with a laser to activate the impurities implanted into the collector layer 14.
FIG. 7 exemplifies a change in the irradiation conditions when irradiating the back surface of the semiconductor wafer 26 with laser. In the case of FIG. 7, since the gate threshold voltage of the split FET structure 40a of the semiconductor device 90 manufactured at the position shown in FIG. 40 is low, the back surface of the position facing the split FET structure 40a has low strength or high speed. It shows that laser scanning is employed. Further, since the gate threshold voltage of the split FET structure 50b of the semiconductor device 90 manufactured at the position shown in FIG. 50 is high, a high intensity or low speed laser scan is employed on the back surface of the position facing the split FET structure 50b. It shows that
According to the present embodiment, in each of the divided regions divided in one semiconductor device 90, variations in the characteristics on the front surface side can be compensated on the back surface side, and the characteristics change depending on the position in the semiconductor device 90. The semiconductor device 90 that does not have to be manufactured can be manufactured.
At the same time, 34 semiconductor devices 90 with uniform characteristics can be manufactured from one semiconductor wafer 26.
In the present embodiment, manufacturing a plurality of semiconductor devices from one semiconductor wafer is also useful when only one semiconductor device is manufactured. Even when only one semiconductor device is manufactured, when it is necessary to manufacture a semiconductor device in which there is little variation in characteristics for each divided region and the characteristics do not change depending on the position in the semiconductor device, The technique of this embodiment is effective.

The semiconductor device 90 illustrated in FIG. 6 can be used by independently controlling the gate voltage applied to the gate pads 22a, 22b, and 22c. However, the gate voltage applied to the gate pads 22a, 22b, and 22c is commonly used. A controlled use is also possible. In this case, when one wire 90 is welded or soldered at one place, the welded place or soldered place 92 extends over all the gate pads 22a, 22b, 22c, and is welded or soldered at one place. Therefore, it is preferable that all the gate pads 22a, 22b, and 22c are connected to the wire 94 at a time. If the gate pads 22a, 22b, and 22c are arranged densely, all the gate pads 22a, 22b, and 22c are connected to the wire 94 at a time by welding or soldering at one place.
In the second embodiment, a semiconductor device 90 having a novel feature in the semiconductor device itself due to the manufacturing method is obtained. The semiconductor device manufactured in the second embodiment has an FET structure on the front surface side and a second conductivity type semiconductor layer on the back surface side, and the FET structure is divided into a plurality of divided FET structures. Has a structure. In the range corresponding to the divided FET structure in which at least one of the on-voltage, the on-resistance, and the gate threshold voltage is high, the second conductivity type semiconductor layer is manufactured to have a high impurity activity rate. In the range corresponding to the divided FET structure in which at least one of the resistance and the gate threshold voltage is low, the second conductivity type semiconductor layer is manufactured to have a low impurity activity rate. As a result, in the manufactured semiconductor device, the impurity conductivity of the second conductivity type semiconductor layer is high in the range corresponding to the divided FET structure in which at least one of the on-voltage, the on-resistance, and the gate threshold voltage is high. The impurity conductivity of the second conductivity type semiconductor layer is low in the range corresponding to the divided FET structure in which at least one of the voltage, the on-resistance, and the gate threshold voltage is low. Usually, there is a semiconductor device having a divided FET structure in which at least one of an on-voltage, an on-resistance, and a gate threshold voltage is low or high in the semiconductor device, but this corresponds to the characteristics of the divided FET structure. There are no semiconductor devices having different impurity activation rates of the second conductivity type semiconductor layer, and the semiconductor device 90 manufactured in the second embodiment has this novel feature.

(Third embodiment)
In the first example and the second example, the variation in the location of the FET structure formed on the surface side was measured by the gate threshold voltage. On the other hand, variation due to the location of the FET structure formed on the surface side can be recognized by measuring variation in on-resistance or on-voltage.
FIG. 8A shows a case where the surface-side electrode functioning as the emitter electrode is divided into a plurality according to the position in the semiconductor device. In this embodiment, the surface-side FET structure 20 is connected to a common gate pad 22, and does not operate independently for each of the divided FET structures 20a, 20b, and 20c, but operates at the same time.
When the measurement probe to be brought into contact with the surface-side electrode 2 is brought into contact with the divided surface-side electrode 2a to complete the circuit of FIG. 3, the on-resistance or the on-voltage of the divided FET structure 20a can be measured. Since the voltage is applied to the gate pad 22 and measured, the split FET structures 20b and 20c are conductive. However, the characteristic measured by the split surface side electrode 2a is the characteristic of the split FET structure 20a. If the surface side electrode is divided into a plurality of parts, the characteristics of each divided FET structure can be measured.

(Fourth embodiment)
As shown in FIG. 8B, the back side electrode may be divided into a plurality of pieces. Also in this case, the characteristics for each divided FET structure can be measured. In the case of this embodiment, after the back side electrode is divided into a plurality of parts, the characteristics of each divided FET structure are measured. Even if the laser beam is irradiated through the back side electrode, the impurity implanted into the collector layer 14 can be activated.

  The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. For example, the schematic diagram of the semiconductor device shown in FIGS. 1 and 2 does not limit the configuration. Any semiconductor device may be used as long as it is formed through a process of performing impurity activation by local heating for forming the collector layer, and can also be applied to a planar IGBT or the like.

It is a figure which shows typically the longitudinal cross-section of the semiconductor device of 1st Example. It is the figure which showed typically the surface structure of the semiconductor device of 1st Example. It is a circuit diagram which measures the gate threshold voltage of a semiconductor device. A layout when manufacturing a plurality of semiconductor devices from the wafer 26 is shown. It is the figure which showed a mode that heat processing conditions were adjusted with the position in a wafer in the process which irradiates a laser on the back surface of the wafer 26, and activates an impurity. It is the figure which showed typically the surface structure of the semiconductor device of 2nd Example. It is the figure which showed a mode that heat processing conditions were adjusted with the position in a wafer in the process which irradiates a laser on the back surface of the wafer of 2nd Example, and activates an impurity. (A) is a figure which shows typically the longitudinal cross-section of the semiconductor device of 3rd Example, (B) is a figure which shows typically the longitudinal cross-section of the semiconductor device of 4th Example. Problems when using semiconductor devices 72, 74, and 76 having uneven gate threshold voltages will be described.

Explanation of symbols

2... Surface side electrodes 2 a, 2 b, 2 c... Split surface side electrode 4... Gate electrode 6. Gate insulator 10a ... trench 12 ... drift layer 14 ... collector layer 16 ... back side electrodes 16a, 16b, 16c ... split back side electrodes 18a, 18b, 18c ... Gate wiring 20... Unit FET structure 20 a, 20 b, 20 c... Split FET structure 22... Gate pad 22 a, 22 b, 22 c. · Wafer 30 ··· Power source 32 ··· Ammeter 34 ··· DC power source 40 ··· Unit FET structure 40a · Split FET structure 44 · · · Laser scan 49 ··· Laser Beam 50 ... ・ Unit FET 50b ... split FET structure 54 ... laser scan 62 ... current 64 ... current 66 ... current 72 ... semiconductor device 74 ... semiconductor device 76 ... ..Semiconductor device 80... Semiconductor device 90... Semiconductor device 92... Welded or soldered point 94.

Claims (6)

A method of manufacturing a plurality of semiconductor devices having a FET structure on the front surface side and a second conductivity type semiconductor layer on the back surface side from a single first conductivity type semiconductor wafer,
A surface side manufacturing process for manufacturing a plurality of unit FET structures constituting one semiconductor device on the surface side of the semiconductor wafer;
An implantation step of implanting a second conductivity type impurity on the back side of the semiconductor wafer;
A measurement process for measuring at least one of an on-voltage, an on-resistance, and a gate threshold voltage for each unit FET structure;
A heating step of activating the second conductivity type impurities implanted in the implantation step by applying heat to the back surface of the semiconductor wafer;
In the heating step, the heating temperature is increased in the range corresponding to the unit FET structure where the measurement result in the measurement step is high, and the heating temperature is decreased in the range corresponding to the unit FET structure where the measurement result in the measurement step is low. ,
The surface side manufacturing process, the measurement process, and the heating process are performed in that order,
A method of manufacturing a plurality of semiconductor devices, wherein the implantation step is performed prior to the heating step. A method of manufacturing a semiconductor device having a FET structure on the front surface side and a second conductivity type semiconductor layer on the back surface side from a first conductivity type semiconductor wafer,
On the surface side of the semiconductor wafer, a surface side manufacturing process for dividing and manufacturing the FET structure constituting the semiconductor device into a plurality of divided FET structures,
An implantation step of implanting a second conductivity type impurity on the back side of the semiconductor wafer;
A measurement step of measuring at least one of an on-voltage, an on-resistance, and a gate threshold voltage for each divided FET structure;
A heating step of activating the second conductivity type impurities implanted in the implantation step by applying heat to the back surface of the semiconductor wafer;
In the heating step, the heating temperature is increased in the range corresponding to the divided FET structure where the measurement result in the measurement step is high, and the heating temperature is decreased in the range corresponding to the divided FET structure where the measurement result in the measurement step is low. ,
The surface side manufacturing process, the measurement process, and the heating process are performed in that order,
A method of manufacturing a semiconductor device, wherein the implantation step is performed prior to the heating step. At least one of the front surface side electrode and the back surface side electrode is a plurality of divided electrodes divided corresponding to the divided FET structure,
3. The manufacturing method according to claim 2, wherein in the measurement step, an on-voltage or an on-resistance is measured for each divided FET structure using the divided electrode. In the surface side manufacturing process, a divided gate pad that is divided into a plurality of parts corresponding to the divided FET structure is formed,
3. The manufacturing method according to claim 2, wherein in the measurement step, a gate threshold voltage is measured for each divided FET structure using the divided gate pad. A semiconductor device manufactured by the manufacturing method according to claim 4,
A semiconductor device, wherein the plurality of divided gate pads are arranged densely so that they can be simultaneously connected to one wire. A semiconductor device having a FET structure on the front side and a second conductivity type semiconductor layer on the back side,
The FET structure is divided into a plurality of divided FET structures;
In the range corresponding to the split FET structure in which at least one of the on-voltage, on-resistance, and gate threshold voltage is high, the impurity conductivity of the second conductivity type semiconductor layer is high. A semiconductor device characterized in that the impurity conductivity of the second conductivity type semiconductor layer is low in a range in which at least one type corresponds to a low divided FET structure.

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