JP2008305514A - Optical disk device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve low electric power and stable playback performance in playback of a signal recorded with recording cords in which two or more same codes are continued, in an optical disk device. <P>SOLUTION: In the optical disk device, digital signal processing is operated with 1/2 or less of a channel bit frequency by using a PR (a, b, c, d, e, f) property for an equalization property of a PRML decoding means, low electric power is reduced by reduction of an operation clock frequency and playback performance is improved by decreasing disturbance components caused by return. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an apparatus for reproducing recorded data from an optical disc on which data is recorded.

Currently, there is an optical disk as a medium on which information can be recorded and reproduced. In recent years, high recording density and high-speed reproduction due to an increase in capacity have been a problem in optical disks. As a method corresponding to this, a reproduction signal is sampled into a digital signal by an analog-digital converter, and a PRML (Partial Response Maximum Likelihood) method is used. It has been proposed to restore the recorded data with higher accuracy using digital signal processing or the like. Various methods have been proposed for reducing power consumption during high-speed playback when the number of consecutive identical codes represented by DVD and the like is 3 or more. (For example, see Patent Document 1)
JP 2003-36612 A

  As described in Patent Document 1, so far, signal processing is performed at a frequency half that of the channel bit frequency with regard to low power consumption during high-speed playback when the number of consecutive identical codes represented by DVD or the like is 3 or more. Realization by reducing the operating frequency of the signal processing circuit by half rate processing or the like has been studied. However, when the number of consecutive identical codes is 2 or more, the shortest signal frequency becomes 1/4 of the channel bit frequency. In this case, according to the sampling theorem, in sampling at a half of the channel bit frequency, there arises a problem that the signal level cannot be normally obtained due to the phase relationship between the signal and the sampling clock. In addition, if the required signal frequency band is defined by the Nyquist characteristic, the signal band increases by the increase in the shortest signal frequency, which increases the aliasing component, that is, the interference component due to sampling, thereby degrading the signal quality. There has been a problem of causing a decrease in PRML processing capacity.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide an optical disc apparatus with improved reproduction signal quality and PRML processing capability.

  The above object can be achieved, for example, by the invention described in the claims.

  The following is a brief description of an outline of typical inventions disclosed in the present application. In the present invention, a frequency unnecessary for reproduction of 1/4 or more of the channel bit frequency is obtained by analog equalization means having equalization characteristics for emphasizing a predetermined band of a reproduction signal and attenuating an unnecessary band in place of the low-frequency cutoff filter. The PR equivalent characteristic of the signal that attenuates the band signal and is input to the PRML decoding means is PR (a, b, c, d, e, f), particularly PR (2, 3, 4, 4, 3, 2). The frequency characteristic is adjusted by the digital equalization means so as to obtain the characteristic expressed by the above, and the interference component due to the aliasing is reduced.

  The present invention can improve the quality of the reproduction signal and the PRML processing capability.

  Hereinafter, embodiments of an optical disk device according to the present invention will be described in detail with reference to the drawings. However, the present invention is not limited thereto.

  In the following embodiment, the analog equalization means attenuates a signal in a frequency band equal to or higher than ¼ of the channel bit frequency, and the PR equivalent characteristic of the signal input to the PRML decoding means is expressed as PR (a, b, c, d, e, f), in particular, by adjusting the frequency characteristics by digital equalization means so that the characteristics expressed by PR (2, 3, 4, 4, 3, 2) are obtained.

  FIG. 1 is a block diagram of an optical disc apparatus according to an embodiment of the present invention. Hereinafter, an example of the reproducing operation of the present invention will be described with reference to FIG.

  A signal recorded on the optical disk 1 is read by the optical head 2 and supplied as a reproduction signal to the analog equalization circuit 3 to emphasize a predetermined band and attenuate an unnecessary band signal. Next, the analog equalization signal equalized by the analog equalization circuit 3 is sampled by the analog-digital converter 4 to generate a digital reproduction signal. Here, the sampling clock is supplied from the PLL circuit 7, and the PLL circuit 7 generates a synchronous clock from the output of the analog-digital converter 4. Here, the synchronous clock generated by the PLL circuit 7 is ½ of the channel bit frequency, whereby the operation speed of the analog-digital converter 4 can be reduced and the power consumption can be reduced.

Next, the operation of each unit will be described. First, the equalization characteristic in the analog equalization circuit 3 can be set from the outside. For example, it is set so as to attenuate an equivalent characteristic that attenuates a signal in a frequency band equal to or higher than ¼ of the channel bit frequency. The This is shown in FIG.
In FIG. 2, the solid line is the signal spectrum input to the analog equalization circuit 3, and the broken line is the spectrum of the signal output from the analog equalization circuit 3.

  As can be seen from FIG. 2, in particular, the signal spectrum in a frequency band of 1/4 or more of the channel bit frequency is attenuated so as to have a level of about −20 dB or less with respect to the low-frequency spectrum, for example. This signal is then sampled by the analog / digital converter 4. The signal spectrum at this time is shown in FIG. Hereinafter, in the diagram showing the spectrum, the horizontal axis represents the normalized frequency normalized by the channel bit frequency, and the vertical axis represents the normalized signal level normalized by the low frequency response of the spectrum.

  In FIG. 3, the solid line is the spectrum of the signal output from the analog equalization circuit 3, that is, the spectrum of the signal input to the analog-digital converter 4, and the analog-digital converter because the sampling clock is ½ of the channel bit frequency. A folded component of the signal sampled at 4 is generated, and the spectrum of the folded component is indicated by a broken line. In the spectrum of the aliasing component, a frequency component equal to or less than ¼ of the channel bit frequency cannot be separated from the frequency component of the required signal, and thus becomes a disturbing component for the signal used for demodulation.

  The digital reproduction signal sampled by the analog / digital converter 4 is equalized to a desired characteristic by a digital equalization circuit 5. Here, the digital equalization circuit 5 is supplied with a synchronous clock generated by the PLL circuit 7 and a frequency-divided synchronous clock obtained by dividing the synchronous clock by the frequency divider 8. Here, the frequency division ratio in the frequency divider 8 is set to 1 or more. Therefore, the digital equalization circuit 5 performs processing by converting a digital reproduction signal input at a synchronous clock cycle into parallel data of a divided synchronous clock using, for example, serial-parallel processing. Here, since the operation clock frequency is further reduced, the digital equalization circuit 5 can also achieve lower power than in the prior art.

  The equalization characteristic in the digital equalization circuit 5 is a characteristic in which the characteristic of the output signal is expressed by PR (a, b, c, d, e, f), particularly PR (2, 3, 4, 4, 3, 2). It is configured to be automatically equivalent so that Specifically, it is configured with an FIR (Finite Impulse Response) filter configuration, and the tap coefficient in the FIR filter is compared with the reference level based on the demodulation result in the PRML decoding circuit 6 in the next stage so that the difference is reduced. A so-called LMS method for updating the coefficient is used. Here, the frequency spectrum after the equivalent in the case of PR (2, 3, 4, 4, 3, 2) is shown by a solid line in FIG. The broken line in the figure is the spectrum of the aliasing component. The figure shows the characteristics when the parallel signal output from the digital equalization circuit 5 is converted into a signal sequence of the channel bit frequency by, for example, serial conversion and interpolation. As can be seen from the figure, in the PR (2, 3, 4, 4, 3, 2) characteristic, the necessary band can be suppressed to a band sufficiently smaller than ¼ of the channel bit frequency. This is to obtain a necessary signal component from a low frequency range. Therefore, as shown by the hatched portion in the figure, the interference component caused by the aliasing generated in the analog-digital converter 4 can be made sufficiently small. Stable signal performance can be realized without being affected.

  Next, the parallel signal equalized to a predetermined PR characteristic by the digital equalization circuit 5 is input to the PRML decoding circuit 6 and decoded using, for example, a Viterbi algorithm. The Viterbi algorithm used here has a configuration suitable for the PR characteristic, that is, a branch metric and a path metric are calculated according to the number of states determined by the PR characteristic, a signal path is selected on the memory, and a decoding result is obtained. Determine. In this PRML decoding circuit 6 as well as the digital equalization circuit 5, the frequency-synchronized clock divided by the frequency divider 8 is input and the parallel signal of the digital equalization circuit 5 is processed in parallel. The frequency can be reduced and low power can be realized.

  According to the embodiment described above, the power can be reduced by reducing the operation clock frequency in the digital signal processing circuit of the analog-digital converter, digital equalization circuit, and PRML decoding circuit, and PR (2, 3, 4, 4, 3, 2) Since the influence of interference components caused by aliasing due to sampling can be reduced with respect to signal components necessary for decoding, stable performance can be obtained.

  In the above embodiment, the PR equivalent characteristic in the digital equalization circuit is the PR (2, 3, 4, 4, 3, 2) characteristic, but the present invention is not limited to this.

  For example, FIG. 5 shows a spectrum of signal components necessary for decoding when the PR (a, b, c, d, e, f) characteristics are PR (1, 2, 3, 3, 2, 1) characteristics. As shown in FIG. 5, the PR (1, 2, 3, 3, 2, 1) characteristic is ¼ of the channel bit frequency compared with the PR (2, 3, 4, 4, 3, 2) characteristic. However, since the ideal frequency characteristic has few frequency components equal to or higher than ¼ of the channel bit frequency, the influence of aliasing can be reduced. At this time, if the automatic equalization target value in the digital equalization circuit 5 and the branch metric target value in the PRML decoding circuit 6 are set so as to match the PR (1, 2, 3, 3, 2, 1) characteristics, The same effect as the embodiment can be obtained. In other words, the present invention only needs to have PR (a, b, c, d, e, f) characteristics that can concentrate signal components necessary for decoding in a low frequency range, thereby reducing the power consumption of digital signal processing. It is possible to achieve both stable reproduction performance.

  As described above, the present invention uses the PR (a, b, c, d, e, f) characteristics to reproduce a signal recorded with a recording code in which the number of consecutive same codes is 2 or more. Digital signal processing can be operated at half or less of the channel bit frequency, and stable reproduction performance can be obtained.

  That is, according to the present invention, since the digital signal processing can be operated at half or less of the channel bit frequency even in the reproduction of the signal recorded with the recording code having the same number of continuous codes of 2 or more, the signal processing has low power. It is suitable for speeding up and speeding up, and by changing the PR equivalent characteristic to PR (a, b, c, d, e, f), particularly PR (2, 3, 4, 4, 3, 2) The aliasing component can be reduced to improve the quality of the reproduced signal and the PRML processing capability.

  As mentioned above, although this invention was demonstrated by the Example, this invention is not limited to what is shown by drawing and what is described in this specification. It will be apparent to those skilled in the art that various modifications can be made without departing from the scope of the present invention.

The block diagram which shows the 1st Example of this invention. The figure which shows the spectrum in an analog equivalent circuit. The figure which shows the spectrum in an analog digital converter. The figure which shows the spectrum in a digital equalization circuit. The figure which shows the spectrum in another PR characteristic.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Optical disk 2 Optical head 3 Analog equalization circuit 4 Analog-digital converter 5 Digital equalization circuit 6 PRML decoding circuit 7 PLL circuit 8 Dividing circuit

Claims (3)

An optical disk device for reproducing a signal recorded with a recording code in which the number of consecutive same codes is 2 or more on an optical disk,
Analog equalization means having equalization characteristics for emphasizing a predetermined band of a reproduction signal and attenuating an unnecessary band;
An analog-to-digital converter for analog-to-digital conversion of the analog equalized signal equalized by the analog equalization means;
Digital equalization means for adjusting the frequency characteristic of the reproduction signal digitized by the analog-digital converter to a predetermined frequency characteristic;
PRML decoding means for decoding the digital equalized signal equalized by the digital equalizing means using the PRML method,
The analog-to-digital conversion means performs sampling at a frequency half the channel bit frequency of the recording code, and the digital equalization means and the PRML decoding means operate at a frequency equal to or less than half the channel bit frequency. And an PR equivalent characteristic for the PRML decoding means is a characteristic expressed by PR (a, b, c, d, e, f). The optical disc apparatus according to claim 1,
An optical disc apparatus characterized in that the analog equalization means has an equivalent characteristic that attenuates a signal in a frequency band of ¼ or more of a channel bit frequency of a recording code. The optical disc apparatus according to claim 1 or 2,
An optical disc apparatus characterized in that a PR equivalent characteristic for the PRML decoding means is a characteristic expressed by PR (2, 3, 4, 4, 3, 2).

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