JP2008304308A - Semiconductor device inspecting method and semiconductor device - Google Patents

Semiconductor device inspecting method and semiconductor device Download PDF

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JP2008304308A
JP2008304308A JP2007151488A JP2007151488A JP2008304308A JP 2008304308 A JP2008304308 A JP 2008304308A JP 2007151488 A JP2007151488 A JP 2007151488A JP 2007151488 A JP2007151488 A JP 2007151488A JP 2008304308 A JP2008304308 A JP 2008304308A
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terminal
inspection
short
power supply
circuit
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Takuro Ikeda
卓郎 池田
Keitaro Deguchi
圭太朗 出口
Kenichi Hattori
健一 服部
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Panasonic Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To eliminate a cost increase, to prevent an inspecting jig from being damaged, and to inhibit an unstable inspection due to a fluctuation in a power supply voltage or a grounding voltage if a large current flows in the inspecting jig connected to a semiconductor element in the case where the large current flows to a power supply terminal or a grounding terminal of the semiconductor element when the semiconductor element is inspected. <P>SOLUTION: When the semiconductor element is inspected, the grounding voltage is applied to the terminal 6 unused for the inspection. Since a short-circuiting switch 8 is turned on by inputting an input signal for turning on a short-circuiting switch 8 to an input terminal 7 while short-circuiting the terminal 6 unused for the inspection and the grounding terminal 2, a current intended to flow to the grounding terminal 2 of the semiconductor element is distributed toward the terminal 6 unused for the inspection. When the inspection is conducted, the quantity of an absolute value of the current flowing to the grounding terminal of the semiconductor element is reduced, the inspecting jig is thereby prevented from being damaged, and the unstable inspection is inhibited. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体素子の検査についての半導体装置の検査方法および半導体装置に関する。   The present invention relates to a semiconductor device inspection method and a semiconductor device for inspection of a semiconductor element.

半導体素子を検査するとき、半導体素子と検査装置を、検査治具を介して接続する。この状態で、検査時に半導体素子の電源端子や接地端子に大電流が流れた場合、以下の二点の問題が発生する。一点目は、半導体素子と検査装置を接続している検査治具に、検査治具の許容電流量を越える大電流が流れ、検査治具が損傷するという問題である。二点目は、検査中に半導体素子の電源端子、あるいは接地端子に大電流が流れることで、半導体素子の電源端子、あるいは接地端子にかかる電圧が変動して検査が不安定になるという問題である。   When inspecting a semiconductor element, the semiconductor element and the inspection apparatus are connected via an inspection jig. In this state, when a large current flows through the power supply terminal and the ground terminal of the semiconductor element during inspection, the following two problems occur. The first problem is that a large current exceeding the allowable current amount of the inspection jig flows through the inspection jig connecting the semiconductor element and the inspection apparatus, and the inspection jig is damaged. The second problem is that a large current flows through the power supply terminal or ground terminal of the semiconductor element during the inspection, and the voltage applied to the power supply terminal or ground terminal of the semiconductor element fluctuates and the inspection becomes unstable. is there.

まず、一点目の問題を改善する一例として、特許文献1では、検査治具であるプローブカードのプローブ針に、ヒューズを電気的に接続している。特許文献1による上記問題の具体的な解決方法を以下に記載する。   First, as an example of improving the first problem, in Patent Document 1, a fuse is electrically connected to a probe needle of a probe card that is an inspection jig. A specific solution to the above problem according to Patent Document 1 will be described below.

プローブカードは、ウェハー上の半導体素子を検査する際に使用する検査治具である。ウェハー上の半導体素子と検査装置を、プローブカードを介して接続し、検査を実施している。この時、半導体素子の電源端子、接地端子、測定端子には、プローブ針が接触している。検査のときに検査装置から半導体素子へ送られる電流、または半導体素子から検査装置へ送られる電流は、必ずプローブ針を通過する。この構成で、半導体素子の電源端子や接地端子に接触するプローブ針に瞬時的に大電流が流れると、この電流がプローブ針の電流許容量を越えたとき、プローブ針の破壊や焼失、つまり検査治具の損傷が起き、検査ができなくなる問題があった。   The probe card is an inspection jig used when inspecting a semiconductor element on a wafer. Inspection is performed by connecting a semiconductor element on a wafer and an inspection device via a probe card. At this time, the probe needle is in contact with the power supply terminal, the ground terminal, and the measurement terminal of the semiconductor element. The current sent from the inspection device to the semiconductor element at the time of inspection or the current sent from the semiconductor element to the inspection device always passes through the probe needle. With this configuration, if a large current flows instantaneously through the probe needle that contacts the power supply terminal or ground terminal of the semiconductor element, the probe needle will be destroyed or burned out, that is, when the current exceeds the allowable current of the probe needle. There was a problem that jigs were damaged and inspection was impossible.

上記検査治具の損傷を防ぐため、特許文献1では、プローブ針に、電気的に接続されたヒューズを有している。半導体素子の電源端子や接地端子に大電流が流れようとしても、大電流はヒューズを介するため、プローブ針に電流が到達する前にヒューズが切断される。これにより、半導体素子に流れる大電流を物理的に遮断することができ、ひいてはプローブ針の破壊、つまり検査治具の損傷を抑制することができる。   In order to prevent the inspection jig from being damaged, Patent Document 1 has a fuse electrically connected to the probe needle. Even if a large current flows through the power supply terminal or the ground terminal of the semiconductor element, the large current passes through the fuse, so that the fuse is cut before the current reaches the probe needle. As a result, a large current flowing through the semiconductor element can be physically cut off, and as a result, destruction of the probe needle, that is, damage to the inspection jig can be suppressed.

次に、二点目の問題を改善する従来の方法として、半導体素子の電源端子、あるいは接地端子の数を増やすことが挙げられる。上記のように、検査する半導体素子の電源端子、あるいは接地端子の数を増やすことで、検査中に半導体素子の電源端子、あるいは接地端子に流れる電流を、複数の電源端子、あるいは接地端子に分散させることができる。これにより、半導体素子の電源端子、あるいは接地端子に大電流が流れることによる、電源端子、あるいは接地端子にかかる電圧の変動を抑え、ひいては検査を安定化することができる。
特開2002−124552号公報(P2002−124552A)
Next, a conventional method for improving the second problem is to increase the number of power supply terminals or ground terminals of the semiconductor element. As described above, by increasing the number of power supply terminals or ground terminals of the semiconductor element to be inspected, the current flowing through the power supply terminal or ground terminal of the semiconductor element during inspection is distributed to a plurality of power supply terminals or ground terminals. Can be made. Thereby, fluctuations in voltage applied to the power supply terminal or the ground terminal due to a large current flowing through the power supply terminal or the ground terminal of the semiconductor element can be suppressed, and the inspection can be stabilized.
JP 2002-124552 A (P2002-124552A)

一点目の問題を解決するための上記従来手法では、過電流が流れようとしてヒューズが切断した時点で検査を続けることができなくなるため、検査効率の低下を招く。また、検査端子毎にヒューズ等の過電流防止素子が必要になるため、プローブカード上に搭載する素子数が増大し、これに伴ってプローブカード、すなわち検査治具の製作にかかるコストが増大するといった課題がある。   In the conventional method for solving the first problem, since it becomes impossible to continue the inspection when the fuse is cut because an overcurrent flows, the inspection efficiency is lowered. Further, since an overcurrent prevention element such as a fuse is required for each inspection terminal, the number of elements mounted on the probe card increases, and accordingly, the cost for manufacturing the probe card, that is, the inspection jig increases. There is a problem.

また、二点目の問題を解決するための上記従来手法では、半導体素子上に電源パッド、あるいは接地パッドを複数設置する事となり、これにより半導体素子の面積増大と、面積増大に伴う単価の増大という課題がある。   Further, in the above conventional method for solving the second problem, a plurality of power supply pads or ground pads are installed on the semiconductor element, thereby increasing the area of the semiconductor element and the unit price accompanying the increase in area. There is a problem.

したがって、本発明の目的は、半導体素子の検査時に、半導体素子の電源端子または接地端子に大電流が流れようとして、そこに繋がる検査治具に大電流が流れた場合、コストをかけることなく、検査治具の損傷や、電源電圧または接地電圧が変動することで検査が不安定になることを抑制することができる半導体装置の検査方法および半導体装置を提供することである。   Accordingly, the object of the present invention is to inspect a semiconductor element, when a large current flows through a power supply terminal or a ground terminal of the semiconductor element, and when a large current flows through an inspection jig connected thereto, without incurring costs, An object of the present invention is to provide a semiconductor device inspection method and a semiconductor device capable of suppressing an inspection jig from becoming unstable due to damage to an inspection jig or fluctuations in power supply voltage or ground voltage.

上記課題を解決するために、本発明の第1の発明の半導体装置の検査方法は、半導体素子の電源端子に電源電圧を印加し、半導体素子の接地端子に接地電圧を印加して検査する際、半導体素子の検査に使用しない端子と接地端子とを短絡することで、接地端子に流れる電流を、検査に使用しない端子と接地端子とに分散させることを特徴とする。   In order to solve the above-described problem, the inspection method for a semiconductor device according to the first aspect of the present invention applies an inspection by applying a power supply voltage to the power supply terminal of the semiconductor element and applying a ground voltage to the ground terminal of the semiconductor element. The terminal that is not used for the inspection of the semiconductor element and the ground terminal are short-circuited, whereby the current flowing through the ground terminal is distributed to the terminal that is not used for the inspection and the ground terminal.

上記の構成によれば、検査時に半導体素子の接地端子に流れる電流を、検査に使用しない端子と接地端子とに分散させ、過電流による検査治具の損傷を防ぎ、あるいは半導体装置の検査不安定を抑止することができる。   According to the above configuration, the current flowing through the ground terminal of the semiconductor element at the time of inspection is distributed to the terminal not used for inspection and the ground terminal to prevent the inspection jig from being damaged due to overcurrent, or the semiconductor device is unstable in inspection. Can be suppressed.

第2の発明の半導体装置の検査方法は、半導体素子の電源端子に電源電圧を印加し、半導体素子の接地端子に接地電圧を印加して検査する際、半導体素子の検査に使用しない端子と電源端子とを短絡することで、電源端子に流れる電流を、検査に使用しない端子と電源端子とに分散させることを特徴とする。   According to a second aspect of the present invention, there is provided a method of inspecting a semiconductor device in which a power supply voltage is applied to a power supply terminal of a semiconductor element and a ground voltage is applied to a ground terminal of the semiconductor element. By short-circuiting the terminals, the current flowing through the power supply terminals is distributed to the terminals not used for inspection and the power supply terminals.

上記の構成によれば、検査時に半導体素子の電源端子に流れる電流を、検査に使用しない端子と電源端子とに分散させ、過電流による検査治具の損傷を防ぎ、あるいは半導体装置の検査不安定を抑止することができる。   According to the above configuration, the current flowing through the power supply terminal of the semiconductor element during the inspection is distributed to the terminal and the power supply terminal that are not used for the inspection, thereby preventing the inspection jig from being damaged due to overcurrent or the instability of the semiconductor device inspection. Can be suppressed.

第3の発明の半導体装置は、半導体素子の電源端子に電源電圧を印加し、半導体素子の接地端子に接地電圧を印加して検査する半導体装置であって、検査に使用しない端子を少なくとも1端子有し、検査に使用しない端子と接地端子との間に配設され、外部からの入力信号によってON/OFFする短絡スイッチ回路を少なくとも1組有し、短絡スイッチ回路をON/OFFする入力信号を印加するための入力端子を少なくとも1端子有し、検査時、検査に使用しない端子に接地電位を印加し、入力端子に、短絡スイッチ回路をONする入力信号を入力して短絡スイッチ回路をONさせることで、検査に使用しない端子と接地端子とを短絡することを特徴とする。   According to a third aspect of the present invention, there is provided a semiconductor device in which a power supply voltage is applied to a power supply terminal of a semiconductor element and a ground voltage is applied to a ground terminal of the semiconductor element for inspection, and at least one terminal not used for the inspection is provided. And at least one short-circuit switch circuit that is disposed between a terminal that is not used for inspection and a ground terminal and that is turned on / off by an external input signal, and that has an input signal for turning on / off the short-circuit switch circuit. At least one input terminal to apply, at the time of inspection, a ground potential is applied to a terminal not used for inspection, and an input signal for turning on the short-circuit switch circuit is input to the input terminal to turn on the short-circuit switch circuit Thus, the terminal not used for the inspection and the ground terminal are short-circuited.

上記の構成によれば、半導体素子を検査する時、入力端子に、短絡スイッチ回路をONする入力信号を入力して短絡スイッチ回路をONさせることにより、検査に使用しない端子を接地端子と短絡する。検査に使用しない端子を接地端子と短絡している時は、検査に使用しない端子を検査装置あるいは検査治具等を通して接地電位に固定する。これにより、検査時に半導体素子の接地端子に流れる電流を、検査に使用しない端子と接地端子とに分散させ、過電流による検査治具の損傷を防ぎ、あるいは半導体装置の検査不安定を抑止することができる。   According to the above configuration, when a semiconductor element is inspected, an input signal for turning on the short-circuit switch circuit is input to the input terminal to turn on the short-circuit switch circuit, thereby short-circuiting a terminal not used for inspection with the ground terminal. . When a terminal not used for inspection is short-circuited to the ground terminal, the terminal not used for inspection is fixed to the ground potential through an inspection device or an inspection jig. As a result, the current that flows to the ground terminal of the semiconductor element during inspection is distributed to the terminals that are not used for inspection and the ground terminal to prevent damage to the inspection jig due to overcurrent, or to suppress instability of inspection of the semiconductor device. Can do.

第4の発明の半導体装置は、半導体素子の電源端子に電源電圧を印加し、半導体素子の接地端子に接地電圧を印加して検査する半導体装置であって、検査に使用しない端子を少なくとも1端子有し、検査に使用しない端子と接地端子との間に配設され、外部からの入力信号によってON/OFFする短絡スイッチ回路を少なくとも1組有し、短絡スイッチ回路をON/OFFする入力信号を供給するための出力端子と、接地端子に繋がる配線に電流が流れることによって、接地端子に繋がる配線のある1点と他の1点間の電位差が印加される入力端子と、一定の基準電圧が印加される入力端子とを有する電圧検知回路を少なくとも1組有し、検査時、検査に使用しない端子に接地電位を印加し、電圧検知回路において、接地端子に繋がる配線のある1点と他の1点間の電位差が、一定の基準電圧以上の電圧値になると、電圧検知回路の出力端子から、短絡スイッチ回路をONする信号を出力して短絡スイッチ回路をONさせることで、検査に使用しない端子と接地端子とを短絡することを特徴とする。   According to a fourth aspect of the present invention, there is provided a semiconductor device in which a power supply voltage is applied to a power supply terminal of a semiconductor element and a ground voltage is applied to a ground terminal of the semiconductor element, and the semiconductor device is inspected. And at least one short-circuit switch circuit that is disposed between a terminal that is not used for inspection and a ground terminal and that is turned on / off by an external input signal, and that has an input signal for turning on / off the short-circuit switch circuit. An output terminal for supplying, an input terminal to which a potential difference between one point of the wiring connected to the ground terminal and the other point is applied by a current flowing through the wiring connected to the ground terminal, and a constant reference voltage Wiring that has at least one set of voltage detection circuit having an input terminal applied, applies a ground potential to a terminal that is not used for inspection at the time of inspection, and is connected to the ground terminal in the voltage detection circuit When the potential difference between one point and the other point is equal to or higher than a certain reference voltage, a signal to turn on the short-circuit switch circuit is output from the output terminal of the voltage detection circuit to turn on the short-circuit switch circuit. Thus, the terminal not used for the inspection and the ground terminal are short-circuited.

上記の構成によれば、半導体素子を検査する時、電圧検知回路により、接地端子に繋がる配線のある1点と他の1点間の電位差が、一定の基準電圧以上の電圧値になることで、短絡スイッチ回路をONさせることにより、検査に使用しない端子を接地端子と短絡する。検査に使用しない端子を接地端子と短絡している時は、検査に使用しない端子を検査装置あるいは検査治具等を通して接地電位に固定する。これにより、検査時に半導体素子の接地端子に流れる電流を、検査に使用しない端子と接地端子とに分散させ、過電流による検査治具の損傷を防ぎ、あるいは半導体装置の検査不安定を抑止することができる。   According to the above configuration, when the semiconductor element is inspected, the voltage detection circuit allows the potential difference between one point of the wiring connected to the ground terminal and the other point to be a voltage value equal to or higher than a certain reference voltage. By turning on the short-circuit switch circuit, a terminal not used for inspection is short-circuited with the ground terminal. When a terminal not used for inspection is short-circuited to the ground terminal, the terminal not used for inspection is fixed to the ground potential through an inspection device or an inspection jig. As a result, the current that flows to the ground terminal of the semiconductor element during inspection is distributed to the terminals that are not used for inspection and the ground terminal to prevent damage to the inspection jig due to overcurrent, or to suppress instability of inspection of the semiconductor device. Can do.

第5の発明の半導体装置は、半導体素子の電源端子に電源電圧を印加し、半導体素子の接地端子に接地電圧を印加して検査する半導体装置であって、検査に使用しない端子を少なくとも1端子有し、検査に使用しない端子と接地端子との間に配設され、外部からの入力信号によってON/OFFする短絡スイッチ回路を少なくとも1組有し、短絡スイッチ回路をON/OFFする入力信号を供給するための出力端子を有する短絡スイッチ回路制御回路を半導体素子内に有し、検査時に、検査に使用しない端子に接地電位を印加し、短絡スイッチ回路制御回路を動作させ、短絡スイッチ回路制御回路の出力端子から、短絡スイッチ回路をONする信号を出力して短絡スイッチ回路をONさせることで、検査に使用しない端子と半導体素子の接地端子とを短絡することを特徴とする。   According to a fifth aspect of the present invention, there is provided a semiconductor device in which a power supply voltage is applied to a power supply terminal of a semiconductor element and a ground voltage is applied to a ground terminal of the semiconductor element for inspection, and at least one terminal not used for the inspection is provided. And at least one short-circuit switch circuit that is disposed between a terminal that is not used for inspection and a ground terminal and that is turned on / off by an external input signal, and that has an input signal for turning on / off the short-circuit switch circuit. A short-circuit switch circuit control circuit having an output terminal for supply is provided in the semiconductor element, and at the time of inspection, a ground potential is applied to a terminal not used for inspection, the short-circuit switch circuit control circuit is operated, and the short-circuit switch circuit control circuit By outputting a signal to turn on the short-circuit switch circuit from the output terminal of, and turning on the short-circuit switch circuit, the terminals not used for inspection and the grounding of the semiconductor element Characterized in that it short-circuits the child.

上記の構成によれば、半導体素子を検査する時、短絡スイッチ回路制御回路により短絡スイッチ回路をONさせることにより、検査に使用しない端子を接地端子と短絡する。検査に使用しない端子を接地端子と短絡している時は、検査に使用しない端子を検査装置あるいは検査治具等を通して接地電位に固定する。これにより、検査時に半導体素子の接地端子に流れる電流を、検査に使用しない端子と接地端子とに分散させ、過電流による検査治具の損傷を防ぎ、あるいは半導体装置の検査不安定を抑止することができる。   According to the above configuration, when the semiconductor element is inspected, the short-circuit switch circuit is turned on by the short-circuit switch circuit control circuit, thereby short-circuiting a terminal not used for the inspection with the ground terminal. When a terminal not used for inspection is short-circuited to the ground terminal, the terminal not used for inspection is fixed to the ground potential through an inspection device or an inspection jig. As a result, the current that flows to the ground terminal of the semiconductor element during inspection is distributed to the terminals that are not used for inspection and the ground terminal to prevent damage to the inspection jig due to overcurrent, or to suppress instability of inspection of the semiconductor device. Can do.

第6の発明の半導体装置は、半導体素子の電源端子に電源電圧を印加し、半導体素子の接地端子に接地電圧を印加して検査する半導体装置であって、検査に使用しない端子を少なくとも1端子有し、検査に使用しない端子と電源端子との間に配設され、外部からの入力信号によってON/OFFする短絡スイッチ回路を少なくとも1組有し、短絡スイッチ回路をON/OFFする入力信号を印加するための入力端子を少なくとも1端子有し、検査時、検査に使用しない端子に電源電位を印加し、入力端子に、短絡スイッチ回路をONする入力信号を入力して短絡スイッチ回路をONさせることで、検査に使用しない端子と電源端子とを短絡することを特徴とする。   According to a sixth aspect of the present invention, there is provided a semiconductor device in which a power supply voltage is applied to a power supply terminal of a semiconductor element and a ground voltage is applied to a ground terminal of the semiconductor element for inspection, and at least one terminal not used for the inspection is provided. And having at least one set of short-circuit switch circuits that are arranged between a terminal not used for inspection and a power supply terminal and are turned on / off by an external input signal, and an input signal for turning on / off the short-circuit switch circuit. It has at least one input terminal for applying, and at the time of inspection, a power supply potential is applied to a terminal not used for inspection, and an input signal for turning on the short-circuit switch circuit is input to the input terminal to turn on the short-circuit switch circuit. Thus, the terminal not used for the inspection and the power supply terminal are short-circuited.

上記の構成によれば、半導体素子を検査する時、入力端子に、短絡スイッチ回路をONする入力信号を入力して短絡スイッチ回路をONさせることにより、検査に使用しない端子を電源端子と短絡する。検査に使用しない端子を電源端子と短絡している時は、検査に使用しない端子を検査装置あるいは検査治具等を通して電源電位に固定する。これにより、検査時に半導体素子の電源端子に流れる電流を、検査に使用しない端子と電源端子とに分散させ、過電流による検査治具の損傷を防ぎ、あるいは半導体装置の検査不安定を抑止することができる。   According to the above configuration, when a semiconductor element is inspected, an input signal for turning on the short-circuit switch circuit is input to the input terminal to turn on the short-circuit switch circuit, thereby short-circuiting a terminal not used for inspection with the power supply terminal. . When a terminal not used for inspection is short-circuited with the power supply terminal, the terminal not used for inspection is fixed to the power supply potential through an inspection device or an inspection jig. As a result, the current flowing through the power supply terminal of the semiconductor element during the inspection is distributed to the terminal and the power supply terminal that are not used for the inspection, thereby preventing the inspection jig from being damaged due to overcurrent, or suppressing the unstable inspection of the semiconductor device. Can do.

第7の発明の半導体装置は、半導体素子の電源端子に電源電圧を印加し、半導体素子の接地端子に接地電圧を印加して検査する半導体装置であって、検査に使用しない端子を少なくとも1端子有し、検査に使用しない端子と電源端子との間に配設され、外部からの入力信号によってON/OFFする短絡スイッチ回路を少なくとも1組有し、短絡スイッチ回路をON/OFFする入力信号を供給するための出力端子と、電源端子に繋がる配線に電流が流れることによって、電源端子に繋がる配線のある1点と他の1点間の電位差が印加される入力端子と、一定の基準電圧が印加される入力端子とを有する電圧検知回路を少なくとも1組有し、検査時、検査に使用しない端子に電源電位を印加し、電圧検知回路において、電源端子に繋がる配線のある1点と他の1点間の電位差が、一定の基準電圧以上の電圧値になると、電圧検知回路の出力端子から、短絡スイッチ回路をONする信号を出力して短絡スイッチ回路をONさせることで、検査に使用しない端子と電源端子とを短絡することを特徴とする。   According to a seventh aspect of the present invention, there is provided a semiconductor device in which a power supply voltage is applied to a power supply terminal of a semiconductor element and a ground voltage is applied to a ground terminal of the semiconductor element for inspection, and at least one terminal not used for inspection is provided. And having at least one set of short-circuit switch circuits that are arranged between a terminal not used for inspection and a power supply terminal and are turned on / off by an external input signal, and an input signal for turning on / off the short-circuit switch circuit. An output terminal for supplying, an input terminal to which a potential difference between one point of the wiring connected to the power supply terminal and another point is applied by a current flowing through the wiring connected to the power supply terminal, and a constant reference voltage Wiring that has at least one set of voltage detection circuit having an input terminal applied, applies a power supply potential to a terminal that is not used for inspection at the time of inspection, and connects to the power supply terminal in the voltage detection circuit When the potential difference between one point and the other point is equal to or higher than a certain reference voltage, a signal to turn on the short-circuit switch circuit is output from the output terminal of the voltage detection circuit to turn on the short-circuit switch circuit. Thus, the terminal not used for the inspection and the power supply terminal are short-circuited.

上記の構成によれば、半導体素子を検査する時、電圧検知回路により、電源端子に繋がる配線のある1点と他の1点間の電位差が、一定の基準電圧以上の電圧値になることで、短絡スイッチ回路をONさせることにより、検査に使用しない端子を電源端子と短絡する。検査に使用しない端子を電源端子と短絡している時は、検査に使用しない端子を検査装置あるいは検査治具等を通して電源電位に固定する。これにより、検査時に半導体素子の電源端子に流れる電流を、検査に使用しない端子と電源端子とに分散させ、過電流による検査治具の損傷を防ぎ、あるいは半導体装置の検査不安定を抑止することができる。   According to the above configuration, when inspecting a semiconductor element, the voltage detection circuit causes the potential difference between one point with a wiring connected to the power supply terminal and the other point to be a voltage value equal to or higher than a certain reference voltage. By turning on the short circuit switch circuit, a terminal not used for inspection is short-circuited with the power supply terminal. When a terminal not used for inspection is short-circuited with the power supply terminal, the terminal not used for inspection is fixed to the power supply potential through an inspection device or an inspection jig. As a result, the current flowing through the power supply terminal of the semiconductor element during the inspection is distributed to the terminal and the power supply terminal that are not used for the inspection, thereby preventing the inspection jig from being damaged due to overcurrent, or suppressing the unstable inspection of the semiconductor device. Can do.

第8の発明の半導体装置は、半導体素子の電源端子に電源電圧を印加し、半導体素子の接地端子に接地電圧を印加して検査する半導体装置であって、検査に使用しない端子を少なくとも1端子有し、検査に使用しない端子と電源端子との間に配設され、外部からの入力信号によってON/OFFする短絡スイッチ回路を少なくとも1組有し、短絡スイッチ回路をON/OFFする入力信号を供給するための出力端子を有する短絡スイッチ回路制御回路を半導体素子内に有し、検査時に、検査に使用しない端子に電源電位を印加し、短絡スイッチ回路制御回路を動作させ、短絡スイッチ回路制御回路の出力端子から、短絡スイッチ回路をONする信号を出力して短絡スイッチ回路をONさせることで、検査に使用しない端子と半導体素子の電源端子とを短絡することを特徴とする。   According to an eighth aspect of the present invention, there is provided a semiconductor device in which a power supply voltage is applied to a power supply terminal of a semiconductor element and a ground voltage is applied to a ground terminal of the semiconductor element for inspection, and at least one terminal not used for the inspection is provided. And having at least one set of short-circuit switch circuits that are arranged between a terminal not used for inspection and a power supply terminal and are turned on / off by an external input signal, and an input signal for turning on / off the short-circuit switch circuit. A short-circuit switch circuit control circuit having an output terminal for supply is provided in the semiconductor element, and at the time of inspection, a power supply potential is applied to a terminal not used for inspection to operate the short-circuit switch circuit control circuit. By outputting a signal to turn on the short-circuit switch circuit from the output terminal, and turning on the short-circuit switch circuit, the terminals not used for inspection and the power supply of the semiconductor element Characterized in that it short-circuits the child.

上記の構成によれば、半導体素子を検査する時、短絡スイッチ回路制御回路により短絡スイッチ回路をONさせることにより、検査に使用しない端子を電源端子と短絡する。検査に使用しない端子を電源端子と短絡している時は、検査に使用しない端子を検査装置あるいは検査治具等を通して電源電位に固定する。これにより、検査時に半導体素子の電源端子に流れる電流を、検査に使用しない端子と電源端子とに分散させ、過電流による検査治具の損傷を防ぎ、あるいは半導体装置の検査不安定を抑止することができる。   According to the above configuration, when the semiconductor element is inspected, the short-circuit switch circuit is turned on by the short-circuit switch circuit control circuit, thereby short-circuiting a terminal not used for the inspection with the power supply terminal. When a terminal not used for inspection is short-circuited with the power supply terminal, the terminal not used for inspection is fixed to the power supply potential through an inspection device or an inspection jig. As a result, the current flowing through the power supply terminal of the semiconductor element during the inspection is distributed to the terminal and the power supply terminal that are not used for the inspection, thereby preventing the inspection jig from being damaged due to overcurrent, or suppressing the unstable inspection of the semiconductor device. Can do.

第9の発明の半導体装置は、半導体素子の電源端子に電源電圧を印加し、半導体素子の接地端子に接地電圧を印加して検査する半導体装置であって、検査に使用しない端子を少なくとも2端子有し、検査に使用しない一方の端子と接地端子との間および検査に使用しない他方の端子と電源端子との間にそれぞれ配設され、外部からの入力信号によってON/OFFする短絡スイッチ回路を少なくとも2組有し、短絡スイッチ回路をON/OFFする入力信号を印加するための入力端子を少なくとも1端子有し、検査時、検査に使用しない一方の端子に接地電位を印加し、かつ検査に使用しない他方の端子に電源電位を印加し、入力端子に、短絡スイッチ回路をONする入力信号を入力して短絡スイッチ回路をONさせることで、検査に使用しない一方の端子と接地端子とを短絡し、かつ検査に使用しない他方の端子と電源端子とを短絡することを特徴とする。   According to a ninth aspect of the present invention, there is provided a semiconductor device in which a power supply voltage is applied to a power supply terminal of a semiconductor element and a ground voltage is applied to a ground terminal of the semiconductor element for inspection, and at least two terminals that are not used for inspection are inspected. A short-circuit switch circuit that is disposed between one terminal that is not used for inspection and the ground terminal and between the other terminal that is not used for inspection and the power supply terminal, and is turned ON / OFF by an external input signal At least two sets, at least one input terminal for applying an input signal for turning ON / OFF the short-circuit switch circuit, at the time of inspection, a ground potential is applied to one terminal not used for inspection, and for inspection The power supply potential is applied to the other terminal that is not used, and the input signal that turns on the short-circuit switch circuit is input to the input terminal to turn on the short-circuit switch circuit. There one terminal and to short-circuit the grounding terminal, and wherein the short-circuiting the other terminal and the power supply pins not used for testing.

上記の構成によれば、半導体素子を検査する時、入力端子に、短絡スイッチ回路をONする入力信号を入力して短絡スイッチ回路をONさせることにより、検査に使用しない一方の端子と接地端子とを短絡し、かつ検査に使用しない他方の端子と電源端子とを短絡する。検査に使用しない一方の端子を接地端子と短絡している時は、検査に使用しない一方の端子を検査装置あるいは検査治具等を通して接地電位に固定し、検査に使用しない他方の端子を電源端子と短絡している時は、検査に使用しない他方の端子を検査装置あるいは検査治具を通して電源電位に固定する。これにより、検査時に半導体素子の接地端子に流れる電流を、検査に使用しない一方の端子と接地端子とに分散させ、半導体素子の電源端子に流れる電流を、検査に使用しない他方の端子と電源端子とに分散させ、過電流による検査治具の損傷を防ぎ、あるいは半導体装置の検査不安定を抑止することができる。   According to the above configuration, when a semiconductor element is inspected, an input signal for turning on the short-circuit switch circuit is input to the input terminal to turn on the short-circuit switch circuit. And the other terminal not used for inspection and the power supply terminal are short-circuited. When one terminal that is not used for inspection is short-circuited with the ground terminal, one terminal that is not used for inspection is fixed to the ground potential through an inspection device or inspection jig, and the other terminal that is not used for inspection is the power supply terminal. When the terminal is short-circuited, the other terminal not used for the inspection is fixed to the power supply potential through the inspection device or the inspection jig. As a result, the current flowing through the ground terminal of the semiconductor element during inspection is distributed to one terminal and the ground terminal that are not used for inspection, and the current flowing through the power supply terminal of the semiconductor element is distributed to the other terminal and the power supply terminal that are not used for inspection. It is possible to prevent the inspection jig from being damaged due to overcurrent, or to suppress the instability of inspection of the semiconductor device.

本発明の半導体装置によれば、半導体素子を制御して、半導体素子の検査をすることで、検査時に検査装置から半導体素子の電源端子あるいは接地端子へ送られる電流、または半導体素子の電源端子あるいは接地端子から検査装置へ送られる電流を、電源端子あるいは接地端子と検査に使用しない端子とに分散させ、電源端子あるいは接地端子に流れる電流の絶対値を下げることができる。以上のことから、
(1)検査効率が低下することなく、かつ検査治具の製作にかかるコストの増大がなく、大電流による検査治具の損傷を抑止することができる。(上記従来手法の一点目の問題解決)
(2)半導体素子中の電源パッドあるいは接地パッドの数を増やすことなく、半導体素子の電源端子あるいは接地端子にかかる電圧の変動を抑えて検査を安定化することができる。(上記従来手法の二点目の問題解決)
According to the semiconductor device of the present invention, by controlling the semiconductor element and inspecting the semiconductor element, the current sent from the inspection apparatus to the power supply terminal or ground terminal of the semiconductor element at the time of inspection, or the power supply terminal of the semiconductor element or The current sent from the ground terminal to the inspection device can be distributed to the power supply terminal or the ground terminal and the terminal not used for the inspection, thereby reducing the absolute value of the current flowing through the power supply terminal or the ground terminal. From the above,
(1) The inspection efficiency is not lowered, the cost for manufacturing the inspection jig is not increased, and damage to the inspection jig due to a large current can be suppressed. (Solving the first problem of the conventional method)
(2) Without increasing the number of power supply pads or ground pads in the semiconductor element, it is possible to suppress the fluctuation of the voltage applied to the power supply terminal or ground terminal of the semiconductor element and stabilize the inspection. (Solving the second problem of the above conventional method)

(実施の形態1)
本発明の実施の形態1について、図1を用いて説明する。実施の形態1は、半導体素子の接地端子に流れようとする大電流の絶対値量を減らすことができる発明の実施形態である。
(Embodiment 1)
Embodiment 1 of the present invention will be described with reference to FIG. The first embodiment is an embodiment of the invention that can reduce the absolute value of a large current that flows to the ground terminal of a semiconductor element.

図1において、1は検査する半導体素子の電源端子を示し、2は検査する半導体素子の接地端子を示す。検査時、半導体素子に電源を供給するため、検査装置から検査治具を介して半導体素子の接地端子2に接地電位を印加し、半導体素子の電源端子1に電源電圧を印加している。また、5は半導体素子の検査時に、検査信号を入力する端子を示し、6は半導体素子の検査時に、検査に使用しない端子を示し、13は検査信号の入力に対する半導体素子の内部回路3の演算結果を出力する端子を示す。検査不使用端子6は少なくとも1端子有する。検査信号入力端子5と検査信号出力端子13と検査不使用端子6は、I/O回路4を介して半導体素子の内部回路3に接続される。   In FIG. 1, 1 indicates a power supply terminal of a semiconductor element to be inspected, and 2 indicates a ground terminal of the semiconductor element to be inspected. At the time of inspection, in order to supply power to the semiconductor element, a ground potential is applied from the inspection apparatus to the ground terminal 2 of the semiconductor element via an inspection jig, and a power supply voltage is applied to the power supply terminal 1 of the semiconductor element. Reference numeral 5 denotes a terminal for inputting an inspection signal when inspecting the semiconductor element. Reference numeral 6 denotes a terminal which is not used for inspection when inspecting the semiconductor element. Reference numeral 13 denotes an operation of the internal circuit 3 of the semiconductor element for the input of the inspection signal. Indicates the terminal that outputs the result. The inspection non-use terminal 6 has at least one terminal. The inspection signal input terminal 5, the inspection signal output terminal 13, and the inspection nonuse terminal 6 are connected to the internal circuit 3 of the semiconductor element via the I / O circuit 4.

さらに、外部からの入力信号によってON/OFFする短絡スイッチ回路を少なくとも1組有する。すなわち検査不使用端子6と接地端子2との間に短絡スイッチ8を設け、検査モード信号入力端子7の信号切替わりによって、短絡スイッチ8がONして検査不使用端子6と接地端子2が短絡するように回路を構成する。入力端子7は少なくとも1端子有し、短絡スイッチ8をON/OFFする入力信号を印加する。   Furthermore, at least one set of short-circuit switch circuits that are turned ON / OFF by an external input signal is provided. That is, the short-circuit switch 8 is provided between the inspection non-use terminal 6 and the ground terminal 2, and the short-circuit switch 8 is turned on by the signal switching of the inspection mode signal input terminal 7 and the inspection non-use terminal 6 and the ground terminal 2 are short-circuited. The circuit is configured as follows. The input terminal 7 has at least one terminal and applies an input signal for turning on / off the short-circuit switch 8.

なお、短絡スイッチ8をONしたとき、配線9−配線10間のインピーダンスを可能な限り低くできるように短絡スイッチ8を構成し、短絡スイッチ8がONする極性は、短絡スイッチ8の構成によって決まる。   When the short-circuit switch 8 is turned on, the short-circuit switch 8 is configured so that the impedance between the wiring 9 and the wiring 10 can be as low as possible, and the polarity of the short-circuit switch 8 being turned on is determined by the configuration of the short-circuit switch 8.

上記構成の半導体素子を検査するとき、接地端子2に大電流が流れるケースは、以下の2通りである。
(1)内部回路3の接地端子に繋がる配線12、またはI/O回路の接地端子に繋がる配線11,14から、接地端子2に向かって大電流が流れるケース
(2)接地端子2から、内部回路3の接地端子2に繋がる配線12、またはI/O回路の接地端子に繋がる配線11,14に向かって大電流が流れるケース
上記のいずれかのケースで、半導体素子の接地端子2と、あるいは接地端子2に接続される検査治具へと大電流が流れようとしたとき、下記に示す本実施形態の回路動作によって、上記の大電流を抑えることができる。
When the semiconductor element having the above configuration is inspected, there are two cases where a large current flows through the ground terminal 2 as follows.
(1) Case where a large current flows from the wiring 12 connected to the ground terminal of the internal circuit 3 or the wirings 11 and 14 connected to the ground terminal of the I / O circuit toward the ground terminal 2 (2) From the ground terminal 2 to the internal A case in which a large current flows toward the wiring 12 connected to the ground terminal 2 of the circuit 3 or the wirings 11 and 14 connected to the ground terminal of the I / O circuit. In any of the above cases, the ground terminal 2 of the semiconductor element, or When a large current is about to flow to the inspection jig connected to the ground terminal 2, the large current can be suppressed by the circuit operation of the present embodiment described below.

上記構成の半導体素子を検査する際、ウェハー上の半導体素子と検査装置を、プローブカード等の検査治具を介して接続し、検査を実施する。この際、あらかじめ検査不使用端子6に、検査装置から検査治具を介して接地電位を印加し、さらに検査モード信号入力端子7に、検査装置から短絡スイッチ8をONするための任意の信号レベルを入力して短絡スイッチ8をON状態にし、検査不使用端子6と接地端子2を短絡させておく。このとき、検査不使用端子6の状態が変化しても半導体素子の内部回路3が誤動作しないように内部回路3を制御しておく。   When inspecting the semiconductor element having the above configuration, the inspection is performed by connecting the semiconductor element on the wafer and the inspection apparatus via an inspection jig such as a probe card. At this time, a ground potential is applied to the inspection non-use terminal 6 from the inspection device via the inspection jig in advance, and an arbitrary signal level is applied to the inspection mode signal input terminal 7 for turning on the short-circuit switch 8 from the inspection device. Is input to turn on the short-circuit switch 8 so that the inspection non-use terminal 6 and the ground terminal 2 are short-circuited. At this time, the internal circuit 3 is controlled so that the internal circuit 3 of the semiconductor element does not malfunction even if the state of the inspection non-use terminal 6 changes.

この状態で、半導体素子検査時、接地端子2に大電流が流れようとした場合、接地端子2と、検査装置から検査治具を介して接地電位が印加されている検査不使用端子6とが短絡されているため、電流を接地端子2と検査不使用端子6に分散することができる。上記の動作により、検査時、半導体素子の接地端子2に流れる電流の絶対値量を減少させることができ、ひいては検査治具の損傷を防ぎ、検査の不安定化を抑止することができる。なお、上記の実施形態は、接地端子2に流れようとする電流を分散できる検査不使用端子6の数が多いほど効果が大きくなる。
(実施の形態2)
本発明の実施の形態2について、図2を用いて説明する。実施の形態2は、半導体素子の接地端子に流れようとする大電流の絶対値量を減らすことができる発明の実施形態である。
In this state, when a large current is about to flow to the ground terminal 2 during the semiconductor element inspection, the ground terminal 2 and the inspection non-use terminal 6 to which the ground potential is applied from the inspection device via the inspection jig are provided. Since it is short-circuited, the current can be distributed to the ground terminal 2 and the inspection non-use terminal 6. With the above-described operation, the absolute value of the current flowing through the ground terminal 2 of the semiconductor element can be reduced during the inspection, and thus the inspection jig can be prevented from being damaged and the inspection can be prevented from becoming unstable. Note that the above-described embodiment becomes more effective as the number of test non-use terminals 6 that can disperse the current to flow to the ground terminal 2 increases.
(Embodiment 2)
A second embodiment of the present invention will be described with reference to FIG. The second embodiment is an embodiment of the invention that can reduce the absolute value of a large current that flows to the ground terminal of a semiconductor element.

図2において、1は検査する半導体素子の電源端子を示し、2は検査する半導体素子の接地端子を示す。検査時、半導体素子に電源を供給するため、検査装置から検査治具を介して半導体素子の接地端子2に接地電位を印加し、半導体素子の電源端子1に電源電圧を印加している。また、5は半導体素子の検査時に、検査信号を入力する端子を示し、6は半導体素子の検査時に、検査に使用しない端子を示し、13は検査信号の入力に対する半導体素子の内部回路3の演算結果を出力する端子を示す。検査不使用端子6は少なくとも1端子有する。検査信号入力端子5と検査信号出力端子13と検査不使用端子6は、I/O回路4を介して半導体素子の内部回路3に接続される。   In FIG. 2, 1 indicates a power supply terminal of a semiconductor element to be inspected, and 2 indicates a ground terminal of the semiconductor element to be inspected. At the time of inspection, in order to supply power to the semiconductor element, a ground potential is applied from the inspection apparatus to the ground terminal 2 of the semiconductor element via an inspection jig, and a power supply voltage is applied to the power supply terminal 1 of the semiconductor element. Reference numeral 5 denotes a terminal for inputting an inspection signal when inspecting the semiconductor element. Reference numeral 6 denotes a terminal which is not used for inspection when inspecting the semiconductor element. Reference numeral 13 denotes an operation of the internal circuit 3 of the semiconductor element for the input of the inspection signal. Indicates the terminal that outputs the result. The inspection non-use terminal 6 has at least one terminal. The inspection signal input terminal 5, the inspection signal output terminal 13, and the inspection nonuse terminal 6 are connected to the internal circuit 3 of the semiconductor element via the I / O circuit 4.

さらに、外部からの入力信号によってON/OFFする短絡スイッチ回路を少なくとも1組有する。すなわち検査不使用端子6と接地端子2との間に短絡スイッチ8を設け、短絡スイッチ8のスイッチ切替え信号入力端子と、電圧検知回路15の出力端子18とを接続する。電圧検知回路15の出力端子18は、短絡スイッチ8をON/OFFする入力信号が供給される。   Furthermore, at least one set of short-circuit switch circuits that are turned ON / OFF by an external input signal is provided. That is, the short-circuit switch 8 is provided between the inspection non-use terminal 6 and the ground terminal 2, and the switch switching signal input terminal of the short-circuit switch 8 and the output terminal 18 of the voltage detection circuit 15 are connected. An output signal for turning ON / OFF the short-circuit switch 8 is supplied to the output terminal 18 of the voltage detection circuit 15.

また、電圧検知回路15は少なくとも1組有し、接地端子2に繋がる配線に電流が流れることによって、接地端子2に繋がる配線のある1点と他の1点間の電位差が印加される入力端子と、一定の基準電圧が印加される入力端子とを有する。この場合、接地端子2に電流が流れることによって生じる配線16−配線17間の電位差を検出し、配線16−配線17間の電位差が一定値以上の電圧値19(以下、検知電圧値と記載)になったとき、電圧検知回路の出力端子18に出力する信号レベルが反転するようになっている。電圧検知回路の出力端子18から出力される信号切替わりによって、短絡スイッチ8がONして配線9と配線10が短絡し、これにより検査不使用端子6と接地端子2が短絡する。   The voltage detection circuit 15 has at least one set, and an input terminal to which a potential difference between one point of the wiring connected to the ground terminal 2 and another point is applied when a current flows through the wiring connected to the ground terminal 2. And an input terminal to which a constant reference voltage is applied. In this case, a potential difference between the wiring 16 and the wiring 17 caused by a current flowing through the ground terminal 2 is detected, and a voltage value 19 in which the potential difference between the wiring 16 and the wiring 17 is equal to or greater than a certain value (hereinafter referred to as a detection voltage value). The signal level output to the output terminal 18 of the voltage detection circuit is inverted. By switching the signal output from the output terminal 18 of the voltage detection circuit, the short-circuit switch 8 is turned ON and the wiring 9 and the wiring 10 are short-circuited, whereby the inspection non-use terminal 6 and the ground terminal 2 are short-circuited.

なお、短絡スイッチ8をONしたとき、配線9−配線10間のインピーダンスを可能な限り低くできるように短絡スイッチ8を構成し、短絡スイッチ8がONする極性は、短絡スイッチ8の構成によって決まり、電圧検知回路の出力端子18から出力される信号の極性は電圧検知回路15の構成によって決まり、電圧検知回路の出力端子18から出力される信号レベルが反転する際の検知電圧値19もまた、電圧検知回路15の構成によって決まる。   In addition, when the short-circuit switch 8 is turned on, the short-circuit switch 8 is configured so that the impedance between the wiring 9 and the wiring 10 can be as low as possible, and the polarity of the short-circuit switch 8 being turned on is determined by the configuration of the short-circuit switch 8, The polarity of the signal output from the output terminal 18 of the voltage detection circuit is determined by the configuration of the voltage detection circuit 15, and the detection voltage value 19 when the signal level output from the output terminal 18 of the voltage detection circuit is inverted is also a voltage. It depends on the configuration of the detection circuit 15.

上記構成の半導体素子を検査するとき、接地端子2に大電流が流れるケースは、以下の2通りである。
(1)内部回路3の接地端子に繋がる配線12、またはI/O回路の接地端子に繋がる配線11,14から、接地端子2に向かって大電流が流れるケース
(2)接地端子2から、内部回路3の接地端子2に繋がる配線12、またはI/O回路の接地端子に繋がる配線11,14に向かって大電流が流れるケース
上記のいずれかのケースで、半導体素子の接地端子2と、あるいは接地端子2に接続される検査治具へと大電流が流れようとしたとき、下記に示す本実施形態の回路動作によって、上記の大電流を抑えることができる。
When the semiconductor element having the above configuration is inspected, there are two cases where a large current flows through the ground terminal 2 as follows.
(1) Case where a large current flows from the wiring 12 connected to the ground terminal of the internal circuit 3 or the wirings 11 and 14 connected to the ground terminal of the I / O circuit toward the ground terminal 2 (2) From the ground terminal 2 to the internal A case in which a large current flows toward the wiring 12 connected to the ground terminal 2 of the circuit 3 or the wirings 11 and 14 connected to the ground terminal of the I / O circuit. In any of the above cases, the ground terminal 2 of the semiconductor element, or When a large current is about to flow to the inspection jig connected to the ground terminal 2, the large current can be suppressed by the circuit operation of the present embodiment described below.

上記構成の半導体素子を検査する際、ウェハー上の半導体素子と検査装置を、プローブカード等の検査治具を介して接続し、検査を実施する。この際、あらかじめ検査不使用端子6に、検査装置から検査治具を介して接地電位を印加する。また、
(配線16−配線17間の電位差)<(検知電圧値19)
のとき、短絡スイッチ8はOFF状態である。このとき、検査不使用端子6の状態が変化しても半導体素子の内部回路3が誤動作しないように内部回路3を制御しておく。
When inspecting the semiconductor element having the above configuration, the inspection is performed by connecting the semiconductor element on the wafer and the inspection apparatus via an inspection jig such as a probe card. At this time, a ground potential is applied in advance to the inspection non-use terminal 6 from the inspection device via the inspection jig. Also,
(Potential difference between wiring 16 and wiring 17) <(detection voltage value 19)
At this time, the short-circuit switch 8 is in an OFF state. At this time, the internal circuit 3 is controlled so that the internal circuit 3 of the semiconductor element does not malfunction even if the state of the inspection non-use terminal 6 changes.

この状態で、半導体素子検査時、接地端子2に大電流が流れようとした場合、配線16−配線17間に電流が流れ、
(配線16−配線17間に流れる電流値)×(配線16−配線17間の抵抗値)
で決まる配線16−配線17間の電位差が、検知電圧値19以上になったとき、電圧検知回路15の出力端子18から出力される信号レベルが反転して短絡スイッチ8がON状態になり、接地端子2と、検査装置から検査治具を介して接地電位が印加されている検査不使用端子6とが短絡され、接地端子2に流れようとする大電流を接地端子2と検査不使用端子6に分散することができる。上記の動作により、検査時、半導体素子の接地端子2に流れる電流の絶対値量を減少させることができ、ひいては検査治具の損傷を防ぎ、検査の不安定化を抑止することができる。なお、上記の実施形態は、接地端子2に流れようとする電流を分散できる検査不使用端子6の数が多いほど効果が大きくなる。
(実施の形態3)
本発明の実施の形態3について、図3を用いて説明する。実施の形態3は、半導体素子の接地端子2に流れようとする大電流の絶対値量を減らすことができる発明の実施形態である。
In this state, when a large current is about to flow to the ground terminal 2 during the semiconductor element inspection, a current flows between the wiring 16 and the wiring 17,
(Current value flowing between wiring 16 and wiring 17) × (resistance value between wiring 16 and wiring 17)
When the potential difference between the wiring 16 and the wiring 17 determined by (1) becomes equal to or higher than the detection voltage value 19, the signal level output from the output terminal 18 of the voltage detection circuit 15 is inverted and the short-circuit switch 8 is turned on, and the grounding The terminal 2 and the inspection non-use terminal 6 to which the ground potential is applied from the inspection device through the inspection jig are short-circuited, and a large current that tends to flow to the ground terminal 2 is caused to flow to the ground terminal 2 and the inspection non-use terminal 6. Can be dispersed. With the above-described operation, the absolute value of the current flowing through the ground terminal 2 of the semiconductor element can be reduced during the inspection, and thus the inspection jig can be prevented from being damaged and the inspection can be prevented from becoming unstable. Note that the above-described embodiment becomes more effective as the number of test non-use terminals 6 that can disperse the current to flow to the ground terminal 2 increases.
(Embodiment 3)
A third embodiment of the present invention will be described with reference to FIG. The third embodiment is an embodiment of the invention that can reduce the absolute value of a large current that flows to the ground terminal 2 of the semiconductor element.

図3において、1は検査する半導体素子の電源端子を示し、2は検査する半導体素子の接地端子を示す。検査時、半導体素子に電源を供給するため、検査装置から検査治具を介して半導体素子の接地端子2に接地電位を印加し、半導体素子の電源端子1に電源電圧を印加している。また、5は半導体素子の検査時に、検査信号を入力する端子を示し、6は半導体素子の検査時に、検査に使用しない端子を示し、13は検査信号の入力に対する半導体素子の内部回路3の演算結果を出力する端子を示す。検査不使用端子6は少なくとも1端子有する。検査信号入力端子5と検査信号出力端子13と検査不使用端子6は、I/O回路4を介して半導体素子の内部回路3に接続される。   In FIG. 3, 1 indicates a power supply terminal of a semiconductor element to be inspected, and 2 indicates a ground terminal of the semiconductor element to be inspected. At the time of inspection, in order to supply power to the semiconductor element, a ground potential is applied from the inspection apparatus to the ground terminal 2 of the semiconductor element via an inspection jig, and a power supply voltage is applied to the power supply terminal 1 of the semiconductor element. Reference numeral 5 denotes a terminal for inputting an inspection signal when inspecting the semiconductor element. Reference numeral 6 denotes a terminal which is not used for inspection when inspecting the semiconductor element. Reference numeral 13 denotes an operation of the internal circuit 3 of the semiconductor element for the input of the inspection signal. Indicates the terminal that outputs the result. The inspection non-use terminal 6 has at least one terminal. The inspection signal input terminal 5, the inspection signal output terminal 13, and the inspection nonuse terminal 6 are connected to the internal circuit 3 of the semiconductor element via the I / O circuit 4.

さらに、外部からの入力信号によってON/OFFする短絡スイッチ回路を少なくとも1組有する。すなわち検査不使用端子6と接地端子2との間に短絡スイッチ8を設け、短絡スイッチ8のスイッチ切替え信号入力端子と、内部回路に組み込まれる短絡スイッチ制御回路20の出力端子21とを接続する。短絡スイッチ制御回路20の出力端子21は、短絡スイッチ8をON/OFFする入力信号が供給される。   Furthermore, at least one set of short-circuit switch circuits that are turned ON / OFF by an external input signal is provided. That is, the short-circuit switch 8 is provided between the inspection non-use terminal 6 and the ground terminal 2, and the switch switching signal input terminal of the short-circuit switch 8 is connected to the output terminal 21 of the short-circuit switch control circuit 20 incorporated in the internal circuit. An output signal for turning ON / OFF the short-circuit switch 8 is supplied to the output terminal 21 of the short-circuit switch control circuit 20.

また、短絡スイッチ制御回路20は、内部回路のレジスタ設定を切替えることによって、短絡スイッチ制御回路の出力端子21に出力する信号レベルが反転するようになっている。短絡スイッチ制御回路の出力端子21から出力される信号切替わりによって、短絡スイッチ8がONして配線9と配線10が短絡し、これにより検査不使用端子6と接地端子2が短絡する。   The short-circuit switch control circuit 20 is configured to invert the signal level output to the output terminal 21 of the short-circuit switch control circuit by switching the register setting of the internal circuit. By switching the signal output from the output terminal 21 of the short-circuit switch control circuit, the short-circuit switch 8 is turned ON and the wiring 9 and the wiring 10 are short-circuited, whereby the inspection non-use terminal 6 and the ground terminal 2 are short-circuited.

なお、短絡スイッチ8をONしたとき、配線9−配線10間のインピーダンスを可能な限り低くできるように短絡スイッチ8を構成し、短絡スイッチ8がONする極性は、短絡スイッチ8の構成によって決まり、短絡スイッチ制御回路の出力端子21から出力される信号の極性は短絡スイッチ制御回路20の構成によって決まる。   In addition, when the short-circuit switch 8 is turned on, the short-circuit switch 8 is configured so that the impedance between the wiring 9 and the wiring 10 can be as low as possible, and the polarity of the short-circuit switch 8 being turned on is determined by the configuration of the short-circuit switch 8, The polarity of the signal output from the output terminal 21 of the short-circuit switch control circuit is determined by the configuration of the short-circuit switch control circuit 20.

上記構成の半導体素子を検査するとき、接地端子2に大電流が流れるケースは、以下の2通りである。
(1)内部回路3の接地端子に繋がる配線12、またはI/O回路の接地端子に繋がる配線11,14から、接地端子2に向かって大電流が流れるケース
(2)接地端子2から、内部回路3の接地端子2に繋がる配線12、またはI/O回路の接地端子に繋がる配線11,14に向かって大電流が流れるケース
上記のいずれかのケースで、半導体素子の接地端子2と、あるいは接地端子2に接続される検査治具へと大電流が流れようとしたとき、下記に示す本発明の回路動作によって、上記の大電流を抑えることができる。
When the semiconductor element having the above configuration is inspected, there are two cases where a large current flows through the ground terminal 2 as follows.
(1) Case where a large current flows from the wiring 12 connected to the ground terminal of the internal circuit 3 or the wirings 11 and 14 connected to the ground terminal of the I / O circuit toward the ground terminal 2 (2) From the ground terminal 2 to the internal A case in which a large current flows toward the wiring 12 connected to the ground terminal 2 of the circuit 3 or the wirings 11 and 14 connected to the ground terminal of the I / O circuit. In any of the above cases, the ground terminal 2 of the semiconductor element, or When a large current is about to flow to the inspection jig connected to the ground terminal 2, the large current can be suppressed by the circuit operation of the present invention described below.

上記構成の半導体素子を検査する際、ウェハー上の半導体素子と検査装置を、プローブカード等の検査治具を介して接続し、検査を実施する。この際、あらかじめ検査不使用端子6に、検査装置から検査治具を介して接地電位を印加し、さらに半導体装置の内部回路のレジスタ設定を切替えて短絡スイッチ制御回路の出力端子21から出力される信号を反転させ、短絡スイッチ8をON状態にし、検査不使用端子6と接地端子2を短絡しておく。このとき、検査不使用端子6の状態が変化しても半導体素子の内部回路3が誤動作しないように内部回路3を制御しておく。   When inspecting the semiconductor element having the above configuration, the inspection is performed by connecting the semiconductor element on the wafer and the inspection apparatus via an inspection jig such as a probe card. At this time, a ground potential is applied to the inspection non-use terminal 6 in advance from the inspection device via the inspection jig, and the register setting of the internal circuit of the semiconductor device is switched and output from the output terminal 21 of the short-circuit switch control circuit. The signal is inverted, the short-circuit switch 8 is turned on, and the inspection non-use terminal 6 and the ground terminal 2 are short-circuited. At this time, the internal circuit 3 is controlled so that the internal circuit 3 of the semiconductor element does not malfunction even if the state of the inspection non-use terminal 6 changes.

この状態で、半導体素子検査時、接地端子2に大電流が流れようとした場合、接地端子2と、検査装置から検査治具を介して接地電位が印加されている検査不使用端子6とが短絡されているため、電流を接地端子2と検査不使用端子6に分散することができる。上記の動作により、検査時、半導体素子の接地端子2に流れる電流の絶対値量を減少させることができ、ひいては検査治具の損傷を防ぎ、検査の不安定化を抑止することができる。なお、上記の実施形態は、接地端子2に流れようとする電流を分散できる検査不使用端子6の数が多いほど効果が大きくなる。
(実施の形態4)
本発明の実施の形態4について、図4を用いて説明する。実施の形態4は、半導体素子の電源端子に流れようとする大電流の絶対値量を減らすことができる発明の実施形態である。
In this state, when a large current is about to flow to the ground terminal 2 during the semiconductor element inspection, the ground terminal 2 and the inspection non-use terminal 6 to which the ground potential is applied from the inspection device via the inspection jig are provided. Since it is short-circuited, the current can be distributed to the ground terminal 2 and the inspection non-use terminal 6. With the above-described operation, the absolute value of the current flowing through the ground terminal 2 of the semiconductor element can be reduced during the inspection, and thus the inspection jig can be prevented from being damaged and the inspection can be prevented from becoming unstable. The above-described embodiment becomes more effective as the number of non-inspection terminals 6 that can disperse the current that flows to the ground terminal 2 increases.
(Embodiment 4)
Embodiment 4 of the present invention will be described with reference to FIG. The fourth embodiment is an embodiment of the invention that can reduce the absolute value of a large current that flows to the power supply terminal of the semiconductor element.

図4において、1は検査する半導体素子の電源端子を示し、2は検査する半導体素子の接地端子を示す。検査時、半導体素子に電源を供給するため、検査装置から検査治具を介して半導体素子の接地端子2に接地電位を印加し、半導体素子の電源端子1に電源電圧を印加している。また、5は半導体素子の検査時に、検査信号を入力する端子を示し、6は半導体素子の検査時に、検査に使用しない端子を示し、13は検査信号の入力に対する半導体素子の内部回路3の演算結果を出力する端子を示す。検査不使用端子6は少なくとも1端子有する。検査信号入力端子5と検査信号出力端子13と検査不使用端子6は、I/O回路4を介して半導体素子の内部回路3に接続される。   In FIG. 4, 1 indicates a power supply terminal of a semiconductor element to be inspected, and 2 indicates a ground terminal of the semiconductor element to be inspected. At the time of inspection, in order to supply power to the semiconductor element, a ground potential is applied from the inspection apparatus to the ground terminal 2 of the semiconductor element via an inspection jig, and a power supply voltage is applied to the power supply terminal 1 of the semiconductor element. Reference numeral 5 denotes a terminal for inputting an inspection signal when inspecting the semiconductor element. Reference numeral 6 denotes a terminal which is not used for inspection when inspecting the semiconductor element. Reference numeral 13 denotes an operation of the internal circuit 3 of the semiconductor element for the input of the inspection signal. Indicates the terminal that outputs the result. The inspection non-use terminal 6 has at least one terminal. The inspection signal input terminal 5, the inspection signal output terminal 13, and the inspection nonuse terminal 6 are connected to the internal circuit 3 of the semiconductor element via the I / O circuit 4.

さらに、外部からの入力信号によってON/OFFする短絡スイッチ回路を少なくとも1組有する。すなわち検査不使用端子6と電源端子1との間に短絡スイッチ8を設け、検査モード信号入力端子7の信号切替わりによって、短絡スイッチ8がONして検査不使用端子6と電源端子1が短絡するように回路を構成する。   Furthermore, at least one set of short-circuit switch circuits that are turned ON / OFF by an external input signal is provided. That is, the short-circuit switch 8 is provided between the inspection non-use terminal 6 and the power supply terminal 1, and the short-circuit switch 8 is turned on by the signal switching of the inspection mode signal input terminal 7, and the inspection non-use terminal 6 and the power supply terminal 1 are short-circuited. The circuit is configured as follows.

なお、短絡スイッチ8をONしたとき、配線9−配線10間のインピーダンスを可能な限り低くできるように短絡スイッチ8を構成し、短絡スイッチ8がONする極性は、短絡スイッチ8の構成によって決まる。   When the short-circuit switch 8 is turned on, the short-circuit switch 8 is configured so that the impedance between the wiring 9 and the wiring 10 can be as low as possible, and the polarity of the short-circuit switch 8 being turned on is determined by the configuration of the short-circuit switch 8.

上記構成の半導体素子を検査するとき、電源端子1に大電流が流れるケースは、以下の2通りである。
(1)内部回路3の電源端子に繋がる配線22、またはI/O回路の電源端子に繋がる配線23,24から、電源端子1に向かって大電流が流れるケース
(2)電源端子1から、内部回路3の電源端子1に繋がる配線22、またはI/O回路の電源端子に繋がる配線23,24に向かって大電流が流れるケース
上記のいずれかのケースで、半導体素子の電源端子1と、あるいは電源端子1に接続される検査治具へと大電流が流れようとしたとき、下記に示す本発明の回路動作によって、上記の大電流を抑えることができる。
When the semiconductor element having the above configuration is inspected, there are the following two cases where a large current flows through the power supply terminal 1.
(1) Case where a large current flows from the wiring 22 connected to the power supply terminal of the internal circuit 3 or the wirings 23 and 24 connected to the power supply terminal of the I / O circuit toward the power supply terminal 1 (2) From the power supply terminal 1 to the internal A case where a large current flows toward the wiring 22 connected to the power supply terminal 1 of the circuit 3 or the wirings 23 and 24 connected to the power supply terminal of the I / O circuit. In any of the above cases, the power supply terminal 1 of the semiconductor element, or When a large current is about to flow to the inspection jig connected to the power supply terminal 1, the above-described large current can be suppressed by the circuit operation of the present invention described below.

上記構成の半導体素子を検査する際、ウェハー上の半導体素子と検査装置を、プローブカード等の検査治具を介して接続し、検査を実施する。この際、あらかじめ検査不使用端子6に、検査装置から検査治具を介して電源電位を印加し、さらに検査モード信号入力端子7に、検査装置から短絡スイッチ8をONするための任意の信号レベルを入力して短絡スイッチ8をON状態にし、検査不使用端子6と電源端子1を短絡させておく。このとき、検査不使用端子6の状態が変化しても半導体素子の内部回路3が誤動作しないように内部回路3を制御しておく。   When inspecting the semiconductor element having the above configuration, the inspection is performed by connecting the semiconductor element on the wafer and the inspection apparatus via an inspection jig such as a probe card. At this time, an arbitrary signal level is applied to the inspection non-use terminal 6 in advance by applying a power supply potential from the inspection device via the inspection jig, and further to the inspection mode signal input terminal 7 for turning on the short-circuit switch 8 from the inspection device. Is input to turn on the short-circuit switch 8 so that the inspection non-use terminal 6 and the power supply terminal 1 are short-circuited. At this time, the internal circuit 3 is controlled so that the internal circuit 3 of the semiconductor element does not malfunction even if the state of the inspection non-use terminal 6 changes.

この状態で、半導体素子検査時、電源端子1に大電流が流れようとした場合、電源端子1と、検査装置から検査治具を介して電源電位が印加されている検査不使用端子6とが短絡されているため、電流を電源端子1と検査不使用端子6に分散することができる。上記の動作により、検査時、半導体素子の電源端子1に流れる電流の絶対値量を減少させることができ、ひいては検査治具の損傷を防ぎ、検査の不安定化を抑止することができる。なお、上記の実施形態は、電源端子1に流れようとする電流を分散できる検査不使用端子6の数が多いほど効果が大きくなる。
(実施の形態5)
本発明の実施の形態5について、図5を用いて説明する。実施の形態5は、半導体素子の電源端子に流れようとする大電流の絶対値量を減らすことができる発明の実施形態である。
In this state, when a large current is about to flow to the power supply terminal 1 during the semiconductor element inspection, the power supply terminal 1 and the inspection non-use terminal 6 to which the power supply potential is applied from the inspection apparatus via the inspection jig are provided. Since they are short-circuited, the current can be distributed to the power supply terminal 1 and the inspection non-use terminal 6. With the above-described operation, the absolute value of the current flowing through the power supply terminal 1 of the semiconductor element can be reduced during the inspection, and thus the inspection jig can be prevented from being damaged and the inspection can be prevented from becoming unstable. Note that the effect of the embodiment described above increases as the number of the inspection non-use terminals 6 that can disperse the current to flow through the power supply terminal 1 increases.
(Embodiment 5)
Embodiment 5 of the present invention will be described with reference to FIG. The fifth embodiment is an embodiment of the invention that can reduce the absolute value of a large current that flows to the power supply terminal of a semiconductor element.

図5において、1は検査する半導体素子の電源端子を示し、2は検査する半導体素子の接地端子を示す。検査時、半導体素子に電源を供給するため、検査装置から検査治具を介して半導体素子の接地端子2に接地電位を印加し、半導体素子の電源端子1に電源電圧を印加している。また、5は半導体素子の検査時に、検査信号を入力する端子を示し、6は半導体素子の検査時に、検査に使用しない端子を示し、13は検査信号の入力に対する半導体素子の内部回路3の演算結果を出力する端子を示す。検査不使用端子6は少なくとも1端子有する。検査信号入力端子5と検査信号出力端子13と検査不使用端子6は、I/O回路4を介して半導体素子の内部回路3に接続される。   In FIG. 5, 1 indicates a power supply terminal of a semiconductor element to be inspected, and 2 indicates a ground terminal of the semiconductor element to be inspected. At the time of inspection, in order to supply power to the semiconductor element, a ground potential is applied from the inspection apparatus to the ground terminal 2 of the semiconductor element via an inspection jig, and a power supply voltage is applied to the power supply terminal 1 of the semiconductor element. Reference numeral 5 denotes a terminal for inputting an inspection signal when inspecting the semiconductor element. Reference numeral 6 denotes a terminal which is not used for inspection when inspecting the semiconductor element. Reference numeral 13 denotes an operation of the internal circuit 3 of the semiconductor element for the input of the inspection signal. Indicates the terminal that outputs the result. The inspection non-use terminal 6 has at least one terminal. The inspection signal input terminal 5, the inspection signal output terminal 13, and the inspection nonuse terminal 6 are connected to the internal circuit 3 of the semiconductor element via the I / O circuit 4.

さらに、外部からの入力信号によってON/OFFする短絡スイッチ回路を少なくとも1組有する。すなわち検査不使用端子6と電源端子1との間に短絡スイッチ8を設け、短絡スイッチ8のスイッチ切替え信号入力端子と、電圧検知回路15の出力端子18とを接続する。電圧検知回路15の出力端子18は、短絡スイッチ8をON/OFFする入力信号が供給される。   Furthermore, at least one set of short-circuit switch circuits that are turned ON / OFF by an external input signal is provided. That is, the short-circuit switch 8 is provided between the inspection non-use terminal 6 and the power supply terminal 1, and the switch switching signal input terminal of the short-circuit switch 8 and the output terminal 18 of the voltage detection circuit 15 are connected. An output signal for turning ON / OFF the short-circuit switch 8 is supplied to the output terminal 18 of the voltage detection circuit 15.

また、電圧検知回路15は少なくとも1組有し、電源端子1に繋がる配線に電流が流れることによって、電源端子1に繋がる配線のある1点と他の1点間の電位差が印加される入力端子と、一定の基準電圧が印加される入力端子とを有する。この場合、電源端子1に電流が流れることによって生じる配線16−配線17間の電位差を検出し、配線16−配線17間の電位差が一定値以上の電圧値19(以下、検知電圧値と記載)になったとき、電圧検知回路の出力端子18に出力する信号レベルが反転するようになっている。電圧検知回路の出力端子18から出力される信号切替わりによって、短絡スイッチ8がONして配線9と配線10が短絡し、これにより検査不使用端子6と電源端子1が短絡する。   The voltage detection circuit 15 has at least one set, and an input terminal to which a potential difference between one point of the wiring connected to the power supply terminal 1 and another point is applied when a current flows through the wiring connected to the power supply terminal 1. And an input terminal to which a constant reference voltage is applied. In this case, a potential difference between the wiring 16 and the wiring 17 caused by a current flowing through the power supply terminal 1 is detected, and a voltage value 19 in which the potential difference between the wiring 16 and the wiring 17 is equal to or greater than a certain value (hereinafter referred to as a detection voltage value). The signal level output to the output terminal 18 of the voltage detection circuit is inverted. By switching the signal output from the output terminal 18 of the voltage detection circuit, the short-circuit switch 8 is turned ON and the wiring 9 and the wiring 10 are short-circuited, whereby the inspection non-use terminal 6 and the power supply terminal 1 are short-circuited.

なお、短絡スイッチ8をONしたとき、配線9−配線10間のインピーダンスを可能な限り低くできるように短絡スイッチ8を構成し、短絡スイッチ8がONする極性は、短絡スイッチ8の構成によって決まり、電圧検知回路の出力端子18から出力される信号の極性は電圧検知回路15の構成によって決まり、電圧検知回路の出力端子18 から出力される信号レベルが反転する際の検知電圧値19もまた、電圧検知回路15の構成によって決まる。   In addition, when the short-circuit switch 8 is turned on, the short-circuit switch 8 is configured so that the impedance between the wiring 9 and the wiring 10 can be as low as possible, and the polarity of the short-circuit switch 8 being turned on is determined by the configuration of the short-circuit switch 8, The polarity of the signal output from the output terminal 18 of the voltage detection circuit is determined by the configuration of the voltage detection circuit 15, and the detected voltage value 19 when the signal level output from the output terminal 18 of the voltage detection circuit is inverted is also a voltage. It depends on the configuration of the detection circuit 15.

上記構成の半導体素子を検査するとき、電源端子1に大電流が流れるケースは、以下の2通りである。
(1)内部回路3の電源端子に繋がる配線22、またはI/O回路の電源端子に繋がる配線23,24から、電源端子1に向かって大電流が流れるケース
(2)電源端子1から、内部回路3の電源端子1に繋がる配線22、またはI/O回路の電源端子に繋がる配線23,24に向かって大電流が流れるケース
上記のいずれかのケースで、半導体素子の電源端子1と、あるいは電源端子1に接続される検査治具へと大電流が流れようとしたとき、下記に示す本発明の回路動作によって、上記の大電流を抑えることができる。
When the semiconductor element having the above configuration is inspected, there are the following two cases where a large current flows through the power supply terminal 1.
(1) Case where a large current flows from the wiring 22 connected to the power supply terminal of the internal circuit 3 or the wirings 23 and 24 connected to the power supply terminal of the I / O circuit toward the power supply terminal 1 (2) From the power supply terminal 1 to the internal A case where a large current flows toward the wiring 22 connected to the power supply terminal 1 of the circuit 3 or the wirings 23 and 24 connected to the power supply terminal of the I / O circuit. In any of the above cases, the power supply terminal 1 of the semiconductor element, or When a large current is about to flow to the inspection jig connected to the power supply terminal 1, the above-described large current can be suppressed by the circuit operation of the present invention described below.

上記構成の半導体素子を検査する際、ウェハー上の半導体素子と検査装置を、プローブカード等の検査治具を介して接続し、検査を実施する。この際、あらかじめ検査不使用端子6に、検査装置から検査治具を介して電源電位を印加する。また、
(配線16−配線17間の電位差)<(検知電圧値19)
のとき、短絡スイッチ8はOFF状態である。このとき、検査不使用端子6の状態が変化しても半導体素子の内部回路3が誤動作しないように内部回路3を制御しておく。
When inspecting the semiconductor element having the above configuration, the inspection is performed by connecting the semiconductor element on the wafer and the inspection apparatus via an inspection jig such as a probe card. At this time, a power supply potential is previously applied to the inspection non-use terminal 6 from the inspection device via the inspection jig. Also,
(Potential difference between wiring 16 and wiring 17) <(detection voltage value 19)
At this time, the short-circuit switch 8 is in an OFF state. At this time, the internal circuit 3 is controlled so that the internal circuit 3 of the semiconductor element does not malfunction even if the state of the inspection non-use terminal 6 changes.

この状態で、半導体素子検査時、電源端子1に大電流が流れようとした場合、配線16-配線17間に電流が流れ、
(配線16−配線17間に流れる電流値)×(配線16−配線17間の抵抗値)
で決まる配線16−配線17間の電位差が、検知電圧値19以上になったとき、電圧検知回路15の出力端子18から出力される信号レベルが反転して短絡スイッチ8がON状態になり、電源端子1と、検査装置から検査治具を介して電源電位が印加されている検査不使用端子6とが短絡される、電源端子1に流れようとする大電流を電源端子1と検査不使用端子6に分散することができる。上記の動作により、検査時、半導体素子の電源端子1に流れる電流の絶対値量を減少させることができ、ひいては検査治具の損傷を防ぎ、検査の不安定化を抑止することができる。なお、上記の実施形態は、電源端子1に流れようとする電流を分散できる検査不使用端子6の数が多いほど効果が大きくなる。
(実施の形態6)
本発明の実施の形態6について、図6を用いて説明する。実施の形態6は、半導体素子の電源端子に流れようとする大電流の絶対値量を減らすことができる発明の実施形態である。
In this state, when a large current is about to flow through the power supply terminal 1 during the semiconductor element inspection, a current flows between the wiring 16 and the wiring 17.
(Current value flowing between wiring 16 and wiring 17) × (resistance value between wiring 16 and wiring 17)
When the potential difference between the wiring 16 and the wiring 17 determined by (1) becomes equal to or higher than the detection voltage value 19, the signal level output from the output terminal 18 of the voltage detection circuit 15 is inverted and the short-circuit switch 8 is turned on. The terminal 1 and the inspection non-use terminal 6 to which the power supply potential is applied from the inspection device through the inspection jig are short-circuited, and a large current that tends to flow to the power supply terminal 1 is supplied to the power supply terminal 1 and the inspection non-use terminal. 6 can be dispersed. With the above-described operation, the absolute value of the current flowing through the power supply terminal 1 of the semiconductor element can be reduced during the inspection, and thus the inspection jig can be prevented from being damaged and the inspection can be prevented from becoming unstable. Note that the effect of the embodiment described above increases as the number of the inspection non-use terminals 6 that can disperse the current to flow through the power supply terminal 1 increases.
(Embodiment 6)
Embodiment 6 of the present invention will be described with reference to FIG. The sixth embodiment is an embodiment of the invention that can reduce the absolute value of a large current that flows to the power supply terminal of the semiconductor element.

図6において、1は検査する半導体素子の電源端子を示し、2は検査する半導体素子の接地端子を示す。検査時、半導体素子に電源を供給するため、検査装置から検査治具を介して半導体素子の接地端子2に接地電位を印加し、半導体素子の電源端子1に電源電圧を印加している。また、5は半導体素子の検査時に、検査信号を入力する端子を示し、6は半導体素子の検査時に、検査に使用しない端子を示し、13は検査信号の入力に対する半導体素子の内部回路3の演算結果を出力する端子を示す。検査不使用端子6は少なくとも1端子有する。検査信号入力端子5と検査信号出力端子13と検査不使用端子6は、I/O回路4を介して半導体素子の内部回路3に接続される。   In FIG. 6, 1 indicates a power supply terminal of a semiconductor element to be inspected, and 2 indicates a ground terminal of the semiconductor element to be inspected. At the time of inspection, in order to supply power to the semiconductor element, a ground potential is applied from the inspection apparatus to the ground terminal 2 of the semiconductor element via an inspection jig, and a power supply voltage is applied to the power supply terminal 1 of the semiconductor element. Reference numeral 5 denotes a terminal for inputting an inspection signal when inspecting the semiconductor element. Reference numeral 6 denotes a terminal which is not used for inspection when inspecting the semiconductor element. Reference numeral 13 denotes an operation of the internal circuit 3 of the semiconductor element for the input of the inspection signal. Indicates the terminal that outputs the result. The inspection non-use terminal 6 has at least one terminal. The inspection signal input terminal 5, the inspection signal output terminal 13, and the inspection nonuse terminal 6 are connected to the internal circuit 3 of the semiconductor element via the I / O circuit 4.

さらに、外部からの入力信号によってON/OFFする短絡スイッチ回路を少なくとも1組有する。すなわち検査不使用端子6と電源端子1との間に短絡スイッチ8を設け、短絡スイッチ8のスイッチ切替え信号入力端子と、内部回路に組み込まれる短絡スイッチ制御回路20の出力端子21とを接続する。短絡スイッチ制御回路20の出力端子21は、短絡スイッチ8をON/OFFする入力信号が供給される。   Furthermore, at least one set of short-circuit switch circuits that are turned ON / OFF by an external input signal is provided. That is, the short circuit switch 8 is provided between the inspection non-use terminal 6 and the power supply terminal 1, and the switch switching signal input terminal of the short circuit switch 8 and the output terminal 21 of the short circuit switch control circuit 20 incorporated in the internal circuit are connected. An output signal for turning ON / OFF the short-circuit switch 8 is supplied to the output terminal 21 of the short-circuit switch control circuit 20.

また、短絡スイッチ制御回路20は、内部回路のレジスタ設定を切替えることによって、短絡スイッチ制御回路の出力端子21に出力する信号レベルが反転するようになっている。短絡スイッチ制御回路の出力端子21から出力される信号切替わりによって、短絡スイッチ8がONして配線9と配線10が短絡し、これにより検査不使用端子6と電源端子1が短絡する。   The short-circuit switch control circuit 20 is configured to invert the signal level output to the output terminal 21 of the short-circuit switch control circuit by switching the register setting of the internal circuit. By switching the signal output from the output terminal 21 of the short-circuit switch control circuit, the short-circuit switch 8 is turned ON and the wiring 9 and the wiring 10 are short-circuited, whereby the inspection non-use terminal 6 and the power supply terminal 1 are short-circuited.

なお、短絡スイッチ8をONしたとき、配線9−配線10間のインピーダンスを可能な限り低くできるように短絡スイッチ8を構成し、短絡スイッチ8がONする極性は、短絡スイッチ8の構成によって決まり、短絡スイッチ制御回路の出力端子21から出力される信号の極性は短絡スイッチ制御回路20の構成によって決まる。   In addition, when the short-circuit switch 8 is turned on, the short-circuit switch 8 is configured so that the impedance between the wiring 9 and the wiring 10 can be as low as possible, and the polarity of the short-circuit switch 8 being turned on is determined by the configuration of the short-circuit switch 8, The polarity of the signal output from the output terminal 21 of the short-circuit switch control circuit is determined by the configuration of the short-circuit switch control circuit 20.

上記構成の半導体素子を検査するとき、電源端子1に大電流が流れるケースは、以下の2通りである。
(1)内部回路3の電源端子に繋がる配線22、またはI/O回路の電源端子に繋がる配線23,24から、電源端子1に向かって大電流が流れるケース
(2)電源端子1から、内部回路3の電源端子1に繋がる配線22、またはI/O回路の電源端子に繋がる配線23,24に向かって大電流が流れるケース
上記のいずれかのケースで、半導体素子の電源端子1と、あるいは電源端子1に接続される検査治具へと大電流が流れようとしたとき、下記に示す本発明の回路動作によって、上記の大電流を抑えることができる。
When the semiconductor element having the above configuration is inspected, there are the following two cases where a large current flows through the power supply terminal 1.
(1) Case where a large current flows from the wiring 22 connected to the power supply terminal of the internal circuit 3 or the wirings 23 and 24 connected to the power supply terminal of the I / O circuit toward the power supply terminal 1 (2) From the power supply terminal 1 to the internal A case where a large current flows toward the wiring 22 connected to the power supply terminal 1 of the circuit 3 or the wirings 23 and 24 connected to the power supply terminal of the I / O circuit. In any of the above cases, the power supply terminal 1 of the semiconductor element, or When a large current is about to flow to the inspection jig connected to the power supply terminal 1, the above-described large current can be suppressed by the circuit operation of the present invention described below.

上記構成の半導体素子を検査する際、ウェハー上の半導体素子と検査装置を、プローブカード等の検査治具を介して接続し、検査を実施する。この際、あらかじめ検査不使用端子6に、検査装置から検査治具を介して電源電位を印加し、さらに半導体装置の内部回路のレジスタ設定を切替えて短絡スイッチ制御回路の出力端子21から出力される信号を反転させ、短絡スイッチ8をON状態にし、検査不使用端子6と電源端子1を短絡しておく。このとき、検査不使用端子6の状態が変化しても半導体素子の内部回路3が誤動作しないように内部回路3を制御しておく。   When inspecting the semiconductor element having the above configuration, the inspection is performed by connecting the semiconductor element on the wafer and the inspection apparatus via an inspection jig such as a probe card. At this time, the power supply potential is applied to the inspection non-use terminal 6 from the inspection device via the inspection jig in advance, and the register setting of the internal circuit of the semiconductor device is switched and output from the output terminal 21 of the short-circuit switch control circuit. The signal is inverted, the shorting switch 8 is turned on, and the inspection non-use terminal 6 and the power supply terminal 1 are short-circuited. At this time, the internal circuit 3 is controlled so that the internal circuit 3 of the semiconductor element does not malfunction even if the state of the inspection non-use terminal 6 changes.

この状態で、半導体素子検査時、電源端子1に大電流が流れようとした場合、電源端子1と、検査装置から検査治具を介して電源電位が印加されている検査不使用端子6とが短絡されているため、電流を電源端子1と検査不使用端子6に分散することができる。上記の動作により、検査時、半導体素子の電源端子1に流れる電流の絶対値量を減少させることができ、ひいては検査治具の損傷を防ぎ、検査の不安定化を抑止することができる。なお、上記の実施形態は、電源端子1に流れようとする電流を分散できる検査不使用端子6の数が多いほど効果が大きくなる。
(実施の形態7)
本発明の実施の形態7について、図7を用いて説明する。実施の形態7は、半導体素子に検査不使用端子が2端子以上存在する場合、検査不使用端子を検査時にそれぞれ電源端子と接地端子として使用することで、半導体素子の電源端子に流れようとする大電流の絶対値量と、半導体素子の接地端子に流れようとする大電流の絶対値量の、両方を減少させることができる発明の実施形態である。
In this state, when a large current is about to flow to the power supply terminal 1 during the semiconductor element inspection, the power supply terminal 1 and the inspection non-use terminal 6 to which the power supply potential is applied from the inspection apparatus via the inspection jig are provided. Since they are short-circuited, the current can be distributed to the power supply terminal 1 and the inspection non-use terminal 6. With the above-described operation, the absolute value of the current flowing through the power supply terminal 1 of the semiconductor element can be reduced during the inspection, and thus the inspection jig can be prevented from being damaged and the inspection can be prevented from becoming unstable. Note that the effect of the embodiment described above increases as the number of the inspection non-use terminals 6 that can disperse the current to flow through the power supply terminal 1 increases.
(Embodiment 7)
A seventh embodiment of the present invention will be described with reference to FIG. In the seventh embodiment, when there are two or more non-inspection terminals in a semiconductor element, the non-inspection terminals are used as a power supply terminal and a ground terminal in the inspection, respectively, so that they flow to the power supply terminal of the semiconductor element. This is an embodiment of the invention that can reduce both the absolute value of a large current and the absolute value of a large current that tends to flow to the ground terminal of the semiconductor element.

図7において、1は検査する半導体素子の電源端子を示し、2は検査する半導体素子の接地端子を示す。検査時、半導体素子に電源を供給するため、検査装置から検査治具を介して半導体素子の接地端子2に接地電位を印加し、半導体素子の電源端子1に電源電圧を印加している。また、5は半導体素子の検査時に、検査信号を入力する端子を示し、6,25は半導体素子の検査時に、検査に使用しない端子を示し、13は検査信号の入力に対する半導体素子の内部回路3の演算結果を出力する端子を示す。検査不使用端子6,25は少なくとも2端子有する。検査信号入力端子5と検査信号出力端子13と検査不使用端子6,25は、I/O回路4を介して半導体素子の内部回路3に接続される。   In FIG. 7, 1 indicates a power supply terminal of a semiconductor element to be inspected, and 2 indicates a ground terminal of the semiconductor element to be inspected. At the time of inspection, in order to supply power to the semiconductor element, a ground potential is applied from the inspection apparatus to the ground terminal 2 of the semiconductor element via an inspection jig, and a power supply voltage is applied to the power supply terminal 1 of the semiconductor element. Reference numeral 5 denotes a terminal for inputting an inspection signal when inspecting the semiconductor element, reference numerals 6 and 25 denote terminals which are not used for the inspection during inspection of the semiconductor element, and reference numeral 13 denotes an internal circuit 3 of the semiconductor element for the input of the inspection signal. The terminal which outputs the operation result of is shown. The inspection non-use terminals 6 and 25 have at least two terminals. The inspection signal input terminal 5, the inspection signal output terminal 13, and the inspection nonuse terminals 6 and 25 are connected to the internal circuit 3 of the semiconductor element via the I / O circuit 4.

さらに、外部からの入力信号によってON/OFFする短絡スイッチ回路を少なくとも2組有する。すなわち検査不使用端子6と接地端子2との間に短絡スイッチ8を設け、また、検査不使用端子25と電源端子1との間に短絡スイッチ26を設け、検査モード信号入力端子7の信号切替わりによって、短絡スイッチ8がONして検査不使用端子6と接地端子2が短絡し、また、短絡スイッチ26がONして検査不使用端子25と電源端子1が短絡するように回路を構成する。入力端子7は少なくとも1端子有し、短絡スイッチ8をON/OFFする入力信号を印加する。   Further, at least two sets of short-circuit switch circuits that are turned ON / OFF by an external input signal are provided. That is, a short-circuit switch 8 is provided between the inspection non-use terminal 6 and the ground terminal 2, and a short-circuit switch 26 is provided between the inspection non-use terminal 25 and the power supply terminal 1 so that the inspection mode signal input terminal 7 is turned off. Instead, the circuit is configured such that the short-circuit switch 8 is turned ON to short-circuit the inspection non-use terminal 6 and the ground terminal 2, and the short-circuit switch 26 is ON to short-circuit the inspection non-use terminal 25 and the power supply terminal 1. . The input terminal 7 has at least one terminal and applies an input signal for turning on / off the short-circuit switch 8.

なお、短絡スイッチ8をONしたとき、配線9−配線10間のインピーダンスを可能な限り低くできるように短絡スイッチ8を構成し、短絡スイッチ26をONしたとき、配線27−配線28間のインピーダンスを可能な限り低くできるように短絡スイッチ26を構成し、短絡スイッチ8,26がONする極性は、短絡スイッチ8,26の構成によって決まる。   When the short-circuit switch 8 is turned on, the short-circuit switch 8 is configured so that the impedance between the wiring 9 and the wiring 10 can be as low as possible. When the short-circuit switch 26 is turned on, the impedance between the wiring 27 and the wiring 28 is changed. The short-circuit switch 26 is configured to be as low as possible, and the polarity with which the short-circuit switches 8 and 26 are turned on is determined by the configuration of the short-circuit switches 8 and 26.

上記構成において、半導体素子の電源端子1、あるいは接地端子2に大電流が流れようとしたとき、下記に示す本実施形態の回路動作によって、上記の大電流を抑えることができる。   In the above configuration, when a large current is about to flow through the power supply terminal 1 or the ground terminal 2 of the semiconductor element, the large current can be suppressed by the circuit operation of the present embodiment described below.

上記構成の半導体素子を検査する際、ウェハー上の半導体素子と検査装置を、プローブカード等の検査治具を介して接続し、検査を実施する。この際、あらかじめ検査不使用端子6に、検査装置から検査治具を介して接地電位を印加し、また、検査不使用端子25に、検査装置から検査治具を介して電源電位を印加し、さらに検査モード信号入力端子7に、検査装置から短絡スイッチ8,26をONするための任意の信号レベルを入力して短絡スイッチ8,26をON状態にし、検査不使用端子6と接地端子2を短絡させ、また、検査不使用端子25と電源端子1を短絡させておく。このとき、検査不使用端子6の状態が変化しても半導体素子の内部回路3が誤動作しないように内部回路3を制御しておく。   When inspecting the semiconductor element having the above configuration, the inspection is performed by connecting the semiconductor element on the wafer and the inspection apparatus via an inspection jig such as a probe card. At this time, a ground potential is previously applied to the inspection non-use terminal 6 from the inspection device via the inspection jig, and a power supply potential is applied to the inspection non-use terminal 25 from the inspection device via the inspection jig. Furthermore, an arbitrary signal level for turning on the short-circuit switches 8 and 26 is input from the inspection device to the inspection mode signal input terminal 7 to turn on the short-circuit switches 8 and 26, and the inspection non-use terminal 6 and the ground terminal 2 are connected. The inspection non-use terminal 25 and the power supply terminal 1 are short-circuited. At this time, the internal circuit 3 is controlled so that the internal circuit 3 of the semiconductor element does not malfunction even if the state of the inspection non-use terminal 6 changes.

この状態で、半導体素子検査時、接地端子1に大電流が流れようとした場合、接地端子1と、検査装置から検査治具を介して接地電位が印加されている検査不使用端子6とが短絡されているため、電流を接地端子2と検査不使用端子6に分散することができる。また、検査時に電源端子1に大電流が流れようとする場合も同様で、電源端子1と、検査装置から検査治具を介して電源電位が印加されている検査不使用端子25とが短絡されているため、電流を電源端子1と検査不使用端子25に分散することができる。   In this state, when a large current is about to flow to the ground terminal 1 during the semiconductor element inspection, the ground terminal 1 and the inspection non-use terminal 6 to which the ground potential is applied from the inspection device via the inspection jig are provided. Since it is short-circuited, the current can be distributed to the ground terminal 2 and the inspection non-use terminal 6. Similarly, when a large current is about to flow through the power supply terminal 1 during inspection, the power supply terminal 1 and the inspection non-use terminal 25 to which the power supply potential is applied from the inspection apparatus via the inspection jig are short-circuited. Therefore, the current can be distributed to the power supply terminal 1 and the inspection nonuse terminal 25.

上記の動作により、検査時、半導体素子の電源端子1あるいは接地端子2に流れる電流の絶対値量を減少させることができ、ひいては検査治具の損傷を防ぎ、検査の不安定化を抑止することができる。なお、上記の実施形態は、電源端子1あるいは接地端子2に流れようとする電流を分散できる検査不使用端子6あるいは検査不使用端子25の数が多いほど効果が大きくなる。   With the above operation, the absolute value of the current flowing through the power supply terminal 1 or the ground terminal 2 of the semiconductor element can be reduced during the inspection, thereby preventing the inspection jig from being damaged and preventing the inspection from becoming unstable. Can do. The above-described embodiment becomes more effective as the number of the inspection non-use terminals 6 or the inspection non-use terminals 25 that can disperse the current that flows to the power supply terminal 1 or the ground terminal 2 increases.

本発明にかかる半導体装置の検査方法および半導体装置は、検査効率が低下することなく、かつ検査治具の製作にかかるコストの増大がなく、大電流による検査治具の損傷を抑止することができ、また半導体素子中の電源パッドあるいは接地パッドの数を増やすことなく、半導体素子の電源端子あるいは接地端子にかかる電圧の変動を抑えて検査を安定化することができるという効果を有し、半導体素子の検査に有用である。   INDUSTRIAL APPLICABILITY The semiconductor device inspection method and the semiconductor device according to the present invention can suppress the inspection jig from being damaged by a large current without lowering the inspection efficiency and without increasing the cost for manufacturing the inspection jig. In addition, there is an effect that the inspection can be stabilized by suppressing the fluctuation of the voltage applied to the power supply terminal or the ground terminal of the semiconductor element without increasing the number of power supply pads or ground pads in the semiconductor element. It is useful for inspection.

本発明の実施の形態1の半導体装置の大電流保護回路の回路構成図である。1 is a circuit configuration diagram of a large current protection circuit of a semiconductor device according to a first embodiment of the present invention. 本発明の実施の形態2の半導体装置の大電流保護回路の回路構成図である。It is a circuit block diagram of the large current protection circuit of the semiconductor device of Embodiment 2 of this invention. 本発明の実施の形態3の半導体装置の大電流保護回路の回路構成図である。It is a circuit block diagram of the large current protection circuit of the semiconductor device of Embodiment 3 of this invention. 本発明の実施の形態4の半導体装置の大電流保護回路の回路構成図である。It is a circuit block diagram of the large current protection circuit of the semiconductor device of Embodiment 4 of this invention. 本発明の実施の形態5の半導体装置の大電流保護回路の回路構成図である。It is a circuit block diagram of the large current protection circuit of the semiconductor device of Embodiment 5 of this invention. 本発明の実施の形態6の半導体装置の大電流保護回路の回路構成図である。It is a circuit block diagram of the large current protection circuit of the semiconductor device of Embodiment 6 of this invention. 本発明の実施の形態7の半導体装置の大電流保護回路の回路構成図である。It is a circuit block diagram of the large current protection circuit of the semiconductor device of Embodiment 7 of this invention.

符号の説明Explanation of symbols

1 半導体素子の電源端子
2 半導体素子の接地端子
3 半導体素子の内部回路
4 半導体素子のI/O回路
5 半導体素子の検査信号入力端子
6 半導体素子の検査不使用端子
7 半導体素子の検査モード信号入力端子
8 短絡スイッチ
9 短絡スイッチに接続される配線
10 短絡スイッチに接続される配線
11 I/O回路の接地端子に繋がる配線
12 内部回路の接地端子に繋がる配線
13 半導体素子の検査信号出力端子
14 I/O回路の接地端子に繋がる配線
15 電圧検知回路
16 電圧検知回路の電圧の基準となる端子に接続される配線
17 電圧検知回路の入力端子に接続される配線
18 電圧検知回路の出力端子
19 電圧検知回路の基準電圧
20 半導体素子の内部回路内に存在する短絡スイッチ制御回路
21 短絡スイッチ制御回路の制御信号を出力する端子
22 内部回路の電源端子に繋がる配線
23 I/O回路の電源端子に繋がる配線
24 I/O回路の電源端子に繋がる配線
25 半導体素子の検査不使用端子
26 短絡スイッチ
27 短絡スイッチに接続される配線
28 短絡スイッチに接続される配線
DESCRIPTION OF SYMBOLS 1 Power supply terminal of semiconductor element 2 Ground terminal of semiconductor element 3 Internal circuit of semiconductor element 4 I / O circuit of semiconductor element 5 Inspection signal input terminal of semiconductor element 6 Non-inspection terminal of semiconductor element 7 Inspection mode signal input of semiconductor element Terminal 8 Short-circuit switch 9 Wiring connected to short-circuit switch 10 Wiring connected to short-circuit switch 11 Wiring connected to ground terminal of I / O circuit 12 Wiring connected to ground terminal of internal circuit 13 Test signal output terminal of semiconductor element 14 I Wiring connected to the ground terminal of the / O circuit 15 Voltage detection circuit 16 Wiring connected to a terminal serving as a voltage reference of the voltage detection circuit 17 Wiring connected to an input terminal of the voltage detection circuit 18 Output terminal of the voltage detection circuit 19 Voltage Reference voltage of detection circuit 20 Short-circuit switch control circuit existing in internal circuit of semiconductor element 21 Short-circuit switch control Terminals for outputting road control signals 22 Wirings connected to power supply terminals of internal circuits 23 Wirings connected to power supply terminals of I / O circuits 24 Wirings connecting to power supply terminals of I / O circuits 25 Non-inspection terminals of semiconductor elements 26 Short-circuit switch 27 Wiring connected to short-circuit switch 28 Wiring connected to short-circuit switch

Claims (9)

半導体素子の電源端子に電源電圧を印加し、前記半導体素子の接地端子に接地電圧を印加して検査する際、前記半導体素子の検査に使用しない端子と前記接地端子とを短絡することで、前記接地端子に流れる電流を、前記検査に使用しない端子と前記接地端子とに分散させることを特徴とする半導体装置の検査方法。   When applying a power supply voltage to the power supply terminal of the semiconductor element and inspecting by applying a ground voltage to the ground terminal of the semiconductor element, by short-circuiting the terminal not used for the inspection of the semiconductor element and the ground terminal, A method for inspecting a semiconductor device, characterized in that a current flowing through a ground terminal is distributed to a terminal not used for the inspection and the ground terminal. 半導体素子の電源端子に電源電圧を印加し、前記半導体素子の接地端子に接地電圧を印加して検査する際、前記半導体素子の検査に使用しない端子と前記電源端子とを短絡することで、前記電源端子に流れる電流を、前記検査に使用しない端子と前記電源端子とに分散させることを特徴とする半導体装置の検査方法。   When applying a power supply voltage to the power supply terminal of the semiconductor element and inspecting by applying a ground voltage to the ground terminal of the semiconductor element, by short-circuiting a terminal not used for the inspection of the semiconductor element and the power supply terminal, A method for inspecting a semiconductor device, characterized in that a current flowing through a power supply terminal is distributed to a terminal not used for the inspection and the power supply terminal. 半導体素子の電源端子に電源電圧を印加し、前記半導体素子の接地端子に接地電圧を印加して検査する半導体装置であって、
検査に使用しない端子を少なくとも1端子有し、前記検査に使用しない端子と前記接地端子との間に配設され、外部からの入力信号によってON/OFFする短絡スイッチ回路を少なくとも1組有し、前記短絡スイッチ回路をON/OFFする入力信号を印加するための入力端子を少なくとも1端子有し、
検査時、前記検査に使用しない端子に接地電位を印加し、前記入力端子に、前記短絡スイッチ回路をONする入力信号を入力して前記短絡スイッチ回路をONさせることで、前記検査に使用しない端子と前記接地端子とを短絡することを特徴とする半導体装置。
A semiconductor device for inspecting by applying a power supply voltage to a power supply terminal of a semiconductor element and applying a ground voltage to a ground terminal of the semiconductor element,
Having at least one terminal not used for inspection, having at least one set of short-circuit switch circuits disposed between the terminal not used for inspection and the ground terminal, and turned ON / OFF by an external input signal; Having at least one input terminal for applying an input signal for turning ON / OFF the short-circuit switch circuit;
At the time of inspection, a ground potential is applied to a terminal not used for the inspection, and an input signal for turning on the short-circuit switch circuit is input to the input terminal to turn on the short-circuit switch circuit. And the ground terminal.
半導体素子の電源端子に電源電圧を印加し、前記半導体素子の接地端子に接地電圧を印加して検査する半導体装置であって、
検査に使用しない端子を少なくとも1端子有し、前記検査に使用しない端子と前記接地端子との間に配設され、外部からの入力信号によってON/OFFする短絡スイッチ回路を少なくとも1組有し、前記短絡スイッチ回路をON/OFFする入力信号を供給するための出力端子と、前記接地端子に繋がる配線に電流が流れることによって、前記接地端子に繋がる配線のある1点と他の1点間の電位差が印加される入力端子と、一定の基準電圧が印加される入力端子とを有する電圧検知回路を少なくとも1組有し、
検査時、前記検査に使用しない端子に接地電位を印加し、前記電圧検知回路において、前記接地端子に繋がる配線のある1点と他の1点間の電位差が、前記一定の基準電圧以上の電圧値になると、前記電圧検知回路の出力端子から、前記短絡スイッチ回路をONする信号を出力して前記短絡スイッチ回路をONさせることで、前記検査に使用しない端子と前記接地端子とを短絡することを特徴とする半導体装置。
A semiconductor device for inspecting by applying a power supply voltage to a power supply terminal of a semiconductor element and applying a ground voltage to a ground terminal of the semiconductor element,
Having at least one terminal not used for inspection, having at least one set of short-circuit switch circuits disposed between the terminal not used for inspection and the ground terminal, and turned ON / OFF by an external input signal; When an electric current flows through an output terminal for supplying an input signal for turning ON / OFF the short-circuit switch circuit and a wiring connected to the ground terminal, a point between one point of the wiring connected to the ground terminal and another point Having at least one set of voltage detection circuits each having an input terminal to which a potential difference is applied and an input terminal to which a constant reference voltage is applied;
At the time of inspection, a ground potential is applied to a terminal that is not used for the inspection, and in the voltage detection circuit, a potential difference between one point of wiring connected to the ground terminal and another point is a voltage that is equal to or higher than the predetermined reference voltage. When the value is reached, a signal for turning on the short-circuit switch circuit is output from the output terminal of the voltage detection circuit to turn on the short-circuit switch circuit, thereby short-circuiting the terminal not used for the inspection and the ground terminal. A semiconductor device characterized by the above.
半導体素子の電源端子に電源電圧を印加し、前記半導体素子の接地端子に接地電圧を印加して検査する半導体装置であって、
検査に使用しない端子を少なくとも1端子有し、前記検査に使用しない端子と前記接地端子との間に配設され、外部からの入力信号によってON/OFFする短絡スイッチ回路を少なくとも1組有し、前記短絡スイッチ回路をON/OFFする入力信号を供給するための出力端子を有する短絡スイッチ回路制御回路を前記半導体素子内に有し、
検査時に、前記検査に使用しない端子に接地電位を印加し、前記短絡スイッチ回路制御回路を動作させ、前記短絡スイッチ回路制御回路の出力端子から、前記短絡スイッチ回路をONする信号を出力して前記短絡スイッチ回路をONさせることで、前記検査に使用しない端子と半導体素子の接地端子とを短絡することを特徴とする半導体装置。
A semiconductor device for inspecting by applying a power supply voltage to a power supply terminal of a semiconductor element and applying a ground voltage to a ground terminal of the semiconductor element,
Having at least one terminal not used for inspection, having at least one set of short-circuit switch circuits disposed between the terminal not used for inspection and the ground terminal, and turned ON / OFF by an external input signal; A short-circuit switch circuit control circuit having an output terminal for supplying an input signal for turning ON / OFF the short-circuit switch circuit in the semiconductor element;
At the time of inspection, a ground potential is applied to a terminal not used for the inspection, the short-circuit switch circuit control circuit is operated, and a signal for turning on the short-circuit switch circuit is output from an output terminal of the short-circuit switch circuit control circuit. A semiconductor device characterized in that, by turning on a short-circuit switch circuit, a terminal not used for the inspection and a ground terminal of the semiconductor element are short-circuited.
半導体素子の電源端子に電源電圧を印加し、前記半導体素子の接地端子に接地電圧を印加して検査する半導体装置であって、
検査に使用しない端子を少なくとも1端子有し、前記検査に使用しない端子と前記電源端子との間に配設され、外部からの入力信号によってON/OFFする短絡スイッチ回路を少なくとも1組有し、前記短絡スイッチ回路をON/OFFする入力信号を印加するための入力端子を少なくとも1端子有し、
検査時、前記検査に使用しない端子に電源電位を印加し、前記入力端子に、前記短絡スイッチ回路をONする入力信号を入力して前記短絡スイッチ回路をONさせることで、前記検査に使用しない端子と前記電源端子とを短絡することを特徴とする半導体装置。
A semiconductor device for inspecting by applying a power supply voltage to a power supply terminal of a semiconductor element and applying a ground voltage to a ground terminal of the semiconductor element,
At least one terminal that is not used for inspection, at least one set of a short-circuit switch circuit that is disposed between the terminal that is not used for inspection and the power supply terminal, and is turned ON / OFF by an external input signal; Having at least one input terminal for applying an input signal for turning ON / OFF the short-circuit switch circuit;
During inspection, a power supply potential is applied to a terminal not used for the inspection, and an input signal for turning on the short-circuit switch circuit is input to the input terminal to turn on the short-circuit switch circuit. And the power supply terminal are short-circuited.
半導体素子の電源端子に電源電圧を印加し、前記半導体素子の接地端子に接地電圧を印加して検査する半導体装置であって、
検査に使用しない端子を少なくとも1端子有し、前記検査に使用しない端子と前記電源端子との間に配設され、外部からの入力信号によってON/OFFする短絡スイッチ回路を少なくとも1組有し、前記短絡スイッチ回路をON/OFFする入力信号を供給するための出力端子と、前記電源端子に繋がる配線に電流が流れることによって、前記電源端子に繋がる配線のある1点と他の1点間の電位差が印加される入力端子と、一定の基準電圧が印加される入力端子とを有する電圧検知回路を少なくとも1組有し、
検査時、前記検査に使用しない端子に電源電位を印加し、前記電圧検知回路において、前記電源端子に繋がる配線のある1点と他の1点間の電位差が、前記一定の基準電圧以上の電圧値になると、前記電圧検知回路の出力端子から、前記短絡スイッチ回路をONする信号を出力して前記短絡スイッチ回路をONさせることで、前記検査に使用しない端子と前記電源端子とを短絡することを特徴とする半導体装置。
A semiconductor device for inspecting by applying a power supply voltage to a power supply terminal of a semiconductor element and applying a ground voltage to a ground terminal of the semiconductor element,
At least one terminal that is not used for inspection, at least one set of a short-circuit switch circuit that is disposed between the terminal that is not used for inspection and the power supply terminal, and is turned ON / OFF by an external input signal; When a current flows through an output terminal for supplying an input signal for turning on / off the short-circuit switch circuit and a wiring connected to the power supply terminal, a point between one point of the wiring connected to the power supply terminal and another point Having at least one set of voltage detection circuits each having an input terminal to which a potential difference is applied and an input terminal to which a constant reference voltage is applied;
At the time of inspection, a power supply potential is applied to a terminal that is not used for the inspection, and in the voltage detection circuit, a potential difference between one point of wiring connected to the power supply terminal and another point is a voltage that is equal to or higher than the predetermined reference voltage. When the value is reached, a signal for turning on the short-circuit switch circuit is output from the output terminal of the voltage detection circuit to turn on the short-circuit switch circuit, thereby short-circuiting the terminal not used for the inspection and the power supply terminal. A semiconductor device characterized by the above.
半導体素子の電源端子に電源電圧を印加し、前記半導体素子の接地端子に接地電圧を印加して検査する半導体装置であって、
検査に使用しない端子を少なくとも1端子有し、前記検査に使用しない端子と前記電源端子との間に配設され、外部からの入力信号によってON/OFFする短絡スイッチ回路を少なくとも1組有し、前記短絡スイッチ回路をON/OFFする入力信号を供給するための出力端子を有する短絡スイッチ回路制御回路を前記半導体素子内に有し、
検査時に、前記検査に使用しない端子に電源電位を印加し、前記短絡スイッチ回路制御回路を動作させ、前記短絡スイッチ回路制御回路の出力端子から、前記短絡スイッチ回路をONする信号を出力して前記短絡スイッチ回路をONさせることで、前記検査に使用しない端子と半導体素子の電源端子とを短絡することを特徴とする半導体装置。
A semiconductor device for inspecting by applying a power supply voltage to a power supply terminal of a semiconductor element and applying a ground voltage to a ground terminal of the semiconductor element,
At least one terminal that is not used for inspection, at least one set of a short-circuit switch circuit that is disposed between the terminal that is not used for inspection and the power supply terminal, and is turned ON / OFF by an external input signal; A short-circuit switch circuit control circuit having an output terminal for supplying an input signal for turning ON / OFF the short-circuit switch circuit in the semiconductor element;
At the time of inspection, a power supply potential is applied to a terminal not used for the inspection, the short-circuit switch circuit control circuit is operated, and a signal for turning on the short-circuit switch circuit is output from the output terminal of the short-circuit switch circuit control circuit. A semiconductor device characterized by short-circuiting a terminal not used for the inspection and a power supply terminal of the semiconductor element by turning on a short-circuit switch circuit.
半導体素子の電源端子に電源電圧を印加し、前記半導体素子の接地端子に接地電圧を印加して検査する半導体装置であって、
検査に使用しない端子を少なくとも2端子有し、前記検査に使用しない一方の端子と前記接地端子との間および前記検査に使用しない他方の端子と前記電源端子との間にそれぞれ配設され、外部からの入力信号によってON/OFFする短絡スイッチ回路を少なくとも2組有し、前記短絡スイッチ回路をON/OFFする入力信号を印加するための入力端子を少なくとも1端子有し、
検査時、前記検査に使用しない一方の端子に接地電位を印加し、かつ前記検査に使用しない他方の端子に電源電位を印加し、前記入力端子に、前記短絡スイッチ回路をONする入力信号を入力して前記短絡スイッチ回路をONさせることで、前記検査に使用しない一方の端子と前記接地端子とを短絡し、かつ前記検査に使用しない他方の端子と前記電源端子とを短絡することを特徴とする半導体装置。
A semiconductor device for inspecting by applying a power supply voltage to a power supply terminal of a semiconductor element and applying a ground voltage to a ground terminal of the semiconductor element,
There are at least two terminals that are not used for inspection, and are arranged between one terminal that is not used for inspection and the ground terminal and between the other terminal that is not used for inspection and the power supply terminal, respectively. Having at least two sets of short-circuit switch circuits that are turned ON / OFF by an input signal from, and having at least one input terminal for applying an input signal for turning ON / OFF the short-circuit switch circuit
During inspection, a ground potential is applied to one terminal not used for the inspection, a power supply potential is applied to the other terminal not used for the inspection, and an input signal for turning on the short-circuit switch circuit is input to the input terminal. Then, by turning on the short-circuit switch circuit, one terminal not used for the inspection and the ground terminal are short-circuited, and the other terminal not used for the inspection and the power supply terminal are short-circuited. Semiconductor device.
JP2007151488A 2007-06-07 2007-06-07 Semiconductor device inspecting method and semiconductor device Pending JP2008304308A (en)

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Cited By (1)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013178758A (en) * 2012-02-06 2013-09-09 Panasonic Corp Card communication device

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