JP2008300866A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the peel-off of a TiN film from Al alloy wiring in an ashing process when the TiN film is used as an antireflection film. <P>SOLUTION: Filling materials 13g, 16g are filled in crystalline grain boundaries of TiN films 13f, 16f which are used as antireflection films for an Al alloy wiring layer formed on a silicon substrate. By such a means, the invasion of oxygen (O<SB>2</SB>) radicals into an Al-Cu films 13c, 16c can be prevented. Therefore, a reaction between oxygen (O<SB>2</SB>) radicals and the Al-Cu film 13c to form AlxOy can be prevented, and in a process of removing polymers, the reduction of AlxOy by fluorine radicals, and the peel-off of the antireflection films 13f, 16f from the Al-Cu film 13c are prevented. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device having metal wiring.

  A conventional metal wiring structure formed on a semiconductor substrate is shown in FIG. As shown in this figure, the metal wiring is configured by sequentially laminating a barrier metal J1, an Al—Cu alloy (Al alloy wiring) J2, and an antireflection film J3.

The patterning process of the metal wiring is performed as follows. First, a photoresist J4 is placed on the antireflection film J3, and etching is performed with chlorine-based gas using the photoresist J4 as a mask, thereby patterning the Al alloy wiring J2 and the like. Next, the photoresist J4 is removed by oxygen (O ₂ ) ashing. Then, the polymer J5 on the side wall portion of the photoresist J4 formed by the reaction between C in the photoresist J4 and the chlorine-based gas during patterning of the Al alloy wiring J2 or the like is removed with fluorine (F) gas. A metal wiring patterning step is performed by these steps.

  At this time, the antireflection film J3 disposed on the Al alloy wiring J2 is exposed to the photoresist pattern by reflection on the surface of the underlying Al alloy wiring J2 when the photoresist J4 is exposed in the patterning process of the Al alloy wiring J2. It is formed in order to prevent thinning. As the antireflection film J3, for example, a single layer of TiN film composed of TiN columnar crystals is used.

However, when a single layer of TiN film is used as the antireflection film as described above, oxygen radicals pass through the grain boundaries of the TiN columnar crystal during the oxygen (O ₂ ) ashing process for removing the photoresist. Then, an AlxOy oxide is formed at the interface between the Al alloy wiring and the TiN film. Since this oxide is chemically unstable, it is reduced by fluorine radicals in the fluorine gas used for polymer removal. For this reason, it has been found that a slit is formed in the oxide and the TiN film is peeled off from the Al alloy wiring.

  In view of the above points, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of suppressing the peeling of a TiN film from an Al alloy wiring in an ashing process when a TiN film is used as an antireflection film. .

In order to achieve the above object, according to the first aspect of the present invention, an Al alloy wiring layer (13c, 16c) electrically connected to the element and a reflection are formed on the semiconductor substrate (1) on which the semiconductor element is formed. In a method of manufacturing a semiconductor device in which a TiN film (13f, 16f) as a prevention film is formed, after performing a step of forming a TiN film having columnar grain boundaries on an Al alloy wiring layer, the TiN film It is characterized by having a step of filling a crystal grain boundary with a filling substance (13 g, 16 g).

After forming TiN having a crystal grain boundary in this way, oxygen (O ₂ ) ashing is performed by filling the crystal grain boundary with this filler so that the passage of oxygen radicals is suppressed in the crystal grain boundary. Oxygen radicals can be prevented from passing through the TiN film in the process. As a result, it is possible to suppress the TiN film from peeling off from the Al alloy wiring in the oxygen (O ₂ ) ashing process.

Specifically, as shown in claim 2, after forming a TiN film having a crystal grain boundary on an Al alloy wiring, annealing in an N ₂ atmosphere is performed to form TiN in the crystal grain boundary. can do. In addition, as shown in claim 3, TiO obtained by reacting unreacted Ti with oxygen in the atmosphere as a filler can be filled in the crystal grain boundary.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

(First embodiment)
As a semiconductor device to which an embodiment of the present invention is applied, a CMOS transistor having a salicide structure is shown in FIG.

The CMOS transistor includes a PMOS transistor formed in the n ⁻ type well region 2 in the p type silicon substrate 1 and an NMOS transistor formed in the p ⁻ type well region 3. The PMOS transistor and the NMOS transistor are separated from each other by an STI film 4 formed on the top of the silicon substrate 1. Note that the structure of the PMOS transistor and the NMOS transistor are only different in conductivity type, and the other structures are the same, so only the structure of the PMOS transistor will be described.

A gate electrode 6 is formed on n ⁻ type well region 2 with gate oxide film 5 interposed. Sidewall oxide films 7 are provided on the side surfaces of the gate electrode 6. Further, a source 8 and a drain 9 made of a p ⁺ -type diffusion layer are formed on both sides of the gate electrode 6, and a channel region is formed between the source 8 and the drain 9. The p-type layer 10 formed on the channel region side of the source 8 and drain 9 is an electric field relaxation layer.

  Further, contact silicide films 6 a, 8 a, 9 a are formed on the gate electrode 6, the source 8, and the drain 9. Thus, a PMOS transistor having a salicide structure is configured.

  On the silicon substrate 1 including these PMOS transistors and NMOS transistors, an interlayer insulating film 11 made of BPSG, TEOS film or the like is formed, and a tungsten plug filling a contact hole formed in the interlayer insulating film 11 12, the 1st Al alloy wiring 13 formed on the interlayer insulating film 11 and the source 8 and the drain 9 are electrically connected.

  An interlayer insulating film 14 made of a TEOS oxide film or the like and a tungsten plug 15 embedded in a contact hole of the interlayer insulating film 14 are formed on the 1stAl alloy wiring 13, and a 2ndAl alloy wiring 16 is further formed thereon. ing. An interlayer insulating film 17 made of a TEOS oxide film or the like and a tungsten plug 18 embedded in a contact hole of the interlayer insulating film 17 are formed on the 2ndAl alloy wiring 16, and a 3rdAl alloy wiring 19 is further formed thereon. Yes. A protective film 20 composed of a P-TEOS film 20 a and a P-SiN film 20 b is formed on the 3rdAl alloy wiring 19. A CMOS transistor is configured with such a structure.

  Details of the metal wiring structure in the thus configured CMOS transistor will be described. FIG. 2 shows an enlarged view of the broken line portion of FIG.

  An interlayer insulating film 11 is formed on the silicon substrate 1 including the PMOS transistor and the NMOS transistor. A contact hole is formed in the interlayer insulating film 11, and a tungsten plug 12 made of an adhesive layer Ti12a, barrier metal TiN12b, and tungsten 12c is buried in the hole. The tungsten plug 12 electrically connects the silicon substrate 1 and the Al alloy wiring 13. Further, an interlayer insulating film 14 is formed on the 1st Al alloy wiring 13. A via hole is formed in the interlayer insulating film 14, and a tungsten plug 15 is embedded in the via hole. With this tungsten plug 15, the 2ndAl alloy wiring 16 is electrically connected to the latitude 13 of the 1stAl alloy.

  The 1stAl alloy wiring 13 and the 2ndAl alloy wiring 16 have the same structure, and contain 0.5 wt% of Ti films 13a, 16a having a thickness of about 20 nm, TiN films 13b, 16b, and Cu having a thickness of about 30 nm. The Al—Cu films 13c and 16c and the antireflection films 13d, 13e, 16d, and 16e each having a film thickness of about 300 to 1000 nm made of the Al alloy thus formed are sequentially stacked.

  FIG. 3 shows an enlarged view of the antireflection films 13d, 13e, 16d, and 16e. As shown in this figure, the antireflection films 13d, 13e, 16d, and 16e have a structure in which amorphous TiN films 13d and 16d and crystalline TiN films 13e and 16e are stacked. The non-crystalline TiN films 13d and 16d are, for example, 10 to 30 nm, and the crystalline TiN films 13e and 16e are, for example, 30 nm. Specifically, the non-crystalline TiN films 13d and 16d are made of amorphous TiN, and do not have columnar crystal grain boundaries like the crystalline TiN films 13e and 16e.

By adopting the TiN films 13d, 13e, 16d, and 16e having such a configuration, O ₂ radicals are blocked by the amorphous TiN films 13d and 16d during oxygen (O ₂ ) ashing described later. The Al—Cu films 13c and 16c are prevented from entering.

  For the 3rdAl alloy wiring 19, the Ti film 19a, the TiN film 19b, and the Al—Cu film 19c have the same configuration as the Ti films 13a, 16a, the TiN films 13b, 16b, and the Al—Cu films 13c, 16c. Yes. However, the TiN film 19d has the same configuration as the crystalline TiN films 13e and 16e. This is because the 3rdAl alloy wiring 19 is not required to have a function as an antireflection film due to a large wiring design margin. As described above, it is particularly effective to employ the antireflection film structure as described above for the 1st, 2ndAl alloy wirings 13 and 16, and for the 3rdAl alloy wiring 19, the 1st, 2ndAl alloy wirings 13 and 16 are used. It is not necessary to adopt a simple antireflection film structure.

  Next, a manufacturing process of the CMOS transistor is shown in FIGS. Hereinafter, a method for manufacturing a CMOS transistor will be described with reference to FIGS.

[Step shown in FIG. 4 (a)]
First, a p-type silicon substrate 1 is prepared. Next, a thermal oxide film (SiO ₂ ) 40 is formed on the silicon substrate 1, and a silicon nitride film (SiN) 41 is further formed on the thermal oxide film 40. Then, through the photolithography process, the silicon nitride film 41 and the thermal oxide film 40 below the silicon nitride film 41 on the region where the element isolation STI film 4 (see FIG. 1) is to be formed are opened. Thereafter, the silicon substrate 1 is etched away from the opening by a predetermined depth, and the trench 42 for element isolation is patterned. At this time, the trench 42 is formed to a depth of about 0.3 to 0.6 μm so that element isolation in the element portion can be sufficiently performed.

[Step shown in FIG. 4B]
A thermal oxide film 43 is formed on the inner wall of the trench 42 to round the trench 42. Thereafter, a TEOS film is deposited on the entire surface of the silicon substrate 1, and the TEOS film is embedded in the trench 42. At this time, HTO-TEOS, LP-TEOS, O ₃ -TEOS, or the like is used as the TEOS film. Then, the entire surface of the TEOS film is ground and planarized by CMP using the silicon nitride film 41 as a stopper. As a result, the TEOS film is left in the trench 42 and the STI film 4 is formed.

[Step shown in FIG. 4C]
The silicon nitride film 41 is removed, an n ⁻ type well region 2 is formed in the PMOS transistor formation planned region through a photoresist process, and then a p ⁻ type well region 3 is formed in the NMOS transistor formation planned region again through a photolithography process. To do.

The thermal oxide film 40 is removed by wet etching. Then, after sacrificial oxidation is performed simultaneously with drive-in to improve the surface state of the n ⁻ type well region 2 and the p ⁻ type well region 3, a gate oxide film 5 is formed by thermal oxidation. Then, after a polysilicon film having a thickness of about 0.35 μm is formed on the gate oxide film 5, the gate electrode 6 is patterned through a photolithography process.

  Next, after depositing an insulating film such as a TEOS film on the entire wafer surface by the CVD method, the insulating film is etched back by anisotropic etching by the RIE method to form the sidewall film 7 on the side surface of the gate electrode 6.

[Step shown in FIG. 5A]
After forming a through film for an ion implantation process by thermal oxidation or the like, the NMOS transistor formation planned region and the PMOS transistor formation planned region are sequentially covered with a photoresist, and a p-type impurity (for example, boron) is obliquely applied to the PMOS transistor formation planned region. Ions are implanted, and n-type impurities (for example, phosphorus) are obliquely implanted into the NMOS transistor formation region. Thereby, ion implantation is performed using the gate electrode 6 covered with the sidewall film 7 as a mask, and the electric field relaxation layer 10 is formed on both sides of the gate electrode 6 from the inside of the gate electrode 6.

  Further, the NMOS transistor formation region and the PMOS transistor formation region are sequentially covered with a photoresist, and p-type impurities (for example, boron) are ion-implanted in a high concentration from the normal direction of the substrate to form the NMOS transistor. An n-type impurity (for example, As) is ion-implanted into the planned region at a high concentration from the substrate normal direction. As a result, the source 8 and the drain 9 are formed on both sides of the gate electrode 6 covered with the side wall surface 7. As a result, a lightly doped drain (LDD) structure is completed.

  Then, after removing the through film, a titanium silicidation step is performed. First, a titanium (Ti) film and a titanium nitride (TiN) film are sequentially formed on the entire surface of the wafer, and further, a short-time heat treatment (RTA) is performed in an Ar atmosphere to cause a silicidation reaction. 8. Titanium silicide films (TiSi 2 films) 6 a, 8 a, 9 a are formed on the exposed surfaces of the drain 9.

  The silicidation heat treatment temperature is a relatively low temperature of 700 ° C. or less from the viewpoint of suppressing the rise of silicide to the sidewall film 7, preventing the reaction of the sidewall film 7 with Si, and suppressing the transformation of TiSi 2 from C49 to C54 phase. It is set to low temperature.

  Then, selective etching is performed with a mixed solution of ammonia and hydrogen peroxide solution, and portions of the titanium film and the titanium nitride film that have not undergone silicidation are removed. As a result, only the titanium silicide films 6a, 8a and 9a remain. Thereby, the salicide structure is completed.

  Thereafter, a second short-time heat treatment is performed at about 850 ° C. to reduce the resistance of the titanium silicide films 6a, 8a, 9a.

[Step shown in FIG. 5B]
After an insulating film 11 made of BPSG, TEOS film or the like is deposited on the entire surface of the wafer, the insulating film 11 is flattened by CMP.

[Step shown in FIG. 5 (c)]
A contact hole is formed in the insulating film 11 through a photolithography process. Then, a Ti film 12a and a TiN film 12b are sequentially stacked in the contact hole as an adhesive layer and a barrier metal, and tungsten (W) 12c is further stacked on the Ti film 12a and the TiN film 12b. As a result, the contact holes are filled with the barrier metals 12a and 12b and the tungsten 12c.

  Thereafter, the barrier metals 12a, 12b and tungsten 12c are etched back, leaving the barrier metals 12a, 12b and tungsten 12c only in the contact holes. As a result, the tungsten plug 12 that is electrically connected to the source 8 and the drain 9 is formed.

[Step shown in FIG. 6A]
In order to form the 1st Al alloy wiring 13, a metal film is formed on the entire wafer surface. As the metal film, a Ti film 13a having a thickness of about 30 nm, a TiN film 13b having a thickness of about 20 nm, and an Al—Cu film 13c having a thickness of about 200 to 1000 nm are sequentially stacked. The Al—Cu film 13c is formed by reflow sputtering, normal sputtering at a substrate temperature of about 100 to 300 ° C., high temperature sputtering at a substrate temperature of about 350 to 450 ° C., or the like. Further, an Al—Si—Cu film may be used instead of the Al—Cu film 13c.

  Subsequently, antireflection films 13d and 13e are formed on the metal film. Specifically, the amorphous TiN film 13d is formed in a thickness of about 10 to 30 nm, and the crystalline TiN film 13e is sequentially formed in a thickness of about 30 nm. A manufacturing method and conditions for the TiN films 13d and 13e will be described below.

First, when forming the amorphous TiN film 13d, sputtering is performed by introducing only Ar gas without introducing N ₂ at the initial stage of film formation, and then Ar gas and N ₂ are mixed at a ratio of 1: 1. The introduced sputtering is performed. The sputtering conditions are such that the DC power is about 3 to 8 kW (when the target diameter is 12 inches) and the temperature is about room temperature to about 130 ° C.

Specifically, TiN is formed on the Ti surface by nitriding the target Ti surface, and sputtering is performed using TiN as a target, thereby forming a film without introducing N ₂ into the atmosphere. From the initial stage, the TiN film 13d is formed on the surface of the Al-Cu film 13c. Then, when all of TiN on the Ti surface is ejected (or before that), N ₂ is introduced into the atmosphere and sputtering is continued to form the TiN film 13d.

  Next, only sputtering and temperature conditions when the amorphous TiN film 13d is formed are changed. Specifically, the sputtering temperature is set to about 150 ° C. to about 350 ° C. Then, a crystalline TiN film 13e is formed by forming a TiN film of about 30 nm under this temperature condition.

[Step shown in FIG. 6B]
Next, a photolithography process is performed to pattern the 1st Al alloy wiring 13. Specifically, first, a photoresist is deposited on the crystalline TiN film 13e, and portions other than the portion to be left as the 1st Al alloy wiring 13 in the photoresist are opened. Thereafter, an etching process using a photoresist as a mask is performed.

First, the TiN films 13e and 13d, the Al—Cu film 13c, the TiN film 13b, and the Ti film 13a are removed by etching using a chlorine-based etching gas. At this time, most of the photoresist is also removed, but since it remains on the TiN film 13e to some extent, oxygen (O ₂ ) ashing is then performed to remove the remaining portion of the photoresist.

At the time of this oxygen (O ₂ ) ashing, oxygen (O ₂ ) radicals enter the crystal grain boundaries of the crystalline TiN film 13e, but the entry is stopped by the amorphous TiN film 13d. It becomes possible to suppress the entry of oxygen (O ₂ ) radicals into the Cu film 13c. For this reason, it is possible to prevent the formation of AlxOy due to the reaction between the oxygen (O ₂ ) radical and the Al—Cu film 13 c.

Thereafter, when the 1stAl alloy wiring 13 is patterned, C formed in the photoresist reacts with the chlorine-based gas to remove the polymer formed on the side wall portion of the photoresist with fluorine (F) gas. At this time, since AlxOy is hardly formed at the time of the oxygen (O ₂ ) ashing performed earlier, AlxOy is reduced by fluorine radicals, and the antireflection films 13d and 13e are peeled off from the Al—Cu film 13c. Nor.

[Step shown in FIG. 6 (c)]
The 2ndAl alloy wiring 15 is formed through the interlayer insulating film 14 through the same process as the 1stAl alloy wiring 13 shown in FIGS. 5C, 6A, and 6B. 5C, FIG. 6A, and FIG. 6B other than the manufacturing process of the amorphous TiN film 13d are performed, and the 3rdAl alloy wiring 19 is formed through the interlayer insulating film 17. Form.

  Thereafter, a protective film 20 made of a P-TEOS film 20a and a P-SiN film 20b is formed on the entire wafer surface, thereby completing the semiconductor device shown in FIG.

  As described above, in the semiconductor device of this embodiment, a structure in which the amorphous TiN films 13d and 16d and the crystalline TiN films 13e and 16e are stacked as the antireflection film of the Al alloy wirings 13 and 16. Is adopted.

Therefore, it is possible to prevent oxygen (O ₂ ) radicals from entering the Al—Cu films 13 c and 16 c during oxygen (O ₂ ) ashing performed after the etching of the 1st and 2nd Al alloy wirings 13 and 16. . Therefore, the reaction between the oxygen (O ₂ ) radical and the Al—Cu film 13c is prevented from forming AlxOy, AlxOy is reduced by the fluorine radical during the removal of the polymer, and the antireflection films 13d and 13e are made of Al—Cu. It does not peel off from the film 13c.

In addition, when the occurrence rate of peeling of the antireflection film when the method for manufacturing a semiconductor device as in the present embodiment was applied was examined, the result shown in FIG. 7 was obtained. In this experiment, when the DC power at the time of sputtering is 3 kW and the ratio of Ar gas to N ₂ is 1: 1, the temperature at which the antireflection film is formed is examined for peeling.

  As shown in this figure, the antireflection film depends on whether or not there is a portion where the TiN film is 150 ° C. or lower, that is, whether or not there is an amorphous TiN film that becomes an amorphous region in the antireflection film. Peeling incidence varies greatly. Also from this result, it can be seen that the above-described effect can be obtained by forming the amorphous TiN films 13d and 16d on the Al-Cu films 13c and 16c.

(Second Embodiment)
A second embodiment of the present invention will be described. In the semiconductor device according to this embodiment, the configuration of the TiN film formed on the surfaces of the Al—Cu films 13c and 16c is changed with respect to the first embodiment, and the other configuration and manufacturing method are exactly the same. It is.

  FIG. 8 shows a cross-sectional configuration of the TiN films 13f and 16f in the 1st, 2ndAl alloy wirings 13 and 16 in the semiconductor device of this embodiment. As shown in this figure, the TiN films 13f and 16f have columnar crystallinity. The columnar crystal grain boundaries of the TiN films 13f and 16f are filled with filling materials 13g and 16g such as TiN and TiO.

Therefore, it is possible to prevent oxygen (O ₂ ) radicals from entering the Al—Cu films 13 c and 16 c during oxygen (O ₂ ) ashing performed after the etching of the 1st and 2nd Al alloy wirings 13 and 16. . Accordingly, reaction of oxygen (O ₂ ) radicals with the Al—Cu film 13 c to prevent AlxOy from being formed, AlxOy is reduced by fluorine radicals during polymer removal, and the antireflection films 13 f and 16 f become Al—Cu. It does not peel off from the film 13c.

  The manufacturing process of the TiN films 13f and 16f and the filling materials 13g and 16g shown in the present embodiment is performed as follows.

For example, in the case of the TiN film 13f, the process is performed up to the step of FIG. 5C shown in the first embodiment. Thereafter, the Al—Cu film 13c is formed by the same process as in FIG. Then, the TiN film 13f is formed by a sputtering process similar to the process of forming the crystalline TiN film 13e without performing the process of forming the amorphous TiN film 13d. At this time, it is possible to prevent N ₂ from being introduced at the initial stage of formation of the TiN film 13f by using a sputtering target having a Ti film surface nitrided.

Next, annealing is performed at about 400 ° C. to about 500 ° C. while introducing N ₂ . By this treatment, Ti 2 or TiN originally present in the TiN film 13f reacts with introduced N ₂ having a weak crystallinity or O ₂ remaining in the atmosphere, whereby the crystal grains of the TiN film 13f. The field is filled with 13 g of filling material.

  The TiN film 16f is the same as the TiN film 13f, and the crystal grain boundaries of the TiN film 16f can be filled with the filling material 16g by the same method as described above.

  As described above, the same effects as those of the first embodiment can also be obtained by filling the crystal grain boundaries of the TiN films 13f and 16f with the filler substances 13g and 16g.

(Other embodiments)
In the first embodiment, the non-crystalline TiN films 13d and 16d are disposed below the crystalline TiN films 13e and 16e. However, they may be formed in the middle thereof.

It is a figure showing the section composition of the semiconductor device in a 1st embodiment of the present invention. It is an enlarged view of the broken-line part of FIG. FIG. 2 is an enlarged view of a TiN film of the semiconductor device shown in FIG. 1. FIG. 2 is a diagram showing a manufacturing process of the semiconductor device shown in FIG. 1. FIG. 5 is a diagram showing a manufacturing step of the semiconductor device following that of FIG. 4; FIG. 6 is a diagram showing a manufacturing step of the semiconductor device following that of FIG. 5; It is the figure which showed the relationship of peeling of an amorphous TiN film | membrane and an antireflection film. It is an enlarged view of the TiN film | membrane of the semiconductor device in 2nd Embodiment of this invention. It is the figure which showed the manufacturing process of the conventional Al alloy wiring.

Explanation of symbols

  13 ... 1stAl alloy wiring, 16 ... 2nd Al alloy wiring, 13c, 16c ... Al-Cu film, 13d, 16d ... non-crystalline TiN film, 13e, 16e ... crystalline TiN film.

Claims (3)

An Al alloy wiring layer (13c, 16c) electrically connected to the element and a TiN film (13f, 16f) as an antireflection film are formed on the semiconductor substrate (1) on which the semiconductor element is formed. In a method for manufacturing a semiconductor device,
Forming the Al alloy wiring layer on the semiconductor substrate;
Forming a TiN film having columnar grain boundaries on the Al alloy wiring layer;
And filling the TiN film crystal grain boundary with a filling material (13 g, 16 g). _{2. The} step of filling the crystal grain boundary with a filler includes forming TiN as the filler material in the crystal grain boundary by performing annealing in an N ₂ atmosphere. Semiconductor device manufacturing method.   The step of filling the crystal grain boundary includes filling TiO serving as the filler into the crystal grain boundary by reacting unreacted Ti present in the TiN film with oxygen in the atmosphere. A method for manufacturing a semiconductor device according to claim 2.

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