JP2008300284A - Semiconductor device - Google Patents

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JP2008300284A
JP2008300284A JP2007147007A JP2007147007A JP2008300284A JP 2008300284 A JP2008300284 A JP 2008300284A JP 2007147007 A JP2007147007 A JP 2007147007A JP 2007147007 A JP2007147007 A JP 2007147007A JP 2008300284 A JP2008300284 A JP 2008300284A
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semiconductor device
fixed electrode
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electrode
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JP4970150B2 (en
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Kazutaka Takagi
一考 高木
Naotaka Tomita
直孝 冨田
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Toshiba Corp
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<P>PROBLEM TO BE SOLVED: To provide an electrostatic MEMS which can be driven at a low voltage with a simple structure, easy to be manufactured, such as a metal movable electrode obtained by integrating a high frequency movable electrode and a movable electrode for electrostatic MEMS driving, and which is not self-actuated or self-held by a high frequency signal. <P>SOLUTION: A semiconductor device consists of an anchor 14 that fixes one end of the movable electrode and the surface of a dielectric substrate so that an air gap is formed between the surface of the dielectric substrate 24 and the movable electrode 10, a high frequency fixed electrode 18 that is arranged on the surface of the dielectric substrate so as to be opposite to the other end of the movable electrode, a via hole 20 in which the lower electrode 22 on the rear face of the dielectric substance and the lower electrode of the high frequency fixed electrode are connected to each other, a driving fixed electrode 16 that is arranged between the anchor on the surface of the dielectric substrate and the high frequency fixed electrode, and an insulating film 12 that covers the high frequency fixed electrode and the driving fixed electrode. In the semiconductor device, a driving voltage is applied between the driving fixed electrode and the movable electrode via a bias circuit with a high impedance at least against the high frequency. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は半導体装置に関し、特に、MEMS(Micro-Electro-Mechanical Systems)技術を用いて形成した可変容量やスイッチなどを低電圧で駆動でき、かつ大電力高周波信号でセルフアクチュエーションやセルフホールディングしない、製造し易い半導体装置(静電MEMS)に関する。   The present invention relates to a semiconductor device, in particular, a variable capacitor or a switch formed using MEMS (Micro-Electro-Mechanical Systems) technology can be driven at a low voltage, and does not self-actuate or self-hold with a high-power high-frequency signal. The present invention relates to an easily manufactured semiconductor device (electrostatic MEMS).

マイクロマシンもしくはMEMS(Micro-Electro-Mechanical Systems)技術を用いて形成した可変容量やスイッチなどの駆動電圧を低電圧にする技術は既に開示されている(例えば、特許文献1参照。)。   A technique for reducing the driving voltage of a variable capacitor or a switch formed by using a micromachine or a MEMS (Micro-Electro-Mechanical Systems) technique has already been disclosed (for example, see Patent Document 1).

特許文献1では駆動電圧を低電圧にするために静電MEMSだけでなく、圧電体層を電極で挟んだ圧電MEMSを併用するので、高周波信号の印加による温度上昇で圧電MEMSの熱膨張係数差の問題が発生しやすい。   In Patent Document 1, since not only electrostatic MEMS but also piezoelectric MEMS in which a piezoelectric layer is sandwiched between electrodes are used in order to reduce the drive voltage, the difference in thermal expansion coefficient between piezoelectric MEMS due to temperature rise due to application of a high-frequency signal. The problem is likely to occur.

また、特許文献1では高周波信号の静電引力によって可動電極が固定電極に引き寄せられるセルフアクチュエーションや離れなくなるセルフホールディングが起き難くするために、高周波(RF)固定電極と静電MEMS駆動用固定電極に対向した高周波可動電極と駆動用可動電極を、絶縁性の駆動アームに別々に配置する必要があるので、圧電MEMSの製造工程に加えて製造工程が複雑で長くなる。
特開2004−302711号公報(第4頁、第1図)
Further, in Patent Document 1, a high frequency (RF) fixed electrode and a fixed electrode for driving an electrostatic MEMS are provided in order to prevent the self-actuation in which the movable electrode is attracted to the fixed electrode by the electrostatic attraction force of the high frequency signal and the self-holding in which the movable electrode is not separated. Since it is necessary to separately arrange the high-frequency movable electrode and the drive movable electrode that face each other on the insulating drive arm, the manufacturing process becomes complicated and long in addition to the manufacturing process of the piezoelectric MEMS.
JP 2004-302711 A (page 4, FIG. 1)

本発明の目的は、高周波可動電極と静電MEMS駆動用可動電極を一体化した金属の可動電極という単純な製造し易い構造で、低電圧で駆動でき、かつ高周波信号でセルフアクチュエーションやセルフホールディングしない半導体装置を提供することにある。   The object of the present invention is a simple and easy-to-manufacture structure, which is a metal movable electrode in which a high-frequency movable electrode and a movable electrode for electrostatic MEMS driving are integrated. An object of the present invention is to provide a semiconductor device that does not.

上記目的を達成するための本発明の請求項1に記載の半導体装置は、誘電体基板の表面と可動電極との間に空隙を形成するように前記可動電極の一端と前記誘電体基板の表面を固定するアンカーと、前記可動電極の他端と対向するように前記誘電体基板の表面に配置された高周波固定電極と、前記誘電体基板の裏面の下部電極と、前記高周波固定電極と前記下部電極を接続するビアホールと、前記誘電体基板の表面の前記アンカーと前記高周波固定電極の間に配置された駆動用固定電極と、前記高周波固定電極と前記駆動用固定電極を覆う絶縁膜とを備え、前記駆動用固定電極と前記可動電極との間に、少なくとも高周波に対してインピーダンスが高いバイアス回路を経由して、駆動電圧を印加することを特徴とする。   In order to achieve the above object, a semiconductor device according to claim 1 of the present invention is characterized in that one end of the movable electrode and the surface of the dielectric substrate are formed so as to form a gap between the surface of the dielectric substrate and the movable electrode. An anchor for fixing the electrode, a high-frequency fixed electrode disposed on the surface of the dielectric substrate so as to face the other end of the movable electrode, a lower electrode on the back surface of the dielectric substrate, the high-frequency fixed electrode, and the lower portion A via hole connecting the electrodes; a driving fixed electrode disposed between the anchor on the surface of the dielectric substrate and the high frequency fixed electrode; and an insulating film covering the high frequency fixed electrode and the driving fixed electrode. A driving voltage is applied between the driving fixed electrode and the movable electrode via a bias circuit having a high impedance at least for a high frequency.

そして、可動電極の駆動用固定電極に対向する領域の一部にスリットを入れて舌状可動部を作り、舌状可動部の先端側の少なくても一部を誘電体基板の方に凸とする。また、凸部までを段差が小さい階段状にするか、なだらかな傾斜面にする。   Then, a slit is made in a part of the region of the movable electrode facing the driving fixed electrode to form a tongue-like movable part, and at least a part of the tip side of the tongue-like movable part protrudes toward the dielectric substrate. To do. Further, the convex part is formed in a stepped shape with a small step or a gentle inclined surface.

本発明によれば、高周波可動電極と静電MEMS駆動用可動電極を一体化した金属の可動電極という単純な製造し易い構造で、低電圧で駆動でき、かつ高周波信号でセルフアクチュエーションやセルフホールディングしない半導体装置を提供することができる。   According to the present invention, a metal movable electrode in which a high-frequency movable electrode and a movable electrode for electrostatic MEMS driving are integrated is a simple and easy-to-manufacture structure, which can be driven at a low voltage and can be driven by a high-frequency signal. It is possible to provide a semiconductor device that does not.

次に、図面を参照して、本発明の実施の形態を説明する。以下の図面の記載において、同一又は類似の部分には同一又は類似の符号を付している。ただし、図面は模式的なものであり、現実のものとは異なることに留意すべきである。又、図面相互間においても互いの寸法の関係や比率が異なる部分が含まれていることはもちろんである。 Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic and different from the actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

また、以下に示す実施の形態は、この発明の技術的思想を具体化するための装置や方法を例示するものであって、この発明の技術的思想は、各構成部品の配置等を下記のものに特定するものでない。この発明の技術的思想は、特許請求の範囲において、種々の変更を加えることができる。 Further, the embodiment described below exemplifies an apparatus and a method for embodying the technical idea of the present invention. The technical idea of the present invention is the arrangement of each component as described below. It is not something specific. The technical idea of the present invention can be variously modified within the scope of the claims.

[第1の実施の形態]
図1は、本発明の第1の実施の形態に係る半導体装置の模式的平面パターン構成図を示す。また、図2は、図1のI―I線に沿う模式的断面構造図、図3は、図1のII―II線に沿う模式的断面構造図、図4は、図1のIII―III線に沿う模式的断面構造図、図5は、図1のIV―IV線に沿う模式的断面構造図をそれぞれ示している。
[First embodiment]
FIG. 1 is a schematic plane pattern configuration diagram of a semiconductor device according to a first embodiment of the present invention. 2 is a schematic cross-sectional structure diagram taken along the line II of FIG. 1, FIG. 3 is a schematic cross-sectional structure diagram taken along the line II-II of FIG. 1, and FIG. FIG. 5 shows a schematic cross-sectional structure diagram along line IV-IV in FIG. 1, respectively.

本発明の第1の実施の形態に係る半導体装置は、図1乃至図5に示すように、誘電体基板24の表面と可動電極10との間に空隙を形成するように可動電極10の一端と誘電体基板24の表面を固定するアンカー14と、可動電極10の他端と対向するように誘電体基板24の表面に配置された高周波固定電極18と、誘電体基板24の裏面の下部電極22と、高周波固定電極18と下部電極22を接続するビアホール20と、誘電体基板24の表面のアンカー14と高周波固定電極18の間に配置された駆動用固定電極16と、高周波固定電極18と駆動用固定電極16を覆う絶縁膜12とを備え、駆動用固定電極16と可動電極10との間に、少なくともRF高周波に対してインピーダンスが高いバイアス回路を経由して、駆動電圧を印加することを特徴とする静電MEMSを構成している。   As shown in FIGS. 1 to 5, the semiconductor device according to the first embodiment of the present invention has one end of the movable electrode 10 so as to form a gap between the surface of the dielectric substrate 24 and the movable electrode 10. The anchor 14 for fixing the surface of the dielectric substrate 24, the high-frequency fixed electrode 18 disposed on the surface of the dielectric substrate 24 so as to face the other end of the movable electrode 10, and the lower electrode on the back surface of the dielectric substrate 24 22, via hole 20 connecting high-frequency fixed electrode 18 and lower electrode 22, driving fixed electrode 16 disposed between anchor 14 and high-frequency fixed electrode 18 on the surface of dielectric substrate 24, high-frequency fixed electrode 18, And an insulating film 12 covering the driving fixed electrode 16, and a driving voltage is applied between the driving fixed electrode 16 and the movable electrode 10 via a bias circuit having a high impedance at least with respect to the RF high frequency. Constitute an electrostatic MEMS, characterized by.

また、本発明の第1の実施の形態に係る半導体装置においては、誘電体基板24の厚さが空隙の高さと絶縁膜12の厚さの和より厚く構成されていても良い。   In the semiconductor device according to the first embodiment of the present invention, the thickness of the dielectric substrate 24 may be greater than the sum of the height of the gap and the thickness of the insulating film 12.

また、本発明の第1の実施の形態に係る半導体装置においては、駆動用固定電極16の面積が高周波固定電極18の面積より広く構成されていても良い。   In the semiconductor device according to the first embodiment of the present invention, the area of the driving fixed electrode 16 may be larger than the area of the high-frequency fixed electrode 18.

本発明の第1の実施の形態に係る半導体装置は、図1乃至図5および図6乃至図9に示すように、アンカー14と駆動用固定電極16までの可動電極10の幅を狭くして、ばねの力を調整している。   In the semiconductor device according to the first embodiment of the present invention, as shown in FIGS. 1 to 5 and FIGS. 6 to 9, the width of the movable electrode 10 to the anchor 14 and the driving fixed electrode 16 is reduced. The spring force is adjusted.

なお、本発明の第1の実施の形態に係る半導体装置において、RF高周波の周波数は、当該半導体装置の適用される応用分野に応じて適宜選択される周波数である。例えば、携帯電話に適用する場合には、数100MHz〜数GHzである。   In the semiconductor device according to the first embodiment of the present invention, the frequency of the RF high frequency is a frequency that is appropriately selected according to the application field to which the semiconductor device is applied. For example, when applied to a mobile phone, it is several hundred MHz to several GHz.

(静電引力)
空隙の高さをT1、絶縁膜12の厚さをT2、誘電体基板24の厚さをT3とする。高周波固定電極18の面積をS1=W1×L1、駆動用固定電極16の面積をS2=W2×L2とする。S1とS2以外の可動電極10の面積は十分狭いとすると、静電引力は以下の様に近似できる。
(Electrostatic attraction)
Assume that the height of the gap is T 1 , the thickness of the insulating film 12 is T 2 , and the thickness of the dielectric substrate 24 is T 3 . The area of the high-frequency fixed electrode 18 is S 1 = W 1 × L 1 , and the area of the driving fixed electrode 16 is S 2 = W 2 × L 2 . If the area of the movable electrode 10 other than S 1 and S 2 is sufficiently small, the electrostatic attractive force can be approximated as follows.

駆動電圧VDRが印加されていない状態に駆動電圧VDRが印加されると、駆動用固定電極16とそれに対向する可動電極10の間のT1+T2に駆動電圧VDRがかかり、静電引力
FDR-20S2VDR 2/{2(T1+T2A)2}
が働く。ここで、ε0は真空中の誘電率、εAは絶縁膜12の比誘電率である。
When the drive voltage V DR is applied in a state where the drive voltage V DR is not applied, the drive voltage V DR is applied to T 1 + T 2 between the drive fixed electrode 16 and the movable electrode 10 facing the drive electrode V DR , Electromotive force
F DR-2 = ε 0 S 2 V DR 2 / {2 (T 1 + T 2 / ε A ) 2 }
Work. Here, ε 0 is the dielectric constant in vacuum, and ε A is the relative dielectric constant of the insulating film 12.

本発明の第1の実施の形態に係る静電MEMSは、高周波固定電極18と可動電極10との間に、少なくともRF高周波に対してインピーダンスが高いバイアス回路を経由して、駆動電圧VDRを印加することを特徴とする。 In the electrostatic MEMS according to the first embodiment of the present invention, the drive voltage VDR is applied between the high-frequency fixed electrode 18 and the movable electrode 10 via a bias circuit having a high impedance with respect to at least the RF high-frequency. It is characterized by applying.

高周波固定電極18とそれに対向する可動電極10にも駆動電圧VDRを印加する場合は、静電引力
FDR-10S1VDR 2/{2(T1+T2A)2}
が働く。
When the drive voltage VDR is also applied to the high-frequency fixed electrode 18 and the movable electrode 10 opposed thereto, the electrostatic attractive force
F DR-1 = ε 0 S 1 V DR 2 / {2 (T 1 + T 2 / ε A ) 2 }
Work.

そして、可動電極10が絶縁膜12に引き寄せられた時(T1=0)の静電引力はそれぞれ
FDR-2’=ε0S2A VDR)2/(2T2 2)
FDR-1’=ε0S1A VDR)2/(2T2 2)
となる。
When the movable electrode 10 is attracted to the insulating film 12 (T 1 = 0), the electrostatic attractive force is
F DR-2 '= ε 0 S 2A V DR ) 2 / (2T 2 2 )
F DR-1 '= ε 0 S 1A V DR ) 2 / (2T 2 2 )
It becomes.

図6は、図2において、この駆動電圧印加時における図1のI―I線に沿う模式的断面構造図を示し、図7は、図3において、駆動電圧印加時における図1のII―II線に沿う模式的断面構造図、図8は、図4において、駆動電圧印加時における図1のIII―III線に沿う模式的断面構造図、図9は、図5において、駆動電圧印加時における図1のIV―IV線に沿う模式的断面構造図をそれぞれ示している。   FIG. 6 is a schematic sectional view taken along the line II of FIG. 1 when the drive voltage is applied in FIG. 2, and FIG. 7 is a cross-sectional view taken along the line II-II of FIG. 8 is a schematic cross-sectional structure diagram taken along the line, FIG. 8 is a schematic cross-sectional structure diagram taken along the line III-III of FIG. 1 when the drive voltage is applied in FIG. 4, and FIG. 4 is a schematic cross-sectional structure diagram taken along line IV-IV in FIG.

駆動電圧VDRが印加されていない状態に高周波(RF)電圧VRFが印加されると、駆動用固定電極16では下部電極22と可動電極10の間のT1+T2+T3に高周波(RF)電圧VRFがかかる。 When the high frequency (RF) voltage V RF is applied in a state where the drive voltage V DR is not applied, the fixed electrode 16 for driving has a high frequency of T 1 + T 2 + T 3 between the lower electrode 22 and the movable electrode 10. (RF) Voltage V RF is applied.

駆動電圧VDRは少なくともRF高周波に対してインピーダンスが高いバイアス回路を経由して印加されるので、RF高周波にとってバイアス回路側は無視できる。 Since the driving voltage VDR is applied via a bias circuit having a high impedance at least with respect to the RF high frequency, the bias circuit side can be ignored for the RF high frequency.

下部電極22と駆動用固定電極16と可動電極10は平行に配置されているので、たとえ駆動用固定電極16を細かく分割しても、それらの電位は同じである。従って、RF高周波では駆動用固定電極16は無視でき、静電引力
FRF-20S2VRF 2/{2(T1+T2A+T3B)2}
が働く。ここで、εBは誘電体基板24の比誘電率である。
Since the lower electrode 22, the driving fixed electrode 16 and the movable electrode 10 are arranged in parallel, even if the driving fixed electrode 16 is divided finely, their potentials are the same. Therefore, the driving fixed electrode 16 can be ignored at RF high frequency, and electrostatic attraction
F RF-2 = ε 0 S 2 V RF 2 / {2 (T 1 + T 2 / ε A + T 3 / ε B ) 2 }
Work. Here, ε B is a relative dielectric constant of the dielectric substrate 24.

一方、高周波固定電極18では高周波固定電極18と可動電極10の間のT1+T2に高周波電圧VRFがかかり、静電引力
FRF-10S1VRF 2/{2(T1+T2A)2}
が働く。
On the other hand, in the high frequency fixed electrode 18, the high frequency voltage V RF is applied to T 1 + T 2 between the high frequency fixed electrode 18 and the movable electrode 10, and electrostatic attraction
F RF-1 = ε 0 S 1 V RF 2 / {2 (T 1 + T 2 / ε A ) 2 }
Work.

そして、可動電極10が絶縁膜12に引き寄せられた時(T1=0)の静電引力はそれぞれ
FRF-2’=ε0S2VRF 2/{2(T2A+T3B)2}
FRF-1’=ε0S1A VRF)2/(2T2 2)
となる。
When the movable electrode 10 is attracted to the insulating film 12 (T 1 = 0), the electrostatic attractive force is
F RF-2 '= ε 0 S 2 V RF 2 / {2 (T 2 / ε A + T 3 / ε B ) 2 }
F RF-1 '= ε 0 S 1A V RF ) 2 / (2T 2 2 )
It becomes.

この高周波電圧VRFによる静電引力でセルフアクチュエーションやセルフホールディングが起こるが、誘電体基板24の厚さT3を十分大きくすれば、静電引力FRF-2やFRF-2’は十分小さくできる。 Self-actuation and self-holding occur due to the electrostatic attractive force generated by the high-frequency voltage V RF. If the thickness T 3 of the dielectric substrate 24 is sufficiently increased, the electrostatic attractive forces F RF-2 and F RF-2 ′ are sufficient. Can be small.

この場合、駆動用固定電極16の面積S2を高周波固定電極18の面積S1より大きくすれば、高周波固定電極18の高周波信号の静電引力(FRF-1やFRF-1’)によるセルフアクチュエーションやセルフホールディングを起こさない様にばねの力を強くした可動電極10を、駆動用固定電極16の低い駆動電圧による静電引力(FDR-2やFDR-2’)で引き寄せることができる。 In this case, if the area S 2 of the driving fixed electrode 16 is larger than the area S 1 of the high-frequency fixed electrode 18, it is caused by the electrostatic attractive force (F RF-1 or F RF-1 ′) of the high-frequency signal of the high-frequency fixed electrode 18. Pulling the movable electrode 10 with a strong spring force so as not to cause self-actuation or self-holding by electrostatic attraction ( FDR-2 or FDR-2 ') due to a low driving voltage of the driving fixed electrode 16 Can do.

また、誘電体基板24の厚さT3を十分大きくすれば静電容量は高周波固定電極18の部分が支配的になる。 Further, if the thickness T 3 of the dielectric substrate 24 is sufficiently increased, the electrostatic capacity is dominated by the portion of the high-frequency fixed electrode 18.

本発明の第1の実施の形態に係る半導体装置においては、誘電体基板24を真性半導体基板,不純物密度の低い高抵抗半導体基板あるいは半絶縁性半導体基板のいずれかに置き換えることもできる。一例としては、誘電体基板24を真性あるいは十分不純物密度が低い半絶縁性GaAs基板に置き換えることもできる。   In the semiconductor device according to the first embodiment of the present invention, the dielectric substrate 24 can be replaced with either an intrinsic semiconductor substrate, a high-resistance semiconductor substrate with a low impurity density, or a semi-insulating semiconductor substrate. As an example, the dielectric substrate 24 can be replaced with a semi-insulating GaAs substrate with intrinsic or sufficiently low impurity density.

本発明の第1の実施の形態に係る半導体装置によれば、高周波可動電極と静電MEMS駆動用可動電極を一体化した金属の可動電極という単純な製造し易い構造で、低電圧で駆動でき、かつ高周波信号でセルフアクチュエーションやセルフホールディングしない静電MEMSを提供することができる。   The semiconductor device according to the first embodiment of the present invention can be driven at a low voltage with a simple and easily manufactured structure of a metal movable electrode in which a high-frequency movable electrode and an electrostatic MEMS driving movable electrode are integrated. In addition, it is possible to provide an electrostatic MEMS that does not self-actuate or self-hold with a high-frequency signal.

[第2の実施の形態]
本発明の第2の実施の形態に係る半導体装置においては、図10乃至図18に示すように、図1乃至図9の構成において、アンカー14あるいは駆動用固定電極16あるいは高周波固定電極18の少なくとも一つを複数に構成することを特徴とする静電MEMSを構成している。
[Second Embodiment]
In the semiconductor device according to the second embodiment of the present invention, as shown in FIGS. 10 to 18, in the configuration of FIGS. 1 to 9, at least the anchor 14, the driving fixed electrode 16, or the high frequency fixed electrode 18 is used. An electrostatic MEMS is characterized in that one is formed into a plurality.

図10は、本発明の第2の実施の形態に係る半導体装置の模式的平面パターン構成図であり、アンカー14と駆動用固定電極16を各2個にした構成を示す。また、図11は、図10のI―I線に沿う模式的断面構造図、図12は、図10のII―II線に沿う模式的断面構造図、図13は、図10のIII―III線に沿う模式的断面構造図、図14は、図10のIV―IV線に沿う模式的断面構造図をそれぞれ示している。   FIG. 10 is a schematic plane pattern configuration diagram of a semiconductor device according to the second embodiment of the present invention, and shows a configuration in which two anchors 14 and two driving fixed electrodes 16 are provided. 11 is a schematic cross-sectional structure diagram taken along line II of FIG. 10, FIG. 12 is a schematic cross-sectional structure diagram taken along line II-II of FIG. 10, and FIG. 13 is III-III of FIG. 14 is a schematic cross-sectional structure diagram taken along the line, and FIG. 14 is a schematic cross-sectional structure diagram taken along the line IV-IV in FIG.

図15は、図11において、駆動電圧印加時における図10のI―I線に沿う模式的断面構造図を示す。また、図16は、図12において、駆動電圧印加時における図10のII―II線に沿う模式的断面構造図、図17は、図13において、駆動電圧印加時における図10のIII―III線に沿う模式的断面構造図、図18は、図14において、駆動電圧印加時における図10のIV―IV線に沿う模式的断面構造図をそれぞれ示している。
本発明の第2の実施の形態に係る半導体装置によれば、高周波可動電極と静電MEMS駆動用可動電極を一体化した金属の可動電極という単純な製造し易い構造で、低電圧で駆動でき、かつ高周波信号でセルフアクチュエーションやセルフホールディングしない静電MEMSを提供することができる。
FIG. 15 is a schematic sectional view taken along the line II of FIG. 10 when a drive voltage is applied in FIG. 16 is a schematic sectional view taken along the line II-II in FIG. 10 when the drive voltage is applied in FIG. 12, and FIG. 17 is a line III-III in FIG. 10 when the drive voltage is applied in FIG. FIG. 18 is a schematic cross-sectional structure diagram taken along the line IV-IV in FIG. 10 when a drive voltage is applied.
According to the semiconductor device of the second embodiment of the present invention, it can be driven at a low voltage with a simple and easy-to-manufacture structure of a metal movable electrode in which a high-frequency movable electrode and an electrostatic MEMS driving movable electrode are integrated. In addition, it is possible to provide an electrostatic MEMS that does not self-actuate or self-hold with a high-frequency signal.

本発明の第2の実施の形態に係る半導体装置においては、アンカー14−駆動用固定電極16−高周波固定電極18−駆動用固定電極16−アンカー14が直線状に配置されているので、可動電極10のばねの力を強くでき、高周波信号によるセルフアクチュエーションやセルフホールディングを起こさない静電MEMSを提供することができる。   In the semiconductor device according to the second embodiment of the present invention, the anchor 14 -the fixed electrode for driving 16 -the high frequency fixed electrode 18 -the fixed electrode for driving 16 -the anchor 14 are arranged in a straight line. Thus, it is possible to provide an electrostatic MEMS that can increase the force of 10 springs and does not cause self-actuation or self-holding by a high-frequency signal.

また、左右対称になっているので、左右バランス良く可動電極10を引き寄せることができる静電MEMSを提供することができる。   Moreover, since it is left-right symmetric, the electrostatic MEMS which can draw the movable electrode 10 with sufficient left-right balance can be provided.

[第3の実施の形態]
本発明の第3の実施の形態に係る半導体装置においては、図19乃至図27に示すように、図10乃至図18の構成において、駆動用固定電極16が高周波固定電極18を囲むことを特徴とする静電MEMSを構成している。
[Third Embodiment]
In the semiconductor device according to the third embodiment of the present invention, as shown in FIGS. 19 to 27, the driving fixed electrode 16 surrounds the high-frequency fixed electrode 18 in the configurations of FIGS. 10 to 18. This constitutes an electrostatic MEMS.

図19は、本発明の第3の実施の形態に係る半導体装置の模式的平面パターン構成図であり、駆動用固定電極16が高周波固定電極18を囲む構成を示す。図20は、図19のI―I線に沿う模式的断面構造図、図21は、図19のII―II線に沿う模式的断面構造図、図22は、図19のIII―III線に沿う模式的断面構造図、図23は、図19のIV―IV線に沿う模式的断面構造図をそれぞれ示している。   FIG. 19 is a schematic plane pattern configuration diagram of a semiconductor device according to the third embodiment of the present invention, and shows a configuration in which the driving fixed electrode 16 surrounds the high-frequency fixed electrode 18. 20 is a schematic cross-sectional structure diagram taken along line II in FIG. 19, FIG. 21 is a schematic cross-sectional structure diagram along line II-II in FIG. 19, and FIG. 22 is taken along line III-III in FIG. FIG. 23 is a schematic cross-sectional structure diagram taken along the line IV-IV in FIG. 19, respectively.

図24は、図20において、駆動電圧印加時における図19のI―I線に沿う模式的断面構造図を示す。また、図25は、図21において、駆動電圧印加時における図19のII―II線に沿う模式的断面構造図、図26は、図22において、駆動電圧印加時における図19のIII―III線に沿う模式的断面構造図、図27は、図23において、駆動電圧印加時における図19のIV―IV線に沿う模式的断面構造図をそれぞれ示している。   FIG. 24 is a schematic sectional view taken along the line II of FIG. 19 when the drive voltage is applied in FIG. 25 is a schematic sectional view taken along the line II-II in FIG. 19 when the drive voltage is applied in FIG. 21, and FIG. 26 is a line III-III in FIG. 19 when the drive voltage is applied in FIG. 27 is a schematic cross-sectional structure diagram taken along line IV-IV in FIG. 19 when a drive voltage is applied.

本発明の第3の実施の形態に係る半導体装置によれば、高周波可動電極と静電MEMS駆動用可動電極を一体化した金属の可動電極という単純な製造し易い構造で、低電圧で駆動でき、かつ高周波信号でセルフアクチュエーションやセルフホールディングしない静電MEMSを提供することができる。   According to the semiconductor device of the third embodiment of the present invention, it can be driven at a low voltage with a simple structure of a metal movable electrode in which a high-frequency movable electrode and an electrostatic MEMS driving movable electrode are integrated. In addition, it is possible to provide an electrostatic MEMS that does not self-actuate or self-hold with a high-frequency signal.

本発明の第3の実施の形態に係る半導体装置においては、高周波固定電極18を囲む駆動用固定電極16で可動電極10を引き寄せることによって、高周波固定電極18とそれに対向する可動電極10には駆動電圧VDRを印加しなくても、高周波固定電極18を囲む可動電極10が均一に高周波固定電極18の部分を押し付けることができる静電MEMSを提供することができる。 In the semiconductor device according to the third embodiment of the present invention, the movable electrode 10 is attracted by the driving fixed electrode 16 surrounding the high-frequency fixed electrode 18, so that the high-frequency fixed electrode 18 and the movable electrode 10 opposed thereto are driven. without applying a voltage V DR, it is possible to provide an electrostatic MEMS movable electrode 10 surrounding the high frequency fixed electrode 18 can be uniformly pressed against the portion of the high-frequency fixed electrode 18.

[第4の実施の形態]
本発明の第4の実施の形態に係る半導体装置においては、図28乃至図40に示すように、図19乃至図27の構成において、可動電極10の駆動用固定電極16に対向する領域の一部にスリット26を入れ、アンカー14側を先端とし、高周波固定電極18側を付け根とする、舌状可動部28を少なくとも一つ備えることを特徴とする静電MEMSを構成している。
[Fourth Embodiment]
In the semiconductor device according to the fourth embodiment of the present invention, as shown in FIGS. 28 to 40, in the configuration shown in FIGS. 19 to 27, one of the regions of the movable electrode 10 facing the fixed electrode 16 for driving. The electrostatic MEMS is characterized by including at least one tongue-like movable portion 28 having a slit 26 in the portion, an anchor 14 side as a tip, and a high-frequency fixed electrode 18 side as a root.

図28は、本発明の第4の実施の形態に係る半導体装置の模式的平面パターン構成図であり、可動電極10の駆動用固定電極16に対向する領域の一部にスリット26を入れ、アンカー14側を先端とし、高周波固定電極18側を付け根とする、舌状可動部28を少なくとも一つ備える構成を示す。また、図29は、図28のI―I線に沿う模式的断面構造図、図30は、図28のII―II線に沿う模式的断面構造図、図31は、図28のIII―III線に沿う模式的断面構造図、図32は、図28のIV―IV線に沿う模式的断面構造図をそれぞれ示す。   FIG. 28 is a schematic plan pattern configuration diagram of a semiconductor device according to the fourth embodiment of the present invention. A slit 26 is formed in a part of a region of the movable electrode 10 facing the driving fixed electrode 16 to fix the anchor. A configuration is shown in which at least one tongue-like movable portion 28 is provided, with the 14 side as a tip and the high frequency fixed electrode 18 side as a root. 29 is a schematic cross-sectional structure diagram taken along line II of FIG. 28, FIG. 30 is a schematic cross-sectional structure diagram taken along line II-II of FIG. 28, and FIG. 31 is III-III of FIG. FIG. 32 is a schematic cross-sectional structure diagram taken along the line IV-IV in FIG. 28, respectively.

また、図33は、図29において、駆動過渡期における図28のI―I線に沿う模式的断面構造図、図34は、図30において、駆動過渡期における図28のII―II線に沿う模式的断面構造図、図35は、図31において、駆動過渡期における図28のIII―III線に沿う模式的断面構造図、図36は、図32において、駆動過渡期における図28のIV―IV線に沿う模式的断面構造図をそれぞれ示している。   FIG. 33 is a schematic cross-sectional structure diagram taken along line II in FIG. 28 in FIG. 29 in FIG. 29, and FIG. 34 is in FIG. 30 along line II-II in FIG. 35 is a schematic cross-sectional structure diagram, FIG. 35 is a schematic cross-sectional structure diagram taken along the line III-III in FIG. 28 in FIG. 31, and FIG. 36 is a schematic cross-sectional structure diagram in FIG. A schematic cross-sectional structure diagram along line IV is shown.

また、図37は、図29において、駆動電圧印加時における図28のI―I線に沿う模式的断面構造図、図38は、図30において、駆動電圧印加時における図28のII―II線に沿う模式的断面構造図、図39は、図31において、駆動電圧印加時における図28のIII―III線に沿う模式的断面構造図、図40は、図32において、駆動電圧印加時における図28のIV―IV線に沿う模式的断面構造図をそれぞれ示す。   37 is a schematic sectional view taken along the line II of FIG. 28 when the drive voltage is applied in FIG. 29, and FIG. 38 is a line II-II of FIG. 28 when the drive voltage is applied in FIG. 39 is a schematic cross-sectional structure diagram taken along line III-III in FIG. 28 when a drive voltage is applied in FIG. 31, and FIG. 40 is a diagram when a drive voltage is applied in FIG. 28 is a schematic cross-sectional structure diagram along line IV-IV.

本発明の第4の実施の形態に係る半導体装置においては、図28乃至図30に示すように、アンカー14に固定される可動電極10を4箇所にしてばねのバランスを良くしている。   In the semiconductor device according to the fourth embodiment of the present invention, as shown in FIGS. 28 to 30, the movable electrode 10 fixed to the anchor 14 is provided at four places to improve the balance of the spring.

本発明の第4の実施の形態に係る半導体装置においては、舌状可動部28の先端のばねの力は弱いので、低い駆動電圧で図33乃至図36に示す様に先ず舌状可動部28の先端側を引き寄せることができる。空隙T1が小さくなると静電引力は大きくなるので、2個のアンカー14で支えられたばねの力の強い可動電極10の部分に繋がる舌状可動部28の付け根まで引き寄せることができ、図37乃至図40に示すようになる。 In the semiconductor device according to the fourth embodiment of the present invention, since the force of the spring at the tip of the tongue-shaped movable portion 28 is weak, the tongue-shaped movable portion 28 is first driven at a low driving voltage as shown in FIGS. The tip side of can be pulled. Since the electrostatic attractive force increases as the gap T 1 decreases, it can be pulled to the root of the tongue-like movable portion 28 connected to the portion of the movable electrode 10 having a strong spring force supported by the two anchors 14. As shown in FIG.

一方、前記のようにT3を十分大きくすれば駆動用固定電極16に対向する舌状可動部28に加わる高周波信号の静電引力は十分小さいので、舌状可動部28ではセルフアクチュエーションやセルフホールディングを起こさない。 On the other hand, if T 3 is sufficiently large as described above, the electrostatic attractive force of the high-frequency signal applied to the tongue-shaped movable part 28 facing the driving fixed electrode 16 is sufficiently small. Does not cause holding.

本発明の第4の実施の形態に係る半導体装置によれば、高周波可動電極と静電MEMS駆動用可動電極を一体化した金属の可動電極という単純な製造し易い構造で、低電圧で駆動でき、かつ高周波信号でセルフアクチュエーションやセルフホールディングしない静電MEMSを提供することができる。   According to the semiconductor device of the fourth embodiment of the present invention, it can be driven at a low voltage with a simple structure of a metal movable electrode in which a high-frequency movable electrode and an electrostatic MEMS driving movable electrode are integrated. In addition, it is possible to provide an electrostatic MEMS that does not self-actuate or self-hold with a high-frequency signal.

[第5の実施の形態]
本発明の第5の実施の形態に係る半導体装置においては、図41乃至図53に示すように、図19乃至図27の構成において、可動電極10の駆動用固定電極16に対向する領域の一部にスリット26を入れ、アンカー14側を付け根とし、高周波固定電極18側を先端とする、舌状可動部28を少なくとも一つ備えることを特徴とする静電MEMSを構成している。
[Fifth Embodiment]
In the semiconductor device according to the fifth embodiment of the present invention, as shown in FIGS. 41 to 53, in the configuration shown in FIGS. 19 to 27, one region in the movable electrode 10 facing the fixed electrode 16 for driving. The electrostatic MEMS is characterized by including at least one tongue-like movable portion 28 having a slit 26 in the portion, the anchor 14 side as a root, and the high-frequency fixed electrode 18 side as a tip.

本発明の第5の実施の形態に係る半導体装置は、第4の実施の形態に係る半導体装置において、図28乃至図40の舌状可動部28の向きを逆にした構成を有する。   The semiconductor device according to the fifth embodiment of the present invention has a configuration in which the direction of the tongue-like movable portion 28 in FIGS. 28 to 40 is reversed in the semiconductor device according to the fourth embodiment.

図41は、本発明の第5の実施の形態に係る半導体装置の模式的平面パターン構成図を示す。また、図42は、図41のI―I線に沿う模式的断面構造図、図43は、図41のII―II線に沿う模式的断面構造図、図44は、図41のIII―III線に沿う模式的断面構造図、図45は、図41のIV―IV線に沿う模式的断面構造図をそれぞれ示している。   FIG. 41 is a schematic plane pattern configuration diagram of a semiconductor device according to the fifth embodiment of the present invention. 42 is a schematic sectional view taken along line II in FIG. 41, FIG. 43 is a schematic sectional view taken along line II-II in FIG. 41, and FIG. 44 is taken along line III-III in FIG. FIG. 45 shows a schematic cross-sectional structure diagram taken along the line IV-IV in FIG. 41, respectively.

また、図46は、図42において、駆動過渡期における図41のI―I線に沿う模式的断面構造図、図47は、図43において、駆動過渡期における図41のII―II線に沿う模式的断面構造図、図48は、図44において、駆動過渡期における図41のIII―III線に沿う模式的断面構造図、図49は、図45において、駆動過渡期における図41のIV―IV線に沿う模式的断面構造図をそれぞれ示している。   46 is a schematic sectional view taken along line II of FIG. 41 in the drive transition period in FIG. 42, and FIG. 47 is taken along line II-II of FIG. 41 in the drive transition period in FIG. 48 is a schematic cross-sectional structure diagram, FIG. 48 is a schematic cross-sectional structure diagram along the line III-III of FIG. 41 in FIG. 44 in FIG. 44, and FIG. A schematic cross-sectional structure diagram along line IV is shown.

また、図50は、図42において、駆動電圧印加時における図41のI―I線に沿う模式的断面構造図、図51は、図43において、駆動電圧印加時における図41のII―II線に沿う模式的断面構造図、図52は、図44において、駆動電圧印加時における図41のIII―III線に沿う模式的断面構造図、図53は、図45において、駆動電圧印加時における図41のIV―IV線に沿う模式的断面構造図をそれぞれ示している。   50 is a schematic cross-sectional structure diagram taken along line II in FIG. 41 when a drive voltage is applied in FIG. 42, and FIG. 51 is a line II-II in FIG. 41 when drive voltage is applied in FIG. 52 is a schematic cross-sectional structure diagram taken along line III-III in FIG. 41 when the drive voltage is applied in FIG. 44, and FIG. 53 is a diagram when the drive voltage is applied in FIG. 41 is a schematic cross-sectional structure diagram taken along line IV-IV in FIG.

本発明の第5の実施の形態に係る半導体装置においては、図41乃至図43に示すように、アンカー14に固定される可動電極10を2箇所にしてばねのバランスを良くしている。   In the semiconductor device according to the fifth embodiment of the present invention, as shown in FIGS. 41 to 43, the movable electrode 10 fixed to the anchor 14 is provided at two places to improve the balance of the spring.

本発明の第5の実施の形態に係る半導体装置においては、舌状可動部28の先端のばねの力は弱いので、低い駆動電圧で図46乃至図49に示す様に先ず舌状可動部28の先端側を引き寄せることができる。空隙T1が小さくなると静電引力は大きくなるので、2個のアンカー14で支えられたばねの力の強い可動電極10の部分に繋がる舌状可動部28の付け根まで引き寄せることができ、図50乃至図53に示すようになる。 In the semiconductor device according to the fifth embodiment of the present invention, since the force of the spring at the tip of the tongue-like movable portion 28 is weak, the tongue-like movable portion 28 is first driven at a low drive voltage as shown in FIGS. The tip side of can be pulled. When the gap T 1 is reduced, the electrostatic attractive force is increased, so that it can be drawn to the root of the tongue-like movable portion 28 connected to the portion of the movable electrode 10 having a strong spring force supported by the two anchors 14. As shown in FIG.

一方、前記のようにT3を十分大きくすれば駆動用固定電極16に対向する舌状可動部28に加わる高周波信号の静電引力は十分小さいので、舌状可動部28ではセルフアクチュエーションやセルフホールディングを起こさない。 On the other hand, if T 3 is sufficiently large as described above, the electrostatic attractive force of the high-frequency signal applied to the tongue-shaped movable part 28 facing the driving fixed electrode 16 is sufficiently small. Does not cause holding.

本発明の第5の実施の形態に係る半導体装置によれば、高周波可動電極と静電MEMS駆動用可動電極を一体化した金属の可動電極という単純な製造し易い構造で、低電圧で駆動でき、かつ高周波信号でセルフアクチュエーションやセルフホールディングしない静電MEMSを提供することができる。   According to the semiconductor device of the fifth embodiment of the present invention, it can be driven at a low voltage with a simple structure of a metal movable electrode in which a high-frequency movable electrode and an electrostatic MEMS driving movable electrode are integrated. In addition, it is possible to provide an electrostatic MEMS that does not self-actuate or self-hold with a high-frequency signal.

[第6の実施の形態]
本発明の第6の実施の形態に係る半導体装置は、図54乃至図66に示すように、図41乃至図53の構成において、舌状可動部28は、幅が変わる領域を備えることを特徴とする静電MEMSを構成している。
[Sixth Embodiment]
As shown in FIGS. 54 to 66, the semiconductor device according to the sixth embodiment of the present invention is characterized in that, in the configuration of FIGS. 41 to 53, the tongue-like movable portion 28 includes a region whose width changes. This constitutes an electrostatic MEMS.

図54は、本発明の第6の実施の形態に係る半導体装置の模式的平面パターン構成図を示す。また、図55は、図54のI―I線に沿う模式的断面構造図、図56は、図54のII―II線に沿う模式的断面構造図、図57は、図54のIII―III線に沿う模式的断面構造図、図58は、図54のIV―IV線に沿う模式的断面構造図をそれぞれ示す。   FIG. 54 is a schematic plane pattern configuration diagram of the semiconductor device according to the sixth embodiment of the present invention. 55 is a schematic sectional view taken along the line II of FIG. 54, FIG. 56 is a schematic sectional view taken along the line II-II of FIG. 54, and FIG. 57 is taken along the line III-III of FIG. FIG. 58 is a schematic cross-sectional structure diagram taken along line IV-IV in FIG. 54.

また、図59は、図55において、駆動過渡期における図54のI―I線に沿う模式的断面構造図、図60は、図56において、駆動過渡期における図54のII―II線に沿う模式的断面構造図、図61は、図57において、駆動過渡期における図54のIII―III線に沿う模式的断面構造図、図62は、図58において、駆動過渡期における図54のIV―IV線に沿う模式的断面構造図をそれぞれ示す。   59 is a schematic cross-sectional structure diagram taken along the line II of FIG. 54 during the drive transition period in FIG. 55, and FIG. 60 is taken along the line II-II of FIG. 54 during the drive transition period in FIG. 61 is a schematic cross-sectional structure diagram, FIG. 61 is a schematic cross-sectional structure diagram taken along the line III-III in FIG. 54 in FIG. 57 in FIG. 57, and FIG. 62 is a schematic cross-sectional structure diagram in FIG. A schematic sectional view along line IV is shown.

また、図63は、図55において、駆動電圧印加時における図54のI―I線に沿う模式的断面構造図、図64は、図56において、駆動電圧印加時における図54のII―II線に沿う模式的断面構造図、図65は、図57において、駆動電圧印加時における図54のIII―III線に沿う模式的断面構造図、図66は、図58において、駆動電圧印加時における図54のIV―IV線に沿う模式的断面構造図をそれぞれ示す。   FIG. 63 is a schematic sectional view taken along the line II of FIG. 54 when the drive voltage is applied in FIG. 55, and FIG. 64 is a line II-II of FIG. 54 when the drive voltage is applied in FIG. 65 is a schematic cross-sectional structure diagram taken along line III-III in FIG. 54 when a drive voltage is applied in FIG. 57, and FIG. 66 is a diagram when a drive voltage is applied in FIG. 54 is a schematic cross-sectional structure diagram along line IV-IV.

本発明の第6の実施の形態に係る半導体装置においては、舌状可動部28の幅を途中で狭くすることにより、先端に対するばねの力はさらに弱くなり、さらに低い駆動電圧で先端を引き寄せることができる。   In the semiconductor device according to the sixth embodiment of the present invention, by reducing the width of the tongue-like movable portion 28 in the middle, the force of the spring against the tip is further weakened, and the tip is attracted with a lower driving voltage. Can do.

本発明の第6の実施の形態に係る半導体装置によれば、高周波可動電極と静電MEMS駆動用可動電極を一体化した金属の可動電極という単純な製造し易い構造で、低電圧で駆動でき、かつ高周波信号でセルフアクチュエーションやセルフホールディングしない静電MEMSを提供することができる。   According to the semiconductor device of the sixth embodiment of the present invention, it can be driven at a low voltage with a simple structure of a metal movable electrode in which a high-frequency movable electrode and an electrostatic MEMS driving movable electrode are integrated. In addition, it is possible to provide an electrostatic MEMS that does not self-actuate or self-hold with a high-frequency signal.

[第7の実施の形態]
本発明の第7の実施の形態に係る半導体装置においては、図67乃至図79に示すように、図54乃至図66の構成において、舌状可動部28の先端側の少なくとも一部を誘電体基板24の方向に凸部とすることを特徴とする静電MEMSを構成している。
[Seventh Embodiment]
In the semiconductor device according to the seventh embodiment of the present invention, as shown in FIGS. 67 to 79, in the configuration of FIGS. 54 to 66, at least a part of the distal end side of the tongue-like movable portion 28 is a dielectric. The electrostatic MEMS is characterized in that a convex portion is formed in the direction of the substrate 24.

図67は、本発明の第7の実施の形態に係る半導体装置の模式的平面パターン構成図を示す。また、図68は、図67のI―I線に沿う模式的断面構造図、図69は、図67のII―II線に沿う模式的断面構造図、図70は、図67のIII―III線に沿う模式的断面構造図、図71は、図67のIV―IV線に沿う模式的断面構造図をそれぞれ示す。   FIG. 67 is a schematic plane pattern configuration diagram of a semiconductor device according to the seventh embodiment of the present invention. 68 is a schematic sectional view taken along the line II of FIG. 67, FIG. 69 is a schematic sectional view taken along the line II-II of FIG. 67, and FIG. 70 is taken along the line III-III of FIG. 71 is a schematic cross-sectional structure diagram taken along the line, and FIG. 71 is a schematic cross-sectional structure diagram taken along the line IV-IV in FIG.

また、図72は、図68において、駆動過渡期における図67のI―I線に沿う模式的断面構造図、図73は、図69において、駆動過渡期における図67のII―II線に沿う模式的断面構造図、図74は、図70において、駆動過渡期における図67のIII―III線に沿う模式的断面構造図、図75は、図71において、駆動過渡期における図67のIV―IV線に沿う模式的断面構造図をそれぞれ示す。   72 is a schematic sectional view taken along the line II of FIG. 67 in the drive transition period in FIG. 68, and FIG. 73 is taken along the line II-II of FIG. 67 in the drive transition period in FIG. 74 is a schematic cross-sectional structure diagram, FIG. 74 is a schematic cross-sectional structure diagram taken along the line III-III in FIG. 67 in the drive transition period in FIG. 70, and FIG. A schematic sectional view along line IV is shown.

また、図76は、図68において、駆動電圧印加時における図67のI―I線に沿う模式的断面構造図、図77は、図69において、駆動電圧印加時における図67のII―II線に沿う模式的断面構造図、図78は、図70において、駆動電圧印加時における図67のIII―III線に沿う模式的断面構造図、図79は、図71において、駆動電圧印加時における図67のIV―IV線に沿う模式的断面構造図をそれぞれ示す。   FIG. 76 is a schematic sectional view taken along the line II of FIG. 67 when the drive voltage is applied in FIG. 68, and FIG. 77 is the line II-II of FIG. 67 when the drive voltage is applied in FIG. 78 is a schematic cross-sectional structure diagram taken along the line III-III in FIG. 67 when the drive voltage is applied in FIG. 70, and FIG. 79 is a diagram when the drive voltage is applied in FIG. 67 is a schematic cross-sectional structure diagram taken along line IV-IV in FIG.

本発明の第7の実施の形態に係る半導体装置においては、図68に示すように、舌状可動部28の先端の面積S4の空隙がT1より狭いT4になっているので、図54乃至図66の構成に比べて、静電引力が(T1+T2A)2/(T4+T2A)2倍になり、さらに低い駆動電圧VDRで図72乃至図75に示す様に、舌状可動部28の先端側を引き寄せることができる。 In the semiconductor device according to the seventh embodiment of the present invention, as shown in FIG. 68, the gap of the area S 4 at the tip of the tongue-like movable portion 28 is T 4 narrower than T 1 . Compared with the configuration of FIGS. 54 to 66, the electrostatic attractive force is (T 1 + T 2 / ε A ) 2 / (T 4 + T 2 / ε A ) 2 times, and at a lower drive voltage V DR , FIG. Thru | or FIG. 75, the front end side of the tongue-like movable part 28 can be pulled near.

空隙T1が小さくなると静電引力は大きくなるので、2個のアンカー14で支えられたばねの力の強い可動電極10に繋がる舌状可動部28の付け根まで引き寄せることができ、図76乃至図79に示す様に、可動電極10の全体を引き寄せることができる。 Since the electrostatic attraction force increases as the gap T 1 decreases, it can be drawn to the root of the tongue-like movable portion 28 connected to the strong movable electrode 10 supported by the two anchors 14, as shown in FIGS. 76 to 79. As shown in FIG. 3, the entire movable electrode 10 can be drawn.

本発明の第7の実施の形態に係る半導体装置によれば、高周波可動電極と静電MEMS駆動用可動電極を一体化した金属の可動電極という単純な製造し易い構造で、低電圧で駆動でき、かつ高周波信号でセルフアクチュエーションやセルフホールディングしない静電MEMSを提供することができる。   According to the semiconductor device of the seventh embodiment of the present invention, it can be driven at a low voltage with a simple structure of a metal movable electrode in which a high-frequency movable electrode and an electrostatic MEMS driving movable electrode are integrated. In addition, it is possible to provide an electrostatic MEMS that does not self-actuate or self-hold with a high-frequency signal.

[第8の実施の形態]
本発明の第8の実施の形態に係る半導体装置においては、図80乃至図92に示すように、図67乃至図79の構成において、凸部30は、段差が小さい階段形状を備えることを特徴とする静電MEMSを構成している。
[Eighth Embodiment]
In the semiconductor device according to the eighth embodiment of the present invention, as shown in FIGS. 80 to 92, in the configuration of FIGS. 67 to 79, the protrusion 30 has a stepped shape with a small step. This constitutes an electrostatic MEMS.

図80は、本発明の第8の実施の形態に係る半導体装置の模式的平面パターン構成図を示す。また、図81は、図80のI―I線に沿う模式的断面構造図、図82は、図80のII―II線に沿う模式的断面構造図、図83は、図80のIII―III線に沿う模式的断面構造図、図84は、図80のIV―IV線に沿う模式的断面構造図をそれぞれ示す。   FIG. 80 is a schematic plane pattern configuration diagram of the semiconductor device according to the eighth embodiment of the present invention. 81 is a schematic cross-sectional structure diagram taken along the line II in FIG. 80, FIG. 82 is a schematic cross-sectional structure diagram taken along the line II-II in FIG. 80, and FIG. 84 is a schematic cross-sectional structure diagram taken along the line, and FIG. 84 is a schematic cross-sectional structure diagram taken along the line IV-IV in FIG.

また、図85は、図81において、駆動過渡期における図80のI―I線に沿う模式的断面構造図、図86は、図82において、駆動過渡期における図80のII―II線に沿う模式的断面構造図、図87は、図83において、駆動過渡期における図80のIII―III線に沿う模式的断面構造図、図88は、図84において、駆動過渡期における図80のIV―IV線に沿う模式的断面構造図をそれぞれ示す。   85 is a schematic sectional view taken along the line II of FIG. 80 in the drive transition period in FIG. 81, and FIG. 86 is taken along the line II-II of FIG. 80 in the drive transition period in FIG. 87 is a schematic cross-sectional structure diagram, FIG. 87 is a schematic cross-sectional structure diagram along the line III-III in FIG. 80 in FIG. 83 in FIG. 83, and FIG. 88 is a schematic cross-sectional structure diagram in FIG. A schematic sectional view along line IV is shown.

また、図89は、図81において、駆動電圧印加時における図80のI―I線に沿う模式的断面構造図、図90は、図82において、駆動電圧印加時における図80のII―II線に沿う模式的断面構造図、図91は、図83において、駆動電圧印加時における図80のIII―III線に沿う模式的断面構造図、図92は、図84において、駆動電圧印加時における図80のIV―IV線に沿う模式的断面構造図をそれぞれ示す。   89 is a schematic cross-sectional structure diagram taken along line II in FIG. 80 when the drive voltage is applied in FIG. 81, and FIG. 90 is a line II-II in FIG. 80 when the drive voltage is applied in FIG. 91 is a schematic cross-sectional structure diagram taken along line III-III in FIG. 80 when a drive voltage is applied in FIG. 83, and FIG. 92 is a diagram when a drive voltage is applied in FIG. A schematic cross-sectional structure diagram along line IV-IV of 80 is shown.

本発明の第8の実施の形態に係る半導体装置においては、凸部30が段差が小さい階段状なので舌状可動部28の変形がなだらかになる。この一例では一段としたが、多段にすることにより効果が高くなる。   In the semiconductor device according to the eighth embodiment of the present invention, since the convex portion 30 has a stepped shape with small steps, the tongue-like movable portion 28 is gently deformed. In this example, the number of stages is one, but the effect is enhanced by using multiple stages.

本発明の第8の実施の形態に係る半導体装置によれば、高周波可動電極と静電MEMS駆動用可動電極を一体化した金属の可動電極という単純な製造し易い構造で、低電圧で駆動でき、かつ高周波信号でセルフアクチュエーションやセルフホールディングしない静電MEMSを提供することができる。   According to the semiconductor device of the eighth embodiment of the present invention, it can be driven at a low voltage with a simple and easy-to-manufacture structure of a metal movable electrode in which a high-frequency movable electrode and an electrostatic MEMS driving movable electrode are integrated. In addition, it is possible to provide an electrostatic MEMS that does not self-actuate or self-hold with a high-frequency signal.

[第9の実施の形態]
本発明の第9の実施の形態に係る半導体装置においては、図93乃至図105に示すように、図67乃至図79の構成において、凸部30は、なだらかな傾斜面を備えることを特徴とする静電MEMSを構成している。
[Ninth Embodiment]
In the semiconductor device according to the ninth embodiment of the present invention, as shown in FIGS. 93 to 105, in the configuration of FIGS. 67 to 79, the convex portion 30 has a gentle inclined surface. The electrostatic MEMS is configured.

図93は、本発明の第9の実施の形態に係る半導体装置の模式的平面パターン構成図を示す。また、図94は、図93のI―I線に沿う模式的断面構造図、図95は、図93のII―II線に沿う模式的断面構造図、図96は、図93のIII―III線に沿う模式的断面構造図、図97は、図93のIV―IV線に沿う模式的断面構造図をそれぞれ示す。   FIG. 93 is a schematic plane pattern configuration diagram of the semiconductor device according to the ninth embodiment of the present invention. 94 is a schematic cross-sectional structure diagram taken along the line II of FIG. 93, FIG. 95 is a schematic cross-sectional structure diagram taken along the line II-II of FIG. 93, and FIG. FIG. 97 is a schematic cross-sectional structure diagram taken along the line IV-IV in FIG. 93, respectively.

また、図98は、図94において、駆動過渡期における図93のI―I線に沿う模式的断面構造図、図99は、図95において、駆動過渡期における図93のII―II線に沿う模式的断面構造図、図100は、図96において、駆動過渡期における図93のIII―III線に沿う模式的断面構造図、図101は、図97において、駆動過渡期における図93のIV―IV線に沿う模式的断面構造図をそれぞれ示す。   FIG. 98 is a schematic sectional view taken along line II of FIG. 93 in the drive transition period in FIG. 94, and FIG. 99 is taken along line II-II in FIG. 93 in the drive transition period in FIG. 100 is a schematic cross-sectional structure diagram, FIG. 100 is a schematic cross-sectional structure diagram along the line III-III of FIG. 93 in FIG. 96 in FIG. 96, and FIG. A schematic sectional view along line IV is shown.

また、図102は、図94において、駆動電圧印加時における図93のI―I線に沿う模式的断面構造図、図103は、図95において、駆動電圧印加時における図93のII―II線に沿う模式的断面構造図、図104は、図96において、駆動電圧印加時における図93のIII―III線に沿う模式的断面構造図、図105は、図97において、駆動電圧印加時における図93のIV―IV線に沿う模式的断面構造図をそれぞれ示す。   FIG. 102 is a schematic sectional view taken along the line II of FIG. 93 when the drive voltage is applied in FIG. 94, and FIG. 103 is the line II-II of FIG. 93 when the drive voltage is applied in FIG. 104 is a schematic cross-sectional structure diagram taken along the line III-III in FIG. 93 when the drive voltage is applied in FIG. 96, and FIG. 105 is a diagram when the drive voltage is applied in FIG. 93 is a schematic cross-sectional structure diagram taken along line IV-IV in FIG.

本発明の第9の実施の形態に係る半導体装置においては、凸部30がなだらかな傾斜面なので舌状可動部28の変形は塑性変形から遠ざかり金属疲労を起こしにくい。   In the semiconductor device according to the ninth embodiment of the present invention, since the convex portion 30 is a gentle inclined surface, the deformation of the tongue-shaped movable portion 28 is far from plastic deformation and hardly causes metal fatigue.

また、この一例ではアンカー14に固定される可動電極10を6箇所にし、幅も変えてばねのバランスを良くしている。   In this example, the movable electrode 10 fixed to the anchor 14 is provided at six locations, and the width is changed to improve the balance of the spring.

本発明の第9の実施の形態に係る半導体装置によれば、高周波可動電極と静電MEMS駆動用可動電極を一体化した金属の可動電極という単純な製造し易い構造で、低電圧で駆動でき、かつ高周波信号でセルフアクチュエーションやセルフホールディングしない静電MEMSを提供することができる。   According to the semiconductor device of the ninth embodiment of the present invention, it can be driven at a low voltage with a simple structure of a metal movable electrode in which a high-frequency movable electrode and an electrostatic MEMS driving movable electrode are integrated. In addition, it is possible to provide an electrostatic MEMS that does not self-actuate or self-hold with a high-frequency signal.

[第10の実施の形態]
本発明の第10の実施の形態に係る半導体装置においては、図106乃至図110に示すように、図19乃至図27の構成において、下部電極22を導電性基板36に、誘電体基板24を誘電体層240に置き換えたことを特徴とする静電MEMSを構成している。
[Tenth embodiment]
In the semiconductor device according to the tenth embodiment of the present invention, as shown in FIGS. 106 to 110, the lower electrode 22 is used as the conductive substrate 36 and the dielectric substrate 24 is used as shown in FIGS. The electrostatic MEMS is characterized in that it is replaced with the dielectric layer 240.

図106は、本発明の第10の実施の形態に係る半導体装置の模式的平面パターン構成図を示す。また、図107は、図106のI―I線に沿う模式的断面構造図、図108は、図106のII―II線に沿う模式的断面構造図、図109は、図106のIII―III線に沿う模式的断面構造図、図110は、図106のIV―IV線に沿う模式的断面構造図をそれぞれ示す。   FIG. 106 is a schematic plane pattern configuration diagram of the semiconductor device according to the tenth embodiment of the present invention. 107 is a schematic cross-sectional structure diagram taken along the line II of FIG. 106, FIG. 108 is a schematic cross-sectional structure diagram taken along the line II-II of FIG. 106, and FIG. 109 is a III-III diagram of FIG. 110 is a schematic cross-sectional structure diagram taken along the line, and FIG. 110 is a schematic cross-sectional structure diagram taken along the line IV-IV in FIG.

本発明の第10の実施の形態に係る半導体装置においては、導電性基板36としては金属や不純物密度の高い半導体を用いることができる。   In the semiconductor device according to the tenth embodiment of the present invention, a metal or a semiconductor with a high impurity density can be used as the conductive substrate 36.

本発明の第10の実施の形態に係る半導体装置の構造は、相補型金属―酸化物―半導体(CMOS:Complementary Metal Semiconducotor)プロセスと親和性が良く、CMOS集積回路を同時プロセスで形成することも可能となり、MEMS駆動回路の集積化が容易となる。   The structure of the semiconductor device according to the tenth embodiment of the present invention has a good affinity with a complementary metal semiconductor (CMOS) process, and a CMOS integrated circuit can be formed by a simultaneous process. This makes it possible to easily integrate the MEMS drive circuit.

本発明の第10の実施の形態に係る半導体装置によれば、高周波可動電極と静電MEMS駆動用可動電極を一体化した金属の可動電極という単純な製造し易い構造で、低電圧で駆動でき、かつ高周波信号でセルフアクチュエーションやセルフホールディングしない静電MEMSを提供することができる。   According to the semiconductor device of the tenth embodiment of the present invention, it can be driven at a low voltage with a simple structure of a metal movable electrode in which a high-frequency movable electrode and an electrostatic MEMS driving movable electrode are integrated. In addition, it is possible to provide an electrostatic MEMS that does not self-actuate or self-hold with a high-frequency signal.

[第11の実施の形態]
本発明の第11の実施の形態に係る半導体装置においては、図111乃至図115に示すように、図19乃至図27の構成において、下部電極22を基板の表面に配置し、誘電体基板24を誘電体層240に置き換え、誘電体層240の表面側において下部電極22と他の回路を接続することを特徴とする静電MEMSを構成している。
[Eleventh embodiment]
In the semiconductor device according to the eleventh embodiment of the present invention, as shown in FIGS. 111 to 115, in the configuration of FIGS. 19 to 27, the lower electrode 22 is disposed on the surface of the substrate, and the dielectric substrate 24 is provided. Is replaced with a dielectric layer 240, and the lower electrode 22 and another circuit are connected on the surface side of the dielectric layer 240 to constitute an electrostatic MEMS.

図111は、本発明の第11の実施の形態に係る半導体装置の模式的平面パターン構成図を示す。また、図112は、図111のI―I線に沿う模式的断面構造図、図113は、図111のII―II線に沿う模式的断面構造図、図114は、図111のIII―III線に沿う模式的断面構造図、図115は、図111のIV―IV線に沿う模式的断面構造図をそれぞれ示す。   FIG. 111 is a schematic plane pattern configuration diagram of the semiconductor device according to the eleventh embodiment of the present invention. 112 is a schematic cross-sectional structure diagram taken along the line II of FIG. 111, FIG. 113 is a schematic cross-sectional structure diagram taken along the line II-II of FIG. 111, and FIG. 115 is a schematic cross-sectional structure diagram taken along the line, and FIG. 115 is a schematic cross-sectional structure diagram taken along the line IV-IV in FIG.

本発明の第11の実施の形態に係る半導体装置においては、動作周波数における表皮効果を考慮して下部電極22を基板の表面に配置している。このように下部電極22を基板の表面に配置することで、誘電体層240の表面側において下部電極22と他の回路を接続することを可能にしている。   In the semiconductor device according to the eleventh embodiment of the present invention, the lower electrode 22 is arranged on the surface of the substrate in consideration of the skin effect at the operating frequency. By disposing the lower electrode 22 on the surface of the substrate in this way, it is possible to connect the lower electrode 22 and other circuits on the surface side of the dielectric layer 240.

本発明の第11の実施の形態に係る半導体装置においては、基板は誘電体層240であっても、また導電性基板36であっても良い。   In the semiconductor device according to the eleventh embodiment of the present invention, the substrate may be the dielectric layer 240 or the conductive substrate 36.

本発明の第11の実施の形態に係る半導体装置においては、導電性基板として、導電率が金属より低い半導体基板を適用する場合には、下部電極22を基板の表面に配置したことによって、図106乃至図110に示す本発明の第10に実施の形に係る半導体装置に比べて、回路の損失を低減することができる。   In the semiconductor device according to the eleventh embodiment of the present invention, when a semiconductor substrate having a conductivity lower than that of a metal is applied as the conductive substrate, the lower electrode 22 is arranged on the surface of the substrate. Compared to the semiconductor device according to the tenth embodiment of the present invention shown in FIGS. 106 to 110, the circuit loss can be reduced.

本発明の第11の実施の形態に係る半導体装置の構造は、CMOSプロセスと親和性が良く、CMOS集積回路を同時プロセスで形成することも可能となり、MEMS駆動回路の集積化が容易となる。   The structure of the semiconductor device according to the eleventh embodiment of the present invention has a good affinity with the CMOS process, it is possible to form a CMOS integrated circuit by a simultaneous process, and the integration of the MEMS drive circuit is facilitated.

本発明の第11の実施の形態に係る半導体装置によれば、高周波可動電極と静電MEMS駆動用可動電極を一体化した金属の可動電極という単純な製造し易い構造で、低電圧で駆動でき、かつ高周波信号でセルフアクチュエーションやセルフホールディングしない静電MEMSを提供することができる。   According to the semiconductor device of the eleventh embodiment of the present invention, it can be driven at a low voltage with a simple structure of a metal movable electrode in which a high-frequency movable electrode and an electrostatic MEMS driving movable electrode are integrated. In addition, it is possible to provide an electrostatic MEMS that does not self-actuate or self-hold with a high-frequency signal.

[第12の実施の形態]
本発明の第12の実施の形態に係る半導体装置においては、図116乃至図120に示すように、図19乃至図27の構成において、絶縁膜12のうち高周波固定電極18を覆う絶縁膜は無く、駆動電圧印加時に高周波固定電極18が可動電極10と接触するように高周波固定電極18の表面の高さを駆動用固定電極16の表面の高さより高く形成することを特徴とする静電MEMSを構成している。
[Twelfth embodiment]
In the semiconductor device according to the twelfth embodiment of the present invention, as shown in FIGS. 116 to 120, there is no insulating film covering the high-frequency fixed electrode 18 in the insulating film 12 as shown in FIGS. An electrostatic MEMS, wherein the height of the surface of the high-frequency fixed electrode 18 is formed to be higher than the height of the surface of the fixed electrode for driving 16 so that the high-frequency fixed electrode 18 contacts the movable electrode 10 when a driving voltage is applied. It is composed.

図116は、本発明の第12の実施の形態に係る半導体装置の模式的平面パターン構成図を示す。また、図117は、図116のI―I線に沿う模式的断面構造図、図118は、図116のII―II線に沿う模式的断面構造図、図119は、図116のIII―III線に沿う模式的断面構造図、図120は、図116のIV―IV線に沿う模式的断面構造図をそれぞれ示す。   FIG. 116 is a schematic plane pattern configuration diagram of the semiconductor device according to the twelfth embodiment of the present invention. 117 is a schematic cross-sectional structure diagram taken along line II of FIG. 116, FIG. 118 is a schematic cross-sectional structure diagram taken along line II-II of FIG. 116, and FIG. 119 is III-III of FIG. 120 is a schematic cross-sectional structure diagram taken along the line, and FIG. 120 is a schematic cross-sectional structure diagram taken along the line IV-IV in FIG.

本発明の第12の実施の形態に係る半導体装置においては、絶縁膜を介さずに高周波固定電極18と可動電極10が接触するので、高周波固定電極18と可動電極10の導通状態を良好にすることができる。   In the semiconductor device according to the twelfth embodiment of the present invention, the high-frequency fixed electrode 18 and the movable electrode 10 are in contact with each other without an insulating film, so that the conductive state between the high-frequency fixed electrode 18 and the movable electrode 10 is improved. be able to.

本発明の第12の実施の形態に係る半導体装置によれば、高周波可動電極と静電MEMS駆動用可動電極を一体化した金属の可動電極という単純な製造し易い構造で、低電圧で駆動でき、かつ高周波信号でセルフアクチュエーションやセルフホールディングしない静電MEMSを提供することができる。   According to the semiconductor device of the twelfth embodiment of the present invention, it can be driven at a low voltage with a simple structure of a metal movable electrode in which a high frequency movable electrode and a movable electrode for electrostatic MEMS driving are integrated. In addition, it is possible to provide an electrostatic MEMS that does not self-actuate or self-hold with a high-frequency signal.

[第13の実施の形態]
本発明の第13の実施の形態に係る半導体装置においては、図121乃至図125に示すように、図19乃至図27の構成において、高周波固定電極18の表面の高さを、駆動用固定電極16の表面の高さより高く形成することを特徴とする静電MEMSを構成している。
[Thirteenth embodiment]
In the semiconductor device according to the thirteenth embodiment of the present invention, as shown in FIGS. 121 to 125, in the configuration of FIGS. 19 to 27, the height of the surface of the high frequency fixed electrode 18 is set to the fixed electrode for driving. The electrostatic MEMS is characterized by being formed higher than the height of the surface of 16.

図121は、本発明の第13の実施の形態に係る半導体装置の模式的平面パターン構成図を示す。また、図122は、図121のI―I線に沿う模式的断面構造図、図123は、図121のII―II線に沿う模式的断面構造図、図124は、図121のIII―III線に沿う模式的断面構造図、図125は、図121のIV―IV線に沿う模式的断面構造図をそれぞれ示す。   FIG. 121 is a schematic plane pattern configuration diagram of a semiconductor device according to a thirteenth embodiment of the present invention. 122 is a schematic sectional view taken along the line II of FIG. 121, FIG. 123 is a schematic sectional view taken along the line II-II of FIG. 121, and FIG. 124 is taken along the line III-III of FIG. 125 is a schematic cross-sectional structure diagram taken along the line, and FIG. 125 is a schematic cross-sectional structure diagram taken along the line IV-IV in FIG.

本発明の第13の実施の形態に係る半導体装置においては、高周波固定電極18の表面の高さを、駆動用固定電極16の表面の高さよりも高く形成するため、可動電極10が高周波固定電極18の部分を押さえる力を強く設定することができる。   In the semiconductor device according to the thirteenth embodiment of the present invention, since the height of the surface of the high frequency fixed electrode 18 is formed higher than the height of the surface of the fixed electrode for driving 16, the movable electrode 10 is a high frequency fixed electrode. The force for pressing the 18 portion can be set strongly.

本発明の第13の実施の形態に係る半導体装置によれば、高周波可動電極と静電MEMS駆動用可動電極を一体化した金属の可動電極という単純な製造し易い構造で、低電圧で駆動でき、かつ高周波信号でセルフアクチュエーションやセルフホールディングしない静電MEMSを提供することができる。   According to the semiconductor device of the thirteenth embodiment of the present invention, it can be driven at a low voltage with a simple and easy-to-manufacture structure of a metal movable electrode in which a high-frequency movable electrode and an electrostatic MEMS driving movable electrode are integrated. In addition, it is possible to provide an electrostatic MEMS that does not self-actuate or self-hold with a high-frequency signal.

[第14の実施の形態]
本発明の第14の実施の形態に係る半導体装置においては、図126乃至図130に示すように、図19乃至図27の構成において、高周波固定電極18の表面の中央の高さを、周辺より階段状に高く形成することを特徴とする静電MEMSを構成している。
[Fourteenth embodiment]
In the semiconductor device according to the fourteenth embodiment of the present invention, as shown in FIGS. 126 to 130, the height of the center of the surface of the high-frequency fixed electrode 18 is higher than that of the periphery in the configuration of FIGS. An electrostatic MEMS is characterized in that it is formed in a stepped shape.

図126は、本発明の第14の実施の形態に係る半導体装置の模式的平面パターン構成図を示す。また、図127は、図126のI―I線に沿う模式的断面構造図、図128は、図126のII―II線に沿う模式的断面構造図、図129は、図126のIII―III線に沿う模式的断面構造図、図130は、図126のIV―IV線に沿う模式的断面構造図をそれぞれ示す。   FIG. 126 is a schematic plane pattern configuration diagram of the semiconductor device according to the fourteenth embodiment of the present invention. 127 is a schematic cross-sectional structure diagram taken along line II of FIG. 126, FIG. 128 is a schematic cross-sectional structure diagram taken along line II-II of FIG. 126, and FIG. 129 is III-III of FIG. FIG. 130 shows a schematic cross-sectional structure diagram along line IV-IV in FIG. 126, respectively.

本発明の第14の実施の形態に係る半導体装置においては、高周波固定電極18の表面の中央の高さを、周辺より階段状に高く形成するので、可動電極10が高周波固定電極18の部分を押さえる力を均等にすることができる。   In the semiconductor device according to the fourteenth embodiment of the present invention, the height of the center of the surface of the high-frequency fixed electrode 18 is formed so as to be stepped higher than the periphery. The pressing force can be made uniform.

この一例では一段としたが、多段にすることにより効果が高くなり隙間も低減化することができる。   In this example, the number of stages is one. However, the effect is increased and the gap can be reduced by using multiple stages.

本発明の第14の実施の形態に係る半導体装置によれば、高周波可動電極と静電MEMS駆動用可動電極を一体化した金属の可動電極という単純な製造し易い構造で、低電圧で駆動でき、かつ高周波信号でセルフアクチュエーションやセルフホールディングしない静電MEMSを提供することができる。   According to the semiconductor device of the fourteenth embodiment of the present invention, it can be driven at a low voltage with a simple and easy-to-manufacture structure of a metal movable electrode in which a high-frequency movable electrode and an electrostatic MEMS driving movable electrode are integrated. In addition, it is possible to provide an electrostatic MEMS that does not self-actuate or self-hold with a high-frequency signal.

[第15の実施の形態]
本発明の第15の実施の形態に係る半導体装置においては、図131乃至図135に示すように、図19乃至図27の構成において、高周波固定電極18の表面の中央の高さを、周辺よりもなだらかな傾斜状に高く形成することを特徴とする静電MEMSを構成している。
[Fifteenth embodiment]
In the semiconductor device according to the fifteenth embodiment of the present invention, as shown in FIGS. 131 to 135, in the configuration of FIGS. The electrostatic MEMS is characterized by being formed so as to have a gentle slope.

図131は、本発明の第15の実施の形態に係る半導体装置の模式的平面パターン構成図を示す。また、図132は、図131のI―I線に沿う模式的断面構造図、図133は、図131のII―II線に沿う模式的断面構造図、図134は、図131のIII―III線に沿う模式的断面構造図、図135は、図131のIV―IV線に沿う模式的断面構造図をそれぞれ示す。   FIG. 131 is a schematic plane pattern configuration diagram of the semiconductor device according to the fifteenth embodiment of the present invention. 132 is a schematic sectional view taken along the line II of FIG. 131, FIG. 133 is a schematic sectional view taken along the line II-II of FIG. 131, and FIG. 134 is taken along the line III-III of FIG. FIG. 135 shows a schematic cross-sectional structure diagram along line IV-IV in FIG. 131, respectively.

本発明の第15の実施の形態に係る半導体装置においては、高周波固定電極18の表面の中央を、なだらかな傾斜状に高く形成するため、可動電極10が隙間なく高周波固定電極18を押さえる構造を提供することができる。   In the semiconductor device according to the fifteenth embodiment of the present invention, since the center of the surface of the high-frequency fixed electrode 18 is formed so as to have a gentle slope, the structure in which the movable electrode 10 holds the high-frequency fixed electrode 18 without a gap is provided. Can be provided.

本発明の第15の実施の形態に係る半導体装置によれば、高周波可動電極と静電MEMS駆動用可動電極を一体化した金属の可動電極という単純な製造し易い構造で、低電圧で駆動でき、かつ高周波信号でセルフアクチュエーションやセルフホールディングしない静電MEMSを提供することができる。   According to the semiconductor device of the fifteenth embodiment of the present invention, it can be driven at a low voltage with a simple structure of a metal movable electrode in which a high-frequency movable electrode and an electrostatic MEMS driving movable electrode are integrated. In addition, it is possible to provide an electrostatic MEMS that does not self-actuate or self-hold with a high-frequency signal.

[第16の実施の形態]
本発明の第16の実施の形態に係る半導体装置においては、図136乃至図140に示すように、図19乃至図27の構成において、高周波固定電極18を覆う絶縁膜13の厚さを、駆動用固定電極16を覆う絶縁膜12の厚さよりも厚く形成することを特徴とする静電MEMSを構成している。
[Sixteenth embodiment]
In the semiconductor device according to the sixteenth embodiment of the present invention, as shown in FIGS. 136 to 140, in the configuration of FIGS. 19 to 27, the thickness of the insulating film 13 covering the high frequency fixed electrode 18 is driven. The electrostatic MEMS is characterized in that it is formed thicker than the insulating film 12 covering the fixed electrode 16 for use.

図136は、本発明の第16の実施の形態に係る半導体装置の模式的平面パターン構成図を示す。また、図137は、図136のI―I線に沿う模式的断面構造図、図138は、136のII―II線に沿う模式的断面構造図、図139は、図136のIII―III線に沿う模式的断面構造図、図140は、図136のIV―IV線に沿う模式的断面構造図をそれぞれ示す。   FIG. 136 is a schematic plane pattern configuration diagram of the semiconductor device according to the sixteenth embodiment of the present invention. 137 is a schematic cross-sectional structure diagram taken along line II of FIG. 136, FIG. 138 is a schematic cross-sectional structure diagram taken along line II-II of 136, and FIG. 139 is a III-III line of FIG. FIG. 140 is a schematic sectional view taken along line IV-IV in FIG. 136.

本発明の第16の実施の形態に係る半導体装置においては、高周波固定電極18を覆う絶縁膜13の厚さを、駆動用固定電極16を覆う絶縁膜12の厚さよりも厚く形成するため、可動電極10が高周波固定電極18の部分を押さえる力を強くすることができる。   In the semiconductor device according to the sixteenth embodiment of the present invention, the insulating film 13 covering the high-frequency fixed electrode 18 is formed thicker than the insulating film 12 covering the driving fixed electrode 16, so that the movable film is movable. The force with which the electrode 10 presses the portion of the high-frequency fixed electrode 18 can be increased.

[第17の実施の形態]
本発明の第17の実施の形態に係る半導体装置は、図141乃至図145に示すように、図19乃至図27の構成において、高周波固定電極18を覆う絶縁膜13の中央の厚さを、周辺より階段状に厚く形成することを特徴とする静電MEMSを構成している。
[Seventeenth embodiment]
In the semiconductor device according to the seventeenth embodiment of the present invention, as shown in FIGS. 141 to 145, the thickness of the center of the insulating film 13 covering the high frequency fixed electrode 18 in the configuration of FIGS. The electrostatic MEMS is characterized in that it is formed thicker in a step shape from the periphery.

図141は、本発明の第17実施の形態に係る半導体装置の模式的平面パターン構成図を示す。また、図142は、図141のI―I線に沿う模式的断面構造図、図143は、図141のII―II線に沿う模式的断面構造図、図144は、図141のIII―III線に沿う模式的断面構造図、図145は、図141のIV―IV線に沿う模式的断面構造図をそれぞれ示す。   FIG. 141 is a schematic plane pattern configuration diagram of the semiconductor device according to the seventeenth embodiment of the present invention. 142 is a schematic cross-sectional structure diagram taken along line II of FIG. 141, FIG. 143 is a schematic cross-sectional structure diagram taken along line II-II of FIG. 141, and FIG. 144 is a III-III diagram of FIG. FIG. 145 is a schematic cross-sectional structure diagram taken along line IV-IV in FIG. 141.

本発明の第17の実施の形態に係る半導体装置においては、高周波固定電極18を覆う絶縁膜13の中央の厚さを、周辺より階段状に厚く形成するため、可動電極10が高周波固定電極18の部分を押さえる力を均等にすることができる。   In the semiconductor device according to the seventeenth embodiment of the present invention, since the central thickness of the insulating film 13 covering the high-frequency fixed electrode 18 is formed to be stepped from the periphery, the movable electrode 10 is the high-frequency fixed electrode 18. It is possible to equalize the force of pressing the part.

この一例では一段としたが、絶縁膜13を多段に構成することにより効果が高くなり隙間も減らすことができる。   In this example, the number of steps is one, but the effect is increased and the gap can be reduced by forming the insulating film 13 in multiple steps.

本発明の第17の実施の形態に係る半導体装置によれば、高周波可動電極と静電MEMS駆動用可動電極を一体化した金属の可動電極という単純な製造し易い構造で、低電圧で駆動でき、かつ高周波信号でセルフアクチュエーションやセルフホールディングしない静電MEMSを提供することができる。   According to the semiconductor device of the seventeenth embodiment of the present invention, it can be driven at a low voltage with a simple and easy-to-manufacture structure of a metal movable electrode in which a high-frequency movable electrode and an electrostatic MEMS driving movable electrode are integrated. In addition, it is possible to provide an electrostatic MEMS that does not self-actuate or self-hold with a high-frequency signal.

[第18の実施の形態]
本発明の第18の実施の形態に係る半導体装置は、図146乃至図150に示すように、図19乃至図27の構成において、高周波固定電極18を覆う絶縁膜13の中央の厚さを、周辺よりもなだらかな傾斜状に厚く形成することを特徴とする静電MEMSを構成している。
[Eighteenth embodiment]
As shown in FIGS. 146 to 150, the semiconductor device according to the eighteenth embodiment of the present invention has the thickness of the center of the insulating film 13 covering the high-frequency fixed electrode 18 in the configuration of FIGS. The electrostatic MEMS is characterized in that it is formed to be thicker and inclined than the periphery.

図146は、本発明の第18の実施の形態に係る半導体装置の模式的平面パターン構成図を示す。図147は、図146のI―I線に沿う模式的断面構造図、図148は、図146のII―II線に沿う模式的断面構造図、図149は、図146のIII―III線に沿う模式的断面構造図、図150は、図146のIV―IV線に沿う模式的断面構造図をそれぞれ示す。   FIG. 146 is a schematic plane pattern configuration diagram of the semiconductor device according to the eighteenth embodiment of the present invention. FIG. 147 is a schematic sectional view taken along the line II of FIG. 146, FIG. 148 is a schematic sectional view taken along the line II-II of FIG. 146, and FIG. 149 is taken along the line III-III of FIG. FIG. 150 is a schematic cross-sectional structure diagram taken along the line IV-IV in FIG. 146, respectively.

本発明の第18の実施の形態に係る半導体装置においては、高周波固定電極18を覆う絶縁膜13の中央の厚さを、なだらかな傾斜状に厚く形成するため、可動電極10が隙間なく高周波固定電極18の部分を押さえることができる。   In the semiconductor device according to the eighteenth embodiment of the present invention, since the central thickness of the insulating film 13 covering the high-frequency fixed electrode 18 is formed to be gently inclined, the movable electrode 10 is fixed to the high-frequency without gaps. The part of the electrode 18 can be pressed down.

本発明の第18の実施の形態に係る半導体装置によれば、高周波可動電極と静電MEMS駆動用可動電極を一体化した金属の可動電極という単純な製造し易い構造で、低電圧で駆動でき、かつ高周波信号でセルフアクチュエーションやセルフホールディングしない静電MEMSを提供することができる。   According to the semiconductor device of the eighteenth embodiment of the present invention, it can be driven at a low voltage with a simple structure of a metal movable electrode in which a high-frequency movable electrode and an electrostatic MEMS driving movable electrode are integrated. In addition, it is possible to provide an electrostatic MEMS that does not self-actuate or self-hold with a high-frequency signal.

[第19の実施の形態]
本発明の第19の実施の形態に係る半導体装置は、図151乃至図155に示すように、図19乃至図27の構成において、可動電極10の少なくとも一部に複数の穴40を形成したことを特徴とする静電MEMSを構成している。
[Nineteenth embodiment]
In the semiconductor device according to the nineteenth embodiment of the present invention, as shown in FIGS. 151 to 155, a plurality of holes 40 are formed in at least a part of the movable electrode 10 in the configuration of FIGS. The electrostatic MEMS characterized by the above is configured.

図151は、本発明の第19の実施の形態に係る半導体装置の模式的平面パターン構成図を示す。また、図152は、図151のI―I線に沿う模式的断面構造図、図153は、図151のII―II線に沿う模式的断面構造図、図154は、図151のIII―III線に沿う模式的断面構造図、図155は、図151のIV―IV線に沿う模式的断面構造図をそれぞれ示す。   FIG. 151 is a schematic plane pattern configuration diagram of the semiconductor device according to the nineteenth embodiment of the present invention. 152 is a schematic sectional view taken along the line II of FIG. 151, FIG. 153 is a schematic sectional view taken along the line II-II of FIG. 151, and FIG. 154 is a sectional view taken along the line III-III of FIG. FIG. 155 shows a schematic cross-sectional structure diagram taken along the line IV-IV in FIG. 151, respectively.

本発明の第19の実施の形態に係る半導体装置においては、可動電極10の一部に複数の穴40を開けることによって、可動電極10の質量を低減でき、また可動電極10が空気を圧搾するために可動電極10の動きが遅くなるスクイーズドダンピングを低減し、粘性を抑制することができる。   In the semiconductor device according to the nineteenth embodiment of the present invention, the mass of the movable electrode 10 can be reduced by opening a plurality of holes 40 in a part of the movable electrode 10, and the movable electrode 10 squeezes air. Therefore, it is possible to reduce squeezed damping that slows the movement of the movable electrode 10 and suppress viscosity.

本発明の第19の実施の形態に係る半導体装置によれば、高周波可動電極と静電MEMS駆動用可動電極を一体化した金属の可動電極という単純な製造し易い構造で、低電圧で駆動でき、かつ高周波信号でセルフアクチュエーションやセルフホールディングしない静電MEMSを提供することができる。   According to the semiconductor device of the nineteenth embodiment of the present invention, it can be driven at a low voltage with a simple and easy-to-manufacture structure of a metal movable electrode in which a high-frequency movable electrode and an electrostatic MEMS driving movable electrode are integrated. In addition, it is possible to provide an electrostatic MEMS that does not self-actuate or self-hold with a high-frequency signal.

[その他の実施の形態]
上記のように、本発明は第1乃至第19の実施の形態によって記載したが、この開示の一部をなす論述及び図面はこの発明を限定するものではなく、実施段階では種々に変形することが可能である。この開示から当業者には様々な代替実施の形態、実施例及び運用技術が明らかとなろう。
[Other embodiments]
As described above, the present invention has been described with reference to the first to nineteenth embodiments. However, the discussion and the drawings constituting a part of this disclosure do not limit the present invention, and various modifications may be made in the implementation stage. Is possible. From this disclosure, various alternative embodiments, examples, and operational techniques will be apparent to those skilled in the art.

このように、本発明はここでは記載していない様々な実施の形態等を含むことは勿論である。したがって、本発明の技術的範囲は上記の説明から妥当な特許請求の範囲に係る発明特定事項によってのみ定められるものである。 As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

本発明の第1乃至第19の実施の形態に係る半導体装置は、静電MEMSとして構成されることから、MEMS応用としてのスイッチ、可変容量、可変整合回路、チューナブルフィルタ、チューナブルアンテナ、携帯電話など幅広い応用分野に適用することができる。   Since the semiconductor devices according to the first to nineteenth embodiments of the present invention are configured as electrostatic MEMS, switches, variable capacitors, variable matching circuits, tunable filters, tunable antennas, mobile phones as MEMS applications It can be applied to a wide range of application fields such as telephones.

本発明の第1の実施の形態に係る半導体装置の模式的平面パターン構成図。1 is a schematic plan pattern configuration diagram of a semiconductor device according to a first embodiment of the present invention. FIG. 図1のI―I線に沿う模式的断面構造図。FIG. 2 is a schematic cross-sectional structure diagram taken along line II in FIG. 1. 図1のII―II線に沿う模式的断面構造図。FIG. 2 is a schematic sectional view taken along line II-II in FIG. 1. 図1のIII―III線に沿う模式的断面構造図。FIG. 3 is a schematic sectional view taken along line III-III in FIG. 1. 図1のIV―IV線に沿う模式的断面構造図。FIG. 4 is a schematic sectional view taken along line IV-IV in FIG. 1. 図2において、駆動電圧印加時における図1のI―I線に沿う模式的断面構造図。2 is a schematic cross-sectional structure diagram taken along the line II of FIG. 1 when a drive voltage is applied. 図3において、駆動電圧印加時における図1のII―II線に沿う模式的断面構造図。FIG. 3 is a schematic sectional view taken along the line II-II in FIG. 1 when a driving voltage is applied in FIG. 図4において、駆動電圧印加時における図1のIII―III線に沿う模式的断面構造図。FIG. 4 is a schematic sectional view taken along the line III-III in FIG. 1 when a drive voltage is applied. 図5において、駆動電圧印加時における図1のIV―IV線に沿う模式的断面構造図。FIG. 5 is a schematic sectional view taken along line IV-IV in FIG. 1 when a drive voltage is applied. 本発明の第2の実施の形態に係る半導体装置の模式的平面パターン構成図。The typical plane pattern block diagram of the semiconductor device which concerns on the 2nd Embodiment of this invention. 図10のI―I線に沿う模式的断面構造図。FIG. 11 is a schematic sectional view taken along the line II of FIG. 10. 図10のII―II線に沿う模式的断面構造図。FIG. 11 is a schematic sectional view taken along the line II-II in FIG. 10. 図10のIII―III線に沿う模式的断面構造図。FIG. 11 is a schematic sectional view taken along line III-III in FIG. 10. 図10のIV―IV線に沿う模式的断面構造図。FIG. 11 is a schematic sectional view taken along line IV-IV in FIG. 10. 図11において、駆動電圧印加時における図10のI―I線に沿う模式的断面構造図。FIG. 11 is a schematic sectional view taken along the line II of FIG. 10 when a drive voltage is applied in FIG. 図12において、駆動電圧印加時における図10のII―II線に沿う模式的断面構造図。FIG. 12 is a schematic sectional view taken along the line II-II in FIG. 10 when a drive voltage is applied. 図13において、駆動電圧印加時における図10のIII―III線に沿う模式的断面構造図。FIG. 13 is a schematic sectional view taken along the line III-III in FIG. 10 when a drive voltage is applied. 図14において、駆動電圧印加時における図10のIV―IV線に沿う模式的断面構造図。FIG. 14 is a schematic sectional view taken along the line IV-IV in FIG. 10 when a drive voltage is applied. 本発明の第3の実施の形態に係る半導体装置の模式的平面パターン構成図。The typical plane pattern block diagram of the semiconductor device which concerns on the 3rd Embodiment of this invention. 図19のI―I線に沿う模式的断面構造図。FIG. 20 is a schematic sectional view taken along the line II of FIG. 図19のII―II線に沿う模式的断面構造図。FIG. 20 is a schematic cross-sectional structure diagram taken along line II-II in FIG. 19. 図19のIII―III線に沿う模式的断面構造図。FIG. 30 is a schematic cross-sectional structure diagram taken along line III-III in FIG. 19. 図19のIV―IV線に沿う模式的断面構造図。FIG. 20 is a schematic sectional view taken along line IV-IV in FIG. 19. 図20において、駆動電圧印加時における図19のI―I線に沿う模式的断面構造図。20 is a schematic cross-sectional structure diagram taken along the line II of FIG. 19 when a drive voltage is applied. 図21において、駆動電圧印加時における図19のII―II線に沿う模式的断面構造図。FIG. 21 is a schematic sectional view taken along the line II-II in FIG. 19 when a drive voltage is applied. 図22において、駆動電圧印加時における図19のIII―III線に沿う模式的断面構造図。FIG. 22 is a schematic sectional view taken along the line III-III in FIG. 19 when a drive voltage is applied. 図23において、駆動電圧印加時における図19のIV―IV線に沿う模式的断面構造図。FIG. 23 is a schematic sectional view taken along the line IV-IV in FIG. 19 when a drive voltage is applied. 本発明の第4の実施の形態に係る半導体装置の模式的平面パターン構成図。The typical plane pattern block diagram of the semiconductor device which concerns on the 4th Embodiment of this invention. 図28のI―I線に沿う模式的断面構造図。FIG. 29 is a schematic sectional view taken along the line II of FIG. 図28のII―II線に沿う模式的断面構造図。FIG. 29 is a schematic sectional view taken along the line II-II in FIG. 28. 図28のIII―III線に沿う模式的断面構造図。FIG. 29 is a schematic sectional view taken along line III-III in FIG. 28. 図28のIV―IV線に沿う模式的断面構造図。FIG. 29 is a schematic sectional view taken along line IV-IV in FIG. 28. 図29において、駆動過渡期における図28のI―I線に沿う模式的断面構造図。FIG. 29 is a schematic sectional view taken along the line II of FIG. 28 in the drive transition period. 図30において、駆動過渡期における図28のII―II線に沿う模式的断面構造図。30 is a schematic cross-sectional structure diagram taken along the line II-II in FIG. 28 in the drive transition period. 図31において、駆動過渡期における図28のIII―III線に沿う模式的断面構造図。FIG. 31 is a schematic sectional view taken along the line III-III in FIG. 28 in the drive transition period. 図32において、駆動過渡期における図28のIV―IV線に沿う模式的断面構造図。32 is a schematic sectional view taken along the line IV-IV in FIG. 28 in the drive transition period. 図29において、駆動電圧印加時における図28のI―I線に沿う模式的断面構造図。FIG. 29 is a schematic sectional view taken along the line II of FIG. 28 when a drive voltage is applied. 図30において、駆動電圧印加時における図28のII―II線に沿う模式的断面構造図。30 is a schematic cross-sectional structure diagram taken along line II-II in FIG. 28 when a drive voltage is applied. 図31において、駆動電圧印加時における図28のIII―III線に沿う模式的断面構造図。FIG. 31 is a schematic sectional view taken along the line III-III of FIG. 28 when a drive voltage is applied. 図32において、駆動電圧印加時における図28のIV―IV線に沿う模式的断面構造図。32 is a schematic cross-sectional structure diagram taken along line IV-IV in FIG. 28 when a drive voltage is applied. 本発明の第5の実施の形態に係る半導体装置の模式的平面パターン構成図。The typical plane pattern block diagram of the semiconductor device which concerns on the 5th Embodiment of this invention. 図41のI―I線に沿う模式的断面構造図。FIG. 42 is a schematic sectional view taken along the line II of FIG. 41. 図41のII―II線に沿う模式的断面構造図。FIG. 42 is a schematic sectional view taken along line II-II in FIG. 41. 図41のIII―III線に沿う模式的断面構造図。FIG. 42 is a schematic sectional view taken along line III-III in FIG. 41. 図41のIV―IV線に沿う模式的断面構造図。FIG. 42 is a schematic sectional view taken along line IV-IV in FIG. 41. 図42において、駆動過渡期における図41のI―I線に沿う模式的断面構造図。42 is a schematic sectional view taken along the line II of FIG. 41 in the drive transition period. 図43において、駆動過渡期における図41のII―II線に沿う模式的断面構造図。43 is a schematic sectional view taken along the line II-II in FIG. 41 in the drive transition period. 図44において、駆動過渡期における図41のIII―III線に沿う模式的断面構造図。44 is a schematic sectional view taken along the line III-III of FIG. 41 in the drive transition period. 図45において、駆動過渡期における図41のIV―IV線に沿う模式的断面構造図。45 is a schematic sectional view taken along the line IV-IV in FIG. 41 in the drive transition period. 図42において、駆動電圧印加時における図41のI―I線に沿う模式的断面構造図。42 is a schematic sectional view taken along the line II of FIG. 41 when a drive voltage is applied. 図43において、駆動電圧印加時における図41のII―II線に沿う模式的断面構造図。43 is a schematic sectional view taken along the line II-II in FIG. 41 when a drive voltage is applied. 図44において、駆動電圧印加時における図41のIII―III線に沿う模式的断面構造図。44 is a schematic sectional view taken along the line III-III in FIG. 41 when a drive voltage is applied. 図45において、駆動電圧印加時における図41のIV―IV線に沿う模式的断面構造図。45 is a schematic sectional view taken along the line IV-IV in FIG. 41 when a drive voltage is applied. 本発明の第6の実施の形態に係る半導体装置の模式的平面パターン構成図。The typical plane pattern block diagram of the semiconductor device which concerns on the 6th Embodiment of this invention. 図54のI―I線に沿う模式的断面構造図。FIG. 55 is a schematic sectional view taken along the line II of FIG. 図54のII―II線に沿う模式的断面構造図。FIG. 55 is a schematic sectional view taken along the line II-II in FIG. 54. 図54のIII―III線に沿う模式的断面構造図。FIG. 56 is a schematic sectional view taken along the line III-III in FIG. 54. 図54のIV―IV線に沿う模式的断面構造図。FIG. 55 is a schematic sectional view taken along the line IV-IV in FIG. 54. 図55において、駆動過渡期における図54のI―I線に沿う模式的断面構造図。55 is a schematic sectional view taken along the line II of FIG. 54 in the drive transition period. 図56において、駆動過渡期における図54のII―II線に沿う模式的断面構造図。56 is a schematic sectional view taken along the line II-II in FIG. 54 in the drive transition period. 図57において、駆動過渡期における図54のIII―III線に沿う模式的断面構造図。57 is a schematic sectional view taken along the line III-III in FIG. 54 in the drive transition period. 図58において、駆動過渡期における図54のIV―IV線に沿う模式的断面構造図。58 is a schematic cross-sectional structure diagram taken along the line IV-IV in FIG. 54 in the drive transition period. 図55において、駆動電圧印加時における図54のI―I線に沿う模式的断面構造図。55 is a schematic sectional view taken along the line II of FIG. 54 when a driving voltage is applied. 図56において、駆動電圧印加時における図54のII―II線に沿う模式的断面構造図。56 is a schematic sectional view taken along the line II-II in FIG. 54 when a drive voltage is applied. 図57において、駆動電圧印加時における図54のIII―III線に沿う模式的断面構造図。57 is a schematic sectional view taken along the line III-III in FIG. 54 when a drive voltage is applied. 図58において、駆動電圧印加時における図54のIV―IV線に沿う模式的断面構造図。58 is a schematic sectional view taken along the line IV-IV in FIG. 54 when a drive voltage is applied. 本発明の第7の実施の形態に係る半導体装置の模式的平面パターン構成図。The typical plane pattern block diagram of the semiconductor device which concerns on the 7th Embodiment of this invention. 図67のI―I線に沿う模式的断面構造図。FIG. 68 is a schematic sectional view taken along the line II of FIG. 67. 図67のII―II線に沿う模式的断面構造図。FIG. 68 is a schematic sectional view taken along the line II-II in FIG. 67. 図67のIII―III線に沿う模式的断面構造図。FIG. 68 is a schematic sectional view taken along line III-III in FIG. 67. 図67のIV―IV線に沿う模式的断面構造図。FIG. 68 is a schematic sectional view taken along the line IV-IV in FIG. 67. 図68において、駆動過渡期における図67のI―I線に沿う模式的断面構造図。68 is a schematic sectional view taken along the line II of FIG. 67 in the drive transition period. 図69において、駆動過渡期における図67のII―II線に沿う模式的断面構造図。69 is a schematic cross-sectional structure diagram taken along the line II-II in FIG. 67 in the drive transition period. 図70において、駆動過渡期における図67のIII―III線に沿う模式的断面構造図。FIG. 70 is a schematic sectional view taken along the line III-III of FIG. 67 in the drive transition period. 図71において、駆動過渡期における図67のIV―IV線に沿う模式的断面構造図。FIG. 71 is a schematic cross-sectional structure diagram taken along the line IV-IV in FIG. 67 in the drive transition period. 図68において、駆動電圧印加時における図67のI―I線に沿う模式的断面構造図。68 is a schematic sectional view taken along the line II of FIG. 67 when a driving voltage is applied. 図69において、駆動電圧印加時における図67のII―II線に沿う模式的断面構造図。69 is a schematic sectional view taken along the line II-II in FIG. 67 when a drive voltage is applied. 図70において、駆動電圧印加時における図67のIII―III線に沿う模式的断面構造図。FIG. 70 is a schematic sectional view taken along the line III-III in FIG. 67 when a drive voltage is applied. 図71において、駆動電圧印加時における図67のIV―IV線に沿う模式的断面構造図。71 is a schematic cross-sectional structure diagram taken along the line IV-IV in FIG. 67 when a drive voltage is applied. 本発明の第8の実施の形態に係る半導体装置の模式的平面パターン構成図。The typical plane pattern block diagram of the semiconductor device which concerns on the 8th Embodiment of this invention. 図80のI―I線に沿う模式的断面構造図。FIG. 81 is a schematic sectional view taken along the line II of FIG. 図80のII―II線に沿う模式的断面構造図。FIG. 81 is a schematic sectional view taken along the line II-II in FIG. 図80のIII―III線に沿う模式的断面構造図。FIG. 81 is a schematic sectional view taken along line III-III in FIG. 80. 図80のIV―IV線に沿う模式的断面構造図。FIG. 81 is a schematic sectional view taken along the line IV-IV in FIG. 図81において、駆動過渡期における図80のI―I線に沿う模式的断面構造図。81 is a schematic cross-sectional structure diagram taken along the line II of FIG. 80 in the drive transition period. 図82において、駆動過渡期における図80のII―II線に沿う模式的断面構造図。82 is a schematic sectional view taken along the line II-II in FIG. 80 in the drive transition period. 図83において、駆動過渡期における図80のIII―III線に沿う模式的断面構造図。83 is a schematic cross-sectional structure diagram taken along the line III-III in FIG. 80 in the drive transition period. 図84において、駆動過渡期における図80のIV―IV線に沿う模式的断面構造図。FIG. 84 is a schematic sectional view taken along the line IV-IV in FIG. 80 in the drive transition period. 図81において、駆動電圧印加時における図80のI―I線に沿う模式的断面構造図。FIG. 81 is a schematic cross-sectional structure diagram taken along the line II of FIG. 80 when a drive voltage is applied. 図82において、駆動電圧印加時における図80のII―II線に沿う模式的断面構造図。82 is a schematic cross-sectional structure diagram taken along the line II-II in FIG. 80 when a drive voltage is applied. 図83において、駆動電圧印加時における図80のIII―III線に沿う模式的断面構造図。83 is a schematic cross-sectional structure diagram taken along line III-III in FIG. 80 when a drive voltage is applied. 図84において、駆動電圧印加時における図80のIV―IV線に沿う模式的断面構造図。FIG. 84 is a schematic sectional view taken along the line IV-IV in FIG. 80 when a drive voltage is applied. 本発明の第9の実施の形態に係る半導体装置の模式的平面パターン構成図。Schematic plane pattern block diagram of the semiconductor device which concerns on the 9th Embodiment of this invention. 図93のI―I線に沿う模式的断面構造図。FIG. 96 is a schematic cross-sectional structure diagram taken along the line II of FIG. 図93のII―II線に沿う模式的断面構造図。FIG. 96 is a schematic cross-sectional structure diagram taken along the line II-II in FIG. 93. 図93のIII―III線に沿う模式的断面構造図。FIG. 96 is a schematic cross-sectional structure diagram taken along line III-III in FIG. 93. 図93のIV―IV線に沿う模式的断面構造図。FIG. 94 is a schematic sectional view taken along the line IV-IV in FIG. 93. 図94において、駆動過渡期における図93のI―I線に沿う模式的断面構造図。94. FIG. 94 is a schematic sectional view taken along the line II of FIG. 93 in the drive transition period. 図95において、駆動過渡期における図93のII―II線に沿う模式的断面構造図。95 is a schematic cross-sectional structure diagram taken along the line II-II in FIG. 93 in the drive transition period. 図96において、駆動過渡期における図93のIII―III線に沿う模式的断面構造図。96 is a schematic cross-sectional structure diagram taken along the line III-III in FIG. 93 in the drive transition period. 図97において、駆動過渡期における図93のIV―IV線に沿う模式的断面構造図。FIG. 97 is a schematic cross-sectional structure diagram taken along the line IV-IV in FIG. 93 in the drive transition period. 図94において、駆動電圧印加時における図93のI―I線に沿う模式的断面構造図。94 is a schematic sectional view taken along the line II of FIG. 93 when a driving voltage is applied. 図95において、駆動電圧印加時における図93のII―II線に沿う模式的断面構造図。FIG. 95 is a schematic sectional view taken along the line II-II in FIG. 93 when a drive voltage is applied. 図96において、駆動電圧印加時における図93のIII―III線に沿う模式的断面構造図。96 is a schematic sectional view taken along the line III-III in FIG. 93 when a drive voltage is applied. 図97において、駆動電圧印加時における図93のIV―IV線に沿う模式的断面構造図。97 is a schematic cross-sectional structure diagram taken along the line IV-IV in FIG. 93 when a drive voltage is applied. 本発明の第10の実施の形態に係る半導体装置の模式的平面パターン構成図。FIG. 20 is a schematic planar pattern configuration diagram of a semiconductor device according to a tenth embodiment of the present invention. 図106のI―I線に沿う模式的断面構造図。FIG. 107 is a schematic sectional view taken along the line II in FIG. 106. 図106のII―II線に沿う模式的断面構造図。FIG. 107 is a schematic sectional view taken along the line II-II in FIG. 図106のIII―III線に沿う模式的断面構造図。FIG. 107 is a schematic cross-sectional structure diagram taken along line III-III in FIG. 106. 図106のIV―IV線に沿う模式的断面構造図。FIG. 107 is a schematic sectional view taken along the line IV-IV in FIG. 106. 本発明の第11の実施の形態に係る半導体装置の模式的平面パターン構成図。Schematic plane pattern block diagram of the semiconductor device which concerns on the 11th Embodiment of this invention. 図111のI―I線に沿う模式的断面構造図。FIG. 111 is a schematic sectional view taken along the line II of FIG. 111. 図111のII―II線に沿う模式的断面構造図。FIG. 111 is a schematic sectional view taken along the line II-II in FIG. 111. 図111のIII―III線に沿う模式的断面構造図。FIG. 111 is a schematic sectional view taken along the line III-III in FIG. 111. 図111のIV―IV線に沿う模式的断面構造図。FIG. 111 is a schematic sectional view taken along the line IV-IV in FIG. 111. 本発明の第12の実施の形態に係る半導体装置の模式的平面パターン構成図。FIG. 20 is a schematic planar pattern configuration diagram of a semiconductor device according to a twelfth embodiment of the present invention. 図116のI―I線に沿う模式的断面構造図。116 is a schematic sectional view taken along the line II of FIG. 116. FIG. 図116のII―II線に沿う模式的断面構造図。116 is a schematic cross-sectional structure diagram taken along line II-II in FIG. 116. FIG. 図116のIII―III線に沿う模式的断面構造図。116 is a schematic cross-sectional structure diagram taken along line III-III in FIG. 116. FIG. 図116のIV―IV線に沿う模式的断面構造図。116 is a schematic cross-sectional structure diagram taken along the line IV-IV in FIG. 116. FIG. 本発明の第13の実施の形態に係る半導体装置の模式的平面パターン構成図。Schematic plane pattern block diagram of the semiconductor device which concerns on the 13th Embodiment of this invention. 図121のI―I線に沿う模式的断面構造図。FIG. 122 is a schematic sectional view taken along the line II of FIG. 121. 図121のII―II線に沿う模式的断面構造図。FIG. 122 is a schematic cross-sectional structure diagram taken along the line II-II in FIG. 121. 図121のIII―III線に沿う模式的断面構造図。FIG. 132 is a schematic sectional view taken along the line III-III in FIG. 121. 図121のIV―IV線に沿う模式的断面構造図。FIG. 122 is a schematic sectional view taken along the line IV-IV in FIG. 121. 本発明の第14の実施の形態に係る半導体装置の模式的平面パターン構成図。Schematic plane pattern block diagram of the semiconductor device which concerns on the 14th Embodiment of this invention. 図126のI―I線に沿う模式的断面構造図。126 is a schematic sectional view taken along the line II of FIG. 126. FIG. 図126のII―II線に沿う模式的断面構造図。FIG. 127 is a schematic sectional view taken along the line II-II in FIG. 126. 図126のIII―III線に沿う模式的断面構造図。126 is a schematic cross-sectional structure diagram taken along line III-III in FIG. 126. FIG. 図126のIV―IV線に沿う模式的断面構造図。126 is a schematic cross-sectional structure diagram taken along the line IV-IV in FIG. 126. FIG. 本発明の第15の実施の形態に係る半導体装置の模式的平面パターン構成図。FIG. 38 is a schematic planar pattern configuration diagram of a semiconductor device according to a fifteenth embodiment of the present invention. 図131のI―I線に沿う模式的断面構造図。FIG. 132 is a schematic sectional view taken along the line II of FIG. 131. 図131のII―II線に沿う模式的断面構造図。FIG. 132 is a schematic sectional view taken along the line II-II in FIG. 131. 図131のIII―III線に沿う模式的断面構造図。FIG. 132 is a schematic sectional view taken along line III-III in FIG. 131. 図131のIV―IV線に沿う模式的断面構造図。132 is a schematic cross-sectional structure diagram taken along a line IV-IV in FIG. 131. FIG. 本発明の第16の実施の形態に係る半導体装置の模式的平面パターン構成図。Schematic plane pattern block diagram of the semiconductor device which concerns on the 16th Embodiment of this invention. 図136のI―I線に沿う模式的断面構造図。136 is a schematic cross-sectional structure diagram taken along the line II of FIG. 136. FIG. 図136のII―II線に沿う模式的断面構造図。FIG. 136 is a schematic sectional view taken along the line II-II in FIG. 136. 図136のIII―III線に沿う模式的断面構造図。Schematic sectional view taken along line III-III in FIG. 図136のIV―IV線に沿う模式的断面構造図。FIG. 136 is a schematic sectional view taken along the line IV-IV in FIG. 136. 本発明の第17実施の形態に係る半導体装置の模式的平面パターン構成図。FIG. 38 is a schematic planar pattern configuration diagram of a semiconductor device according to a seventeenth embodiment of the present invention. 図141のI―I線に沿う模式的断面構造図。141 is a schematic cross-sectional structure diagram taken along the line II of FIG. 141. FIG. 図141のII―II線に沿う模式的断面構造図。FIG. 142 is a schematic sectional view taken along the line II-II in FIG. 141. 図141のIII―III線に沿う模式的断面構造図。FIG. 143 is a schematic cross-sectional structure diagram taken along a line III-III in FIG. 141. 図141のIV―IV線に沿う模式的断面構造図。FIG. 141 is a schematic sectional view taken along line IV-IV in FIG. 141. 本発明の第18の実施の形態に係る半導体装置の模式的平面パターン構成図。Schematic plane pattern configuration diagram of a semiconductor device according to an eighteenth embodiment of the present invention. 図146のI―I線に沿う模式的断面構造図。146 is a schematic cross-sectional structure diagram taken along a line II in FIG. 図146のII―II線に沿う模式的断面構造図。146 is a schematic cross-sectional structure diagram taken along line II-II in FIG. 図146のIII―III線に沿う模式的断面構造図。Schematic cross-sectional structure diagram along line III-III in FIG. 図146のIV―IV線に沿う模式的断面構造図。146 is a schematic cross-sectional structure diagram taken along a line IV-IV in FIG. 本発明の第19の実施の形態に係る半導体装置の模式的平面パターン構成図。FIG. 38 is a schematic planar pattern configuration diagram of a semiconductor device according to a nineteenth embodiment of the present invention. 図151のI―I線に沿う模式的断面構造図。FIG. 151 is a schematic sectional view taken along the line II of FIG. 151. 図151のII―II線に沿う模式的断面構造図。FIG. 152 is a schematic sectional view taken along the line II-II in FIG. 151. 図151のIII―III線に沿う模式的断面構造図。FIG. 131 is a schematic sectional view taken along line III-III in FIG. 151. 図151のIV―IV線に沿う模式的断面構造図。Schematic cross-sectional structure diagram along line IV-IV in FIG.

符号の説明Explanation of symbols

10…可動電極
12,13…絶縁膜
14…アンカー
16…駆動用固定電極
18…高周波固定電極
20…ビアホール
22…下部電極
24…誘電体基板
26…スリット
28…舌状可動部
30…凸部
32…階段状部
34…なだらかな傾斜面
36…導電性基板
38…下部電極接続部
40…穴
240…誘電体層
DESCRIPTION OF SYMBOLS 10 ... Movable electrodes 12, 13 ... Insulating film 14 ... Anchor 16 ... Driving fixed electrode 18 ... High frequency fixed electrode 20 ... Via hole 22 ... Lower electrode 24 ... Dielectric substrate 26 ... Slit 28 ... Tongue movable part 30 ... Convex part 32 ... Step-like portion 34 ... Sloping inclined surface 36 ... Conductive substrate 38 ... Lower electrode connecting portion 40 ... Hole 240 ... Dielectric layer

Claims (23)

誘電体基板の表面と可動電極との間に空隙を形成するように前記可動電極の一端と前記誘電体基板の表面を固定するアンカーと、
前記可動電極の他端と対向するように前記誘電体基板の表面に配置された高周波固定電極と、
前記誘電体基板の裏面の下部電極と、
前記高周波固定電極と前記下部電極を接続するビアホールと、
前記誘電体基板の表面の前記アンカーと前記高周波固定電極の間に配置された駆動用固定電極と、
前記高周波固定電極と前記駆動用固定電極を覆う絶縁膜と
を備え、
前記駆動用固定電極と前記可動電極との間に、少なくとも高周波に対してインピーダンスが高いバイアス回路を経由して、駆動電圧を印加することを特徴とする半導体装置。
An anchor for fixing one end of the movable electrode and the surface of the dielectric substrate so as to form a gap between the surface of the dielectric substrate and the movable electrode;
A high-frequency fixed electrode disposed on the surface of the dielectric substrate to face the other end of the movable electrode;
A lower electrode on the back surface of the dielectric substrate;
A via hole connecting the high-frequency fixed electrode and the lower electrode;
A fixed electrode for driving disposed between the anchor on the surface of the dielectric substrate and the high-frequency fixed electrode;
An insulating film covering the high-frequency fixed electrode and the driving fixed electrode;
A semiconductor device, wherein a driving voltage is applied between the driving fixed electrode and the movable electrode via a bias circuit having a high impedance at least for a high frequency.
前記誘電体基板の厚さが前記空隙の高さと前記絶縁膜の厚さの和より厚いことを特徴とする請求項1に記載の半導体装置。   The semiconductor device according to claim 1, wherein a thickness of the dielectric substrate is thicker than a sum of a height of the gap and a thickness of the insulating film. 前記駆動用固定電極の面積が前記高周波固定電極の面積より広いことを特徴とする請求項1または2に記載の半導体装置。   The semiconductor device according to claim 1, wherein an area of the driving fixed electrode is larger than an area of the high-frequency fixed electrode. 前記高周波固定電極と前記可動電極との間に、少なくとも高周波に対してインピーダンスが高いバイアス回路を経由して、駆動電圧を印加することを特徴とする請求項1に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein a drive voltage is applied between the high-frequency fixed electrode and the movable electrode via a bias circuit having a high impedance at least for a high frequency. 前記誘電体基板を、真性半導体基板,不純物密度の低い高抵抗半導体基板あるいは半絶縁性半導体基板のいずれかに置き換えたことを特徴とする請求項1乃至4の内、いずれか1項に記載の半導体装置。   5. The dielectric substrate according to claim 1, wherein the dielectric substrate is replaced with an intrinsic semiconductor substrate, a high-resistance semiconductor substrate with a low impurity density, or a semi-insulating semiconductor substrate. Semiconductor device. 前記可動電極の前記駆動用固定電極に対向する領域の一部にスリットを入れ、前記アンカー側を先端とし、前記高周波固定電極側を付け根とする、舌状可動部を少なくとも一つ備えることを特徴とする請求項1乃至5の内、いずれか1項に記載の半導体装置。   The movable electrode includes at least one tongue-shaped movable portion having a slit in a part of a region facing the fixed electrode for driving, the anchor side as a tip, and the high-frequency fixed electrode side as a root. The semiconductor device according to any one of claims 1 to 5. 前記可動電極の前記駆動用固定電極に対向する領域の一部にスリットを入れ、前記アンカー側を付け根とし、前記高周波固定電極側を先端とする、舌状可動部を少なくとも一つ備えることを特徴とする請求項1乃至5の内、いずれか1項に記載の半導体装置。   The movable electrode includes at least one tongue-like movable portion having a slit formed in a part of a region facing the driving fixed electrode, the anchor side as a root, and the high-frequency fixed electrode side as a tip. The semiconductor device according to any one of claims 1 to 5. 前記舌状可動部は、幅が変わる領域を備えることを特徴とする請求項6または7に記載の半導体装置。   The semiconductor device according to claim 6, wherein the tongue-like movable portion includes a region whose width changes. 前記舌状可動部の先端側の少なくとも一部を前記誘電体基板の方向に凸部とすることを特徴とする請求項6乃至8の内、いずれか1項に記載の半導体装置。   9. The semiconductor device according to claim 6, wherein at least a part of the front end side of the tongue-like movable portion is a convex portion in the direction of the dielectric substrate. 前記凸部は、段差が小さい階段形状を備えることを特徴とする請求項9に記載の半導体装置。   The semiconductor device according to claim 9, wherein the convex portion has a step shape with a small step. 前記凸部は、傾斜面を備えることを特徴とする請求項9に記載の半導体装置。   The semiconductor device according to claim 9, wherein the convex portion includes an inclined surface. 前記下部電極を導電性基板に、前記誘電体基板を誘電体層に置き換えたことを特徴とする請求項1乃至11の内、いずれか1項に記載の半導体装置。   12. The semiconductor device according to claim 1, wherein the lower electrode is replaced with a conductive substrate, and the dielectric substrate is replaced with a dielectric layer. 前記下部電極を基板の表面に配置し、前記誘電体基板を誘電体層に置き換え、前記誘電体層の表面側で前記下部電極と他の回路を接続することを特徴とする請求項1乃至11の内、いずれか1項に記載の半導体装置。   12. The lower electrode is disposed on a surface of a substrate, the dielectric substrate is replaced with a dielectric layer, and the lower electrode is connected to another circuit on the surface side of the dielectric layer. The semiconductor device according to any one of the above. 前記絶縁膜のうち前記高周波固定電極を覆う絶縁膜は無く、前記駆動電圧印加時に前記高周波固定電極が前記可動電極と接触するように前記高周波固定電極の表面の高さを前記駆動用固定電極の表面の高さより高く形成することを特徴とする請求項1乃至請求項13の内、いずれか1項に記載の半導体装置。   There is no insulating film that covers the high-frequency fixed electrode in the insulating film, and the height of the surface of the high-frequency fixed electrode is set so that the high-frequency fixed electrode contacts the movable electrode when the driving voltage is applied. The semiconductor device according to claim 1, wherein the semiconductor device is formed higher than a height of a surface. 前記高周波固定電極の表面の高さが前記駆動用固定電極の表面の高さより高く形成することを特徴とする請求項1乃至13の内、いずれか1項に記載の半導体装置。   14. The semiconductor device according to claim 1, wherein a height of a surface of the high-frequency fixed electrode is formed higher than a height of a surface of the driving fixed electrode. 前記高周波固定電極の表面の中央の高さを、周辺より階段状に高く形成することを特徴とする請求項1乃至14の内、いずれか1項に記載の半導体装置。   15. The semiconductor device according to claim 1, wherein the height of the center of the surface of the high-frequency fixed electrode is formed to be stepwise higher than the periphery. 前記高周波固定電極の表面の中央の高さを、周辺より傾斜状に高く形成することを特徴とする請求項1乃至14の内、いずれか1項に記載の半導体装置。   15. The semiconductor device according to claim 1, wherein the height of the center of the surface of the high-frequency fixed electrode is formed so as to be inclined from the periphery. 前記高周波固定電極を覆う絶縁膜の厚さを、前記駆動用固定電極を覆う前記絶縁膜の厚さより厚く形成することを特徴とする請求項1乃至13の内、いずれか1項に記載の半導体装置。   14. The semiconductor according to claim 1, wherein a thickness of the insulating film covering the high-frequency fixed electrode is formed thicker than a thickness of the insulating film covering the driving fixed electrode. apparatus. 前記高周波固定電極を覆う前記絶縁膜の中央の厚さを、周辺より階段状に厚く形成することを特徴とする請求項1乃至13の内、いずれか1項に記載の半導体装置。   14. The semiconductor device according to claim 1, wherein a thickness of the center of the insulating film covering the high-frequency fixed electrode is formed so as to be stepped from the periphery. 前記高周波固定電極を覆う前記絶縁膜の中央の厚さを、周辺より傾斜状に厚く形成することを特徴とする請求項1乃至13の内、いずれか1項に記載の半導体装置。   14. The semiconductor device according to claim 1, wherein a thickness of a center of the insulating film covering the high-frequency fixed electrode is formed so as to be inclined from a periphery thereof. 前記駆動用固定電極が前記高周波固定電極を囲むことを特徴とする請求項1乃至20の内、いずれか1項に記載の半導体装置。   21. The semiconductor device according to claim 1, wherein the driving fixed electrode surrounds the high-frequency fixed electrode. 前記アンカー,前記駆動用固定電極,あるいは前記高周波固定電極の少なくとも一つを複数にすることを特徴とする請求項1乃至21の内、いずれか1項に記載の半導体装置。   The semiconductor device according to any one of claims 1 to 21, wherein at least one of the anchor, the driving fixed electrode, or the high-frequency fixed electrode is plural. 前記可動電極の少なくとも一部に複数の穴を形成したことを特徴とする請求項1乃至22の内、いずれか1項に記載の半導体装置。












The semiconductor device according to any one of claims 1 to 22, wherein a plurality of holes are formed in at least a part of the movable electrode.












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