JP2008300022A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve a data transfer speed from a semiconductor storage circuit to a logical circuit. <P>SOLUTION: When an output data control circuit 20 outputs data DOBi switched from a high level to a low level, an output of a CMOS inverter 31 becomes a high level, and an output of a CMOS inverter 32 becomes a low level. However, since a potential difference between the source and the gate of a P channel type MOS transistor 40p is not large so much, the P channel MOS transistor 40p is not turned on soon and an output of the a CMOS inverter 40 of the last stage does not become a high level soon. Since voltage of a high level being an output of a CMOS inverter 31 is supplied to a gate of an N channel type MOS transistor 50 at that time, the N channel type MOS transistor 50 is turned on. Then, the N channel type MOS transistor 50 lifts an output of the CMOS inverter 40 of the last stage to be a high level. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit that transfers data between a semiconductor memory circuit and a logic circuit.

  2. Description of the Related Art Conventionally, as an example of a multi-chip package (semiconductor device) having a plurality of semiconductor chips, a semiconductor device called SIP having a semiconductor chip having an arithmetic processing function and a semiconductor chip having a memory circuit is known (Patent Literature). 1).

  The semiconductor device of Patent Document 1 provides a test technology that can reduce the package size by reducing the number of terminals (pins) in a semiconductor device such as an SIP in which a plurality of semiconductor chips are mounted in a single package.

Specifically, as shown in FIG. 22 of Patent Document 1, in the SIP 102 in which a plurality of semiconductor chips such as the ASIC 100 and the SDRAM 101 are mounted in a single package, a test circuit (SDRAMBIST 109) of the SDRAM 101 is provided in the ASIC 100. Then, the SDRAM 101 is tested from the outside of the SDRAM 101, that is, from the ASIC 100. Thus, by providing the test circuit of the SDRAM 101 inside the ASIC 100, it is not necessary to provide a terminal for testing the SDRAM 101 outside the SIP 102.
Japanese Patent Laying-Open No. 2005-300485 (FIG. 22)

  In the semiconductor integrated circuit such as the SIP 102, the power supply voltage VDDQ of the logic circuit such as the ASIC 100 is considerably lower than the power supply voltage VDD of the semiconductor memory circuit such as the SDRAM 101. For this reason, in consideration of reduction of power consumption and noise, it is desirable that the voltage of the interface circuit of the semiconductor integrated circuit be lowered as in the case of the power supply voltage VDDQ of the logic circuit.

  Specifically, the interface circuit is composed of a plurality of CMOS inverters, and the power supply voltage of the CMOS inverter at the final stage is made lower than the power supply voltages of other CMOS inverters to the same level as the power supply voltage VDDQ of the logic circuit. Need to lower.

  However, when the power supply voltage of the final stage CMOS inverter is lowered to VDDQ which is considerably lower than VDD, the potential difference between the drain and source of the P-channel MOS transistor constituting the CMOS inverter becomes small. As a result, there is a problem that the capability of the P channel type MOS transistor is lowered, the rising speed of the high level is very slow, and the data transfer speed from the semiconductor memory circuit to the logic circuit is lowered.

  The present invention has been proposed to solve the above-described problems, and an object of the present invention is to provide a semiconductor integrated circuit capable of improving the data transfer rate from a semiconductor memory circuit to a logic circuit.

  According to a first aspect of the present invention, there is provided a semiconductor memory circuit for storing data, an output data control circuit for outputting data read from the semiconductor recording circuit based on a predetermined clock, and a first power supply voltage for generating a first power supply voltage. One power supply voltage generation circuit; a second power supply voltage generation circuit that generates a second power supply voltage lower than the first power supply voltage; an output terminal of one CMOS inverter; and an input terminal of another CMOS inverter; Are evenly connected, and the first power supply voltage generated by the first power supply voltage generation circuit is supplied to the drain of the P-channel MOS transistor of each CMOS inverter, and the output An interface circuit for outputting data supplied from the data control circuit; and an input terminal connected to the output terminal of the interface circuit; A final stage CMOS inverter in which the second power supply voltage generated by the voltage generation circuit is supplied to the drain of the P-channel MOS transistor, and a logic circuit to which the data output from the output terminal of the final stage CMOS inverter is supplied The second power supply voltage generated by the second power supply voltage generation circuit is supplied to the drain, the gate is connected to the input terminal of the even-numbered CMOS inverter of the interface circuit, and the output terminal of the final-stage CMOS inverter And an output side N-channel MOS transistor having a source connected thereto.

  According to the first aspect of the present invention, when the second power supply voltage lower than the first power supply voltage is supplied to the final stage CMOS inverter, the final stage CMOS inverter is not immediately turned on, and the final stage CMOS inverter The output voltage does not rise immediately. At this time, the output side N-channel MOS transistor is turned on to raise the output voltage of the final stage CMOS inverter. Thereby, the rise of data supplied from the semiconductor memory circuit to the logic circuit is accelerated, and the data transfer rate can be improved.

  According to a second aspect of the present invention, there is provided a semiconductor memory circuit for storing data, an output data control circuit for outputting data read from the semiconductor recording circuit based on a predetermined clock, and a first power supply voltage for generating a first power supply voltage. One power supply voltage generation circuit; a second power supply voltage generation circuit that generates a second power supply voltage lower than the first power supply voltage; an output terminal of one CMOS inverter; and an input terminal of another CMOS inverter; 2n (n: natural number) CMOS inverters are sequentially connected, and the first power supply voltage generated by the first power supply voltage generation circuit is supplied to the drain of the P-channel MOS transistor of each CMOS inverter. An interface circuit that outputs data supplied from the output data control circuit, and an input terminal connected to the output terminal of the interface circuit; The last power supply voltage generated by the second power supply voltage generation circuit is supplied to the drain of the P-channel MOS transistor, and the data output from the output terminal of the last power supply CMOS inverter is supplied. Logic circuit, and (2n + 1) (n: natural number) CMOS inverters in which an output terminal of one CMOS inverter and an input terminal of another CMOS inverter are sequentially connected, and the first power supply voltage generation A first power supply voltage generated in the circuit is supplied to a drain of a P-channel MOS transistor of each CMOS inverter and outputs data supplied from the output data control circuit; and the second power supply voltage The second power supply voltage generated by the generation circuit is supplied to the drain, and the output terminal of the data path circuit is connected to the gate. There are connected, and a, and output-side N-channel type MOS transistor whose source is connected to the output terminal of the last-stage CMOS inverter.

  According to the second aspect of the present invention, the voltage via the same number of CMOS inverters is supplied to the gate and source of the output side N-channel MOS transistor. For this reason, the output side CMOS inverter is turned on at an optimum timing at which the output voltage of the final stage CMOS inverter should be raised, and the output voltage of the final stage CMOS inverter can be raised at that timing.

  The semiconductor integrated circuit according to the present invention can improve the data transfer rate from the semiconductor memory circuit to the logic circuit.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit according to the first embodiment of the present invention.

  The semiconductor integrated circuit is a so-called SIP (System In Package) semiconductor integrated circuit including a DRAM array 10 that stores data and a logic circuit 70 such as an ASIC that exchanges data with the DRAM array 10. is there.

  Here, the semiconductor integrated circuit includes an output data control circuit 20 that reads and outputs data from the DRAM array 10, an interface circuit 30, a final stage CMOS inverter 40, an N-channel MOS transistor 50, a voltage generation circuit 61, 62.

  The output data control circuit 20 reads data RDi from the DRAM array 10 and outputs data DOBi in synchronization with a predetermined clock DCK.

  The interface circuit 30 is supplied with the power supply voltage VDD generated by the voltage generation circuit 61 and outputs data DOBi supplied from the output data control circuit 20. Here, the interface circuit 30 has two CMOS inverters 31 and 32 in this embodiment. The number of CMOS inverters is not particularly limited as long as it is an even number.

  The CMOS inverter 31 includes a P-channel MOS transistor 31p and an N-channel MOS transistor 31n. The input terminal of the CMOS inverter 31 is connected to the output terminal of the output data control circuit 20, and the output terminal of the CMOS inverter 31 is connected to the input terminal of the CMOS inverter 32.

  The CMOS inverter 32 is provided in the subsequent stage of the CMOS inverter 31, and is composed of a P-channel MOS transistor 32p and an N-channel MOS transistor 32n. The output terminal of the CMOS inverter is connected to the input terminal of the final stage CMOS inverter 40.

  The power supply voltage VDD generated by the voltage generating circuit 61 is supplied to the sources of the P-channel MOS transistors 31p and 32p. The power supply voltage VDD is a power supply voltage mainly used on the DRAM side and is, for example, 1.8V. The sources of the N channel type MOS transistors 31n and 31p are grounded.

  The final stage CMOS inverter 40 includes a P-channel MOS transistor 40p and an N-channel MOS transistor 40n. The power supply voltage VDDQ generated by the voltage generation circuit 62 is supplied to the source of the P-channel MOS transistor 40p. Here, the power supply voltage VDDQ is a power supply voltage mainly used in the logic circuit 70, and is 1.2 V, for example. For this reason, the power supply voltage VDDQ can be set lower than the power supply voltage VDD.

  The power supply voltage VDDQ generated by the voltage generation circuit 62 is supplied to the source of the N-channel MOS transistor 50. The gate of the N-channel MOS transistor 50 is connected to the input terminal of the CMOS inverter 32 (the gates of the P-channel MOS transistor 32p and the N-channel MOS transistor 32n). The source of the N channel type MOS transistor 50 is connected to the output terminal of the final stage CMOS inverter 40.

  The semiconductor integrated circuit configured as described above operates as follows.

  When the output data control circuit 20 outputs high level data DOBi, the output of the CMOS inverter 31 is low level and the output of the CMOS inverter 32 is high level. Therefore, the output of the final stage CMOS inverter 40 is at a low level.

  Next, when the output data control circuit 20 outputs the data DOBi switched from the high level to the low level, the output of the CMOS inverter 31 becomes the high level and the output of the CMOS inverter 32 becomes the low level. Therefore, the output of the final stage CMOS inverter 40 should immediately become a high level.

  However, since the potential difference between the source and gate of the P-channel MOS transistor 40p is not so large, the P-channel MOS transistor 40p does not turn on immediately, and the output of the final stage CMOS inverter 40 does not immediately become high level.

  However, at this time, since the high-level voltage that is the output of the CMOS inverter 31 is supplied to the gate of the N-channel MOS transistor 50, the N-channel MOS transistor 50 is turned on. Therefore, the output of the final stage CMOS inverter 40 is raised by the N-channel MOS transistor 50 and becomes high level.

  FIG. 2 is a timing chart of data Qi that is the output voltage of the final stage CMOS inverter 40. Conventionally, when the N-channel MOS transistor 50 does not exist, the data Qi output from the final stage CMOS inverter 40 does not rise immediately but becomes a dotted line.

  On the other hand, in the semiconductor integrated circuit, since the N-channel MOS transistor 50 is turned on to raise the output voltage of the final stage CMOS inverter 40, the data Qi rises with a large slope. After a while, the P-channel type MOS transistor 40p of the final stage CMOS inverter 40 is turned on, so that the data Qi rises with a slightly smaller slope. As a result, the data Qi rises faster than before.

  As described above, in the semiconductor integrated circuit according to the first embodiment, the power supply voltage VDDQ lower than the normal power supply voltage VDD is supplied to the final stage CMOS inverter 40, and the output voltage of the final stage CMOS inverter 40 immediately increases. Even if there is not, the output voltage of the final stage CMOS inverter 40 can be raised by turning on the N-channel MOS transistor 50. Thereby, the semiconductor integrated circuit can improve the data transfer rate from the DRAM array 10 to the logic circuit 70 as compared with the conventional semiconductor integrated circuit.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. The same circuits as those in the first embodiment are denoted by the same reference numerals, and different points will be mainly described.

  FIG. 3 is a diagram illustrating a configuration of a semiconductor integrated circuit according to the second embodiment. The semiconductor integrated circuit includes a data path circuit 80 in addition to the first configuration.

  The data path circuit 80 is composed of a plurality of CMOS inverters 81, 82, 83. The input terminal of the CMOS inverter 81 is connected to the output terminal of the output data control circuit 20. The output terminal of the CMOS inverter 81 is connected to the input terminal of the CMOS inverter 82. The output terminal of the CMOS inverter 82 is connected to the input terminal of the CMOS inverter 83. The output terminal of the CMOS inverter 83 is connected to the gate of the N-channel MOS transistor 50.

  Here, the number of CMOS inverters constituting the data path circuit 80 is the same as the number of CMOS inverters constituting the interface circuit 30 and the final stage CMOS inverter 40.

  Therefore, a delay time until the data DOBi input to the interface circuit 30 is output from the final stage CMOS inverter 40 and a delay until the data DOBi input to the data path circuit 80 is output from the data path circuit 80. The time will be the same. That is, the data appearing at the gate and source of the N-channel MOS transistor 50 are synchronized.

  As a result, the ON / OFF timing time of the N-channel MOS transistor 50 matches the driving speed of the final stage CMOS inverter 40. That is, the N-channel MOS transistor 50 is turned on in synchronization with the timing at which the output voltage of the final stage CMOS inverter 40 is raised, so that the data Qi can be raised at the optimum timing at which the data Qi should be raised. .

  As described above, the semiconductor integrated circuit according to the second embodiment has the gate of the N-channel MOS transistor 50 via the data path circuit 80 even when the number of CMOS inverters constituting the interface circuit 30 is large. Is supplied with a predetermined voltage (data DOi). As a result, the semiconductor integrated circuit can start up the data Qi at an optimal timing at which the data Qi should be started up.

  Note that the present invention is not limited to the above-described embodiment, and it is needless to say that the present invention can also be applied to a design modified within the scope of the claims.

1 is a diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. 4 is a timing chart of data Qi that is an output voltage of the final stage CMOS inverter 40. It is a figure which shows the structure of the semiconductor integrated circuit which concerns on 2nd Embodiment.

Explanation of symbols

10 DRAM array 20 Output data control circuit 30 Interface circuit 40 Final stage CMOS inverter 50 N-channel MOS transistors 61 and 62 Voltage generation circuit 70 Logic circuit 80 Data path circuit

Claims (2)

A semiconductor memory circuit for storing data;
An output data control circuit for outputting data read from the semiconductor recording circuit based on a predetermined clock;
A first power supply voltage generating circuit for generating a first power supply voltage;
A second power supply voltage generating circuit for generating a second power supply voltage lower than the first power supply voltage;
An even multiple of CMOS inverters in which an output terminal of one CMOS inverter and an input terminal of another CMOS inverter are sequentially connected, and the first power supply voltage generated by the first power supply voltage generation circuit is An interface circuit that is supplied to the drain of the P-channel MOS transistor of the CMOS inverter and outputs data supplied from the output data control circuit;
A final-stage CMOS inverter having an input terminal connected to the output terminal of the interface circuit and the second power supply voltage generated by the second power supply voltage generation circuit being supplied to the drain of a P-channel MOS transistor;
A logic circuit to which data output from the output terminal of the final stage CMOS inverter is supplied;
The second power supply voltage generated by the second power supply voltage generation circuit is supplied to the drain, the gate is connected to the input terminal of the even-numbered CMOS inverter of the interface circuit, and the output terminal of the final-stage CMOS inverter is connected. An output side N-channel MOS transistor to which a source is connected;
A semiconductor integrated circuit. A semiconductor memory circuit for storing data;
An output data control circuit for outputting data read from the semiconductor recording circuit based on a predetermined clock;
A first power supply voltage generating circuit for generating a first power supply voltage;
A second power supply voltage generating circuit for generating a second power supply voltage lower than the first power supply voltage;
There are 2n (n: natural number) CMOS inverters in which an output terminal of one CMOS inverter and an input terminal of another CMOS inverter are sequentially connected, and the first power supply voltage generating circuit generates the first An interface circuit that supplies power supply voltage to the drain of the P-channel MOS transistor of each CMOS inverter and outputs data supplied from the output data control circuit;
A final-stage CMOS inverter having an input terminal connected to the output terminal of the interface circuit and the second power supply voltage generated by the second power supply voltage generation circuit being supplied to the drain of a P-channel MOS transistor;
A logic circuit to which data output from the output terminal of the final stage CMOS inverter is supplied;
There are (2n + 1) (n: natural number) CMOS inverters in which the output terminal of one CMOS inverter and the input terminal of another CMOS inverter are sequentially connected, and the first power supply voltage generating circuit generates 1 is supplied to the drain of the P-channel MOS transistor of each CMOS inverter and outputs data supplied from the output data control circuit;
The second power supply voltage generated by the second power supply voltage generation circuit is supplied to the drain, the gate is connected to the output terminal of the data path circuit, and the source is connected to the output terminal of the final stage CMOS inverter. An output side N-channel MOS transistor;
A semiconductor integrated circuit.

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