JP2008299924A - Semiconductor device and inspection method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure of a semiconductor device and inspection method thereof, for efficiently detecting a failure of the semiconductor device by a measurement and management of various kinds of characteristic values of the semiconductor device. <P>SOLUTION: The semiconductor device is provided with: a plurality of capacitors 40 which are arranged in a matrix form in an array area of a semiconductor substrate and have lower electrodes 34, dielectric films 36 and upper electrodes 38 respectively; wirings 76 connected to the lower electrodes 34 of a part of capacitors among the plurality of capacitors 40, which is formed on a part of areas in the array area; wirings 72a connected to the upper electrodes 38 of a part of capacitors; an electrode 78 for measurement electrically connected to the lower electrodes 34 of a part of capacitors through the wirings 76; and an electrode 74a for measurement electrically connected to the upper electrodes 38 of a part of capacitors through the wirings 72a. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and an inspection method thereof, and more particularly, to a semiconductor device having a capacitive element and a manufacturing method thereof.

  A volatile memory such as a dynamic random access memory (DRAM) and a static random access memory (SRAM) is used for a main storage device of a computer. The volatile memory can hold data only during a period when power is supplied, and the stored data is lost when the supply of power is stopped.

  On the other hand, a ferroelectric random access memory (hereinafter referred to as “FeRAM”) using a ferroelectric film as a nonvolatile memory that can be freely rewritten and does not lose data even when power supply is stopped. Is known). In addition to being a non-volatile memory, FeRAM has the advantages of low power consumption and high integration.

  The FeRAM is manufactured by incorporating a process for forming a ferroelectric capacitor having spontaneous polarization into an existing semiconductor device manufacturing process. For this reason, in order to guarantee the reliability of the FeRAM, it is necessary to guarantee items unique to the FeRAM in addition to the guarantee contents in the normal semiconductor process. As guarantee items peculiar to FeRAM, there are a high temperature storage test on a sample sample, a FeRAM characteristic test on all wafers, and a FeRAM function test.

As test measurement in the wafer state performed in the manufacturing process of FeRAM, characteristic test for measuring characteristic values unique to FeRAM, for example, the amount of inversion polarization (Q _SW ) of a ferroelectric capacitor, and the operation and reliability of FeRAM. Test has been performed to measure performance, write and read operations, data retention characteristics, and the like.
JP 2001-085634 A

  In the test measurement of FeRAM, no abnormality is observed in the measurement management (characteristic test) of various characteristic values, but an abnormality may be found in a functional test performed thereafter. In recent years, semiconductor manufacturers have increased the number of business negotiations in which only functional management of various characteristic values is performed and functional tests are performed by customers. For this reason, the abnormality of the semiconductor device cannot be sufficiently detected by the characteristic test, and the abnormality often occurs in the function test or the like in the customer.

  An object of the present invention is to provide a structure of a semiconductor device and an inspection method capable of efficiently detecting an abnormality of the semiconductor device by measuring and managing various characteristic values of the semiconductor device.

  According to one aspect of the present invention, a lower electrode, a dielectric film formed on the lower electrode, and an upper electrode formed on the dielectric film are arranged in a matrix in an array region of a semiconductor substrate. Each of the plurality of capacitors, a first wiring connected to the lower electrode of a part of the capacitors formed in a part of the array region, and the part A second wiring connected to the upper electrode of the capacitor, a first measurement electrode electrically connected to the lower electrode of the partial capacitor via the first wiring, There is provided a semiconductor device having a second measuring electrode electrically connected to the upper electrode of the partial capacitor through two wirings.

  According to another aspect of the present invention, a lower electrode, a dielectric film formed on the lower electrode, and a dielectric film formed on the dielectric film are arranged in a matrix in the array region of the semiconductor substrate. A plurality of capacitors each having an upper electrode, and a first wiring connected to the lower electrode of a part of the plurality of capacitors formed in a part of the array region; A second wiring connected to the upper electrode of the partial capacitor; a first measurement electrode electrically connected to the lower electrode of the partial capacitor via the first wiring; And a second measuring electrode electrically connected to the upper electrode of the partial capacitor through the second wiring, wherein the first measuring electrode And the second measuring electrode By applying a constant measuring voltage, a method of inspecting a semiconductor device for measuring the characteristic value of the portion of the capacitor is provided.

  According to the present invention, in the characteristic test of the semiconductor device, the characteristic value at a specific location in the array region where the measurement element is formed is measured, so that the abnormality of the semiconductor device depending on the specific location in the array region can be efficiently performed. Can be detected. Thereby, the sensitivity for detecting an abnormality of the semiconductor device at the stage of the characteristic test is improved, and the result of the functional test can be forgotten from the result of the characteristic test. Further, even when shipping before a function test, it is possible to suppress frequent occurrences of abnormalities in a function test or the like by a customer. In addition, the result of the characteristic test can be quickly fed back to the manufacturing process, and the quality of the semiconductor device can be improved.

  A semiconductor device and an inspection method thereof according to an embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is a schematic sectional view showing the structure of FeRAM, FIG. 2 is a flowchart showing the inspection method according to the present embodiment, FIG. 3 is a plan view showing the structure of a measuring element in a general semiconductor device, and FIG. FIG. 5 is a schematic cross-sectional view showing the structure of a measuring element in a semiconductor device, FIG. 5 is a diagram showing a result of a characteristic test measured using the measuring element of FIGS. 3 and 4, and FIG. 6 is a wafer on which the measurement of FIG. FIG. 7 is a diagram showing a fail bit map of a chip determined to be defective by the functional test, and FIG. 8 is a plan view showing the structure of the measuring element in the semiconductor device according to the present embodiment. FIG. 9 is a schematic cross-sectional view showing the structure of the measuring element in the semiconductor device according to the present embodiment. FIGS. 10 and 11 are diagrams showing the results of characteristic tests measured using the measuring element of FIGS. is there.

  First, the basic structure of FeRAM will be described with reference to FIG.

  An element isolation region 12 that defines an active region is formed on the silicon substrate 10. A well 14 is formed in the silicon substrate 10 in the active region. A MIS transistor 22 having a gate electrode 16 and source / drain regions 18 and 20 is formed on the surface of the active region.

  An interlayer insulating film 24 is formed on the silicon substrate 10 on which the MIS transistor 22 is formed. Contact plugs 26 and 28 made of tungsten or the like and connected to the source / drain regions 18 and 20 are buried in the interlayer insulating film 24.

  On the interlayer insulating film 24 in which the contact plugs 26 and 28 are embedded, an antioxidant film 30 for preventing the contact plugs 26 and 28 from being oxidized and an adhesion layer 32 made of alumina or the like are formed. On the adhesion layer 32, a lower electrode 34 made of platinum or the like, a ferroelectric film 36 made of a ferroelectric material such as PZT formed on the lower electrode 34, and a ferroelectric film 36 are formed. A ferroelectric capacitor 40 having an upper electrode 38 made of iridium oxide or the like is formed. A protective film 42 is formed on the ferroelectric capacitor 40.

  On the ferroelectric capacitor 40, an interlayer insulating film 44 is formed. The interlayer insulating film 44 includes contact plugs 46 and 48 made of tungsten or the like and connected to the contact plugs 26 and 28, a contact plug 50 made of tungsten or the like and connected to the lower electrode 34, and the upper electrode 38 made of tungsten or the like. The contact plug 52 connected to is embedded.

  On the interlayer insulating film 44 in which the contact plugs 46, 48, 50, 52 are embedded, a wiring layer 54 connected to the source / drain region 18 of the MIS transistor 22 via the contact plugs 26, 46, and the contact plug 28 48 are connected to the source / drain region 20 of the MIS transistor 22 through the contact plug 38 and the upper electrode 38 through the contact plug 38, respectively, and electrically connect the source / drain region 20 and the upper electrode 38. In addition, a wiring layer 58 connected to the lower electrode 34 through the contact plug 34 is formed.

  On the wiring layers 54, 56, and 58, a plurality of wiring layers (not shown) are laminated via an interlayer insulating film (not shown).

  Thus, an FeRAM in which one memory cell is constituted by one MIS transistor 22 and one ferroelectric capacitor 40 is formed.

  Next, the flow from the wafer process to shipment of the semiconductor device will be described with reference to FIG.

In the manufacturing process of the semiconductor device, when the wafer process (step S11) for forming various elements on the semiconductor wafer is completed, the completed semiconductor device is subjected to characteristic tests on various characteristic values in the wafer state (step S12). This characteristic test includes measurement of various characteristic values of the MIS transistor, measurement of contact resistance, and the like. In a semiconductor device having FeRAM, a characteristic value unique to FeRAM, for example, the amount of inversion polarization (Q _SW ) of a ferroelectric capacitor is measured.

  3 and 4 are general measurement elements for performing a FeRAM characteristic test in step S12. 3 and 4 includes only the FeRAM ferroelectric capacitors 40 shown in FIG. 1 arranged in a matrix and connected in parallel.

  As shown in FIGS. 3 and 4, a plurality of lower electrodes 34 extending in the y direction are provided adjacent to each other in the x direction. On each lower electrode 34, a plurality of upper electrodes 38 are formed via a ferroelectric film. In the measuring element shown in FIG. 3, a plurality of upper electrodes 38 are arranged on each lower electrode 34 so as to form two rows along the y direction.

  A plurality of wiring layers 60 extending in the y direction are provided on the plurality of ferroelectric capacitors 40 thus formed. The wiring layer 60 is formed to extend on the ferroelectric capacitor 40 adjacent in the y direction, and is connected to the upper electrode 38 of the ferroelectric capacitor 40 through the contact plug 52. That is, two wiring layers 60 are provided for each lower electrode 34. The plurality of wiring layers 60 are connected to the wiring layer 62 at one end. A measurement pad 64 is provided at one end of the wiring layer 62.

  A wiring layer 66 is connected to one end of each of the plurality of lower electrodes 34 via a contact plug 50. A measuring pad 68 is provided at one end of the plurality of wiring layers 66.

In the measurement of the polarization inversion amount Q _SW using the measurement device, reverses the polarization direction of a predetermined intensity by applying a driving voltage dielectric capacitor between the measuring pad 64 and the measurement pad 68, when the The amount of polarization reversal _QSW is measured.

  Next, it is determined whether the characteristic value obtained by the characteristic test is within the standard or whether an abnormal tendency is observed with respect to the trend even if the characteristic value is within the standard. If there is a problem with the characteristic value, the production history and device status of the product are investigated, and the cause and effect are judged. If the impact on the product is significant or unknown, stop shipping the product.

  When there is no problem in the characteristic value, or when it is considered that the influence on the product is small even if there is a problem, the next function test (step S13) is performed. In recent business talks, as will be described later, products may be shipped after a characteristic test. In the functional test, tests such as element operation and reliability are performed. In a semiconductor device having FeRAM, measurements relating to writing and reading operations and data retention characteristics of FeRAM are performed.

  The function test of the semiconductor device is performed in the wafer state as in the characteristic test. The FeRAM functional test is performed, for example, by the following procedure. Unlike the above-described characteristic test, the FeRAM functional test is performed using individual FeRAM cells.

  First, the initial function operation is confirmed and sorted into a non-defective product and a defective product (step S31).

  Next, data is written into the ferroelectric capacitor, and an aging process is performed at a temperature of 150 to 250 ° C. (step S32).

  Next, it is tested whether the data written in step S32 can be read (step S33).

  Next, data is written in the opposite direction to the data written in step S33, and a test is performed to determine whether the written data can be read (step S34).

  Next, the non-defective product and the defective product are sorted again (step S35).

  Next, data in a direction opposite to the data written in step S33 is written, and an aging process is performed at a temperature of 150 to 250 ° C. (step S36).

  Next, it is tested whether the data written in step S36 can be read (step S37).

  Next, data in the direction opposite to the data written in step S36 is written, and a test is performed to determine whether the written data can be read (step S38).

  Next, the non-defective product and the defective product are sorted again (step S39).

  Next, it is determined whether the result obtained by the functional test is within the standard or whether an abnormal tendency is observed with respect to the trend even if the result is within the standard. If there is a problem with the function or reliability of the product, the manufacturing history of the product and the state of the device are investigated, and the cause and effect are judged. If the impact on the product is significant or unknown, stop shipping the product.

  Next, the tested wafer is sent to an assembly factory, and non-defective chips are assembled from the wafer into a package or module (step S14).

  Thereafter, the final test of the product is performed (step S15), and the reliability test of the semiconductor device is completed.

  Next, the product that has undergone the warranty test is shipped to the customer (step S16).

  In order to ship to customers, it is necessary to pass a reliability test that guarantees long-term reliability. The contents need to add FeRAM-specific test items in addition to the normal semiconductor device test items. The test is a functional test of the above-described steps S11 to S19.

  In the functional test described above, it is possible to guarantee a period in which data can be retained under a certain defect rate from the time of aging processing and the activation energy. After passing this test, it is determined whether the product can be shipped. Also, when actually shipping a product, it is checked whether there are any abnormalities with respect to various trends, and the reliability of the product is guaranteed before shipping.

  Conventionally, a semiconductor manufacturer performs everything from design to manufacturing and testing and then ships to customers. However, in recent years, there has been an increase in negotiations where customers design and test, and semiconductor manufacturers only manufacture and ship.

  In this case, as shown in FIG. 2, the semiconductor manufacturer measures only various characteristics of the semiconductor device (step S12) and ships in a wafer state (step S17). The customer performs the above-described function test (step S21), package assembly (step S22), and final test (step S23).

  In this type of business negotiation, only the characteristic test on the ferroelectric capacitor is performed, and the subsequent functional test is performed in the wafer state, but the result of the functional test cannot be predicted only by managing the characteristic value. In the inspection at the customer, there was a frequent occurrence of defects.

FIG. 5 is a view showing an example of the in-wafer distribution of the reversal polarization measured using the measuring element shown in FIGS. 3 and 4. The numerical value shown in the figure is the amount of inversion polarization Q _SW (μC / cm ² ) measured by the measuring element formed in the shot corresponding to each position on the wafer.

In the results shown in FIG. 5, the value of the inverted polarization Q _SW measured in each shot on the wafer is substantially uniform in the wafer plane, the variation was small. For this reason, in this characteristic test, all chips pass the inspection as non-defective products.

  FIG. 6 is a diagram illustrating an example of a result of performing the above-described functional test (steps S11 to S19) on the same wafer. In the figure, hatched areas indicate locations where defective cells exist.

As shown in FIG. 6, in the result of the functional test, defective cells are frequently generated in the shot on the upper part of the wafer (the circled area in the figure), whereas in the result of the characteristic test shown in FIG. The reversal polarization amount Q _SW is substantially uniform within the wafer surface, and no decrease in the reversal polarization amount Q _{SW or} the like is observed in the upper portion of the wafer. That is, this result shows that even if no abnormality is observed in the characteristic test of the ferroelectric capacitor, the abnormality may be detected in the functional test.

  Next, the results of investigations made by the inventors of the present invention that an abnormality could not be detected only by the characteristic test of the ferroelectric capacitor will be described.

  FIG. 7 shows the result of confirming which bit in the cell array is defective with respect to a chip that is defective in the functional test by FBM (Fail Bit Map). This FBM is an image diagram of the entire cell array, and a plot is attached to a portion corresponding to a defective bit, and a non-plotted portion is a non-defective bit.

  From the results of FIG. 7, it was found that the defective bits are not uniformly generated from the entire cell array, but the bits in the end region of the cell array are defective.

For example, as shown in FIGS. 3 and 4, the conventional measuring element used for the characteristic test is one in which a plurality of ferroelectric capacitors are connected in parallel so that the total area becomes 2500 μm ² , for example. For this reason, the inversion polarization quantity Q _SW obtained by the measuring element of this structure is the average value of the inversion polarization quantity Q _SW of all the ferroelectric capacitors in the array, and the abnormality of the ferroelectric capacitor at the end of the array is It is buried in the characteristics of other normal ferroelectric capacitors and cannot be detected.

  As described above, the difference between the characteristic test and the functional test occurs because each capacitor characteristic is reflected in the measurement result in the functional test, whereas in the characteristic test, a set of a plurality of capacitors is collected. This is because the result of the body is reflected. In a ferroelectric capacitor, the ferroelectric characteristics may vary greatly depending on where the capacitor is placed in the cell array, so the measurement element is configured so that the characteristic value can be measured for each capacitor placement location on the cell array It is desirable to do.

  FIGS. 8 and 9 are a plan view and a schematic cross-sectional view showing the structure of a measuring element that can detect a defective chip that cannot be detected by the measuring element shown in FIGS. 3 and 4 in a characteristic test.

  The structure of the measuring element shown in FIGS. 8 and 9 is basically the same as the measuring element shown in FIGS. 3 and 4 except for the connection and arrangement of the upper wiring layer.

  As shown in FIGS. 8 and 9, a plurality of lower electrodes 34 extending in the y direction are provided adjacent to each other in the x direction in the array region on the semiconductor substrate. The array region is a region in which elements are formed in a matrix, and is a region in which memory cell array regions and measurement elements (for example, ferroelectric capacitors) are formed in a matrix.

  On each lower electrode 34, a plurality of upper electrodes 38 are formed via a ferroelectric film. In the measurement element shown in FIG. 8, a plurality of upper electrodes 38 are arranged on each lower electrode 34 so as to form two rows along the y direction.

  A wiring layer 72 extending in the x direction is provided on the plurality of ferroelectric capacitors 40 thus formed. The wiring layer 72 includes a wiring layer 72a that is commonly connected to the upper electrodes 38 of the plurality of ferroelectric capacitors 40 that are located at the end of the array region and are adjacent to each other in the x direction. Wiring layers 72b and 72c for commonly connecting upper electrodes 38 of a plurality of adjacent ferroelectric capacitors 40 are included.

  The wiring layers 72 a, 72 b and 72 c are connected to the upper electrode of the ferroelectric capacitor 40 through the contact plug 52. Measurement pads 74a, 74b, and 74c are provided at one ends of the wiring layers 72a, 72b, and 72c, respectively.

  A wiring layer 76 is connected to one end of each of the plurality of lower electrodes 34 via a contact plug 50. A measuring pad 78 is provided at one end of the plurality of wiring layers 76.

  By configuring the measurement element in this manner, the two-terminal element formed between the measurement pad 74a and the measurement pad 78 is a parallel connection body of ferroelectric capacitors located at the end of the array region. Thus, the two-terminal element formed between the measurement pad 74b and the measurement pad 78 or between the measurement pad 74c and the measurement pad 78 is a parallel arrangement of ferroelectric capacitors located in the center of the array region. It becomes a connection body. That is, by arbitrarily selecting the measurement pads 74a to 74c, the characteristic test of the ferroelectric capacitor formed at the end of the array region and the characteristic test of the ferroelectric capacitor formed at the center of the array region Can be performed individually.

FIG. 10 shows a measurement element shown in FIGS. 8 and 9 using a ferroelectric capacitor (measurement pad 74b and measurement pad 78 or measurement pad 74c and measurement pad 78) in the center of the array region. It is a figure which shows an example of distribution in the wafer surface of the measured amount of reverse polarization _QSW . The numerical value shown in the figure is the amount of inversion polarization Q _SW (μC / cm ² ) measured by the measuring element formed in the shot corresponding to each position on the wafer.

In the results shown in FIG. 10, the value of the inverted polarization Q _SW measured in each shot on the wafer is substantially uniform in the wafer plane, the variation was small. For this reason, in this characteristic test, all chips pass the inspection as non-defective products.

FIG. 11 shows the in-wafer distribution of the amount of inversion polarization measured using the ferroelectric capacitors (measurement pad 74a and measurement pad 78) at the end of the array region in the measurement element shown in FIGS. It is a figure which shows an example. The numerical value shown in the figure is the amount of inversion polarization Q _SW (μC / cm ² ) measured by the measuring element formed in the shot corresponding to each position on the wafer.

As shown in FIG. 11, the test result of the ferroelectric capacitor at the end of the array region is generally smaller in the amount of inversion polarization Q _SW than the test result in FIG. large. In particular, three shots of the wafer top for (in the figure, the shot circled), it can be seen that the value of the inverted polarization Q _SW is very small compared to other shot.

That is, the amount of inversion polarization _QSW changes greatly depending on where the ferroelectric capacitor is located in the cell array in the layout. This result corresponds to the result that the bit at the end of the cell array becomes defective in the FBM shown in FIG.

  As described above, by applying the measuring element shown in FIGS. 8 and 9 to the characteristic test of the ferroelectric capacitor, it is possible to detect the abnormality of the semiconductor device at the stage of the characteristic test.

  The measurement element used for the characteristic test is inserted between the chips cut by wafer dicing (scribe lines) in a reduced size cell array, or one chip in one shot is connected by wiring. Or can be arranged for property testing.

  As described above, according to the present embodiment, in the characteristic test of the semiconductor device, the characteristic value at the specific location in the array region where the measurement element is formed is measured. Therefore, the semiconductor device that depends on the specific location in the array region. Can be detected efficiently. Thereby, the sensitivity for detecting an abnormality of the semiconductor device at the stage of the characteristic test is improved, and the result of the functional test can be forgotten from the result of the characteristic test. Further, even when shipping before a function test, it is possible to suppress frequent occurrences of abnormalities in a function test or the like by a customer. In addition, the result of the characteristic test can be quickly fed back to the manufacturing process, and the quality of the semiconductor device can be improved.

  The present invention is not limited to the above embodiment, and various modifications can be made.

  For example, in the above embodiment, as shown in FIG. 8, the measuring element is configured by connecting in parallel one row of ferroelectric capacitors located in the end or center of the array region and adjacent in the x direction. For example, as shown in FIG. 12, a measuring element may be configured by connecting in parallel one row of ferroelectric capacitors located in the end or center of the array region and adjacent in the y direction.

  Alternatively, for example, as shown in FIG. 13, ferroelectric capacitors formed in an arbitrary region in the array region (regions 82 and 84 indicated by dotted lines in the figure) are connected in parallel to connect the measuring element. You may make it comprise.

  It is desirable to select which ferroelectric capacitors in the array region are connected in parallel in consideration of which region is likely to be defective due to the structure of the semiconductor device and the manufacturing process.

  In the above embodiment, the lower electrode of the capacitor arranged in the y direction is a common electrode. However, it may be an individual electrode similarly to the upper electrode. Further, the wiring layer and the measurement pad connected to the lower electrode may be common as described in the above embodiment, or may be provided for each measurement region in the array region.

  Further, in the above embodiment, the area of each ferroelectric capacitor in the array region constituting the measuring element is not particularly described, but the area of all the ferroelectric capacitors may be the same, A ferroelectric capacitor having a different area may be provided in part.

In the above-described embodiment, the case where the characteristic value of the ferroelectric capacitor measured in the characteristic test is the inversion polarization quantity _QSW has been described. However, the characteristic value of the ferroelectric capacitor to which the present invention can be applied is the inversion polarization quantity QSW. It is not limited to _SW . As the characteristic value, for example, a capacitance value or a leakage current can be applied in addition to the inversion polarization amount _QSW .

  In the above embodiment, the example in which the present invention is applied to the measurement element for measuring the characteristics of the FeRAM ferroelectric capacitor has been described. However, the characteristics of the paraelectric capacitor used in other capacitance elements such as DRAMs are described. You may make it apply this invention to the element for a measurement which measures.

  As described above in detail, the features of the present invention are summarized as follows.

(Supplementary note 1) A plurality of lower electrodes, a dielectric film formed on the lower electrode, and an upper electrode formed on the dielectric film, arranged in a matrix in the array region of the semiconductor substrate. Capacitors of
A first wiring connected to the lower electrode of a part of the capacitors formed in a part of the array region among the plurality of capacitors;
A second wiring connected to the upper electrode of the partial capacitor;
A first measurement electrode electrically connected to the lower electrode of the partial capacitor through the first wiring;
And a second measuring electrode electrically connected to the upper electrode of the partial capacitor through the second wiring.

(Appendix 2) In the semiconductor device according to Appendix 1,
The partial region in the array region is a peripheral portion of the array region.

(Supplementary note 3) In the semiconductor device according to supplementary note 1,
The partial region in the array region is a central portion of the array region.

(Appendix 4) In the semiconductor device according to any one of appendices 1 to 3,
The partial capacitor is a plurality of capacitors arranged in a first direction among the plurality of capacitors.

(Appendix 5) In the semiconductor device according to any one of appendices 1 to 4,
The semiconductor device, wherein the lower electrodes of the plurality of capacitors arranged in the second direction are integrally formed by an electrode layer.

(Appendix 6) In the semiconductor device described in Appendix 5,
The semiconductor device, wherein the second direction is parallel to the first direction.

(Appendix 7) In the semiconductor device described in Appendix 5,
The semiconductor device is characterized in that the second direction is a direction crossing the first direction.

(Appendix 8) In the semiconductor device according to Appendix 1,
A third wiring connected to the lower electrode of another partial capacitor formed in another partial region in the array region among the plurality of capacitors;
A fourth wiring connected to the upper electrode of the other part of the capacitors;
A third measuring electrode electrically connected to the lower electrode of the other part of the capacitor via the third wiring;
And a fourth measuring electrode electrically connected to the upper electrode of the other part of the capacitor via the fourth wiring.

(Supplementary note 9) In the semiconductor device according to supplementary note 8,
The partial area in the array area is a peripheral edge of the array area,
The other partial region in the array region is a central portion of the array region. A semiconductor device, wherein:

(Supplementary note 10) In the semiconductor device according to supplementary note 8 or 9,
The first measurement electrode and the third measurement electrode are common electrodes,
The semiconductor device, wherein the first wiring and the third wiring are common wiring.

(Appendix 11) In the semiconductor device according to any one of appendices 1 to 10,
The plurality of capacitors are ferroelectric capacitors. A semiconductor device, wherein:

(Supplementary Note 12) A plurality of lower electrodes, a dielectric film formed on the lower electrode, and an upper electrode formed on the dielectric film, which are arranged in a matrix in the array region of the semiconductor substrate. A capacitor, a first wiring connected to the lower electrode of a part of the capacitors formed in a part of the array region, and the upper part of the part of the capacitors A second wiring connected to the electrode, a first measurement electrode electrically connected to the lower electrode of the partial capacitor via the first wiring, and the second wiring. A second measuring electrode electrically connected to the upper electrode of the part of the capacitors,
Inspecting a semiconductor device, wherein a characteristic value of the partial capacitor is measured by applying a predetermined measurement voltage between the first measurement electrode and the second measurement electrode Method.

(Additional remark 13) In the inspection method of the semiconductor device of Additional remark 12,
The semiconductor device includes: a third wiring connected to the lower electrode of another part of the plurality of capacitors formed in another part of the array region; and the other wiring A fourth wiring connected to the upper electrode of a part of the capacitors, and a third measuring electrode electrically connected to the lower electrode of the other part of the capacitor via the third wiring And a fourth measurement electrode electrically connected to the upper electrode of the other part of the capacitor through the fourth wiring,
By applying a predetermined measurement voltage between the first measurement electrode and the second measurement electrode, the partial capacitors formed in the partial region in the array region Measure the characteristic value,
By applying a predetermined measurement voltage between the third measurement electrode and the fourth measurement electrode, the other one formed in the other partial region in the array region. A method for inspecting a semiconductor device, comprising: measuring a characteristic value of a capacitor in a part.

(Additional remark 14) In the inspection method of the semiconductor device according to additional remark 13,
The partial area in the array area is a peripheral edge of the array area,
The method of inspecting a semiconductor device, wherein the other partial area in the array area is a central portion of the array area.

(Supplementary Note 15) In the semiconductor device inspection method according to any one of supplementary notes 12 to 14,
The plurality of capacitors are ferroelectric capacitors;
The characteristic value of the capacitor is the amount of inversion polarization of the ferroelectric capacitor.

It is a schematic sectional drawing which shows the structure of FeRAM. It is a flowchart which shows the inspection method by one Embodiment of this invention. It is a top view which shows the structure of the element for a measurement in a common semiconductor device. It is a schematic sectional drawing which shows the structure of the element for a measurement in a common semiconductor device. It is a figure which shows the result of the characteristic test measured using the element for a measurement shown in FIG.3 and FIG.4. It is a figure which shows the result of having performed the function test about the wafer which performed the measurement of FIG. It is a figure which shows the fail bit map of the chip | tip determined as the defect by a functional test. It is a top view which shows the structure of the element for a measurement in the semiconductor device by one Embodiment of this invention. It is a schematic sectional drawing which shows the structure of the element for a measurement in the semiconductor device by one Embodiment of this invention. FIG. 10 is a diagram (part 1) illustrating a result of a characteristic test measured using the measurement element illustrated in FIGS. 8 and 9; FIG. 10 is a diagram (part 2) illustrating a result of a characteristic test measured using the measurement element illustrated in FIGS. 8 and 9. It is a top view which shows the structure of the element for a measurement in the semiconductor device by the 1st modification of embodiment of this invention. It is a top view which shows the structure of the element for a measurement in the semiconductor device by the 2nd modification of embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Silicon substrate 12 ... Element isolation film 14 ... Well 16 ... Gate electrode 18, 20 ... Source / drain region 22 ... MIS transistor 24, 44 ... Interlayer insulating film 26, 28, 46, 48, 50, 52 ... Contact plug 30 ... Antioxidation film 32 ... Adhesion layer 34 ... Lower electrode 36 ... Ferroelectric film 38 ... Upper electrode 40 ... Ferroelectric capacitor 42 ... Protective films 54, 56, 58, 60, 62, 66, 72, 76 ... Wiring layer 64, 68, 74, 78 ... measuring pads 82, 84 ... area

Claims (6)

A plurality of capacitors disposed in a matrix in the array region of the semiconductor substrate, each having a lower electrode, a dielectric film formed on the lower electrode, and an upper electrode formed on the dielectric film;
A first wiring connected to the lower electrode of a part of the capacitors formed in a part of the array region among the plurality of capacitors;
A second wiring connected to the upper electrode of the partial capacitor;
A first measurement electrode electrically connected to the lower electrode of the partial capacitor through the first wiring;
And a second measuring electrode electrically connected to the upper electrode of the partial capacitor through the second wiring. The semiconductor device according to claim 1,
The partial region in the array region is a peripheral portion of the array region. The semiconductor device according to claim 1 or 2,
The partial capacitor is a plurality of capacitors arranged in a first direction among the plurality of capacitors. The semiconductor device according to claim 1,
A third wiring connected to the lower electrode of another partial capacitor formed in another partial region in the array region among the plurality of capacitors;
A fourth wiring connected to the upper electrode of the other part of the capacitors;
A third measuring electrode electrically connected to the lower electrode of the other part of the capacitor via the third wiring;
And a fourth measuring electrode electrically connected to the upper electrode of the other part of the capacitor via the fourth wiring. The semiconductor device according to claim 4.
The partial area in the array area is a peripheral edge of the array area,
The other partial region in the array region is a central portion of the array region. A semiconductor device, wherein: A plurality of capacitors disposed in a matrix in the array region of the semiconductor substrate, each having a lower electrode, a dielectric film formed on the lower electrode, and an upper electrode formed on the dielectric film; Of the plurality of capacitors, a first wiring connected to the lower electrode of a part of the capacitor formed in a part of the array region, and connected to the upper electrode of the part of the capacitor. A second wiring, a first measurement electrode electrically connected to the lower electrode of the capacitor via the first wiring, and the part via the second wiring. And a second measuring electrode electrically connected to the upper electrode of the capacitor of the semiconductor device,
Inspecting a semiconductor device, wherein a characteristic value of the partial capacitor is measured by applying a predetermined measurement voltage between the first measurement electrode and the second measurement electrode Method.

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