JP2008294807A - Charge amplifier circuit and charge amplifier correction method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a charge amplifier circuit and a charge amplifier correction method, wherein storing electric charges in a charging capacitor by a charge injection phenomenon is reliably suppressed and an appropriate amplification signal can be outputted from an amplifier circuit. <P>SOLUTION: The charge amplifier circuit 1 comprises: a charging capacitor 3 for storing electric charges Q that a photoelectrically converting means 11 which receives a light generates in response to an amount of received light; an electric charge resetting switch 4 for discharging the electric charges Q stored from the charging capacitor 3 in response to an electric charge reset signal Sr applied from an electric charge reset signal applying means 5; and an amplifier circuit 2. The charge amplifier circuit 1 further comprises a charge injection correction circuit 6 having: a correcting capacitor 7 having one electrode connected to a terminal "a" at the side of the photoelectrically converting means 11 of the electric charge resetting switch 4; and a correction signal applying means 8 for applying a correction signal Sc in order to generate a voltage Vsc whose polarity (positive and negative) is opposite to that of the electric charge reset signal Sr at another electrode of the correcting capacitor 7. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a charge amplifier circuit and a charge amplifier correction method, and more particularly to a charge amplifier circuit and a charge amplifier correction method for amplifying a weak signal.

  Sensors that receive light emitted from a light-emitting device or light emitted from a sample, convert it into electric charge, and output it, and in photoelectric conversion means such as CCD (Charge Coupled Device), photomultiplier tube, photodiode, etc. In many cases, the output charge is amplified by connecting an amplifier circuit to the output. At that time, a charge amplifier circuit (integration circuit) as shown in FIG. 11 may be used (see, for example, Patent Document 1).

  The charge amplifier circuit 100 basically includes an amplifier circuit 101, also called an operational amplifier, and a charge capacitor 102 that is connected in parallel to the amplifier circuit 101 and accumulates charges generated according to the amount of light received by the photoelectric conversion means 103. Thus, the charge capacitor 102 accumulates charges in the charge capacitor 102 and discharges the accumulated charges from the charge capacitor 102 in accordance with the charge reset signal output from the charge reset signal applying means 105 having a power source. A charge reset switch 104 is connected in parallel.

  In the charge amplifier circuit 100, as shown in the graph of FIG. 12, the charge is accumulated in the charging capacitor 102 at a time point ta when a constant voltage is applied as the charge reset signal Sr from the charge reset signal applying unit 105 to the charge reset switch 104. The charged charge Q is discharged. Subsequently, after the application of the charge reset signal Sr is stopped at time tb and the charge reset switch 104 is turned off, for example, when the photoelectric conversion means 103 senses light reception during the light amount detection period from time tc to td, Meanwhile, the charge Q generated according to the light received by the photoelectric conversion means 103 is accumulated in the charging capacitor 102, and the amplified signal Sa output from the amplifier circuit 101 is increased accordingly.

  When the charge reset signal Sr is applied again at the time te and the charge reset switch 104 is turned on, the charge Q accumulated in the charge capacitor 102 is discharged, and the amplified signal output from the amplifier circuit 101 is discharged. Sa is also zero.

  However, in reality, when the application of the charge reset signal Sr applied to the charge reset switch 104 is stopped and the switch is turned off, the charge accumulated in the parasitic capacitance of the charge reset switch 104 is released. Then, a phenomenon called charge injection that is injected and accumulated in the charging capacitor 102 occurs slightly.

  Specifically, the charge reset switch 104 can be formed in various forms, but the charge reset signal Sr from the charge reset signal applying unit 105 does not flow into the circuit via the charge reset switch 104 in FIG. The terminals a and b of the charge reset switch 104 shown are insulated from the wiring A extending from the charge reset signal applying means 105 to the charge reset switch 104. Therefore, parasitic capacitance is generated between the wiring A and the terminal a and between the wiring A and the terminal b. In addition, when the charge reset switch 104 is turned off, both terminals a and b of the switch are insulated and a parasitic capacitance is generated.

  In this state, when the charge reset signal Sr is applied from the charge reset signal applying means 105 to the charge reset switch 104 and the switch is turned on, both terminals of the charge reset switch 104 are schematically shown in FIG. A and b are short-circuited to have the same potential, and are positive on the wiring A side according to the voltage of the charge reset signal and the parasitic capacitances between the wiring A and the terminal a and between the wiring A and the terminal b. Negative charges are accumulated in the terminals a and b of the charge reset switch 104, respectively. 13 and 14 shown below, a case where a positive voltage is applied as the charge reset signal is shown. In FIG. 13, between the wiring A and the terminal a and between the wiring A and the terminal b. Each parasitic capacitance is shown as a capacitor.

  In this state, when the application of the charge reset signal Sr from the charge reset signal applying unit 105 to the charge reset switch 104 is stopped and the switch is turned off, the charge reset signal Sr from the charge reset signal applying unit 105 It takes a certain amount of time after the application is stopped until the charge reset switch 4 is actually turned off.

  The phenomenon occurring during this time will be described with time. When the application of the charge reset signal Sr from the charge reset signal applying unit 105 is stopped, each between the wiring A and the terminal a and between the wiring A and the terminal b. With the parasitic capacitances remaining, the short circuit between the terminals a and b is solved and an equivalent resistance value is generated between the terminals a and b, which gradually increases as time elapses. Then, the negative charges accumulated in the terminals a and b are changed according to the parasitic capacitance between the wiring A and the terminal a and between the wiring A and the terminal b and the equivalent resistance value between the both terminals a and b. Side and terminal b side respectively.

  When the charge reset switch 104 is turned off, the positive charge accumulated on the wiring A side is released to the charge reset signal applying unit 105, and the negative charge moved to the terminal b side of the charge reset switch 104. Is absorbed by the amplifier circuit 101, but the negative charge moved to the terminal a side is isolated and loses its place of travel, and moves to the charging capacitor 102 as schematically shown in FIG. As a result, the same amount of positive charge is accumulated on the opposite electrode of the charging capacitor 102.

  When the charge injection phenomenon occurs in this way, as shown in FIG. 15, at the moment when the application of the charge reset signal Sr is stopped and the charge reset switch 104 is turned off at time tb, the charge capacitor 102 Charge Qi is slightly accumulated, and an amplification signal Sai is output from the amplification circuit 101 accordingly. Hereinafter, the amplified signal Sai derived from this charge injection phenomenon is referred to as an offset signal Sai.

  The charge accumulation Qi due to this charge injection phenomenon is very small, and is generated in the photoelectric conversion means 103 and is generated in the charging capacitor 102 as in the case of monitoring the light emission intensity of the backlight of the liquid crystal panel described in Patent Document 1. When the flowing charge Q is relatively very large compared to the charge Qi accumulated in the charging capacitor 102 due to the charge injection phenomenon, there is often no problem.

  However, when the photoelectric conversion means 103 detects weak light, as shown in FIG. 16, the charge flowing from the photoelectric conversion means 103 into the charging capacitor 102 and the charge accumulated in the charging capacitor 102 due to the charge injection phenomenon. The relative size is about the same, or the latter is larger than the former. Then, the offset signal Sai derived from the charge injection phenomenon is also greatly amplified by an amplification factor that is set large in order to greatly amplify the weak light.

  For this reason, the dynamic range of light amount detection by the photoelectric conversion means 103 is narrowed by the amount of the greatly amplified offset signal Sai. Further, unlike the case of detecting the large amount of light, the amplified signal Sa output from the amplifier circuit 101 includes the large offset signal Sai. Therefore, the amplified signal Sa output from the amplifier circuit 101 is directly used as the photoelectric conversion unit 103. This causes a problem that it cannot be handled as a signal corresponding to the detected light quantity.

Therefore, in Patent Document 2, the pin side opposite to the pin of the amplifier circuit 101 connected to the photoelectric conversion means 103, that is, the opposite side to the minus pin of the amplifier circuit 101 connected to the photoelectric conversion means 103 in FIG. Similarly to the minus pin side, a charge capacitor and a charge reset switch are provided on the plus pin side of the, thereby generating an offset signal having a reverse polarity, thereby offsetting the offset signal Sai from the charge injection phenomenon, or It has been proposed to reduce.
JP 2007-80572 A JP 2002-57840 A

  According to the charge amplifier circuit described in Patent Document 2, the offset signals input from the plus pin and the minus pin of the amplifier circuit 101 cancel each other, and the offset signal Sai output from the amplifier circuit 101 is reduced. There is.

  However, there are variations in the product of the electrostatic capacitance of the charging capacitor, the parasitic capacitance of the charge reset switch, etc., and there are many error factors. Therefore, the positive and negative offset signals do not necessarily cancel out sufficiently, and a certain amount is obtained from the amplifier circuit 101. May be output.

  In such a case, the amplified signal Sa output from the amplifier circuit 101 also includes a certain amount of offset signal Sai, so that the amplified signal Sa output from the amplifier circuit 101 directly corresponds to the amount of light detected by the photoelectric conversion means 103. The problem remains that it cannot be handled as a signal.

  The present invention has been made in view of the above-described problems, and it is possible to reliably suppress the accumulation of charges in the charging capacitor due to the charge injection phenomenon and to output an appropriate amplified signal from the amplifier circuit. An object is to provide a charge amplifier circuit and a charge amplifier correction method.

In order to solve the above problem, the invention according to claim 1
A charge capacitor that accumulates the charge generated by the received photoelectric conversion means according to the amount of received light, and a charge that discharges the charge accumulated from the charge capacitor according to the charge reset signal applied from the charge reset signal applying means In a charge amplifier circuit including a reset switch and an amplifier circuit,
A correction capacitor having one electrode connected to a terminal on the photoelectric conversion means side of the charge reset switch, and a voltage having a polarity opposite to that of the charge reset signal is generated on the other electrode of the correction capacitor. A charge injection correction circuit having correction signal applying means for applying a correction signal is provided.

  According to a second aspect of the present invention, in the charge amplifier circuit according to the first aspect, the capacitance of the correction capacitor and the voltage applied between both electrodes of the correction capacitor upon application of the correction signal are: The absolute value of the product is set to be equal to the absolute value of the product of the parasitic capacitance of the charge reset switch and the voltage applied as the charge reset signal.

  According to a third aspect of the present invention, in the charge amplifier circuit according to the second aspect, the voltage applied between the two electrodes of the correction capacitor by the application of the correction signal is a constant voltage, and the electrostatic capacitance of the correction capacitor is The capacity is adjusted.

  According to a fourth aspect of the present invention, in the charge amplifier circuit according to the second aspect, a capacitance of the correction capacitor is fixed, and a voltage applied between both electrodes of the correction capacitor due to the application of the correction signal. It is characterized by being adjusted.

  According to a fifth aspect of the present invention, in the charge amplifier circuit according to any one of the first to fourth aspects, the correction signal is applied to the correction capacitor from the charge reset signal applying unit. It is started after the charge reset signal is applied to the charge reset switch.

According to a sixth aspect of the present invention, in the charge amplifier circuit according to the fifth aspect,
Control means for controlling the operation of the correction signal applying means,
A delay circuit is provided between the control means and the correction signal applying means;
A signal that instructs the correction signal applying unit to apply the correction signal to the correction capacitor simultaneously from the control unit when the charge reset signal is applied from the charge reset signal applying unit to the charge reset switch. And the delay circuit delays the start of application of the correction signal from the correction signal application unit to the correction capacitor by reaching the correction signal application unit. Features.

  According to a seventh aspect of the present invention, in the charge amplifier circuit according to any one of the first to sixth aspects, the correction signal is applied to the correction capacitor from the charge reset signal applying unit. It is stopped after application of the charge reset signal to the charge reset switch is stopped.

The invention according to claim 8 is the charge amplifier circuit according to claim 7,
Control means for controlling the operation of the correction signal applying means,
A delay circuit is provided between the control means and the correction signal applying means;
When the application of the charge reset signal from the charge reset signal applying means to the charge reset switch is stopped, the correction signal is applied from the control means to the correction signal applying means to the correction capacitor. A stop instruction signal is output, and the delay circuit delays the signal to reach the correction signal application unit, thereby stopping the application of the correction signal from the correction signal application unit to the correction capacitor. It is delayed.

The invention according to claim 9 is the charge amplifier circuit according to claim 7 or 8, wherein
A sampling means for removing an error by correlated double sampling from the amplified signal output from the amplifier circuit and outputting an appropriate value,
The sampling means performs optimization of the amplified signal by the correlated double sampling after application of the correction signal to the correction capacitor is stopped.

  According to a tenth aspect of the present invention, in the charge amplifier circuit according to any one of the first to ninth aspects, the photoelectric conversion means is a photodiode.

  The invention according to claim 11 is the charge amplifier circuit according to any one of claims 1 to 10, wherein the charge amplifier circuit amplifies a signal when the stimulated light is read by the photoelectric conversion means of the radiation image reading apparatus. It is used.

The invention according to claim 12
A charge capacitor that accumulates the charge generated by the received photoelectric conversion means according to the amount of received light, and a charge that discharges the charge accumulated from the charge capacitor according to the charge reset signal applied from the charge reset signal applying means In a charge amplifier correction method in a charge amplifier circuit including a reset switch and an amplifier circuit,
With respect to a correction capacitor having one electrode connected to a terminal on the photoelectric conversion means side of the charge reset switch, the charge reset signal and the charge reset signal from the correction signal applying means connected to the other electrode of the correction capacitor A correction signal is applied in order to generate a voltage having opposite polarity.

  A charge amplifier correction method according to a twelfth aspect of the present invention is the charge amplifier correction method according to the twelfth aspect, wherein the capacitance of the correction capacitor and the voltage applied between both electrodes of the correction capacitor upon application of the correction signal. The absolute value of the product is set to be equal to the absolute value of the product of the parasitic capacitance of the charge reset switch and the voltage applied as the charge reset signal.

  According to a fourteenth aspect of the present invention, in the charge amplifier correction method according to the thirteenth aspect, a voltage applied between both electrodes of the correction capacitor by applying the correction signal is set to a constant voltage, and the correction capacitor is statically corrected. The electric capacity is adjusted.

  According to a fifteenth aspect of the present invention, in the charge amplifier correction method according to the thirteenth aspect, the capacitance of the correction capacitor is fixed, and the voltage applied between both electrodes of the correction capacitor when the correction signal is applied. It is characterized by adjusting.

  According to a sixteenth aspect of the present invention, in the charge amplifier correction method according to any one of the twelfth to fifteenth aspects, the charge reset signal is applied from the charge reset signal applying means to the charge reset switch. Thereafter, the application of the correction signal to the correction capacitor is started.

  According to a seventeenth aspect of the present invention, in the charge amplifier correction method according to the sixteenth aspect, the charge reset signal is applied to the charge reset switch from the charge reset signal applying unit and simultaneously to the correction signal applying unit. On the other hand, a signal instructing the application of the correction signal to the correction capacitor is output, the signal is delayed by a delay circuit and reaches the correction signal application means, and the correction signal application means to the correction capacitor. The start of application of the correction signal is delayed.

  The invention according to claim 18 is the charge amplifier correction method according to any one of claims 12 to 17, wherein the charge reset signal is applied from the charge reset signal applying means to the charge reset switch. After the stop, the application of the correction signal to the correction capacitor is stopped.

  According to a nineteenth aspect of the present invention, in the charge amplifier correction method according to the eighteenth aspect, the correction signal is simultaneously applied when the application of the charge reset signal from the charge reset signal applying unit to the charge reset switch is stopped. A signal instructing the application means to stop applying the correction signal to the correction capacitor is output, the signal is delayed by a delay circuit and reaches the correction signal application means, and the correction signal application means Stopping application of the correction signal to the correction capacitor is delayed.

  According to a twentieth aspect of the present invention, in the charge amplifier correction method according to the eighteenth or nineteenth aspect, the amplification output from the amplifier circuit after the application of the correction signal to the correction capacitor is stopped. An error is removed from the signal by correlated double sampling and an appropriate value is output.

  According to the invention described in claim 1 or claim 12, the voltage applied between both electrodes of the correction capacitor by the correction signal applied to the correction capacitor from the correction signal applying means of the charge injection correction circuit is changed to the charge reset switch. Since the charge reset signal applied to the charge reset switch to turn on / off the voltage has a polarity opposite to that of the charge reset signal, the photoelectric conversion means side of the charge reset switch portion is derived from the parasitic capacitance of the charge reset switch. The charge-injection correction circuit of the charge-injection correction circuit discharges positive and negative charges from the charge-injection phenomenon caused by the charge-injection phenomenon that occurs when the charge-reset switch is turned off. Can be offset. For this reason, it is possible to reliably suppress the accumulation of charges in the charging capacitor due to the charge injection phenomenon.

  Further, by appropriately adjusting the amount of charge discharged from the correction capacitor, the charge accumulation in the charge capacitor can be made almost zero, so that the offset signal caused by the charge accumulation can be effectively suppressed and substantially reduced. It can be set to zero.

  Therefore, it is possible to output an appropriate amplified signal from the amplifier circuit, and as shown in FIG. 16 for the conventional charge amplifier circuit, the dynamic range of light amount detection by the photoelectric conversion means using the greatly amplified offset signal Sai. It is possible to effectively prevent the occurrence of a situation where the signal is narrowed, and to appropriately acquire an amplified signal under a large dynamic range.

  According to the second or thirteenth aspect of the present invention, the product of the capacitance of the correction capacitor and the voltage applied between both electrodes of the correction capacitor upon application of the correction signal, that is, is stored in the correction capacitor. Charge reset by setting the absolute value of the charge to be equal to the product of the parasitic capacitance of the charge reset switch and the voltage applied as the charge reset signal, that is, the absolute value of the charge generated in the charge reset switch part The charge generated in the switch part can be accurately canceled by the charge stored in the correction capacitor, and the effect of the invention according to claim 1 or claim 12 can be exhibited very effectively. It becomes.

  According to the invention described in claim 3, 4, 14, or 15, in addition to the effect of the invention described in each of the above claims, the correction signal is applied between both electrodes of the correction capacitor. By fixing one of the voltage and the capacitance of the correction capacitor and adjusting the other, the charge generated in the charge reset switch and the charge accumulated in the correction capacitor are opposite in polarity, and their absolute values are equal. It becomes possible to adjust as easily.

  According to the fifth or sixteenth aspect of the invention, when the charge reset switch is in the OFF state, the charge injection correction circuit side of the charge reset switch is an isolated system. When the correction signal is started to be applied and charge is accumulated in the correction capacitor, the amount of charge accumulated in the charge capacitor is affected, and the amplified signal output from the amplifier circuit is adversely affected.

  Therefore, as in the invention described in claim 5 or claim 16, the charge reset signal is applied from the charge reset signal applying means to the charge reset switch, and the charge reset switch is turned on and stored in the charge capacitor. After the generated charge is discharged, by starting application of the correction signal to the correction capacitor, the charge is accumulated in the correction capacitor without affecting the amplified signal output from the amplifier circuit. The effects of the invention described in each claim can be exhibited accurately, and the reliability of the amplified signal output from the amplifier circuit can be improved.

  According to the invention described in claim 6 or claim 17, a delay circuit is provided between the control means for controlling the operation of the correction signal applying means and the correction signal applying means so that the charge reset signal applying means can be used for charge resetting. 6. A signal for instructing application of a correction signal to a correction capacitor, which is output simultaneously with the application of a charge reset signal to the switch, is delayed by a delay circuit to reach the correction signal applying means. It becomes possible to implement | achieve the invention of Claim 16 exactly, and it becomes possible to show | play the effect similar to those inventions.

  According to the invention described in claim 7 or claim 18, since it takes some time from the stop of application of the charge reset signal until the charge reset switch 4 is actually turned off, the charge to the charge reset switch, for example, If the stop of the application of the reset signal and the stop of the application of the correction signal to the correction capacitor are performed at the same time, the charge generated in the charge reset switch part remains there, and the charge released from the correction capacitor is reduced. Part of the charge reset switch part is not completely off, so that the charge generated in the charge reset switch part is not sufficiently canceled out, and the charge that has not been canceled is transferred to the charge capacitor. It will flow in.

  Therefore, as in the invention described in claim 7 or claim 18, by stopping application of the correction signal to the correction capacitor after stopping application of the charge reset signal to the charge reset switch, Since the switch is turned off, the charge flowing into the charge capacitor from the charge reset switch portion and the charge released from the correction capacitor are accurately offset, so that the effects of the respective inventions can be exhibited more accurately. It becomes possible to make it.

  According to the invention described in claim 8 or claim 19, similarly to the invention described in claim 6 or claim 17, a delay circuit is provided between the control means and the correction signal applying means, and the charge reset signal is provided. A signal for instructing the stop of the application of the correction signal to the correction capacitor that is output at the same time as the application of the charge reset signal from the application unit to the charge reset switch is stopped is delayed to reach the correction signal application unit. Thus, the invention described in claim 7 or claim 18 can be accurately realized, and the same effects as those inventions can be achieved.

  According to the invention of claim 9 or claim 20, in addition to the effects of the above-mentioned inventions, the optimization for removing the error due to the influence of kTC noise or the like generated when the charge reset switch is turned off is performed. In this state, it is possible to output an appropriate value of the amplified signal, and it is possible to further improve the reliability of the amplified signal output as the appropriate value.

  According to the invention described in claim 10, by using the photodiode as the photoelectric conversion means, in addition to the effects of the respective inventions, a charge amplifier circuit and a device using the same can be configured at low cost.

  According to the invention of claim 11, the influence of the offset signal derived from the charge injection phenomenon appears particularly large when the photoelectric conversion means detects weak light, but by adopting the configuration of each of the inventions, The offset signal derived from the charge injection phenomenon can be made almost zero, and when the photoelectric conversion means detects weak light, the amplified signal can be properly acquired under the large dynamic range described above. An advantageous effect can be exhibited.

  Therefore, for example, when used for amplification of a signal when reading the stimulated light emitted as weak fluorescence from the stimulable phosphor layer of the radiation image conversion plate by the photoelectric conversion means provided in the radiation image reading apparatus. The effects of the above inventions are particularly effective.

  Embodiments of a charge amplifier circuit and a charge amplifier correction method according to the present invention will be described below with reference to the drawings.

  First, the charge amplifier circuit will be described. As shown in FIG. 1, the charge amplifier circuit 1 according to the present embodiment includes an amplifier circuit 2, a charge capacitor 3, a charge reset switch 4, a charge reset signal applying unit 5, a correction capacitor 7, and a correction. A charge injection correction circuit 6 including a signal applying unit 8, a control unit 9 for controlling operations of the charge reset signal applying unit 5 and the correction signal applying unit 8, and a sampling unit 10 are provided.

  As the amplification circuit 2, a known amplification circuit such as an operational amplifier can be used. In FIG. 1, an amplifier circuit having a normal plus pin (non-inverting input), a minus pin (inverting input), and an output pin is shown. It is also possible to use a special circuit.

  The amplifying circuit 2 is connected in parallel with a charging capacitor 3, and the amplifying circuit 2 and the charging capacitor 3 form an integrating circuit. In the charging capacitor 3, charges generated by the photoelectric conversion means 11 made of a photodiode or the like according to the amount of received light are accumulated.

  The charge capacitor 3 is connected in parallel with a charge reset switch 4 composed of an FET (field effect transistor) or the like. The charge reset switch 4 applies a charge reset signal Sr to the charge reset switch 4. Application means 5 is connected.

  The charge reset signal applying means 5 includes a power source (not shown), and applies a charge reset signal Sr to the charge reset switch 4 to turn on the charge reset switch 4 and turn on the charge capacitor 3 in accordance with the control of the control means 9 described later. The accumulated charge is discharged, and the application of the charge reset signal Sr to the charge reset switch 4 is stopped to turn off the charge reset switch 4 so that the charge capacitor 3 stores the charge.

  An injection correction circuit 6 including a correction capacitor 7 and a correction signal application unit 8 is connected to a terminal a on the photoelectric conversion unit 11 side of the charge reset switch 4. Specifically, one electrode of the correction capacitor 7 of the injection correction circuit 6 is connected to the terminal a on the photoelectric conversion means 11 side of the charge reset switch 4, and the other electrode is connected to the correction signal applying means 8. Has been.

  The correction signal applying means 8 includes a power source (not shown), and the correction signal Sc having a voltage opposite in polarity to the charge reset signal Sr applied by the charge reset signal applying means 5 to the charge reset switch 4 is described later as control means. 9 is applied to the correction capacitor 7 in accordance with the control 9. For example, if the charge reset signal Sr output from the charge reset signal applying unit 5 has a positive voltage, the correction signal Sc having a negative voltage is applied from the correction signal applying unit 8 to the correction capacitor 7.

  Further, in the present embodiment, the charge accumulated in the correction capacitor 7 by applying the correction signal Sc from the correction signal applying means 8 is used for charge reset by applying the charge reset signal Sr by the parasitic capacitance of the charge reset switch 4. From the correction signal applying means 8 and the capacitance of the correction capacitor 7 so that the charge flowing into the charging capacitor 3 due to the charge injection phenomenon described above and the absolute value thereof are equal to each other. The voltage applied between both electrodes of the correction capacitor 7 is set by applying the correction signal Sc applied to the correction capacitor 7.

Specifically, since the charge Q accumulated when the voltage V is applied to the capacitor having the capacitance C is calculated by Q = C · V, the terminal of the charge reset switch 4 as shown in FIG. If the parasitic capacitance generated between a and the wiring A from the charge reset signal applying means 5 to the charge reset switch 4 is expressed as a capacitor, the parasitic capacitance between the terminal a and the wiring A is Ca, and the charge reset signal applying means. When the voltage of the charge reset signal Sr applied from 5 to the charge reset switch 4 is Vsr, between the terminal a of the charge reset switch 4 and the wiring A,
Qa = Ca · Vsr (1)
Is generated.

  As shown in FIG. 2, when the parasitic capacitance between the terminal b of the charge reset switch 4 and the wiring A is Cb, the distance between the terminal b and the wiring A is expressed by Qb = Cb · Vsr. However, since the charge Qb is absorbed by the amplifier circuit 2 when the charge reset switch 4 is turned off as described above, the charge Qb is not related to the occurrence of the charge injection phenomenon.

On the other hand, the capacitance of the correction capacitor 7 of the injection correction circuit 6 is Cc, and the voltage applied between both electrodes of the correction capacitor 7 by the application of the correction signal Sc from the correction signal applying means 8 to the correction capacitor 7 is Vsc. Then, the correction capacitor 7 has
Qc = Cc · Vsc (2)
Is stored.

  In the present embodiment, the charge Qa and the charge Qc are opposite in polarity, and their absolute values are equal to each other, so that the capacitance Cc of the correction capacitor 7 and the electrodes of the correction capacitor 7 are between the two electrodes. The absolute value of the product of the voltage Vsc is equal to the absolute value of the product of the parasitic capacitance Ca between the terminal a of the charge reset switch 4 and the wiring A and the voltage Vsr applied as the charge reset signal Sr. In addition, the capacitance Cc of the correction capacitor 7 and the voltage Vsc of the correction signal Sc are set.

  Here, the voltage Vsc applied between both electrodes of the correction capacitor 7 by the application of the correction signal Sc is from the correction signal applying means 8 to the correction capacitor 7 when the voltage at the minus pin of the amplifier circuit 2 is 0V. Is equal to the voltage of the correction signal Sc applied to. However, when the voltage at the minus pin does not become completely 0V due to the characteristics of the amplifier circuit 2 itself, or when an offset voltage is applied to the plus pin side of the amplifier circuit 2, the voltage at the minus pin side is constant. Is loaded, the sum of the voltage of the minus pin of the amplifier circuit 2 and the voltage of the correction signal Sc becomes the voltage Vsc applied between both electrodes of the correction capacitor 7.

  Therefore, in the present embodiment, the correction capacitor 7 having a fixed capacitance Cc is used, and the voltage value of the correction signal Sc is adjusted in consideration of the voltage of the minus pin of the amplifier circuit 2 and the sum thereof is obtained. The voltage Vsc applied between both electrodes of a certain correction capacitor 7 is appropriately adjusted so that the charge Qa and the charge Qc are controlled to have the same absolute value.

  The voltage Vsc applied between both electrodes of the correction capacitor 7 can be fixed to a constant voltage, and the capacitance Cc of the correction capacitor 7 can be changed and adjusted. The voltage Vsc applied between both electrodes of the correction capacitor 7 and the electrostatic capacitance Cc of the correction capacitor 7 can be both changed and adjusted.

  Further, the value of the parasitic capacitance Ca generated between the terminal a of the charge reset switch 4 and the wiring A from the charge reset signal applying means 5 to the charge reset switch 4 is applied, and the charge reset signal Sr of the predetermined voltage Vsr is applied. In this case, it is also possible to obtain in advance by measuring the charge Qa accumulated. Further, as will be described later, the voltage applied between both electrodes of the correcting capacitor 7 so that the amplified signal Sai due to the charge injection phenomenon outputted from the amplifier circuit 2 becomes 0 at the moment when the charge reset switch 4 is turned off. Vsc, the capacitance Cc of the correction capacitor 7 or both may be varied and adjusted.

  Here, in FIG. 2 and the following description, the expressions “+ Qa”, “−Qa”, “+ Qc”, and “−Qc” are used as the description of charges. These expressions are positive charges and negative charges. It expresses the image of. That is, for example, if Qc itself is a negative value, mathematically -Qc represents a positive charge. However, in this specification and the drawings, a charge represented by adding "+" is a positive charge. It should be understood that a charge expressed with “−” represents a negative charge.

  The control means 9 is composed of a computer in which a CPU, ROM, RAM, input / output interface and the like (not shown) are connected to a bus.

  Hereinafter, the configuration of the charge injection suppression control by the control unit 9 will be described, and the operation of the charge amplifier circuit and the charge amplifier correction method according to the present embodiment will be described. The sampling means 10 will be described in this section.

  In the charge amplifier circuit 1 and the charge amplifier correction method according to the present embodiment, the charge accumulated in the correction capacitor 7 is discharged with respect to the charge flowing into the charge capacitor 3 from the charge reset switch 4 due to the charge injection phenomenon. By canceling out, the accumulation of charges in the charging capacitor 3 due to the charge injection phenomenon is suppressed.

  Specifically, the control unit 9 is connected to the charge reset signal applying unit 5 and the correction signal applying unit 8 and controls application of the charge reset signal Sr from the charge reset signal applying unit 5 to the charge reset switch 4. The charge reset switch 4 is turned on / off, and the correction signal Sc from the correction signal applying means 8 to the correction capacitor 7 is controlled to accumulate and correct the charge Qc in the correction capacitor 7. The discharge of the charge Qc from the capacitor 7 is controlled.

  First, the control means 9 stops the application of the charge reset signal Sr from the charge reset signal application means 5 to the charge reset switch 4 in the normal light quantity detection operation so that the charge reset switch 4 is turned off. It has become. In this case, the control means 9 stops the application of the correction signal Sc from the correction signal applying means 8 to the correction capacitor 7 during this time. That is, no charge is accumulated in the correction capacitor 7.

  When the photoelectric conversion means 11 receives light in this state, charges are generated according to the amount of received light, and the charges are accumulated in the charging capacitor 3. In this way, as shown in FIG. 3, the amount of charge stored in the charging capacitor 3 increases as the photoelectric conversion means 11 receives light. Then, the amplified signal Sa output from the amplifier circuit 2 increases accordingly, and the amount of light received by the photoelectric conversion means 11 is detected.

  The reason why the control means 9 stops the application of the correction signal Sc from the correction signal applying means 8 to the correction capacitor 7 during the light quantity detection period is that the charge reset switch 4 is turned off during the light quantity detection period. Since the photoelectric conversion means 11 side of the charge reset switch 4 is isolated, if the charge is stored in the correction capacitor 7, the charge amount Q stored in the charge capacitor 3 is affected thereby, and the amplifier circuit This is because the amplified signal Sa output from 2 also has an adverse effect.

Next, when the light amount detection period by the photoelectric conversion means 11 ends, the control means 9 applies the charge reset signal Sr from the charge reset signal applying means 5 to the charge reset switch 4 to turn on the switch. ing. As a result, the charge Q accumulated in the charging capacitor 3 is discharged. Therefore, if the switch is turned on at time t _A as shown in FIG. 4, for example, the amplified signal Sa output from the amplifier circuit 2 at that moment becomes zero.

Then, as shown in FIG. 5, the control unit 9, the time t after the charge reset switch 4 to the ON state at _A, the correction at the time t _B after time t _A signal applying means 8 compensation capacitor 7 Then, the correction signal Sc is applied to start the accumulation of the electric charge Qc in the correction capacitor 7. The reason for this control in the present embodiment is the same reason as described above.

  At this time, as shown in FIG. 2, the voltage applied between both electrodes of the correction capacitor 7 by the capacitance Cc of the correction capacitor 7 and the correction signal Sc applied from the correction signal applying means 8 to the correction capacitor 7. As shown in FIG. 2, when the charge reset signal Sr is applied to the charge reset switch 4 to be turned on as shown in FIG. 2, the Vsc is adjusted between the terminal a of the charge reset switch 4 and the wiring A. The charge Qa generated from the generated parasitic capacitance Ca and the charge Qc having the same absolute value but opposite positive and negative are stored in the correction capacitor 7.

In this state, as shown in FIG. 6, at time t _C , the control means 9 controls the charge reset signal applying means 5 to detect the next light quantity so that the charge reset signal Sr is applied to the charge reset switch 4. When the switch is stopped and the switch is turned off, as shown in FIG. 7, the charge of -Qa stored in the terminal a portion of the charge reset switch 4 is released at that moment and moves in the direction of the charge capacitor 3. A charge injection phenomenon occurs.

  Therefore, the control means 9 controls the correction signal applying means 8 after turning off the charge reset switch 4 so as to stop the application of the correction signal Sc from the correction signal applying means 8 to the correction capacitor 7. It has become. When the application of the correction signal Sc is stopped, among the charges accumulated in the correction capacitor 7, the charge of -Qc accumulated in the electrode on the correction signal applying means 8 side of the correction capacitor 7 is applied to the correction signal. The charge of + Qc that has been discharged to the means 8 and accumulated in the electrode on the opposite side of the correction capacitor 7 is discharged to the charge capacitor 3 or charge reset switch 4 side.

  Since the absolute value of the charge of -Qa moving from the charge reset switch 4 side and the charge of + Qc released from the correction capacitor 7 are equal as described above, the charge of -Qa and the charge of + Qc are the same. Are offset. Therefore, it is possible to suppress the charge from being accumulated in the charging capacitor 3 due to the charge injection phenomenon.

  Thus, in the charge amplifier circuit 1 and the charge amplifier correction method according to the present embodiment, the charge Qc is discharged from the correction capacitor 7 of the charge injection correction circuit 6 and flows into the charge capacitor 3 due to the charge injection phenomenon. Is canceled to suppress the accumulation of charges in the charging capacitor 3 and to suppress the offset signal Sai (see FIG. 16 and the like) that has occurred in the conventional charge amplifier circuit 100 due to the charge injection phenomenon. It becomes possible.

If Shimese phenomena or chronologically, as shown in FIG. 8, after the control unit 9 has a charge reset switch 4 off, the time t _D from the correction signal application means 8 to the correction capacitor 7 When the application of the correction signal Sc is stopped, the charge Q accumulated to some extent in the charge capacitor 3 due to the charge injection phenomenon is canceled to 0 at that moment, and the charge Q is accumulated to some extent in the charge capacitor 3. Thus, the amplified signal output from the amplifier circuit 2, that is, the offset signal Sai also becomes zero.

  Here, in the present embodiment, the reason for stopping the application of the correction signal Sc to the correction capacitor 7 after the charge reset switch 4 is turned off is that the charge reset signal applying means 5 applies the charge reset switch 4 to the charge reset switch 4. This is because it takes some time until the charge reset switch 4 is actually turned off after the application of the charge reset signal Sr is stopped.

  That is, for example, when stopping the application of the charge reset signal Sr to the charge reset switch 4 and stopping the application of the correction signal Sc to the correction capacitor 7 are performed simultaneously, the application of the charge reset signal Sr is actually stopped. The equivalent resistance value generated between each of the parasitic capacitances Ca and Cb between the terminal a and the wiring A and between the terminals b and A and the terminals a and b while it takes some time until the charge reset switch 4 is turned off. Accordingly, the charges generated on the terminals a and b side move to the terminal a side and the terminal b side, respectively, and the charge of −Qa remains in the terminal a portion of the charge reset switch 4.

  On the other hand, since it takes some time until the charge reset switch 4 is actually turned off after the application of the charge reset signal Sr is stopped, a part of the + Qc charge released from the correction capacitor 7 is completely turned off. It flows out downstream through the charge reset switch 4 which is not. As a result, the charge reset switch 4 is turned off, and the charge of −Qa flowing from the terminal a due to the charge injection phenomenon flows out of the charge reset switch 4 out of the + Qc charge discharged from the correction capacitor 7. Even if the remaining charges cancel each other, all of them cannot be canceled, and a part of the charge of −Qa that has not been canceled flows into the charging capacitor 3.

  Stopping the application of the correction signal Sc to the correction capacitor 7 after stopping the application of the charge reset signal Sr to the charge reset switch 4 prevents the above-described state from occurring, and the charge reset switch This is because the charge of −Qa flowing into the charging capacitor 3 from the four portions and the charge of + Qc released from the correction capacitor 7 are accurately offset.

At which timing the charge of + Qc is released from the correction capacitor 7, that is, in FIG. 8, the time t _C when the application of the charge reset signal Sr from the charge reset signal applying means 5 to the charge reset switch 4 is stopped The timing at which the interval from the correction signal Sc from the correction signal applying means 8 to the correction capacitor Sc at which the correction signal Sc is stopped is set to the time t _D is actually in the OFF state from the stop of the application of the charge reset signal Sr. Since it depends on the characteristics of the charge reset switch 4 such as the time until it becomes, it is adjusted in advance prior to normal light amount detection by the photoelectric conversion means 11.

  In the present embodiment, after suppressing the flow of charge into the charging capacitor 3 due to the charge injection phenomenon as described above, as shown in FIG. In this manner, on / off of the charge reset switch 4 and application and stop of the correction signal Sc to the correction capacitor 7 are repeated.

  It is well known that thermal noise caused by the equivalent resistivity of the switch, that is, so-called kTC noise occurs immediately after the switch is turned off when the switch is operated. Also in the embodiment, noise is generated when the charge reset switch 4 is switched from the on state to the off state.

  In the present embodiment, as shown in FIG. 8 and FIG. 9, after the charge reset switch 4 is turned off, + Qc charge is released from the correction capacitor 7 and -Qa caused by the charge injection phenomenon is generated. The charge Q is accumulated to some extent in the charging capacitor 3 until the charge is canceled, and an offset signal Sai having a certain strength is generated accordingly.

  Then, the kTC noise is added to the offset signal Sai, and the signal output from the amplifier circuit 2 becomes relatively large. For this reason, even if the charge injection phenomenon effectively cancels the charge due to the discharge of the charge from the correction capacitor 7, a certain value is added to the data of the amount of light acquired by the photoelectric conversion means 11 thereafter. The impact may remain.

  Therefore, in the present embodiment, the sampling unit 10 is provided on the downstream side of the amplifier circuit 2, and the sampling unit 10 removes an error from the amplified signal Sa output from the amplifier circuit 2 by correlated double sampling to further obtain an appropriate value. It is designed to output downstream.

Specifically, as shown in FIG. 10, the application of the correction signal Sc to the correction capacitor 7 is stopped by the control means 9, the application of the correction signal Sc to the correction capacitor 7 is stopped, and the correction capacitor 7 When the normal light amount detection by the photoelectric conversion unit 11 is started after the + Qc charge is released from the sampling unit 10, the sampling unit 10 has two sampling timings T ₁ before and after being set between the start and the end of the light amount detection. , T ₂ records the value of the amplified signal Sa output from the amplifier circuit 2.

The sampling means 10 performs a correlated double sampling calculating a difference obtained by subtracting the value Sa ₁ of the amplified signal Sa recorded at sampling timing T ₁ from the value Sa ₂ of the amplified signal Sa recorded at sampling timing T _2, The difference calculated by correlated double sampling is output to the downstream side as an appropriate value of the amplified signal Sa acquired during the light amount detection period.

As described above, the correlated double sampling is performed by the sampling unit 10 so that an error due to the influence of kTC noise or the like that may be included in the _two values Sa ₁ and Sa ₂ of the amplified signal Sa is removed. Thus, it is possible to output an appropriate value of the amplified signal Sa, and the reliability of the amplified signal Sa output as the appropriate value is further improved.

  As described above, according to the charge amplifier circuit 1 and the charge amplifier correction method according to the present embodiment, correction is performed by applying the correction signal Sc applied from the correction signal applying unit 8 of the charge injection correction circuit 6 to the correction capacitor 7. The voltage applied between both electrodes of the capacitor 7 is a voltage that is opposite in polarity to the charge reset signal Sr applied to the charge reset switch 4 to turn on / off the charge reset switch 4.

  With this configuration, the charge injection phenomenon that occurs due to the parasitic capacitance of the charge reset switch 4 being accumulated in the terminal a portion of the charge reset switch 4 and the charge reset switch 4 being turned off. As a result, the charge flowing into the charging capacitor 3 can be canceled by discharging charges having opposite polarity from the correcting capacitor 7 of the charge injection correcting circuit 6. Therefore, it is possible to reliably suppress the accumulation of electric charges in the charging capacitor 3 due to the charge injection phenomenon.

  Further, by appropriately adjusting the amount of charge discharged from the correction capacitor 7, the charge accumulation in the charge capacitor 3 can be made almost zero, so that the offset signal Sai caused by the charge accumulation is effectively suppressed. And can be almost zero.

  Therefore, it is possible to output an appropriate amplified signal Sa from the amplifier circuit 2, and as shown in FIG. 16 for the conventional charge amplifier circuit 100, the light amount detection by the photoelectric conversion means based on the greatly amplified offset signal Sai. Thus, it is possible to effectively prevent the occurrence of a situation where the dynamic range is narrowed, and to appropriately acquire the amplified signal Sa under a large dynamic range.

  Furthermore, as described above, the influence of the offset signal Sai derived from the charge injection phenomenon is particularly significant when the photoelectric conversion means 11 detects weak light. For this reason, the charge amplifier circuit and the charge amplifier correction method according to the present invention that can make the offset signal Sai derived from the charge injection phenomenon almost zero are, for example, radiation image conversion by photoelectric conversion means provided in the radiation image reading apparatus. This effect is particularly effective when detecting faint light, such as when used to amplify signals when reading the photostimulated light emitted as fluorescence from the photostimulable phosphor layer of the plate.

  In the present embodiment, by shifting the control timing from the control means 9 to the charge reset signal applying means 5 and the correction signal applying means 8, the charge reset switch 4 is turned on and then applied to the correction capacitor 7. A case has been described in which the application of the correction signal Sc is started or the application of the correction signal Sc to the correction capacitor 7 is stopped after the charge reset switch 4 is turned off.

  However, in addition to this, for example, a delay circuit (not shown) including a buffer, an inverter, or the like is provided between the control unit 9 and the correction signal applying unit 8, and the charge from the control unit 9 to the charge reset signal applying unit 5 is charged. It is configured to output a signal instructing on / off of the reset switch 4 and at the same time a signal instructing the correction signal applying means 8 to apply or stop the correction signal Sc to the correction capacitor 7. Is also possible.

  With this configuration, the signal output from the control means 9 to the correction signal applying means 8 is delayed by the delay circuit and arrives, and is delayed by the on / off of the charge reset switch 4 to be corrected by the correction capacitor 7. Application of the correction signal Sc to is started or stopped, and the same effect as in the present embodiment can be obtained.

  In the present embodiment, the case where the positive charge reset signal Sr is output from the charge reset signal applying unit 5 and the negative voltage correction signal Sc is output from the correction signal applying unit 8 has been described. It goes without saying that even if the signal and the correction signal Sc are opposite in polarity, the description can be made in the same manner as in the present embodiment.

It is a figure which shows the structure of the charge amplifier circuit which concerns on this embodiment. It is a figure explaining the electric charge etc. which are produced in the terminal part of an electric charge reset switch, and a capacitor for amendment. It is a graph which shows the state where the amplified signal output from an amplifier circuit increases. It is a graph which shows the state in which the charge reset switch is turned on and the amplified signal becomes zero. 6 is a graph showing a state in which a correction signal is applied to the correction capacitor after the charge reset switch is turned on. It is a graph which shows the state by which the switch for charge reset was made into the OFF state. It is a figure explaining the state from which + Qc electric charge is discharge | released from the capacitor | condenser for correction | amendment with respect to -Qa electric charge derived from a charge injection phenomenon. It is a graph which shows the state from which the charge derived from a charge injection phenomenon is canceled by discharge | release of the electric charge from the capacitor | condenser for correction | amendment, and an offset signal becomes zero. It is a graph which shows the cycle of ON / OFF of a charge reset switch, application of a correction signal to a correction capacitor, stop, and increase / decrease of an amplification signal. It is a graph explaining the correlation double sampling by a sampling means. It is a figure which shows the structure of the conventional charge amplifier circuit. It is a graph which shows the cycle of the detection of the light reception by the photoelectric conversion means in the conventional charge amplifier circuit, application of a charge reset signal, a stop, and increase / decrease of an amplification signal. It is a figure explaining the state in which electric charge is accumulate | stored in a wiring or a terminal part by the parasitic capacitance which the switch for electric charge reset has. It is a figure explaining the charge injection phenomenon in which the electric charge accumulate | stored in the terminal part of the charge reset switch moves to the capacitor for charge. It is a graph which shows the state from which an offset signal is output from an amplifier circuit by a charge injection phenomenon. It is a graph explaining the offset signal greatly amplified when a photoelectric conversion means detects weak light.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Charge amplifier circuit 2 Amplifying circuit 3 Charge capacitor 4 Charge reset switch 5 Charge reset signal application means 6 Charge injection correction circuit 7 Correction capacitor 8 Correction signal application means 9 Control means 10 Sampling means 11 Photoelectric conversion means a For charge reset Terminal Ca on the photoelectric conversion means side of the switch Parasitic capacitance Cc of the charge resetting switch Capacitance Q of the correcting capacitor Q Charge Vsc accumulated in the charging capacitor Sc applied between both electrodes of the correcting capacitor Sc Correction signal Sr Charge resetting signal

Claims (20)

A charge capacitor that accumulates the charge generated by the received photoelectric conversion means according to the amount of received light, and a charge that discharges the charge accumulated from the charge capacitor according to the charge reset signal applied from the charge reset signal applying means In a charge amplifier circuit including a reset switch and an amplifier circuit,
A correction capacitor having one electrode connected to a terminal on the photoelectric conversion means side of the charge reset switch, and a voltage having a polarity opposite to that of the charge reset signal is generated on the other electrode of the correction capacitor. A charge amplifier circuit comprising a charge injection correction circuit having correction signal applying means for applying a correction signal.   The capacitance of the correction capacitor and the voltage applied between both electrodes of the correction capacitor by application of the correction signal are the absolute value of the product of the parasitic capacitance of the charge reset switch and the charge. 2. The charge amplifier circuit according to claim 1, wherein the charge amplifier circuit is set to be equal to an absolute value of a product of a voltage applied as a reset signal.   3. The charge amplifier circuit according to claim 2, wherein a voltage applied between the electrodes of the correction capacitor is set to a constant voltage by applying the correction signal, and a capacitance of the correction capacitor is adjusted.   3. The charge amplifier circuit according to claim 2, wherein a capacitance of the correction capacitor is fixed, and a voltage applied between both electrodes of the correction capacitor is adjusted by applying the correction signal.   5. The application of the correction signal to the correction capacitor is started after the charge reset signal is applied from the charge reset signal applying means to the charge reset switch. The charge amplifier circuit according to any one of the above. Control means for controlling the operation of the correction signal applying means,
A delay circuit is provided between the control means and the correction signal applying means;
A signal that instructs the correction signal applying unit to apply the correction signal to the correction capacitor simultaneously from the control unit when the charge reset signal is applied from the charge reset signal applying unit to the charge reset switch. And the delay circuit delays the start of application of the correction signal from the correction signal application unit to the correction capacitor by reaching the correction signal application unit. 6. The charge amplifier circuit according to claim 5, wherein:   The application of the correction signal to the correction capacitor is stopped after the application of the charge reset signal from the charge reset signal applying unit to the charge reset switch is stopped. The charge amplifier circuit according to claim 6. Control means for controlling the operation of the correction signal applying means,
A delay circuit is provided between the control means and the correction signal applying means;
When the application of the charge reset signal from the charge reset signal applying means to the charge reset switch is stopped, the correction signal is applied from the control means to the correction signal applying means to the correction capacitor. A stop instruction signal is output, and the delay circuit delays the signal to reach the correction signal application unit, thereby stopping the application of the correction signal from the correction signal application unit to the correction capacitor. 8. The charge amplifier circuit according to claim 7, wherein the charge amplifier circuit is delayed. A sampling means for removing an error by correlated double sampling from the amplified signal output from the amplifier circuit and outputting an appropriate value,
9. The sampling means according to claim 7 or 8, wherein after the application of the correction signal to the correction capacitor is stopped, the amplification signal is optimized by the correlated double sampling. Charge amplifier circuit.   The charge amplifier circuit according to claim 1, wherein the photoelectric conversion unit is a photodiode.   11. The charge amplifier circuit according to claim 1, wherein the charge amplifier circuit is used for amplification of a signal when the photostimulated light is read by the photoelectric conversion unit of the radiation image reading apparatus. A charge capacitor that accumulates the charge generated by the received photoelectric conversion means according to the amount of received light, and a charge that discharges the charge accumulated from the charge capacitor according to the charge reset signal applied from the charge reset signal applying means In a charge amplifier correction method in a charge amplifier circuit including a reset switch and an amplifier circuit,
With respect to a correction capacitor having one electrode connected to a terminal on the photoelectric conversion means side of the charge reset switch, the charge reset signal and the charge reset signal from the correction signal applying means connected to the other electrode of the correction capacitor A charge amplifier correction method, wherein a correction signal is applied in order to generate a voltage having opposite polarity.   The absolute value of the product of the capacitance of the correction capacitor and the voltage applied between both electrodes of the correction capacitor when the correction signal is applied is applied as the parasitic capacitance of the charge reset switch and the charge reset signal. 13. The charge amplifier correction method according to claim 12, wherein the charge amplifier correction method is set so as to be equal to an absolute value of a product of a voltage to be applied.   14. The charge amplifier correction method according to claim 13, wherein a voltage applied between both electrodes of the correction capacitor is made constant by applying the correction signal, and a capacitance of the correction capacitor is adjusted.   14. The charge amplifier correction method according to claim 13, wherein a capacitance of the correction capacitor is fixed, and a voltage applied between both electrodes of the correction capacitor is adjusted by applying the correction signal.   16. The application of the correction signal to the correction capacitor is started after the charge reset signal is applied to the charge reset switch from the charge reset signal applying unit. The charge amplifier correction method according to claim 1.   The charge reset signal is applied to the charge reset switch from the charge reset signal applying means, and at the same time, a signal instructing the correction signal applying means to apply the correction signal to the correction capacitor is output. The delay circuit delays the start of the application of the correction signal from the correction signal application unit to the correction capacitor by delaying the signal to the correction signal application unit. The charge amplifier correction method described.   13. The application of the correction signal to the correction capacitor is stopped after the application of the charge reset signal from the charge reset signal applying means to the charge reset switch is stopped. 18. The charge amplifier correction method according to any one of items 17.   When the application of the charge reset signal from the charge reset signal applying unit to the charge reset switch is stopped, the correction signal applying unit is instructed to stop the application of the correction signal to the correction capacitor. A signal is output, the signal is delayed by a delay circuit and reaches the correction signal applying unit, and the stop of the application of the correction signal from the correction signal applying unit to the correction capacitor is delayed. The charge amplifier correction method according to claim 18.   19. After the application of the correction signal to the correction capacitor is stopped, an error is removed from the amplified signal output from the amplifier circuit by correlated double sampling, and an appropriate value is output. The charge amplifier correction method according to claim 19.

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