JP2008294775A - Solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a contact type linear sensor capable of reducing power consumption. <P>SOLUTION: A source follower circuit included in a solid-state imaging element in the contact type linear sensor has a depletion MOS transistor connected to a power supply potential and an enhancement MOS transistor connected to a ground potential, wherein a signal voltage passed through an amplifier circuit is applied to the gate electrode of the depletion MOS transistor and a selection signal is applied as a gate voltage of the depletion MOS transistor. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device. Specifically, the present invention relates to a contact type linear sensor used as a reading device such as an OA device.

Conventionally, there are two main types of linear sensor reading methods: a reduction type reading method and a contact type reading method. Linear sensors that use a reduction type reading method reduce information from a subject via a lens system. In this structure, it is read by a solid-state image sensor of a linear sensor.
On the other hand, a linear sensor that employs a contact-type reading method (hereinafter referred to as “contact-type linear sensor”) has a structure that reads information on a subject on a one-to-one basis without using a lens system (for example, Patent Document 1). reference.).

  Here, as described above, the contact-type linear sensor needs to have a solid-state image sensor having a length at least longer than the width of the subject in order to read the information of the subject on a one-to-one basis. In order to form such an elongated solid-state imaging device, a wafer having a diameter larger than this length is required, but it is very difficult to obtain such a wafer having a large diameter.

  Therefore, a plurality of solid-state image sensors are arranged, each solid-state image sensor is operated at the same time, and electrical signals from each solid-state image sensor are output from a single wiring. A contact-type linear sensor configured to select and output an electrical signal from a selected solid-state imaging device has been proposed.

Hereinafter, a conventional contact linear sensor will be described with reference to the drawings. In the following description, a contact linear sensor having eight solid-state image sensors is taken as an example.
As shown in FIG. 3, in the conventional contact linear sensor, eight solid-state image sensors (1st Chip to 8th Chip) are arranged in a line, and the output wiring from each solid-state image sensor is combined into one. In addition, by controlling the operation of each solid-state image sensor, the output signal from the solid-state image sensor can be continuously output as a signal of the contact linear sensor.

  Here, each solid-state imaging device is configured to be supplied with a selection signal (VOSEL_O) from a timing generator (TG), and the selection signal becomes a high level (hereinafter referred to as “H level”). In this case, an electrical signal is output. Specifically, the first solid-state imaging is performed at the timing when the selection signal for the first solid-state imaging device (1st Chip) indicated by the symbol VOSEL_O1 in FIG. 4 becomes the H level (timing indicated by the symbol T1 in FIG. 4). The timing at which the element (1st Chip) outputs an electrical signal and the selection signal for the second solid-state imaging device (2nd Chip) indicated by the symbol VOSEL_O2 in FIG. 4 becomes the H level (timing indicated by the symbol T2 in FIG. 4). ) At which the second solid-state imaging device (2nd Chip) outputs an electrical signal, and the selection signal for the third solid-state imaging device (3rd Chip) indicated by the symbol VOSEL_O3 in FIG. The third solid-state imaging device (3rd Chip) outputs an electrical signal at a timing indicated by a symbol T3 in FIG. 4, and is indicated by a symbol VOSEL_O4 in FIG. The fourth solid-state imaging device (4th Chip) outputs an electrical signal at the timing when the selection signal for the solid-state imaging device (4th Chip) becomes H level (the timing indicated by the symbol T4 in FIG. 4). The fifth solid-state imaging device (5th Chip) is electrically connected at the timing when the selection signal for the fifth solid-state imaging device (5th Chip) indicated by the middle symbol VOSEL_O5 becomes H level (timing indicated by the symbol T5 in FIG. 4). The sixth solid-state imaging is output at a timing (timing indicated by symbol T6 in FIG. 4) at which the selection signal for the sixth solid-state imaging device (6th Chip) indicated by symbol VOSEL_O6 in FIG. The element (6th Chip) outputs an electrical signal, and is selected for the seventh solid-state image sensor (7th Chip) indicated by the symbol VOSEL_O7 in FIG. The seventh solid-state imaging device (7th Chip) outputs an electrical signal at the timing when the selection signal becomes H level (timing indicated by symbol T7 in FIG. 4), and the eighth solid-state imaging device (indicated by symbol VOSEL_O8 in FIG. 4) The eighth solid-state imaging device (8th Chip) is configured to output an electrical signal at the timing when the selection signal for 8th Chip) becomes the H level (the timing indicated by the symbol T8 in FIG. 4).

As shown in FIG. 5, each solid-state imaging device constituting the contact linear sensor includes a sensor array 101 in which a large number of photoelectric conversion units (pixels) each including a photodiode are linearly arranged, and one side of the sensor array. The readout gate 102 for reading out the signal charges photoelectrically converted by each photoelectric conversion unit of the sensor array, and the signal charge read out by the readout gate arranged on the opposite side of the sensor array of the readout gate A horizontal transfer register 103 for transferring to the signal, a charge / voltage conversion unit 104 for converting the signal charge horizontally transferred by the horizontal transfer register into a signal voltage, and an output circuit unit 105 for amplifying the signal voltage converted by the charge / voltage conversion unit. ing.
Then, the signal charge accumulated in the sensor array in accordance with the amount of incident light is read to the read gate at the timing when the read voltage indicated by the symbol ROG in FIG. 4 becomes H level, and the selection signal becomes H level. Horizontal transfer is performed by the horizontal transfer register, converted into a signal voltage by the charge voltage conversion unit, and then output through the output circuit unit.

Further, as shown in FIG. 6, the output circuit unit uses the signal voltage converted by the charge voltage conversion unit as an input signal (Vin), amplifies the input signal, and outputs from the amplifier circuit. And a source follower circuit 107 that generates a final output signal (Vout) using the signal as an input signal. Here, in the source follower circuit, an N-channel depletion MOS transistor 108 connected to the power supply voltage (VDD) and an N-channel depletion MOS transistor 109 connected to the ground potential are connected in series. The depletion MOS is used to reduce the MOS resistance in order to pass a large amount of current.
Then, the signal voltage converted by the charge voltage conversion unit (or the signal voltage already amplified by the amplifier circuit (not shown) before the amplifier circuit 106) is input to the amplifier circuit 106 as an input signal, and the amplifier circuit When the signal voltage amplified by 106 is applied to the gate electrode of the N-channel depletion type MOS transistor 108, a final output signal is output.

JP-A-4-256279

  By the way, since the contact-type linear sensor has a plurality of solid-state image sensors, all the solid-state image sensors operate when reading with the contact-type linear sensor. The amount of current flowing is the sum of the amount of current flowing through each solid-state image sensor. In the conventional output circuit unit, a current always flows through the amplifier circuit and the source follower circuit.

  On the other hand, the output from the close contact type linear sensor is to output the output signal of the solid state image pickup device that is sequentially selected from a plurality of solid state image pickup devices as the output signal of the close contact type linear sensor. An unselected solid-state image sensor is in a standby state.

  The present invention has been devised in view of the above points, and an object of the present invention is to realize a reduction in power consumption of a solid-state imaging device that employs a contact-type reading method.

  In order to achieve the above object, the solid-state imaging device according to the present invention converts the signal charge accumulated in accordance with the amount of incident light into an electrical signal, and outputs the electrical signal through an amplifier circuit and a source follower circuit. N solid-state image sensors (N: integer greater than or equal to 2) are provided, which are sequentially selected from the first solid-state image sensor to the N-th solid-state image sensor, and an electric signal is received from the selected solid-state image sensor. In the output solid-state imaging device, the source follower circuit included in the nth (n: natural number less than or equal to N) solid-state imaging device has one end connected to a high level potential and an output from the amplifier circuit on the gate electrode. A first MOS transistor to which a signal is applied; a second MOS transistor having one end connected to the other end of the first MOS transistor and the other end connected to a low level potential; An electrical signal output unit connected to a connection part of the first MOS transistor and the second MOS transistor, the second MOS transistor is an enhancement type, and the nth solid-state image sensor is selected When this is done, the second MOS transistor is turned on to output an electrical signal from the output section.

  Here, the source follower circuit included in the n-th solid-state imaging device has one end connected to a high level potential and a first MOS transistor to which an output signal from the amplifier circuit is applied to the gate electrode, and one end Is connected to the other end of the first MOS transistor, and is connected to the second MOS transistor having the other end connected to the low level potential, and to the connection portion of the first MOS transistor and the second MOS transistor. And the second MOS transistor is an enhancement type, and when the nth solid-state imaging device is selected, the second MOS transistor is turned on and the electric signal is output from the output unit. , Only the source follower circuit of the solid-state image sensor selected from the N solid-state image sensors operates, and the selected solid-state image The current flows only in the source follower circuit of the child. In other words, the source follower circuit of (N-1) solid-state image sensors that are not selected from the N solid-state image sensors does not operate, and (N-1) solid-state image sensors that are not selected. No current flows through the source follower circuit.

  In addition, the solid-state imaging device according to the present invention converts N signal charges accumulated according to the amount of incident light into an electrical signal, and outputs the electrical signal through an amplifier circuit and a push-pull circuit (N ( N: an integer greater than or equal to 2), and a solid-state imaging device that sequentially and selectively selects from the first solid-state imaging device to the N-th solid-state imaging device and outputs an electrical signal from the selected solid-state imaging device, The push-pull circuit included in the n-th (n: natural number equal to or less than N) solid-state imaging device has a first end connected to a high-level potential and an output signal from the amplifier circuit applied to the gate electrode. A second MOS transistor having one end connected to the other end of the first MOS transistor and the other end connected to a low level potential; and the first MOS transistor; An output portion of an electrical signal connected to a connection portion of the second MOS transistor, and the second MOS transistor is turned on when the nth solid-state imaging device is selected. Output electrical signals from

  Here, the push-pull circuit included in the n-th solid-state imaging device has one end connected to a high-level potential, a first MOS transistor to which an output signal from the amplifier circuit is applied to the gate electrode, and one end Is connected to the other end of the first MOS transistor, and is connected to the second MOS transistor having the other end connected to the low level potential, and to the connection portion of the first MOS transistor and the second MOS transistor. When the n-th solid-state imaging device is selected, the second MOS transistor is turned on to output an electrical signal from the output unit, so that N solid-state imaging devices are provided. Only the push-pull circuit of the solid-state image sensor selected from the above operates, and the current flows only in the push-pull circuit of the selected solid-state image sensor. In other words, the push-pull circuit of the (N−1) solid-state image sensors that are not selected from the N solid-state image sensors does not operate, and the (N−1) solid-state image sensors that are not selected. No current flows through the push-pull circuit.

  In general, in the output circuit design, the frequency characteristics are improved by increasing the size of the MOS transistor of the source follower circuit or push-pull circuit in the final stage so that a large current can flow. Therefore, since the ratio of the current that flows to the source follower circuit and push-pull circuit in the final stage is large among the current that flows in the output circuit section, do not flow current to the source follower circuit and push-pull circuit in the final stage. The technical implications of doing so are enormous.

  On the other hand, when considering only the viewpoint of reducing the amount of current, only the amplifier circuit of the selected solid-state image sensor is operated and selected for the amplifier circuit as well as the source follower circuit and push-pull circuit in the final stage. Although it is conceivable that the amplifier circuit of the solid-state image sensor that does not flow does not flow current, the amplifier circuit adjusts the amplification factor to the source follower circuit or push-pull circuit in the final stage. These gain output adjustment circuits are very sensitive to noise and operate from the operating state to the non-operating state (the state where current is not flowing) or from the non-operating state. When a change occurs in the operating state such as a state (a state in which no current is flowing), it is affected by noise caused by these changes. Theft is a concern. In consideration of the function as an imaging device, it is important to suppress the generation of noise as much as possible. Therefore, the operation control is not performed on the amplifier circuit, and a current always flows. .

  In the solid-state imaging device to which the present invention is applied, current flows only in the source follower circuit or push-pull circuit of the solid-state imaging device that is alternatively selected, and in the source follower circuit or push-pull circuit of the solid-state imaging device that is not selected. Since no current flows, the amount of current as a whole can be suppressed, and power consumption can be reduced.

Hereinafter, embodiments of the present invention will be described with reference to the drawings to facilitate understanding of the present invention.
In the contact linear sensor that is an example of the solid-state imaging device to which the present invention is applied, eight solid-state image sensors (1st Chip to 8th Chip) are arranged in a line as in the conventional contact linear sensor described above. The output wiring from each solid-state image sensor is combined into one, and by controlling the operation of each solid-state image sensor, the output signal from the solid-state image sensor is continuously used as the signal of the contact linear sensor. It is configured so that it can be output (see FIG. 3).

Each solid-state imaging device is configured to be supplied with a selection signal (VOSEL_O) from a timing generator (TG), and outputs an electrical signal when the selection signal becomes H level. Specifically, the first solid-state imaging is performed at the timing when the selection signal for the first solid-state imaging device (1st Chip) indicated by the symbol VOSEL_O1 in FIG. 4 becomes the H level (timing indicated by the symbol t1 in FIG. 4). The timing at which the element (1st Chip) outputs an electrical signal and the selection signal for the second solid-state imaging device (2nd Chip) indicated by the symbol VOSEL_O2 in FIG. 4 becomes the H level (timing indicated by the symbol t2 in FIG. 4). ) At which the second solid-state imaging device (2nd Chip) outputs an electrical signal, and the selection signal for the third solid-state imaging device (3rd Chip) indicated by the symbol VOSEL_O3 in FIG. The third solid-state imaging device (3rd Chip) outputs an electric signal at a timing indicated by a symbol t3 in FIG. The fourth solid-state imaging device (4th Chip) outputs an electrical signal at the timing when the selection signal for the body imaging device (4th Chip) becomes the H level (the timing indicated by the symbol t4 in FIG. 4). At the timing when the selection signal for the fifth solid-state imaging device (5th Chip) indicated by the symbol VOSEL_O5 becomes H level (timing indicated by the symbol t5 in FIG. 4), the fifth solid-state imaging device (5th Chip) receives the electric signal. And the sixth solid-state imaging device at the timing when the selection signal for the sixth solid-state imaging device (6th Chip) indicated by symbol VOSEL_O6 in FIG. 4 becomes H level (timing indicated by symbol t6 in FIG. 4). (6th Chip) outputs an electrical signal, and a selection signal for the seventh solid-state imaging device (7th Chip) indicated by a symbol VOSEL_O7 in FIG. The seventh solid-state imaging device (7th Chip) outputs an electrical signal at the timing of reaching the level (timing indicated by symbol t7 in FIG. 4), and the eighth solid-state imaging device (8th Chip) indicated by symbol VOSEL_O8 in FIG. On the other hand, the eighth solid-state imaging device (8th Chip) is configured to output an electric signal at the timing when the selection signal becomes the H level (the timing indicated by the symbol t8 in FIG. 4).
Here, VOSEL_O1 is generated by adjusting the timing of VOSEL_IN with a flip-flop circuit or the like provided with CT1 in the first solid-state imaging device and shifting the rising edge of the VOSEL_IN signal to the rising edge of the CT1 signal. Similarly, the timing of VOSEL_O2 is adjusted by a flip-flop circuit or the like provided in the second solid-state image pickup device with VOSEL_01 as CT1. Hereinafter, VOSEL_O3 and subsequent ones are sequentially generated by the same method.

  In addition, each solid-state image sensor constituting the contact linear sensor also has a large number of photoelectric conversion units (pixels) composed of photodiodes linearly arranged in the same manner as each solid-state image sensor of the conventional contact linear sensor described above. A sensor gate, a read gate that is arranged on one side of the sensor row and that reads the signal charges photoelectrically converted by each photoelectric conversion unit of the sensor row, and a horizontal that transfers the signal charge read by the read gate to the output unit side It has a transfer register, a charge-voltage converter that converts the signal charge horizontally transferred by the horizontal transfer register into a signal voltage, and an output circuit that amplifies the signal voltage converted by the charge-voltage converter. The signal charges accumulated in the sensor array in accordance with the amount of incident light are read out to the readout gate at the timing when the readout voltage becomes H level, and the horizontal transfer register performs horizontal transfer when the selection signal becomes H level. After being converted into a signal voltage by the charge voltage converter, an output is made through the output circuit (see FIG. 5).

  Further, as shown in FIG. 1, the output circuit unit in the solid-state imaging device to which the present invention is applied is an amplifier that amplifies and outputs the input signal using the signal voltage converted by the charge voltage conversion unit as an input signal (Vin). The circuit 6 includes a source follower circuit 7 that generates a final output signal (Vout) using an output signal from the amplifier circuit as an input signal, and a current control circuit 1 that controls a current flowing through the source follower circuit.

  Here, in the source follower circuit, an N-channel depletion MOS transistor 8 connected to the power supply voltage (VDD) and an N-channel enhancement MOS transistor 9 connected to the ground potential are connected in series.

  The current control circuit includes a first MOS transistor 10, a second MOS transistor 11, a third MOS transistor 12, and a fourth MOS transistor 13. One end of the first MOS transistor 10 is amplified. The other end of the first MOS transistor 10 is connected to the gate electrode of the depletion MOS transistor 8. One end of the second MOS transistor 11 is connected to the ground potential, and the other end of the second MOS transistor 11 is connected to the gate electrode of the depletion MOS transistor 8. Further, one end of the third MOS transistor 12 is connected to a predetermined potential (VGG), and the other end of the third MOS transistor 12 is connected to the gate electrode of the enhancement MOS transistor 9. One end of the fourth MOS transistor 13 is connected to the ground potential, and the other end of the fourth MOS transistor 13 is connected to the gate electrode of the enhancement MOS transistor 9.

Further, a selection signal (VOSEL_O) (voltage: 0 V to 3 V) is applied to the gate electrode of the first MOS transistor and the gate electrode of the third MOS transistor by the first inverter circuit 14 and the inverted signal ( A signal (voltage: 0 V to 5 V) obtained by inverting the voltage (0 V to 5 V) by the second inverter circuit 15 is further applied to the gate electrode of the second MOS transistor and the gate electrode of the fourth MOS transistor. The signal obtained by inverting the selection signal (VOSEL_O) by the first inverter circuit 14 is further inverted by the second inverter circuit 15, and the signal further inverted by the third inverter circuit 16 is applied. Yes.
Here, three inverter circuits are provided because the first inverter circuit 14 optimizes the MOS structure and size in order to perform voltage adjustment, and the second inverter circuit 15 and the third inverter circuit 16 in the subsequent stage. This is because the inverter circuit 15 and the inverter circuit 16 have the same size and the same MOS output characteristics in order to accurately output signals for applying the first to fourth gates.

In the output circuit portion configured as described above, when the selection signal (VOSEL_O) is at the low level (hereinafter referred to as “L level”), the gate electrode of the first MOS transistor and the third MOS transistor An L level signal is applied to the gate electrode, and an H level signal is applied to the gate electrode of the second MOS transistor and the gate electrode of the fourth MOS transistor, so that the first MOS transistor and the third MOS transistor are applied. Is turned off and the second MOS transistor and the fourth MOS transistor are turned on, so that a ground potential is applied to both the gate electrode of the depletion MOS transistor 8 and the gate electrode of the enhancement MOS transistor 9. (See FIG. 2A).
Note that when a ground potential is applied to the gate electrode of the enhancement MOS transistor 9, the operation of the source follower circuit at the final stage of the output circuit unit is stopped, and no current flows through the source follower circuit.

On the other hand, when the selection signal (VOSEL_O) is at the H level, the H level signal is applied to the gate electrode of the first MOS transistor and the gate electrode of the third MOS transistor, and the gate electrode and the second MOS transistor of the second MOS transistor. The L level signal is applied to the gate electrode of the fourth MOS transistor, the first MOS transistor and the third MOS transistor are turned on, and the second MOS transistor and the fourth MOS transistor are turned off. Therefore, the output signal of the amplifier circuit is applied to the gate electrode of the depletion MOS transistor 8, and a predetermined potential (VGG) is applied to the gate electrode of the enhancement MOS transistor 9 (see FIG. 2B). .)
The output signal of the amplifier circuit is applied to the gate electrode of the depletion MOS transistor 8, and a predetermined potential (VGG) is applied to the gate electrode of the enhancement MOS transistor 9, so that the source follower circuit in the final stage of the output circuit section is changed. The source follower circuit is operated and a current flows.

In this embodiment, the case where the source follower circuit is formed at the final stage of the output circuit unit is described as an example, but a push-pull circuit may be provided at the final stage of the output circuit unit. .
Specifically, as shown in FIG. 7 (a), the signal voltage converted by the charge-voltage converter is used as an input signal (Vin), and an amplifier circuit that amplifies the input signal and an output signal from the amplifier circuit are input. A push-pull circuit 17 that generates a final output signal (Vout) as a signal. The push-pull circuit is connected to a ground potential and an N-channel depletion MOS transistor 18 connected to a power supply voltage (VDD). A P-channel depletion MOS transistor 19 may be connected in series. Also in the case of an output circuit portion having a push-pull circuit, a current does not flow through the push-pull circuit when the selection signal (VOSEL_O) is at an L level as in the output circuit portion having a source follower circuit (FIG. 7 ( b)), when the selection signal (VOSEL_O) is at the H level, a current flows through the push-pull circuit (see FIG. 7C).

  In the contact linear sensor to which the present invention is applied, only the source follower circuit of the solid-state imaging device to which the selection signal (VOSEL_O) is applied operates, and the source follower of the solid-state imaging device to which the selection signal (VOSEL_O) is not applied. Since the circuit does not operate, in other words, the current flows only to the source follower circuit of the solid-state image sensor that is outputting the electric signal, and the current does not flow to the source follower circuit of the solid-state image sensor that is on standby. The amount of current flowing through the entire linear sensor can be suppressed, and power consumption can be reduced.

It is a schematic diagram for demonstrating the output circuit part of the solid-state image sensor of the contact | adherence linear sensor of this invention. It is a schematic diagram (1) for demonstrating operation | movement of the output circuit part of the solid-state image sensor of the contact | adherence linear sensor of this invention. It is a schematic diagram (2) for demonstrating operation | movement of the output circuit part of the solid-state image sensor of the contact | adherence linear sensor of this invention. It is a schematic diagram for demonstrating the conventional contact | adherence linear sensor. It is a schematic diagram for demonstrating the timing chart of each pulse. It is a schematic diagram for demonstrating the conventional solid-state image sensor. It is a schematic diagram for demonstrating the output circuit part of the solid-state image sensor of the conventional contact | adherence linear sensor. It is a schematic diagram for demonstrating the modification of the output circuit part of the solid-state image sensor of the contact | adherence linear sensor of this invention. It is a schematic diagram (1) for demonstrating the operation | movement of the modification of the output circuit part of the solid-state image sensor of the contact | adherence linear sensor of this invention. It is a schematic diagram (2) for demonstrating operation | movement of the modification of the output circuit part of the solid-state image sensor of the contact | adherence linear sensor of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Current control circuit 6 Amplifying circuit 7 Source follower circuit 8 Depletion MOS transistor 9 Enhancement MOS transistor 10 1st MOS transistor 11 2nd MOS transistor 12 3rd MOS transistor 13 4th MOS transistor 14 4th inverter circuit 15 Second inverter circuit 16 Third inverter circuit 17 Push-pull circuit 18 Depletion MOS transistor 19 Depletion MOS transistor

Claims (6)

N solid-state image sensors (N: integer greater than or equal to 2) for converting the signal charge accumulated according to the amount of incident light into an electric signal and outputting the electric signal through an amplifier circuit and a source follower circuit are provided. In the solid-state imaging device that sequentially selects from the N-th solid-state imaging device to the N-th solid-state imaging device and outputs an electrical signal from the selected solid-state imaging device,
The source follower circuit included in the n-th (n: natural number less than or equal to N) solid-state imaging device includes:
A first MOS transistor having one end connected to a high level potential and an output signal from an amplifier circuit applied to the gate electrode;
A second MOS transistor having one end connected to the other end of the first MOS transistor and the other end connected to a low level potential;
An output portion of an electric signal connected to a connection portion of the first MOS transistor and the second MOS transistor;
The second MOS transistor is an enhancement type,
When the nth solid-state imaging device is selected, the second MOS transistor is turned on to output an electric signal from the output unit. The gate of the second MOS transistor is connected to a predetermined potential via the third transistor and is connected to the ground potential via the fourth transistor.
The solid-state imaging device according to claim 1, wherein complementary signals are input to the gate of the third transistor and the gate of the fourth transistor. The gate of the first MOS transistor receives an output signal from the amplifier circuit via a fifth transistor and is connected to the ground potential via a sixth transistor.
The solid-state imaging device according to claim 2, wherein complementary signals are input to a gate of the fourth transistor and a gate of the fifth transistor. The solid-state imaging device according to claim 2, wherein the complementary signal is an output of an inverting circuit after the second stage of an inverting circuit including three or more stages. N solid-state image sensors (N: integer greater than or equal to 2) for converting the signal charge accumulated according to the amount of incident light into an electric signal and outputting the electric signal via an amplifier circuit and a push-pull circuit are provided. In the solid-state imaging device that sequentially selects from the N-th solid-state imaging device to the N-th solid-state imaging device and outputs an electrical signal from the selected solid-state imaging device,
The push-pull circuit included in the n-th (n: natural number less than or equal to N) solid-state imaging device includes:
A first MOS transistor having one end connected to a high-level potential and an output signal from an amplifier circuit applied to the gate electrode;
A second MOS transistor having one end connected to the other end of the first MOS transistor and the other end connected to a low level potential;
An output portion of an electric signal connected to a connection portion of the first MOS transistor and the second MOS transistor;
When the nth solid-state imaging device is selected, the second MOS transistor is turned on to output an electric signal from the output unit. The gate of the second MOS transistor is connected to a predetermined potential via the third transistor and is connected to the ground potential via the fourth transistor.
The solid-state imaging device according to claim 5, wherein complementary signals are input to a gate of the third transistor and a gate of the fourth transistor.

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