JP2008294215A - Nonvolatile semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance writing speed by preventing the generation of variations in transistor threshold. <P>SOLUTION: In the nonvolatile semiconductor storage device, the film thickness of a control gate electrode 106a is made to be thinner than that of an upper gate electrode 106b so as to have the relation of Hsg×8/9>Hcell≥Hsg×7/9-Heb×11/9, where the thickness of the control gate electrode 106a above a floating gate electrode 104a of a memory cell transistor 1 is Hcell, a film thickness of an upper gate electrode 106b of a selection transistor 2 is Hsg, and the difference between the height of an upper surface of the floating gate electrode 104a and the height of an upper surface of an element isolation region 107 is Heb. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device.

  As the nonvolatile semiconductor memory device is highly integrated, the gate length of the memory cell is being reduced to a nanometer size. This miniaturization of the gate length causes a reduction in the coupling ratio and an increase in word line resistance due to the fine line effect, thereby reducing the writing speed to the memory cell. In order to prevent this decrease in the writing speed, the resistance of the word line control gate electrode is reduced, the word line control gate electrode is thinned (parasitic capacitance is reduced), and the depletion of the word line control gate electrode is improved (coupling ratio is improved). Three items are required.

  The silicidation of only a part of the control gate electrode by the conventional silicide technique (partial silicide) greatly increases the word line resistance due to the thin line effect. Moreover, it is difficult to reduce the thickness of the word line electrode polysilicon. Therefore, a metal electrode with low resistance and no gate depletion is suitable for the control gate electrode of the memory cell. Since the metal electrode has a structure in which full silicide (FUSI) is applied to the control gate electrode, the manufacturing process becomes extremely easy, which is advantageous in terms of manufacturing cost.

  In the structure of the stack gate type nonvolatile semiconductor memory device, a stack structure (control gate electrode / interpoly insulating film / floating gate electrode / tunnel oxide film stack gate type memory cell structure) is employed in the memory cell portion. . Also, the control gate electrode and the floating gate electrode are made conductive by partially removing (removing) the interpoly insulating film from the gate electrode of the selection gate transistor and the control transistor of the peripheral circuit section (sense amplifier and row decoder section). An etched interpoly (EI) structure is employed (see, for example, Non-Patent Document 1).

  When full silicide is applied to the control gate electrode of a nonvolatile semiconductor memory device having two gate structures, such as a stack structure and an etching / interpoly structure, the interpoly insulating film is removed in the etching / interpoly structure transistor. There is a possibility that the silicide proceeds to the floating gate electrode side through the portion, and the silicide layer comes into contact with the tunnel oxide film.

  When the silicide layer comes into contact with the tunnel oxide film, the work function of the gate electrode changes, and a threshold shift occurs between the selection transistor and the control transistor in the peripheral circuit portion. Since the progress of silicide depends on the area and dimensions of the gate electrode, there arises a problem of threshold variation.

  In addition, there is a problem that the capacity increases due to the fact that the distance between the word lines is close as the inter-wiring shrinkage due to miniaturization.

  Also, a nitride film trap type nonvolatile semiconductor memory device such as a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) structure or a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) structure is used for improving the coupling ratio. A high dielectric film (High-k film) is stacked on the trap nitride film, and a word line control gate electrode is stacked immediately above. When full silicide is applied to the word line control gate electrode, a phenomenon called “Fermi Level Pinning” occurs in which the work function of the word line control gate electrode is fixed near the work function of polysilicon before silicidation (for example, non-patent Reference 2). For this reason, even when full silicide is applied, the write voltage does not decrease, and the leakage resistance of the interpoly insulating film cannot be improved.

It is known that this phenomenon can be suppressed by making the word line control gate electrode a metal-rich full silicide electrode. However, when the word line control gate electrode is a metal-rich full silicide electrode, silicidation of the gate electrode of the selection transistor or the peripheral transistor proceeds and the silicide film may come into contact with the tunnel oxide film. In this case as well, the problem of threshold variation occurs as described above.
Kenichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Toshihiko Himeno, Ken Takeuchi, Tamio Ikehashi, Kazushige Kanda, Koji Hosono, Riichiro Shirota, Seiichi Aritome, Kazuhiro Shimizu, Kazuo Hatakeyama, and Koji Sakui, “A 130-mm2, 256-Mbit NAND Flash with Shallow Trench Isolation Technology ”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, NOVEMBER 1999, VOL.34, NO.11, pp1536-1543 Moon Sig Joo, Byung Jin Cho, N. Balasubramanian, and Dim-Lee Kwong, “Stoichiometry Dependence of Fermi-Level Pinning in Fully Silicided (FUSI) NiSi Gate on High-K Dielectric”, IEEE ELECTRON DEVICE LETTERS, DECEMBER 2005, VOL .26, NO.12, pp882-884

  An object of the present invention is to provide a nonvolatile semiconductor memory device that prevents the occurrence of transistor threshold variation and has a high writing speed.

  A nonvolatile semiconductor memory device according to an aspect of the present invention includes a semiconductor substrate, a plurality of first tunnel oxide films formed on the semiconductor substrate at a predetermined interval along a first direction, and the plurality of the plurality of tunnel oxide films. A plurality of floating gate electrodes formed on the first tunnel oxide film and a groove formed in the surface portion of the semiconductor substrate between the plurality of first tunnel oxide films are embedded, and an upper surface of the floating gate electrode An element isolation region formed lower than the upper surface; an interpoly insulating film formed in a strip shape along the first direction so as to cover the floating gate electrode and the element isolation region; and on the interpoly insulating film A plurality of memory cell transistors each having a control gate electrode made of a formed metal silicide film, and one at each end of each of the plurality of memory cell transistors. A selection transistor having a second tunnel oxide film, a lower gate electrode, an insulating film including an opening, and an upper gate electrode connected to the lower gate electrode through the opening; When the thickness of the control gate electrode above the floating gate electrode is Hcell, the thickness of the upper gate electrode is Hsg, and the difference in height between the upper surface of the floating gate electrode and the upper surface of the element isolation region is Heb, Hsg X8 / 9> Hcell ≧ Hsg × 7 / 9−Heb × 11/9.

  In addition, a nonvolatile semiconductor memory device according to an aspect of the present invention includes a semiconductor substrate, a plurality of first tunnel oxide films formed on the semiconductor substrate at predetermined intervals along a first direction, A plurality of trap nitride films formed on the plurality of first tunnel oxide films and a groove formed in the semiconductor substrate surface portion between the plurality of first tunnel oxide films are embedded, and an upper surface is the trap nitride film An element isolation region formed at the same height as or higher than the upper surface of the film, an interpoly insulating film formed in a strip shape along the first direction on the trap nitride film and the element isolation region, and A plurality of memory cell transistors each having a control gate electrode made of a metal silicide film formed on an interpoly insulating film, and one at each end of each of the plurality of memory cell transistors. And a selection transistor having a second tunnel oxide film and a gate electrode formed on the second tunnel oxide film, the control gate electrode having a thickness of Hcell, and the gate electrode having a thickness of Is Hsg, the thickness of the interpoly insulating film is Hipd, and the thickness of the trap nitride film is Hsin, 0 <Hcell <Hsg × 8 / 9−Hipd−Hsin.

  According to the present invention, it is possible to prevent the occurrence of variations in transistor thresholds and increase the writing speed.

  Hereinafter, a nonvolatile semiconductor memory device according to an embodiment of the present invention will be described with reference to the drawings.

  (First Embodiment) FIG. 1 shows a schematic configuration of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. FIG. 1 shows a cross section along the bit line direction (arrow I in the figure) and a cross section along the word line direction (arrow II in the figure).

  Impurity diffusion layers 102 are formed on the surface portion of the semiconductor substrate 101 at predetermined intervals along the bit line direction (arrow I in the figure). A plurality of memory cell transistors 1 in which a tunnel oxide film 103, a floating gate electrode 104a, an interpoly insulating film 105a, and a control gate electrode 106a are sequentially stacked are formed on the semiconductor substrate 101 between the impurity diffusion layers 102.

  In the memory cell transistor 1, a plurality of buried element isolation regions 107 are formed in the semiconductor substrate 101 at predetermined intervals along the word line direction (arrow II in the figure). A tunnel oxide film 103 is formed on the semiconductor substrate 101 between the element isolation regions 107, and a floating gate electrode 104 a having an upper surface higher than the upper surface of the element isolation region 107 is formed on the tunnel oxide film 103. .

  An interpoly insulating film 105 a is formed on the floating gate electrode 104 a and the element isolation region 107. The interpoly insulating film 105a has an uneven shape corresponding to the surface shapes of the floating gate electrode 104a and the element isolation region 107 in the lower layer.

  A control gate electrode 106a is formed on the interpoly insulating film 105a. The lower surface of the control gate electrode 106a has an uneven shape corresponding to the surface shape of the lower interpoly insulating film 105a.

  One selection transistor 2 is formed at each end of the plurality of memory cell transistors 1 arranged in the bit line direction (arrow I in the figure) (only one end is shown in the figure). The selection transistor 2 has the same configuration as that of the memory cell transistor 1, but an opening 108 is formed in a part of the interpoly insulating film 105b, and the floating gate electrode 104b and the control gate electrode 106b are connected. An etching interpoly structure having a gate electrode 109 is formed. Hereinafter, the floating gate electrode 104b portion of the gate electrode 109 is referred to as a lower gate electrode, and the control gate electrode 106b portion is referred to as an upper gate electrode.

  The control gate electrode 106a of the memory cell transistor 1 is a nickel full silicide (FUSI) gate electrode. On the other hand, the gate electrode 109 of the select transistor 2 has a partial silicide structure having a nickel silicide film 106c and a polysilicon film 106d.

  An interlayer insulating film 110 is formed on the semiconductor substrate 101 between the memory cell transistors 1 and between the memory cell transistor 1 and the selection transistor 2.

The film thickness of the control gate electrode 106a of the memory cell transistor 1 is smaller than the film thickness of the upper gate electrode 106b of the selection transistor 2. Specifically, the film thickness H _cell of the control gate electrode 106a of the memory cell transistor 1 and the film thickness H _sg of the upper gate electrode 106b of the selection transistor 2 have a relationship of H _cell <8 × H _sg / 9. The significance of the numerical value will be described later.

  This prevents the silicide film formed on the gate electrode 109 of the selection transistor 2 from reaching the tunnel oxide film 103 in the step of fully siliciding the control gate electrode 106a, and causes threshold variation due to threshold deviation. Can be suppressed. In addition, by reducing the thickness of the control gate electrode, the capacity between word lines can be reduced and the operation speed of the memory cell can be increased.

  Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to process cross-sectional views shown in FIGS. The process sectional view shows (a) a vertical section along the bit line direction (corresponding to arrow I in FIG. 1) and (b) a vertical direction along the word line direction (corresponding to arrow II in FIG. 1) with respect to the same process. A vertical section in two directions of the section is shown.

  First, as shown in FIG. 2, a tunnel oxide film 202 made of, for example, a silicon oxide film having a thickness of 8 nm is formed on a semiconductor substrate 201 by chemical vapor deposition (CVD). A floating gate electrode 203 made of, for example, a polysilicon film having a thickness of 80 nm is formed thereon by CVD, and then the semiconductor substrate 201, tunnel oxide film 202, and floating gate electrode 203 are formed along the bit line direction with a predetermined interval therebetween. Etching is performed by anisotropic etching such as RIE (reactive ion etching) to form a plurality of grooves T1. The element isolation region 204 is formed by embedding, for example, a silicon oxide film in the plurality of trenches T1. Thereafter, an interpoly insulating film 205 made of, for example, a silicon oxide film having a thickness of 15 nm is formed on the entire surface by CVD. The interpoly insulating film 205 has a concavo-convex shape corresponding to the surface shape of the floating gate electrode 203 and the element isolation region 204 in the lower layer.

  As shown in FIG. 3, a polysilicon film 301a is formed on the interpoly insulating film 205 by the CVD method, and a part of the polysilicon film 301a and the interpoly insulating film 205 in the region A1 where the selection transistor is formed later and the floating film are formed. The gate electrode 203 is removed by RIE using a patterned resist (not shown) to form a trench T2.

  The interpoly insulating film 205 is required to have high reliability, and it is not preferable to directly contact the resist applied when forming the trench T2 with the interpoly insulating film. Therefore, the trench T2 is formed after the polysilicon film 301a is once formed.

  As shown in FIG. 4, a polysilicon film 301b is formed on the polysilicon film 301a so as to fill the trench T2 by the CVD method. The total film thickness of the polysilicon films 301a and 301b is set to 150 nm.

  As shown in FIG. 5, a mask material 501 made of, for example, a silicon nitride film is formed on the entire surface by CVD. Then, the mask material 501, the polysilicon films 301 a and 301 b, the interpoly insulating film 205, the floating gate electrode 203 and the tunnel oxide film 202 are removed by RIE along the word line direction with a predetermined interval, and the surface of the semiconductor substrate 201 is removed. A plurality of grooves T3 that exposes are formed.

  As a result, a word line is formed, and the shapes of the memory cell transistor 1 and the select transistor 2 are determined. In the memory cell transistor 1, the polysilicon films 301a and 301b serve as the control gate electrode 401. In the select transistor 2, the gate electrode 402 has an etching / interpoly structure to which the polysilicon films above and below the interpoly insulating film 205 are connected. Hereinafter, the upper portion of the interpoly insulating film 205 of the gate electrode 402 is referred to as an upper gate electrode 402a, and the lower portion of the interpoly insulating film 205 is referred to as a lower gate electrode 402b.

  Thereafter, impurities are implanted into the semiconductor substrate 201 and heat treatment is performed, so that a diffusion layer 502 is formed.

  As shown in FIG. 6, for example, a silicon oxide film is formed to fill the trench T3 by a CVD method, and a planarization process is performed by a CMP (chemical mechanical polishing) method using a mask material 501 as a stopper film, and an interlayer insulating film 601 is formed. Form.

  As shown in FIG. 7, a resist 701 is formed on the selection transistor 2. In consideration of misalignment and the like, the resist 701 is formed slightly larger than the selection transistor 2.

  As shown in FIG. 8, the mask material 501 on the memory cell transistor 1 is removed.

  As shown in FIG. 9, the control gate electrode (polysilicon film) 401 is etched back using the resist 701 as an etching mask. The etching method is, for example, CDE (Chemical Dry Etching). At this time, the interlayer insulating film 601 is also somewhat removed. The etch back amount of the control gate electrode 401 will be described later.

  As shown in FIG. 10, the resist 701 and the mask material 501 are removed. For the removal of the resist 701, a process combining Ashing (ashing), SPM (sulfuric acid / hydrogen peroxide) cleaning, and APM (ammonia hydrogen peroxide) cleaning is used. In addition, the interlayer insulating film 601 is etched so that the upper surface of the interlayer insulating film 601 adjacent to the upper surface of the upper gate electrode 402a of the select transistor 2 becomes flat.

  As shown in FIG. 11, a nickel film 1101 is formed on the entire surface.

  As shown in FIG. 12, the control gate electrode (polysilicon film) 401 and the nickel film 1101 are reacted by heat treatment to form a nickel silicide film 1201. The control gate electrode of the memory cell transistor is fully silicided. The height of the control gate electrode of the memory cell transistor is reduced by the process shown in FIG. In addition, silicidation is dependent on the gate length, and the selection transistor is slower in silicidation than the memory cell transistor. Therefore, when the full silicidation of the control gate electrode 401 is completed, the silicidation of the gate electrode 402 of the selection transistor 2 is part of the upper gate electrode 402a or part of the lower gate electrode 402b, and the tunnel oxide film 202 is not reached. After full silicidation of the control gate electrode 401, the unreacted nickel film 1101 is removed by etching with a chemical solution.

  After that, silicon nitride film, silicon oxide film deposition, silicon oxide film surface flattening, formation of contact hole exposing the upper surface of the control gate electrode, embedding of a conductive layer inside the contact hole, formation of a wiring layer, etc. A non-volatile semiconductor memory device is manufactured (not shown).

An etch back amount of the control gate electrode 401 in the step shown in FIG. 9 will be described. The etch back amount (film thickness) of the control gate electrode 401 is ΔH _cell , the film thickness of the upper gate electrode 402a of the selection transistor 2 is H _sg , and the film thickness of the control gate electrode 401 after the etch back is H _cell (= H _sg − ΔH _cell ), the film thickness of the interpoly insulating film 205 is H _ipd , the film thickness of the lower gate electrode 402b of the selection transistor (floating gate electrode 203 of the memory cell transistor) is H _fg , and the element isolation region 204 of the interpoly insulating film 205 The amount dropped above is H _eb .

  Silicidation has a gate length dependency, and the selection transistor 2 has a larger gate length than the memory cell transistor 1, and therefore silicidation is slow. Therefore, if the upper surface of the control gate electrode 401 after the etch back is lower than the upper surface of the upper gate electrode 402a of any selection transistor, when the full silicidation of the control gate electrode 401 is completed, the gate electrode of the selection transistor is completed. It is considered that the silicide film formed in this does not reach the tunnel oxide film 202.

  The film thickness of the upper gate electrode 402a (control gate electrode 401 before etch back) of the selection transistor made of the polysilicon film formed by the CVD method has a variation of about ± 10%. Further, the variation in the etch back amount of the control gate electrode (polysilicon film) 401 is ± 10%.

Therefore, the condition that the upper surface of the control gate electrode 401 after the etch back is lower than the upper surface of the upper gate electrode 402a of any selection transistor is 0.9 × H _sg > H _sg −0.9 × ΔH _cell.
ΔH _cell > H _sg / 9
It becomes. That is, the lower limit value of the etch back amount (film thickness) ΔH _cell of the control gate electrode 401 is 1/9 times the film thickness H _sg of the upper gate electrode 402a (control gate electrode 401 before etch back) of the select transistor. The film thickness H _cell of the control gate electrode 401 after the back needs to be less than 8/9 times the film thickness H _sg of the upper gate electrode 402a of the selection transistor.

Further, the amount of dropping of the interpoly insulating film 205, the lower gate electrode 402b of the select transistor (the floating gate electrode 203 of the memory cell transistor), and the element isolation region 204 of the interpoly insulating film 205 also varies by about 10%. is there. In consideration of this, the condition that the silicide film formed on the gate electrode of the selection transistor does not reach the tunnel oxide film 202 is 1.1 × H _sg −0.9 × ΔH _cell + 1.1 × H _eb > 0. 9 (H _sg + H _ipd + H _fg )
ΔH _cell <2 × H _sg / 9 + 11 × H _eb / 9− (H _ipd + H _fg )
It becomes. This value is the upper limit value of the etch back amount (film thickness) ΔH _cell of the control gate electrode 401. That is, the lower limit value of the film thickness H _cell of the control gate electrode 401 after the etch back is 7 × H _sg / 9−11 × H _eb / 9 + H _ipd + H _fg .

The polysilicon film that becomes the lower gate electrode 402b of the selection transistor is an aggregate of granular polysilicon. There is a possibility that the silicidation proceeds downward (in the direction toward the tunnel oxide film 202) quickly so as to travel along the interface of the granular polysilicon, and the silicide film may come into contact with the tunnel oxide film 202. Therefore, the control gate electrode 401 may be etched back so that silicidation in the selection transistor stops when it contacts the interpoly insulating film 205 and does not enter the lower gate electrode 402b. In this case, the condition of the etch back amount is
1.1 × H _sg −0.9 × ΔH _cell + 1.1 × H _eb ≧ 0.9 × H _sg
ΔH _cell ≦ 2 × H _sg / 9 + 11 × H _eb / 9
It becomes. Therefore, 2 × H _sg / 9 + 11 × H _eb / 9 may be set as the condition for the upper limit value of the etch back amount (film thickness) ΔH _cell of the control gate electrode 401. At this time, the film thickness H _cell of the control gate electrode 401 after the etch back is 7 × H _sg / 9−11 × H _eb / 9.

  Note that since the transistor (peripheral transistor) in the peripheral circuit portion is formed in the same process as the selection transistor shown in FIGS. 2 to 12, the silicidation of the gate electrode 1302 is performed on the lower gate electrode 1302b as shown in FIG. It is part or up to part of the upper gate electrode 1302a and does not reach the tunnel oxide film 202. Since the peripheral transistor is larger than the selection transistor, a plurality of openings 1303 connecting the upper gate electrode 1302a and the lower gate electrode 1302b may be formed.

  Since the silicide film is formed after the control gate electrode of the memory cell transistor is etched back in this manner, the silicide film formed on the selection transistor and the peripheral transistor when the full silicidation of the control gate electrode of the memory cell transistor is completed. Does not come into contact with the tunnel oxide film, and a non-volatile semiconductor memory device in which occurrence of threshold variation due to threshold shift is suppressed can be manufactured. Further, by reducing the thickness of the control gate electrode, a nonvolatile semiconductor memory device in which the capacity between word lines is reduced and the operation speed is increased is obtained.

  (First Comparative Example) A method of manufacturing a nonvolatile semiconductor memory device according to the first comparative example will be described. Since the steps shown in FIGS. 2 to 6 are the same as those in the first embodiment, description thereof will be omitted.

  As shown in FIG. 14, the mask material 501 is removed, and the upper surfaces of the control gate electrode 401 and the upper gate electrode 402a are exposed.

  As shown in FIG. 15, a nickel film 1501 is formed on the entire surface.

  As shown in FIG. 16, the control gate electrode 401, the gate electrode 402, and the nickel film 1501, which are polysilicon films, are reacted by heat treatment to form nickel silicide films 1601 and 1602. The control gate electrode of the memory cell transistor is fully silicided. After full silicidation of the control gate electrode 401, the unreacted nickel film 1501 is removed by etching with a chemical solution.

  At this time, the nickel silicide film 1602 formed in the selection transistor may reach the tunnel oxide film 202 as shown in FIG. When the silicide film 1602 comes into contact with the tunnel oxide film 202, the work function of the gate electrode changes, resulting in a threshold variation due to a threshold shift, which degrades the device performance. This can occur not only in select transistors but also in peripheral transistors.

  As described above, the semiconductor memory device according to the first comparative example may cause a threshold variation, and the capacity increases due to the fact that the distance between the word lines is close due to the reduction in the wiring between the miniaturization, thereby reducing the operation speed. Have the problem of

  On the other hand, in the semiconductor memory device according to the first embodiment, since the control gate electrode of the memory cell transistor is lower than that of the selection transistor or the peripheral transistor, the capacity between word lines is reduced and the operation speed is increased. In addition, when full silicidation of the control gate electrode of the memory cell transistor is completed, the silicide film formed in the selection transistor and the peripheral transistor is prevented from coming into contact with the tunnel oxide film, and variation in threshold value due to threshold deviation occurs. Can be suppressed.

  (Second Embodiment) FIG. 17 shows a schematic configuration of a nonvolatile semiconductor memory device according to a second embodiment of the present invention. FIG. 17 shows a cross section along the bit line direction (arrow I in the figure) and a cross section along the word line direction (arrow II in the figure).

  Impurity diffusion layers 1702 are formed on the surface portion of the semiconductor substrate 1701 at a predetermined interval along the bit line direction (arrow I in the figure). A plurality of memory cell transistors 71 in which a tunnel oxide film 1703, a trap nitride film 1704, an interpoly insulating film 1705, and a control gate electrode 1706 are sequentially stacked are formed on the semiconductor substrate 1701 between the impurity diffusion layers 1702. The tunnel oxide film 1703 is, for example, a silicon oxide film, the trap nitride film 1704 is, for example, a silicon nitride film, and the interpoly insulating film 1705 is a high dielectric film, for example, a hafnium aluminate (HfAlO) film.

  In the memory cell transistor 71, a plurality of buried element isolation regions 1707 are formed in the semiconductor substrate 1701 at predetermined intervals along the word line direction (arrow II in the figure). The element isolation region 1707 is, for example, a silicon oxide film.

  A tunnel oxide film 1703 is formed on the semiconductor substrate 101 between the element isolation regions 1707, and a trap nitride film 1704 having the same height as the upper surface of the element isolation region 1707 is formed on the tunnel oxide film 1703. .

  An interpoly insulating film 1705 and a control gate electrode 1706 are sequentially formed on the trap nitride film 1704 and the element isolation region 1707.

  One select transistor 72 is formed at each end of the plurality of memory cell transistors 71 arranged in the bit line direction (only one end is shown in the figure). The select transistor 72 has a tunnel oxide film 1703 and a gate electrode 1708 formed on the tunnel oxide film 1703.

The control gate electrode 1706 of the memory cell transistor 71 is a nickel full silicide (FUSI) gate electrode. This is a metal-rich full silicide electrode having a composition ratio of nickel and silicon of 2: 1 (Ni ₂ Si) or 3: 1 (Ni ₃ Si). On the other hand, the gate electrode 1708 of the selection transistor 72 has a partial silicide structure having a nickel silicide film 1708a and a polysilicon film 1708b.

  An interlayer insulating film 1709 is formed on the semiconductor substrate 1701 between the memory cell transistors 71 and between the memory cell transistor 71 and the selection transistor 72.

  While the first embodiment has a stacked gate type memory cell structure of control gate electrode / interpoly insulating film / floating gate electrode / tunnel oxide film, this embodiment has a MONOS structure.

The upper surface of the control gate electrode 1706 of the memory cell transistor 71 is lower than the upper surface of the gate electrode 1708 of the selection transistor 72. Specifically, the film thickness H _cell of the control gate electrode 1706 of the memory cell transistor 71, the film thickness H _ipd of the interpoly insulating film 1705, the film thickness H _sin of the trap nitride film 1704, and the film thickness H _sg of the gate electrode 1708 , 0 <H _cell <8 × H _sg / 9−H _sin −H _ipd . The significance of the numerical value will be described later.

  This prevents the silicide film formed on the gate electrode 1708 of the selection transistor 72 from reaching the tunnel oxide film 1703 in the step of fully siliciding the control gate electrode 1706, thereby causing threshold variation due to threshold deviation. Can be suppressed. In addition, since the control gate electrode on the interpoly insulating film, which is a high dielectric film, is a metal-rich full silicide electrode, the “Fermi Level Pinning” phenomenon can be suppressed and the leakage resistance of the interpoly insulating film is improved. can do. In addition, by reducing the thickness of the control gate electrode, the capacity between word lines can be reduced and the operation speed of the memory cell can be increased.

  Next, the semiconductor device manufacturing method according to the present embodiment will be described with reference to process cross-sectional views shown in FIGS. The process sectional view shows (a) a vertical section along the bit line direction (corresponding to arrow I in FIG. 17) and (b) a vertical direction along the word line direction (corresponding to arrow II in FIG. 17) with respect to the same process. A vertical section in two directions of the section is shown.

  First, as shown in FIG. 18, a tunnel oxide film 1802 made of, for example, a silicon oxide film having a thickness of 5 nm is formed on a semiconductor substrate 1801 by chemical vapor deposition (CVD). A trap nitride film 1803 made of, for example, a silicon nitride film having a thickness of 5 nm is formed thereon by ALD, and then a semiconductor substrate 1801, a tunnel oxide film 1802, and a trap nitride film 1803 are formed along the bit line direction with a predetermined interval. Etching is performed by anisotropic etching such as RIE (reactive ion etching) to form a plurality of grooves T4. An element isolation region 1804 is formed by embedding, for example, a silicon oxide film in the plurality of trenches T4. After planarization, an interpoly insulating film 1805 made of, for example, a hafnium aluminate (HfAlO) film having a film thickness of 15 nm is formed on the entire surface by CVD.

  As shown in FIG. 19, a polysilicon film 1901 is deposited on the interpoly insulating film 1805 by a CVD method, and a polysilicon film 1901, an interpoly insulating film 1805, and a trap nitride film 1803 other than the region that will later become a memory cell transistor are formed. The resist is removed by RIE using a patterned resist (not shown).

  As shown in FIG. 20, a polysilicon film 2001 is deposited, and a mask material 2002 made of, for example, a silicon nitride film is formed on the polysilicon film 2001.

  As shown in FIG. 21, the mask material 2002, the polysilicon film 2001, and the tunnel oxide film 1802 are removed by RIE along the word line direction with a predetermined interval, and a plurality of trenches T5 exposing the surface of the semiconductor substrate 1801. Form. As a result, a word line is formed, and the shapes of the memory cell transistor 71 and the selection transistor 72 are determined. The polysilicon films 1901 and 2001 of the memory cell transistor 71 become the control gate electrode 2102, and the polysilicon film 2001 of the selection transistor 72 becomes the gate electrode 2103. After that, impurities are implanted into the semiconductor substrate 1801 and heat treatment is performed, so that a diffusion layer 2101 is formed.

  As shown in FIG. 22, for example, a silicon oxide film is formed by CVD to fill the trench T5, and planarization is performed by CMP (Chemical Mechanical Polishing) using the mask material 2002 as a stopper film, and an interlayer insulating film 2201 is formed. Form.

  As shown in FIG. 23, a resist 2301 is formed on the selection transistor 72. The resist 2301 is formed slightly larger than the selection transistor 72 in consideration of misalignment and the like.

  As shown in FIG. 24, the mask material 2002 on the memory cell transistor 71 is removed.

  As shown in FIG. 25, the control gate electrode (polysilicon film) 2102 is etched back using the resist 2301 as an etching mask. The etching method is, for example, CDE (Chemical Dry Etching). At this time, the interlayer insulating film 2201 is also removed somewhat. The etch back amount will be described later.

  As shown in FIG. 26, the resist 2301 and the mask material 2002 are removed. For removing the resist 2301, a process combining Ashing (ashing), SPM (sulfuric acid / hydrogen peroxide) cleaning, and APM (ammonia hydrogen peroxide) cleaning is used. In addition, the interlayer insulating film 2201 is etched so that the upper surface of the gate electrode of the selection transistor and the upper surface of the interlayer insulating film 2201 become flat.

  As shown in FIG. 27, a nickel film 2701 is formed on the entire surface.

As shown in FIG. 28, the control gate electrode (polysilicon film) 2102 and the nickel film 2701 are reacted by heat treatment to form a nickel silicide film 2801. The control gate electrode of the memory cell transistor is fully silicided. In the step shown in FIG. 27, the nickel film 2701 is formed thick (for example, with the same film thickness Hcell as the polysilicon film 2102) to form metal-rich full silicide. As a result, the composition of the control gate electrode becomes Ni ₂ Si or Ni ₃ Si.

  The height of the control gate electrode of the memory cell transistor is reduced by the process shown in FIG. Silicidation generally depends on the gate length, and the selection transistor is slower in silicidation than the memory cell transistor. Therefore, when full silicidation is completed, silicidation of the gate electrode 2103 of the selection transistor is up to a part of the gate electrode, and does not reach the tunnel oxide film 1802. After full silicidation of the control gate electrode, the unreacted nickel film 2701 is removed by etching with a chemical solution.

  After that, silicon nitride film, silicon oxide film deposition, silicon oxide film surface flattening, formation of contact hole exposing the upper surface of the control gate electrode, embedding of a conductive layer inside the contact hole, formation of a wiring layer, etc. A non-volatile semiconductor memory device is manufactured (not shown).

An etch back amount of the control gate electrode in the step shown in FIG. 25 will be described. The etch back amount (film thickness) of the control gate electrode 2102 is ΔH _cell , the film thickness of the interpoly insulating film 1805 is H _ipd , the film thickness of the trap nitride film 1803 is H _sin , and the film thickness of the gate electrode 2103 of the select transistor is H _sg , the thickness of the control gate electrode 2102 after the etch-back is H _cell (= H _sg −ΔH _cell −H _sin −H _ipd ).

  Silicidation generally depends on the gate length, and the selection transistor has a larger gate length than the memory cell transistor, and therefore silicidation is slow. Therefore, if the upper surface of the control gate electrode 2102 after the etch back is lower than the upper surface of the gate electrode 2103 of any selection transistor, it is formed on the gate electrode of the selection transistor when the full silicidation of the control gate electrode is completed. It is considered that the silicide film to be reached does not reach the tunnel oxide film 1802.

  There is a variation of about ± 10% in the film thickness of the gate electrode (control gate electrode before the etch back) of the selection transistor formed of the planarized polysilicon film formed by the CVD method. Further, the variation of the etch back amount of the control gate electrode (polysilicon film) is ± 10%.

Therefore, the condition that the upper surface of the control gate electrode after etch-back is lower than the upper surface of the gate electrode of any selection transistor is 0.9 × H _sg > H _sg −0.9 × ΔH _cell
ΔH _cell > H _sg / 9
It becomes. That lower limit value of the control etch-back amount of the gate electrode (film thickness) [Delta] H _cell is 1/9 times the thickness _{H sg} of the gate electrode of the selection transistor, the thickness _{H cell} control gate electrode after etch back, inter The total of the film thickness H _ipd of the poly insulating film 1805 and the film thickness H _sin of the trap nitride film 1803 only needs to be less than 8/9 times the film thickness H _sg of the gate electrode of the selection transistor.

Further, the film thicknesses of the interpoly insulating film 1805 and the trap nitride film 1803 have a variation of about ± 10%. In consideration of this, the condition that the silicide film formed on the gate electrode of the selection transistor does not reach the tunnel oxide film 1802 is 1.1 × H _sg −0.9 × ΔH _cell −0.9 (H _sin + H _ipd )> 0.9 × H _sg
ΔH _cell <2 × H _sg / 9− (H _ipd + H _sin )
It becomes. This value may be the upper limit value of the etch back amount (film thickness) ΔH _cell of the control gate electrode 401. That is, the total lower limit of the thickness H _cell of the control gate electrode after etch back, the thickness H _ipd of the interpoly insulating film 1805 and the thickness H _sin of the trap nitride film 1803 is 7 × H _sg / 9 + H _ipd + H _sin . is there.

However, H _sg / 9 <ΔH _cell <2 × H _sg / 9− (H _ipd + H _sin ) does not hold depending on the film thickness H _ipd of the interpoly insulating film 1805 and the film thickness H _sin of the trap nitride film 1803. In some cases. In that case, processing is performed to satisfy H _sg / 9 <ΔH _cell .

  Since the transistor (peripheral transistor) in the peripheral circuit portion is formed in the same process as the selection transistor shown in FIGS. 18 to 27, silicidation reaches only a part of the gate electrode and reaches the tunnel oxide film. No (not shown).

  Since the silicide film is formed after the control gate electrode of the memory cell transistor is etched back in this manner, the silicide film formed on the selection transistor and the peripheral transistor when the full silicidation of the control gate electrode of the memory cell transistor is completed. Does not come into contact with the tunnel oxide film, and a non-volatile semiconductor memory device in which occurrence of threshold variation due to threshold shift is suppressed can be manufactured.

  In addition, since the control gate electrode on the interpoly insulating film, which is a high dielectric film, is a metal-rich full silicide electrode, the “Fermi Level Pinning” phenomenon can be suppressed and the leakage resistance of the interpoly insulating film is improved. can do.

  Further, by reducing the thickness of the control gate electrode, a nonvolatile semiconductor memory device in which the capacity between word lines is reduced and the operation speed is increased is obtained.

  (Second Comparative Example) A method for manufacturing a nonvolatile semiconductor memory device according to a second comparative example will be described. Since the steps shown in FIGS. 18 to 22 are the same as those in the above embodiment, the description thereof is omitted.

  As shown in FIG. 29, the mask material is removed to expose the control gate electrode and the upper surface of the gate electrode, and then a nickel film 2901 is formed on the entire surface. The nickel film 2901 is made thick so that a metal-rich silicide electrode can be formed in a later process.

  As shown in FIG. 30, the control gate electrode, which is a polysilicon film, and the nickel film 2901 are reacted by heat treatment to form nickel silicide films 3001 and 3002. The control gate electrode of the memory cell transistor is fully silicided so as to be metal rich. After full silicidation of the control gate electrode, the unreacted nickel film 2901 is removed by etching with a chemical solution.

  At this time, as shown in FIG. 30, the nickel silicide film 3002 formed in the selection transistor reaches the tunnel oxide film 1802 by fully siliciding the control gate electrode of the memory cell transistor so as to be metal rich. There is. When the silicide film 3002 is in contact with the tunnel oxide film 1802, the work function of the gate electrode is changed, causing variation in threshold value due to threshold shift, thereby deteriorating device performance. This can occur not only in select transistors but also in peripheral transistors.

  As described above, in the semiconductor memory device according to the second comparative example, there is a possibility that threshold variation may occur, and the capacity increases due to the fact that the distance between the word lines is close due to the reduction in the wiring between the miniaturization, and the operation speed is reduced. Have the problem of

  On the other hand, in the semiconductor memory device according to the second embodiment, since the control gate electrode of the memory cell transistor is lower than that of the selection transistor and the peripheral transistor, the capacity between word lines is reduced and the operation speed is increased. In addition, since the control gate electrode on the interpoly insulating film, which is a high dielectric film, is a metal-rich full silicide electrode, the “Fermi Level Pinning” phenomenon can be suppressed and the leakage resistance of the interpoly insulating film is improved. can do. In addition, when full silicidation of the control gate electrode of the memory cell transistor is completed, the silicide film formed in the selection transistor and the peripheral transistor is prevented from coming into contact with the tunnel oxide film, and variation in threshold value due to threshold deviation occurs. Can be suppressed.

  In the above embodiment, the control gate electrode of the memory cell transistor is etched back to be lower than the selection transistor. At this time, although less than the control gate electrode, the interlayer insulating film between the memory cell transistors is also etched back. As a result, when an insulating film or the like is deposited on the cell array, the shape becomes undulating as shown in FIG. 31A, and there is a possibility that the processing becomes difficult in a flattening process in a later step. When etching back the control gate electrode, etching is performed under an etching condition with a high selection ratio of the control gate electrode (polysilicon film), and by suppressing the height of the interlayer insulating film between the memory cell transistors, As shown in FIG. 31 (b), the entire structure can be made flat.

  Each of the above-described embodiments is an example and should be considered not restrictive. For example, although nickel is used for the silicide metal material in the above embodiment, a metal belonging to Group 4 to 11 of transition metals such as Ti, Co, Pt, Pd, Ta, and Mo can be used.

  The technical scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a schematic configuration diagram of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. It is process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device by the said 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device by the said 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device by the said 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device by the said 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device by the said 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device by the said 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device by the said 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device by the said 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device by the said 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device by the said 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device by the said 1st Embodiment. It is a schematic block diagram of a peripheral transistor. It is process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device by a 1st comparative example. It is process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device by a 1st comparative example. It is process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device by a 1st comparative example. FIG. 4 is a schematic configuration diagram of a nonvolatile semiconductor memory device according to a second embodiment of the present invention. It is process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device by the 2nd Embodiment. It is process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device by the 2nd Embodiment. It is process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device by the 2nd Embodiment. It is process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device by the 2nd Embodiment. It is process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device by the 2nd Embodiment. It is process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device by the 2nd Embodiment. It is process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device by the 2nd Embodiment. It is process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device by the 2nd Embodiment. It is process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device by the 2nd Embodiment. It is process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device by the 2nd Embodiment. It is process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device by the 2nd Embodiment. It is process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device by the 2nd comparative example. It is process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device by the 2nd comparative example. It is a figure which shows the difference in the shape of the non-volatile semiconductor memory device in the post process by the difference in the height of an interlayer insulation film.

Explanation of symbols

1 memory cell transistor 2 selection transistor 101 semiconductor substrate 102 impurity diffusion layer 103 tunnel oxide film 104a floating gate electrode 104b lower gate electrode 105a interpoly insulating film 106a control gate electrode 106b upper gate electrode 107 element isolation region 108 opening 109 gate electrode 110 Interlayer insulation film

Claims (5)

A semiconductor substrate;
A plurality of first tunnel oxide films formed on the semiconductor substrate at predetermined intervals along a first direction; a plurality of floating gate electrodes formed on the plurality of first tunnel oxide films; A trench formed in a surface portion of the semiconductor substrate between the plurality of first tunnel oxide films, an element isolation region having an upper surface formed lower than an upper surface of the floating gate electrode, the floating gate electrode, and the floating gate electrode A plurality of interpoly insulating films formed in a strip shape along the first direction so as to cover the element isolation region, and a control gate electrode made of a metal silicide film formed on the interpoly insulating film. Memory cell transistors of
A second tunnel oxide film, a lower gate electrode, an insulating film including an opening, and an insulating film including an opening, which are respectively disposed at both ends of each of the plurality of memory cell transistors, and are sequentially stacked on the lower gate electrode. A select transistor having an upper gate electrode connected thereto;
With
When the thickness of the control gate electrode above the floating gate electrode is Hcell, the thickness of the upper gate electrode is Hsg, and the difference in height between the upper surface of the floating gate electrode and the upper surface of the element isolation region is Heb, A nonvolatile semiconductor memory device, wherein Hsg × 8/9> Hcell ≧ Hsg × 7 / 9−Heb × 11/9.   When the thickness of the interpoly insulating film is Hipd and the thickness of the floating gate electrode is Hfg, Hsg × 8/9> Hcell> Hsg × 7 / 9−Heb × 11/9 + Hipd + Hfg. The nonvolatile semiconductor memory device according to claim 1. A semiconductor substrate;
A plurality of first tunnel oxide films formed on the semiconductor substrate at predetermined intervals along a first direction; a plurality of trap nitride films formed on the plurality of first tunnel oxide films; A device isolation region having a groove formed in a surface portion of the semiconductor substrate between the plurality of first tunnel oxide films and having an upper surface formed at the same height as the upper surface of the trap nitride film; and the trap nitridation An interpoly insulating film formed in a strip shape along the first direction on the film and the element isolation region, and a control gate electrode made of a metal silicide film formed on the interpoly insulating film. A plurality of memory cell transistors;
A selection transistor having a second tunnel oxide film and a gate electrode formed on the second tunnel oxide film, one at each end of the plurality of memory cell transistors;
With
When the thickness of the control gate electrode is Hcell, the thickness of the gate electrode is Hsg, the thickness of the interpoly insulating film is Hipd, and the thickness of the trap nitride film is Hsin, 0 <Hcell <Hsg × 8 / 9-Hipd-Hsin, a nonvolatile semiconductor memory device.   4. The nonvolatile semiconductor memory device according to claim 3, wherein the metal silicide film constituting the control gate electrode has a composition ratio of silicon atoms to metal atoms of ½ or less.   5. The metal silicide film according to claim 3, wherein the metal silicide film is any one of a nickel silicide film, a titanium silicide film, a cobalt silicide film, a platinum silicide film, a tantalum silicide film, a palladium silicide film, and a molybdenum silicide film. Nonvolatile semiconductor memory device.

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