JP2008293654A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simplify designing and manufacturing by requiring only one chip for flash memories with or without a boot block. <P>SOLUTION: Blocks B000 to B007 are boot and parameter blocks of storage capacities smaller than that of a normal block. When no boot block is necessary, a signal BOOTE is set to an L level by a bonding option or the like. When a signal BLKSEL is at an H level during erasure, a control unit 2 simultaneously selects four blocks arrayed in a horizontal direction. In this case, the control unit 2 simultaneously selects two blocks of a longitudinal direction. Thus, eight blocks of B000 to B007 are selected. The boot and parameter blocks are collectively erasable as one block having a capacity equal to that of a normal block. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a flash memory whose erasure unit block configuration can be changed.

  Functionally, the flash memory is a batch erasing type electrically erasable nonvolatile semiconductor memory device. Flash memory has a great demand for portable devices because of its low cost and electrical erasing function, and research and development has been actively conducted in recent years. A flash memory uses, for example, a transistor having a floating gate and capable of changing a threshold voltage (hereinafter referred to as a memory transistor) as a memory cell.

FIG. 26 is a diagram showing an array configuration of a conventional flash memory.
In FIG. 26, in order to simplify the description, the case of an 8 Mbit memory array as a whole is described. The memory array 500 includes blocks B000 to B007 each including memory cells corresponding to 4k words (64k bits), and blocks B008 to B022 each including memory cells corresponding to 32k words (512k bits). , Block B100. Each of the blocks B000 to B022 is a block that is a basic unit of an erase operation in the flash memory.

  A flash memory often requires an area of 4k words. For this reason, the memory array 500 includes blocks B000 to B007 having a smaller storage capacity than a normal data storage area. Such a 4k word region is called, for example, a boot block or a parameter block.

  The boot block is an area that is read by the CPU of the system in which the flash memory is mounted when the system is started up immediately after the power is turned on. The parameter block is an area in which data that is likely to be frequently rewritten is temporarily written. On the other hand, a block with a storage capacity of 32k words is used as an area for storing normal data and programs. Thus, in the flash memory, it is necessary to provide blocks of different sizes depending on applications.

  The block B100 is an area corresponding to the blocks B000 to B007 in terms of address allocation, and is an unused area. Even if it is not used, the memory block B100 has the same configuration as each of the blocks B008 to B022 because it is necessary to maintain continuity of signals on the memory array.

  The selection of the memory block is performed by block selection signals BAVS0, BAVS1, BAVM0 to BAVM3 for selecting the vertical position of the block, and block selection signals BAH0 to BAH3 for selecting the horizontal position of the block. . When both the vertical block position and the horizontal block position are activated, the block corresponding to the intersection is selected. For example, when selecting block B008, selection signals BAVM0 and BAH1 are activated and the remaining selection signals are deactivated.

  FIG. 27 is a block diagram showing a configuration of a conventional block selection decoder for generating a memory block selection signal.

  Referring to FIGS. 26 and 27, block selection decoder 502 generates block selection signals BAVS0, BAVS1, BAVM0-BAVM3, BAH0-BAH3 using address bits A12-A18 of an externally applied address signal. The block selection decoder 502 receives the address bits A15, A16, A17, A18 and outputs a selection signal BOP. The block selection decoder 502 has a vertical position corresponding to the address bits A14, A17, A18 and the selection signal BOP. A vertical block selection circuit 564 that outputs selection signals BAVS0, BAVS1, BAVM0 to BAVM3, and a horizontal direction that outputs selection signals BAH0 to BAH3 in the horizontal direction according to address bits A12, A13, A15, A16 and selection signal BOP. And a block selection circuit 566.

  The vertical block selection circuit 564 is activated in response to the selection signal BOP, decodes the address bit A14 and outputs the signals BAVS0 and BAVS1, and operates when the selection signal BOP is inactive. And an address decode unit 584 that stops its operation when the BOP is activated. Address decoder 584 decodes address bits A17 and A18 and outputs signals BAVM0 to BAVM3 when activated.

  When the selection signal BOP is activated, the horizontal block selection circuit 566 outputs the address bits A12 and A13 as the selection address bits SA0 and SA1, and when the selection signal BOP is inactivated, the address bits A15 and A16 are output as the selection address bits. An address selection unit 610 that outputs as SA0 and SA1 and an address decoding unit 612 that decodes the selected address bits SA0 and SA1 and outputs signals BAH0 to BAH3 are included.

  In the case of the 8-Mbit memory array shown in FIG. 26, when a 1-word 16-bit configuration is used, the address bits for selecting a 32k word block are A15, A16, A17, and A18. The address bits for selecting the 4k word block are A12, A13, and A14. In the conventional example described here, a case where four memory blocks are arranged in the horizontal direction as shown in FIG. 26 will be described.

  First, the NOR circuit 562 determines whether the signal BOP for selecting the 4k word region is active / inactive.

  When an address corresponding to memory blocks B008 to B022 is input, signal BOP is deactivated, address decoding unit 582 deactivates signals BAVS0 and BAVS1, and address decoding unit 584 responds to address bits A17 and A18. Any one of the selection signals BAVM0 to BAVM3 in the vertical memory block is activated.

  In this case, since the address selection unit 610 outputs the address bits A15 and A16 as the selection address bits SA0 and SA1, the address decoding unit 612 decodes the address bits A15 and A16 and outputs one of the selection signals BAH0 to BAH3. Activate.

  On the other hand, when all of address bits A15 to A18 are at L level, selection signal BOP is activated. This indicates that there was an address input corresponding to the memory block B100 which is not used in FIG. In this case, instead of selecting the memory block B100, the corresponding area of the memory blocks B000 to B007 is selected. Specifically, when signal BOP is activated, address decode unit 584 is deactivated and signals BAVM0 to BAVM3 are deactivated. The address decoding unit 582 decodes the address bit A14 and activates one of the signals BAVS0 and BAVS1.

  Further, when the signal BOP is activated, the address selection unit 610 outputs the address bits A12 and A13 as the selection address bits SA0 and SA1, so that the address decoding unit 612 decodes the address bits A12 and A13 and outputs the signals BAH0 to BAH3. Either one is activated.

  Conventionally, block division and address assignment determined by the block selection decoder 502 have always been fixed. That is, the area of 8M bits has always been treated as a total of 23 blocks of 8 blocks of 4k word blocks and 15 blocks of B008 to B022 of 32k word blocks.

  As described above, the memory array 500 of FIG. 26 has 23 memory blocks B000 to B022, and therefore, in order to erase the entire 8-Mbit memory array, 23 erase operations are performed outside the chip. Need to tell more.

  In FIG. 26, 4k word blocks, 8 blocks, that is, blocks B000 to B007 are assigned to the lowest address. This is called a bottom boot type. However, depending on the system used, a top boot type flash memory in which a block of 4k words is allocated to the highest side of the address may be required. Conventionally, in order to change a bottom boot type memory to a top boot type memory for use, a specific address bit is inverted in an address input buffer.

FIG. 28 is a circuit diagram showing a configuration of a conventional address input buffer 516.
Referring to FIG. 28, address input buffer 516 is an address for switching normal rotation / inversion of address bits A15, A16, A17 in accordance with signal TOP activated when switching to a top boot type memory. Inversion circuits 520, 522, and 524 are included.

  Address inversion circuit 520 has an address bit ext. Inverter 526 receiving and inverting signal A15, inverter 528 receiving and inverting signal TOP, NAND circuit 530 receiving the output of inverter 526 and signal TOP, address bit ext. NAND circuit 532 that receives A15 and the output of inverter 528, and NAND circuit 534 that receives the outputs of NAND circuits 530 and 532 and outputs address bit A15.

  Address inversion circuit 522 has address bits ext. The difference is that A16 is input and address bit A16 is output, but the internal configuration is the same as that of address inverting circuit 520, and description thereof will not be repeated. Address inversion circuit 524 has address bits ext. The difference is that A17 is input and address bit A17 is output, but the internal configuration is the same as that of address inverting circuit 520, and description thereof will not be repeated.

FIG. 29 is a diagram showing an array configuration of another conventional flash memory.
Referring to FIG. 29, blocks B000 to B015 are memory blocks each composed of memory cells corresponding to 32k words (512k bits). In the memory array 700, there is no memory block composed of memory cells corresponding to 4k words, and an 8M bit area is composed of 16 blocks all composed of memory cells corresponding to 32k words. In the case of the memory array 500 of FIG. 26, the erase operation of 23 times is necessary for erasing the 8M bit region, but in the case of the memory array 700, the erase operation of 16 times is sufficient for erasing the 8M bit region. .
JP 2002-133877 A

  Conventionally, block division and address assignment to each block have always been fixed. As a result, for example, as described with reference to FIG. 26, an 8M-bit flash memory product has a specification having 4k word blocks, and there are 23 blocks of 8 blocks of 4k word blocks and 15 blocks of 32k word blocks. To do.

  On the other hand, as described with reference to FIG. 29, in the flash memory product having no 4k word block, the 32M word block 16 blocks constitute 8M bits. In other words, it is necessary to design and manufacture a completely different product with or without 4k words.

  As the capacity of the flash memory is increased, a chip having a 4k word block boot block has been developed on both the lowest address side and the highest address side as well as the highest address side or the lowest address side. . Such a chip is called a dual boot type chip. When a dual-boot type chip is used as a large memory space by combining two chips, there is a problem in that a 4k-word block is present in the center of the address space, resulting in poor usability.

  The present invention has been made to solve the above problems. According to the present invention, a flash memory having a 4k word block and a flash memory not having a 4k word block in a flash memory including a block having a small storage capacity, for example, a boot block, which are divided into a plurality of erase blocks, are simultaneously realized on one chip. The purpose is to simplify the design and manufacture.

  In summary, the present invention is a non-volatile semiconductor memory device, and includes a first basic memory block, a plurality of second basic memory blocks, which are a unit for batch erase, and an erase control circuit. Each of the plurality of second basic memory blocks has a smaller storage capacity than the first basic memory block, and serves as a unit for batch erasure. The erase control circuit erases one of the plurality of second basic memory blocks in response to the erase command and the plurality of second basic memory blocks in response to the erase command. The second operation is switched according to the switching signal.

  A non-volatile semiconductor memory device according to another aspect of the present invention includes a first basic memory block serving as a unit for batch erase, a plurality of second basic memory blocks, and an erase control circuit. Each of the plurality of second basic memory blocks has a smaller storage capacity than the first basic memory block, and serves as a unit for batch erasure. The erase control circuit erases one of the plurality of second basic memory blocks according to the erase command, and a second operation erases the first basic memory block according to the erase command Are switched according to the switching signal.

  According to the present invention, there are a plurality of types of non-volatile semiconductor memory devices, one having a small block as an erasing unit and one having a small block as an erasing unit when the switching signal is applied. This can be realized, and the development costs and manufacturing management costs of multiple products can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

[Embodiment 1]
FIG. 1 is a schematic block diagram showing the configuration of the nonvolatile memory device according to Embodiment 1 of the present invention.

  Referring to FIG. 1, nonvolatile semiconductor memory device 1 includes an input / output data buffer 22, a control unit 2 for controlling writing, reading and erasing, a row / column decoder 20, a Y gate 24, a memory Array 26.

  Input / output data buffer 22 receives signals DQ0 to DQ15 from the outside of the chip at the time of writing, and outputs signals DQ0 to DQ15 to the outside of the chip at the time of reading.

  The control unit 2 includes a program & verify circuit 4, a sense amplifier 6, an internal controller 8, an address buffer 16, a predecoder 18, and a switching signal generation circuit 10. The internal controller 8 receives control signals such as signals CE, WE, OE, RP, and WP from the outside and recognizes instructions given from the outside, and controls the address buffer 16, predecoder 18 and program & verify circuit 4. Do. The internal controller 8 releases the reset after activating the power-on reset signal POR output to the switching signal generation circuit 10 when the power is turned on to the chip for a certain period.

  The switching signal generation circuit 10 outputs a signal BOOTE according to a predetermined setting. The address buffer 16 is provided with address bits ext. A0-ext. In response to A18, address bits A0 to A18 are output to predecoder 18. The predecoder 18 is switched in operation by a control signal such as the signal BLKSEL supplied from the internal controller 8 and a signal BOOTE supplied from the switching signal generation circuit 10, and changes the decoding result of the address bits A0 to A18. The predecoder 18 outputs the decoding result to the row / column decoder 20.

  Memory array 26 includes memory blocks B000-B007 having a storage capacity of 4k words and memory blocks B008-B022, B100 each having a storage capacity of 32k words. However, the memory block B100 is an area that is not normally used, but has the same configuration as the memory blocks B008 to B022 in order to maintain the continuity of the pattern for the convenience of manufacturing the memory array.

  Blocks B000 to B007 are boot blocks and parameter blocks having a smaller storage capacity than normal blocks. When the boot block is unnecessary, the signal BOOTE is set to L level by a bonding option or the like. When the signal BLKSEL is at the H level at the time of erasing, the control unit 2 performs simultaneous selection of four blocks arranged in the horizontal direction. At this time, the control unit 2 simultaneously selects two blocks in the vertical direction. As a result, eight blocks B000 to B007 are selected. The boot block and the parameter block can be collectively erased as one block having the same capacity as the normal block.

  FIG. 2 is a cross-sectional view for explaining the memory transistors MT arranged in a matrix in each memory block of the memory array 26.

  Referring to FIG. 2, memory transistor MT includes a source S and a drain D, which are impurity regions formed on substrate SUB, and a floating gate F formed above a region between source S and drain D, And a control gate G formed above the floating gate F.

  By changing the voltage VG applied to the control gate, the voltage VS applied to the source, the voltage VD applied to the drain, and the voltage VWELL applied to the substrate to predetermined conditions, the amount of charge charged in the floating gate F of the memory transistor MT is changed. As a result, the threshold voltage of the memory transistor MT changes, so that the memory transistor MT can store information given by the value of the threshold voltage.

FIG. 3 is a circuit diagram showing a configuration of switching signal generation circuit 10 in FIG.
Referring to FIG. 3, switching signal generating circuit 10 includes a resistor 32 connected between pad 56 to which signal #NOBOOT is applied and node N2, and between pad 58 to which signal #BOOT is applied and node N1. Input to node N2, a capacitor 36 connected between node N1 and a node to which power supply potential VCC is applied, a capacitor 42 connected between node N2 and the ground node, and an input to node N2. An inverter 38 connected to the output of the node N1, an inverter 40 having an input connected to the node N1 and an output connected to the node N2, an inverter 44 having an input connected to the node N2, and an output of the inverter 44 And an inverter 46 that receives and inverts and outputs a signal BOOTE.

  FIG. 4 is a diagram for explaining a bonding option for the switching signal generation circuit of FIG.

  FIG. 5 is a diagram for explaining the relationship between the setting state of signals #NOBOOT and #BOOT and the signal BOOTE for switching.

  Referring to FIGS. 4 and 5, when pad 56 to which signal #NOBOOT is applied is set to L level, lead 52 and pad 56 to which ground potential is applied among a plurality of leads existing around chip 50. Are connected by a wire 54. In this case, the pad 58 is not connected to any lead, or is connected to a lead to which a power supply potential is applied by another wire. With this setting, the signal BOOTE for switching is set to the L level.

  When the signal BOOTE is set to L level, the memory blocks B000 to B007 in FIG. 1 can be collectively erased as one block having a storage capacity of 32k words by one instruction. When the boot block is not necessary, the bonding option is selected in this way to shorten the erase time, and the nonvolatile semiconductor memory device is produced.

  On the other hand, when the lead 52 and the pad 58 are connected by the wire 55 instead of being connected by the wire 54, the signal #BOOT is set to the L level. In this case, the pad 56 may be connected to a lead to which a power supply potential is applied using another wire or may be in an unconnected state. With this setting, the signal BOOTE for switching is set to the H level.

  When signal BOOTE is set to H level, this corresponds to the case where a boot block is required, and each of memory blocks B000 to B007 is handled as the basis of the erase unit.

FIG. 6 is a block diagram for explaining the configuration of the predecoder of FIG.
Referring to FIG. 6, predecoder 18 receives address bits A15, A16, A17, A18 and outputs 4-bit NOR circuit 62, and receives signals BOOTE, BLKSEL and BOP as control signals, and address bit A14. , A17, A18 in accordance with vertical block selection circuit 64 for outputting signals BAVS0, BAVS1, BAVM0-BAVM3 for selecting vertical block positions, and signals BOOTE, BLKSEL and BOP as control signals, and address bits A12, A horizontal block selection circuit 66 for outputting signals BAH0 to BAH3 for selecting horizontal block positions based on A13, A15, and A16, and a predecode signal PDROW related to row selection in response to address bits A6 to A15. Prede to output And over de circuit 68, and a predecode circuit 70 which outputs a pre-decode signal PDCOL about columns selected based on the address bits A0-A5.

  Row decoder 72 selects a row based on signals BAVS0, BAVS1, BAVM0-BAVM3, signals BAH0-BAH3, and predecode signal PDROW. Column decoder 74 performs column selection based on signals BAH0 to BAH3 and predecode signal PDCOL.

  The signal BOOTE given as a control signal is a signal generated by the switching signal generation circuit 10 of FIG. 1, and is set to the H level when a 4k word boot block is required. The signal BLKSEL is an output signal of the internal controller 8 in FIG. 1, and is a signal for controlling the simultaneous selection operation of a plurality of blocks.

FIG. 7 is a circuit diagram for explaining the configuration of the vertical block selection circuit of FIG.
Referring to FIG. 7, vertical block selecting circuit 64 has an address decode unit 82 that outputs signals BAVS0 and BAVS1 in response to address bit A14, and an address that outputs signals BAVM0 to BAVM3 in response to address bits A17 and A18. A decoding unit 84.

  The address decoding unit 82 outputs a signal at H level when the signal BLKSEL is at H level and the signal BOOTE is at L level, and outputs a signal at L level in other cases, and the signal BOOTE A gate circuit 88 that outputs an H level signal when the address bit A14 is at the H level and outputs an L level signal when the address bit A14 is at the L level, and an AND circuit 90 that receives the signal BOOTE and the address bit A14 Including.

  Address decode unit 82 further includes an OR circuit 92 that receives the outputs of gate circuits 86 and 88, an OR circuit 94 that receives the outputs of gate circuit 86 and AND circuit 90, the output of OR circuit 92, and signal BOP. And an AND circuit 96 that outputs the signal BAVS0 and an AND circuit 98 that receives the output of the OR circuit 94 and the signal BOP and outputs the signal BAVS1.

  Address decoder 84 receives signal BOP and address bits A17 and A18 and outputs signal BAVM0, and is activated when signal BOP is at L level, and address bit A17 is at H level. A gate circuit 104 that activates the signal BAVM1 when the address bit A18 is at the L level, and a gate that activates the signal BAVM2 when the address bit A17 is at the L level and the address bit A18 is at the H level. Circuit 106 and AND circuit 108 which receives address bits A17 and A18 and outputs signal BAVM3.

  The signal BOP is not input to the gate circuit 106 and the AND circuit 108 because when the address bit A18 is at the H level, the BOP is set to the L level by the NOR circuit 62 of FIG. Because.

  When the signal BOOTE is at the H level, the operation of the vertical block selecting circuit 64 is exactly the same as that of the conventional vertical block selecting circuit. Even when the signal BOOTE is at the L level and the signal BLKSEL is at the L level, the operation of the vertical block selecting circuit 64 is exactly the same as that of the conventional vertical block selecting circuit.

  When the signal BOOTE is at the L level and the signal BLKSEL is at the H level, the signals BAVS0 and BAVS1 are both at the H level regardless of whether the address bit A14 is at the L level or the H level. Two blocks are simultaneously selected.

FIG. 8 is a circuit diagram showing a configuration of the horizontal block selection circuit in FIG.
Referring to FIG. 8, horizontal block selecting circuit 66 selects address bits A12 and A13 as selected address bits SA0 and SA1 or address bits A15 and A16 as selected address bits SA0 and SA1 according to signal BOP. Address selection unit 110 that determines whether to select, address decoding unit 112 that decodes selected address bits SA0 and SA1, and output unit 114 that determines whether or not the output of address decoding unit 112 is valid are included. .

  Address selection unit 110 receives inverter B 116 that receives and inverts signal BOP, NAND circuit 118 that receives address bit A 12 and signal BOP, NAND circuit 120 that receives address bit A 15 and the output of inverter 116, and NAND circuit 118. , 120 and a NAND circuit 122 that outputs a selected address bit SA0.

  The address selection unit 110 further receives a NAND circuit 124 that receives the address bit A13 and the signal BOP, a NAND circuit 126 that receives the output of the address bit A16 and the inverter 116, and a selection address that receives the outputs of the NAND circuits 124 and 126. NAND circuit 128 that outputs bit SA1.

  The address decoding unit 112 detects the case where both of the selected address bits SA0 and SA1 are at the L level, and when the selected address bit SA0 is at the H level and the selected address bit SA1 is at the L level. , A decode gate circuit 132 for detecting that the selected address bit SA0 is at L level and a selected address bit SA1 is at H level, and both of the selected address bits SA0 and SA1 are at H level. And a decode gate circuit 136 for detecting the presence of the data.

  The output unit 114 receives the signal BAH0 in response to the gate circuit 138 that detects that the signals BLKSEL and BOP are both at the H level and the signal BOOTE is at the L level, the output of the gate circuit 138, and the output of the decode gate circuit 130. OR circuit 140 that outputs the signal, the OR circuit 142 that receives the output of the gate circuit 138 and the output of the decode gate circuit 132 and outputs the signal BAH1, the output of the gate circuit 138, and the output of the decode gate circuit 134 An OR circuit 144 that outputs signal BAH2 and an OR circuit 146 that receives the output of gate circuit 138 and the output of decode gate circuit 136 and outputs signal BAH3 are included.

  When the signal BOOTE is at the H level, the operation of the horizontal block selection circuit 66 shown in FIG. 8 is exactly the same as that of the conventional horizontal block selection circuit. Even when the signal BOOTE is at the L level and the signal BLKSEL is at the L level, the operation of the horizontal block selecting circuit 66 is exactly the same as that of the conventional horizontal block selecting circuit.

  When the signal BOOTE is at the L level and the signal BLKSEL is at the H level, the signals BAH0, BAH1, BAH2, and BAH3 are all at the H level regardless of whether the address bits A12 and A13 are at the L level or the H level. Thus, simultaneous selection of four blocks arranged in the horizontal direction is performed. At this time, in the vertical direction block selection circuit of FIG. 7, both the signals BAVS0 and BAVS1 are at the H level regardless of whether the address bit A14 is at the L level or the H level, and simultaneous selection of two vertical blocks is performed. As a result, eight blocks B000 to B007 are selected as a result.

  FIG. 9 is a flowchart for explaining an operation flow at the time of block erasing of the internal controller in FIG.

  Referring to FIG. 9, a block-unit erase operation characteristic of the flash memory according to the first embodiment will be described.

  Flash memory is characterized by performing block erasing in batches. However, in the flow of the erase operation, the pulse is applied to the memory cells in the entire block at once by the block collective write in step S2 and the application of the block collective erase pulse 1 executed in step S4. The block batch soft writing performed in step S5 and the block batch erase pulse 2 applied in step S7. Note that the block collective soft writing is weak collective writing in which the pulse application time is shortened or the voltage of the pulse to be applied is suppressed to be lower than the writing performed in step S2.

  In the present invention, during the execution of the four steps S2, S4, S5, and S7, eight 4k word blocks B000 to B007 are converted into the vertical block selection circuit 64 shown in FIG. 7 and the horizontal direction shown in FIG. The block selection circuit 66 allows simultaneous selection. In these four steps, eight 4k word blocks can be handled as one main block (32k word block).

  The operation flow of FIG. 9 will be described in order. When an address corresponding to the erase command is input from the outside, the erase operation is started in step S1. In step S2, batch writing is instructed to a block to be erased. The internal controller 8 sets the signal BLKSEL to the H level when executing step S2. As a result, a plurality of blocks are simultaneously selected, and when 4k words are set not to be used, memory blocks B000 to B007 in FIG. 1 are simultaneously selected and a write pulse is applied collectively.

  This signal BLKSEL is set to H level only in the step of applying a pulse to the memory cells in the erase block at once. That is, in addition to the execution of step S2, it is set to the H level when executing steps S4, S5 and S7, and is set to the L level in other cases.

  In step S3, erase verify 1 is performed. Erase verify 1 is an operation for confirming whether or not the threshold voltage of the memory transistor of the specified memory block is a threshold voltage corresponding to a predetermined erase state. If the predetermined erase state has not been reached, the erase verify is failed and the process proceeds to step S4, where a block batch erase pulse is applied to the erase target block. When the application of the erase pulse in step S4 is completed, the process proceeds to step S3 again and erase verify 1 is executed.

  When the erase verify 1 is passed in step S3, the process proceeds to step S5 and block batch software writing is executed. In step S6, erase verify 2 is executed. If the erase verify 2 has not been completed, the process proceeds to step S7 where the block collective erase pulse 2 is applied to the selected block. In step S6, erase verify 2 is executed again.

  If erase verify 2 passes in step S6, over erase verify for detecting an over erase state is performed in step S8. Over-erasing is that the threshold voltage of the memory transistor changes beyond a predetermined range by applying an erase pulse.

  When overerasure is detected and overerase verify fails, an overerase recovery operation is performed in step S9. In step S10, the lower limit value of the threshold voltage Vth is verified, that is, verified. If the result is a failure, the process returns to step S9. If the verify result is a pass in step S10, over-erase verification is performed again in step S8. If the result is “pass” in step S8, the process proceeds to step S11 to complete the block erase operation.

[Modification of switching signal generation circuit]
FIG. 10 is a circuit diagram for explaining a first modification of the switching signal generating circuit explained in FIG.

  Referring to FIG. 10, switching signal generating circuit 10A includes a resistor 156 connected between pad 152 to which signal #BOOT is applied and node N3, an inverter 154 which receives and inverts power-on reset signal POR, P channel MOS transistor 158 connected between the power supply node and node N3 and receiving the output of inverter 154 at the gate, and capacitor 160 connected between the power supply node and node N3 are included.

  Switch signal generating circuit 10A further includes an inverter 164 having an input connected to node N3 and an output connected to node N4, and a P-channel MOS connected between a power supply node and node N3 and having a gate connected to node N4. Transistor 162, capacitor 166 connected between node N4 and the ground node, inverter 168 whose input is connected to node N4, and inverter 170 which receives and inverts the output of inverter 168 and outputs signal BOOTE Including.

FIG. 11 is a diagram for explaining setting and output of the switching signal generating circuit shown in FIG.
Referring to FIG. 11, when pad 152 is connected to a lead to which a ground potential is applied by the wire bonding option, signal #BOOT is set to L level, and signal BOOTE is set to H level accordingly.

  On the other hand, when pad 152 is connected to a lead receiving a power supply potential by a wire, or in a state where it is opened and not connected to the lead, signal BOOTE is set to L level. In this way, the switching signal generation circuit 10 may be modified.

FIG. 12 is a circuit diagram showing a second modification of the switching signal generating circuit.
Referring to FIG. 12, switching signal generating circuit 10B includes an inverter 172 that receives and inverts power-on reset signal POR, and a P-channel MOS that is connected between a power supply node and node N5 and receives the output of inverter 172 at its gate. Transistor 174, fuse element 176 connected between nodes N5 and N6, which can be cut by a laser beam, and N-channel MOS transistor 178 connected between node N6 and the ground node and receiving the output of inverter 172 at its gate Including.

  Switch signal generating circuit 10B further includes an inverter 182 having an input connected to node N5 and an output connected to node N7, and a P-channel MOS connected between a power supply node and node N5 and having a gate connected to node N7. Transistor 174, inverter 184 that receives and inverts the output of inverter 172, NOR circuit 186 that receives the output of inverter 182 and the output of inverter 184, inverter 188 that receives and inverts the output of NOR circuit 186, and inverter 188 And an inverter 190 that inverts and outputs a signal BOOTE.

  FIG. 13 is a diagram for explaining the relationship between the state of the fuse element and the signal BOOTE that controls switching.

  Referring to FIGS. 12 and 13, when fuse element 176 is cut by a laser beam, node N5 is held at H level and node N7 is at L level. Then, after the power-on reset is released, the output of the inverter 184 also becomes L level. Then, signal BOOTE for switching control is set to H level.

  On the other hand, when fuse element 176 is in a conductive state, node N5 is set to L level and node N7 is set to H level when the power-on reset is released. Then, since the output of NOR circuit 186 becomes L level, signal BOOTE for switching is set to L level.

  A semiconductor memory device such as a nonvolatile semiconductor memory device often has a step of cutting a fuse element in order to replace a redundant memory cell when a defective memory cell exists. Accordingly, if the fuse element of the switching signal generating circuit is cut in this cutting step, the setting of the switching signal can be changed without preparing a special device.

FIG. 14 is a circuit diagram showing a third modification of the switching signal generating circuit.
Referring to FIG. 14, switching signal generation circuit 10C includes an inverter 192 that receives and inverts power-on reset signal POR, and a P-channel MOS that is connected between the power supply node and node N8 and receives the output of inverter 192 at its gate. A transistor 196, a switch 198 that selectively couples node N8 and power supply potential HVCC higher than the normal power supply potential to N9, a memory transistor 200 connected between nodes N9 and N10, and node N10 And a switch 202 connected between the memory node 200 and the ground node, and a switch 194 for controlling the control gate of the memory transistor 200.

  The memory transistor 200 has the same configuration as the memory transistor included in the memory array of the nonvolatile semiconductor memory device of the present invention. Therefore, it is possible to provide the memory transistor 200 in the switching signal generation circuit 10C by changing the pattern design without adding a new process. Switches 198, 194 and 202 are provided for controlling the control gates of node N9, node N10 and memory transistor 200 in accordance with an erase command or a program command in a predetermined test mode. In this predetermined test mode, the contents held in the floating gate of the memory transistor 200 are set.

  After the storage contents of the memory transistor 200 are set, the switch 194 applies the output of the inverter 192 to the control gate of the memory transistor 200, the switch 198 connects the node N8 and the node N9, and the switch 202 connects the node N10 to the ground node. Connecting.

  Switch signal generating circuit 10C further includes an inverter 206 having an input connected to node N8 and an output connected to node N10, and a P-channel MOS connected between a power supply node and node N8 and having a gate connected to node N10. Transistor 204, inverter 208 that receives and inverts the output of inverter 192, NOR circuit 210 that receives the output of inverter 206 and the output of inverter 208, inverter 212 that receives and inverts the output of NOR circuit 210, and inverter 212 And an inverter 214 that inverts and outputs a signal BOOTE.

  FIG. 15 is a diagram showing the relationship between the threshold voltage set in the memory transistor of the switching signal generation circuit of FIG. 14 and the signal BOOTE.

  Referring to FIGS. 14 and 15, when threshold voltage Vth of memory transistor 200 is higher than a predetermined voltage, memory transistor 200 is rendered non-conductive even when the output of inverter 192 is activated. Accordingly, in FIG. 12, the state is the same as the state in which fuse element 176 is cut, and signal BOOTE is set to the H level accordingly.

  On the other hand, when threshold voltage Vth of memory transistor 200 is lower than a predetermined value, when the output of inverter 192 becomes H level, memory transistor 200 becomes conductive and node N9 is connected to node N10. Therefore, the signal BOOTE is set to the L level as in the case where the fuse element 176 is conductive in the circuit of FIG.

  As described above, since the process flow for manufacturing the nonvolatile memory cell is applied in the present invention, a manufacturing process is added even if a memory transistor similar to the nonvolatile memory cell is used to set the signal BOOTE. The switching signal can be suitably generated without any problem.

[Modification of Embodiment 1]
In the above embodiment, the configuration in which a plurality of blocks are simultaneously erased by one instruction by selecting a plurality of block selections simultaneously when a certain pulse is applied in the predecoder 18 of FIG. 1 has been described. A similar operation can be executed when viewed from the outside by sequentially erasing a plurality of blocks in response to a single external instruction.

  FIG. 16 is a block diagram for explaining a configuration of a nonvolatile semiconductor memory device according to a modification of the first embodiment.

  Referring to FIG. 16, nonvolatile semiconductor memory device 221 includes a control unit 2 </ b> A instead of control unit 2 in the configuration of nonvolatile semiconductor memory device 1 described with reference to FIG. 1. The control unit 2A includes an internal controller 8A and a predecoder 18A in place of the internal controller 8 and the predecoder 18 in the configuration of the control unit 2 of FIG. The configuration of the other part of nonvolatile semiconductor memory device 221 is similar to that of nonvolatile semiconductor memory device 1 shown in FIG. 1, and therefore description thereof will not be repeated.

  Predecoder 18A performs the same operation as the conventional block selection operation described in FIG.

  FIG. 17 is a flow chart for explaining the erase operation of the internal controller in FIG.

  Referring to FIG. 17, internal controller 8A starts an erasing operation in step S21 when it receives an erasing instruction for a predetermined block by a control signal from the outside.

  In step S22, batch writing is instructed to the block to be erased. In step S23, erase verify 1 is performed. Erase verify 1 is an operation for confirming whether or not the threshold voltage of the memory transistor of the specified memory block is a threshold voltage corresponding to a predetermined erase state. If the predetermined erase state has not been reached, the erase verify is failed and the process proceeds to step S24, where a block batch erase pulse is applied to the erase target block. When the application of the erase pulse in step S24 is completed, the process proceeds to step S23 again and erase verify 1 is executed.

  When the erase verify 1 is passed in step S23, the process proceeds to step S25, and block batch software writing is executed. In step S26, erase verify 2 is executed. If the erase verify 2 has not been completed, the process proceeds to step S27 where the block collective erase pulse 2 is applied to the selected block. In step S26, erase verify 2 is executed again.

  When erase verify 2 passes in step S26, over erase verify for detecting an overerased state is performed in step S28.

  When overerasure is detected and overerase verify fails, overerase recovery operation is performed in step S29. In step S30, the lower limit value of the threshold voltage Vth is verified, that is, verified. If the result is a failure, the process returns to step S29.

  If the verification result is pass in step S30, over-erase verification is performed again in step S28. If the result is a pass in step S28, the process proceeds to step S31.

  In step S31, the signal BOOTE generated by the switching signal generator is checked. If the signal BOOTE is at the H level, it means that a boot block is necessary. Therefore, only the first designated block is erased, and the process proceeds to step S34, where the erase operation is terminated.

  On the other hand, if the signal BOOTE is at the L level, it means that a boot block is not necessary, so that the blocks B000 to B007 of 4k words are to be erased collectively. Therefore, the process proceeds to step S32, and it is determined whether or not the block that has been erased is the last block among the blocks to be erased at once.

  If it is not the last block, the process proceeds to step S33, and the erase target is changed to the next block. For example, if the block that has been erased is block B000, the erase target is changed to the next block B001. Then, the process proceeds to step S22 again, and the batch erasure of the target block is executed.

  If it is detected in step S32 that the block is the last block, that is, if erasure proceeds sequentially from block B000 and the block that has been erased is B007, the process proceeds to step S34. If the currently erased block is not a 4k word block, that is, if it is a block B008 to B022, the process similarly proceeds to step S34 and the erase operation is completed.

  A sequence for erasing a plurality of blocks one block at a time in response to one erasure instruction may be incorporated in the controller without selecting a plurality of blocks at the same time.

[Embodiment 2]
In the first embodiment, the nonvolatile memory capable of switching between the case of individually erasing the 4k word memory blocks B000 to B007 of FIG. In this case, the memory block B100 was an area that was always used, although it was necessary to provide it for the continuity of the memory array. When the 4k word block is not required, the predecoder may be configured to select the memory block B100 that has been conventionally unused instead of the memory blocks B000 to B007.

  FIG. 18 is a block diagram showing a configuration of predecoder 18B in the second embodiment.

  Referring to FIG. 18, predecoder 18B includes a BOP generation circuit 62B in place of NOR circuit 62 in the configuration of predecoder 18 described in FIG. 6, and a vertical block selection in place of vertical block selection circuit 64. A circuit 64B is included, and a horizontal block selection circuit 66B is included instead of the horizontal block selection circuit 66. The configuration of predecoder 18B in the other part is similar to that of predecoder 18 described in FIG. 6, and description thereof will not be repeated.

  BOP generation circuit 62B includes a 4-input NOR circuit 222 that receives address bits A15, A16, A17, and A18, and an AND circuit 223 that receives an output from NOR circuit 222 and a signal BOOTE and outputs a signal BOP.

  In the first embodiment, this signal BOP is a signal for switching the operation of the predecoder to the operation of selecting the blocks B000 to B007 instead when the address corresponding to the memory block B100 which has not been used is input. there were. In the configuration shown in FIG. 18, whenever the signal BOOTE is at the L level, the signal BOP is deactivated to the L level and the blocks B000 to B007 are not selected. Instead, the block B100 of 32k words is selected. Will be. Therefore, the erase instruction given from the outside is only required 16 times as in the memory array 700 described with reference to FIG.

FIG. 19 is a circuit diagram showing a configuration of the vertical block selection circuit in FIG.
Referring to FIG. 19, vertical block selecting circuit 64B includes an address decoding unit 82A in place of address decoding unit 82 in the configuration of vertical block selecting circuit 64 described with reference to FIG. The configuration of the vertical block selection circuit 64B in other parts is the same as that of the vertical block selection circuit 64 described with reference to FIG. 7, and description thereof will not be repeated.

  Address decode unit 82A receives gate circuit 224 that inverts address bit A14 and outputs signal BAVS0 when signal BOP is activated to H level, and receives signal BOP and address bit A14, and outputs signal BAVS1. And an AND circuit 226.

  When signal BOP is deactivated to L level, signals BAVS0 and BAVS1 for selecting the vertical block are both deactivated to L level, and memory blocks B000 to B007 are not selected. On the other hand, when signal BOP is activated to H level, one of signals BAVS0 and BAVS1 is activated to H level according to address bit A14, and any of memory blocks B000 to B007 can be selected.

FIG. 20 is a circuit diagram showing a configuration of the horizontal block selection circuit in FIG.
Referring to FIG. 20, horizontal block selection circuit 66B includes an address selection unit 110 and an address decoding unit 112. Since configurations of address selection unit 110 and address decoding unit 112 have already been described with reference to FIG. 8, description thereof will not be repeated. The horizontal block selection circuit 66B is different from FIG. 8 in that signals BAH0, BAH1, BAH2, and BAH3 are output from the decode gate circuits 130, 132, 134, and 136 of the address decoding unit 112, respectively.

  The signal BOOTE in FIG. 18 is a signal for determining whether or not it has a 4k word area as in the first embodiment. In the second embodiment, the switching signal generating circuits 10, 10A, 10B, and 10C as described in the first embodiment can be used. In the BOP generation circuit 62B of FIG. 18, the signal BOP is directly controlled by the signal BOOTE to select the memory blocks B000 to B007 when the signal BOP is at the H level, and the memory block B100 is selected when the signal BOP is at the L level. It becomes possible. This makes it possible to simultaneously realize a flash memory having a 4k word memory block and a flash memory not having a 4k word memory block in one type.

  In the embodiment described above, 8 blocks of the 4k word area are located only on the smaller address side (bottom side). However, even if this is located on the larger address side (top side), the same switching operation is performed. Is possible. Further, 8 blocks of 4k word area memory blocks may be located on both the bottom side and the top side.

[Application example]
FIG. 21 is a diagram for explaining a so-called dual boot type memory array in which 4k word memory blocks are arranged on both the bottom side and the top side of the address area by applying the present invention.

  Referring to FIG. 21, memory array 300 includes memory blocks B000-B007 corresponding to the bottom boot, memory blocks B008-B021 corresponding to the main block, and memory blocks B022-B029 corresponding to the top boot.

  The reason why the top boot and the bottom boot are required is because there are two types of areas depending on the type of the CPU that is accessed first by the CPU mounted in the system in which the nonvolatile semiconductor memory device is used. .

  If the system to be used is compatible with bottom boot, the memory blocks B000 to B007 are configured to be individually erasable, and the memory blocks B022 to B029 are collectively displayed with one erasure instruction as described in the first embodiment. The memory block B200 may be selected instead of the memory block B022 to B029.

  If the system to be used is compatible with the top boot, the memory blocks B022 to B029 are configured to be individually erasable, and as described in the first embodiment, the memory blocks B000 to B007 are batched with one erasure instruction. Then, the memory block B100 may be switched to select the memory block B100 instead of selecting the memory blocks B000 to B007.

  If the block selection configuration of the present invention is applied to a memory array capable of dual boot in this way, one type of chip can be produced regardless of whether the system is a bottom boot, top boot, or no boot type. If necessary, it is possible to cope with various configurations by changing the wire bonding, cutting the fuse, or changing the stored contents of a predetermined nonvolatile memory cell as required.

  By the way, in the case of using such a non-volatile memory corresponding to dual boot in combination with two chips, there has been a problem that the conventional method is inconvenient due to the existence of a block of 4k words at the center of the address. However, various types of nonvolatile memories can be realized even in the case of a two-chip configuration by using the nonvolatile memory of the present invention by switching to the top boot type, the bottom boot type and the non-boot type.

  FIG. 22 is a diagram illustrating a configuration for realizing dual boot when two chips are combined.

  Referring to FIG. 22, memory 302 is implemented by combining memory array 304 and memory array 306. The memory array 304 is realized by making the dual boot memory array 300 described in FIG. 21 correspond to the bottom boot, and the memory array 306 is used using the memory array 300 corresponding to the top boot. As a result, a 4k-word block that is cut into pieces at the center of the address does not exist from the user's point of view, which improves usability.

  FIG. 23 is a diagram for explaining a configuration for realizing bottom boot when two chips are combined.

  Referring to FIG. 23, memory 308 is realized by combining memory array 310 and memory array 312. The memory array 310 is realized by making the dual boot product memory array 300 described with reference to FIG. 21 correspond to the bottom boot, and the memory array 312 is used by making the memory array 300 correspond to the non-boot type. Also in this case, a 4k word block is not present at the center or top of the address from the user's point of view, which improves usability.

  FIG. 24 is a diagram for explaining a configuration for realizing a top boot when two chips are combined.

  Referring to FIG. 24, memory 314 is implemented by combining memory array 316 and memory array 318. The memory array 316 is realized by making the dual boot product memory array 300 described in FIG. 21 correspond to the non-boot type, and the memory array 318 is used by making the memory array 300 correspond to the top boot. In this case as well, the 4k word block is not present at the center or bottom of the address from the user's point of view, improving usability.

  FIG. 25 is a diagram for explaining a configuration for realizing a non-boot type when two chips are combined.

  Referring to FIG. 25, memory 320 is implemented by combining memory array 322 and memory array 324. The memory arrays 322 and 324 are realized by corresponding to the non-boot type memory array 300 of the dual boot product described in FIG. In this case as well, the 4k word block is not present in the top, middle, and bottom portions of the address from the user's point of view, improving usability.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a schematic block diagram illustrating a configuration of a nonvolatile memory device according to a first embodiment of the present invention. 4 is a cross-sectional view for explaining memory transistors MT arranged in a matrix in each memory block of the memory array 26. FIG. FIG. 2 is a circuit diagram showing a configuration of a switching signal generation circuit 10 in FIG. 1. It is a figure for demonstrating the bonding option with respect to the switching signal generation circuit of FIG. FIG. 6 is a diagram for explaining the relationship between setting states of signals #NOBOOT and #BOOT and a signal BOOTE for switching. It is a block diagram for demonstrating the structure of the predecoder of FIG. It is a circuit diagram for demonstrating the structure of the vertical direction block selection circuit of FIG. FIG. 7 is a circuit diagram showing a configuration of a horizontal block selection circuit in FIG. 6. 2 is a flowchart for explaining an operation flow at the time of block erasing of an internal controller in FIG. 1. FIG. 5 is a circuit diagram for explaining a first modification of the switching signal generation circuit explained in FIG. 3. It is a figure explaining the setting and output of the switching signal generation circuit shown in FIG. It is a circuit diagram which shows the 2nd modification of a switching signal generation circuit. It is a figure for demonstrating the relationship between the signal BOOTE which controls the state of a fuse element, and switching. It is a circuit diagram which shows the 3rd modification of a switching signal generation circuit. FIG. 15 is a diagram showing a relationship between a threshold voltage set in a memory transistor of the switching signal generation circuit of FIG. 14 and a signal BOOTE. FIG. 6 is a block diagram for explaining a configuration of a nonvolatile semiconductor memory device according to a modification of the first embodiment. FIG. 17 is a flowchart for explaining an erase operation of the internal controller in FIG. 16. FIG. FIG. 10 is a block diagram showing a configuration of a predecoder 18B in the second embodiment. It is a circuit diagram which shows the structure of the vertical direction block selection circuit in FIG. It is the circuit diagram which showed the structure of the horizontal direction block selection circuit in FIG. FIG. 3 is a diagram for explaining a so-called dual boot type memory array in which 4k word memory blocks are arranged on both the bottom side and the top side of an address area by applying the present invention. It is a figure explaining the structure which implement | achieves the dual boot at the time of combining 2 chips | tips. It is a figure explaining the structure which implement | achieves bottom boot at the time of combining 2 chips | tips. It is a figure explaining the structure which implement | achieves the top boot at the time of combining 2 chips | tips. It is a figure explaining the structure which implement | achieves the type without a boot at the time of combining 2 chips | tips. It is the figure which showed the array structure of the conventional flash memory. It is a block diagram showing a configuration of a conventional block selection decoder that generates a memory block selection signal. FIG. 10 is a circuit diagram showing a configuration of a conventional address input buffer 516. It is a figure which shows the array structure of the other conventional flash memory.

Explanation of symbols

  1,221 Nonvolatile semiconductor memory device, 2,2A control unit, 4 program & verify circuit, 6 sense amplifier, 8,8A internal controller, 10, 10A to 10C switching signal generation circuit, 16 address buffer, 18, 18A, 18B Predecoder, 20 row / column decoder, 22 input / output data buffer, 24 Y gate, 26, 300, 304, 306, 310, 312, 316, 318, 322, 324 memory array, 36, 42, 160, 166 capacitor, 50 chips, 52 leads, 54, 55 wires, 56, 58, 152 pads, 62 NOR circuit, 62B BOP generation circuit, 64, 64B vertical block selection circuit, 66, 66B horizontal block selection circuit, 68, 70 predecode Circuit, 72 row decoder, 7 4 column decoder, 82, 82A, 84, 112 address decode unit, 86, 88, 138, 224 gate circuit, 110 address selection unit, 114 output unit, 130, 132, 134, 136 decode gate circuit, 176 fuse element, 194 , 198, 202 switch, 200 memory transistor, 302, 308, 314, 320 memory.

Claims (3)

A first basic memory block as a unit of batch erasure;
A plurality of second basic memory blocks each having a smaller storage capacity than the first basic memory block and serving as a unit of batch erasure;
A first operation for erasing one of the plurality of second basic memory blocks in response to an erase command and a plurality of the second basic memory blocks in accordance with the erase command are simultaneously selected and erased. An erasing control circuit for switching the second operation according to the switching signal,
The non-volatile semiconductor memory device, wherein the capacity of the plurality of second basic memory blocks to be simultaneously selected and erased is equal to the capacity of the first basic memory block. A first basic memory block as a unit of batch erasure;
A plurality of second basic memory blocks each having a smaller storage capacity than the first basic memory block and serving as a unit of batch erasure;
An erase control circuit for simultaneously selecting and erasing the plurality of second basic memory blocks in response to an erase command, wherein the capacity of the plurality of second basic memory blocks to be simultaneously selected and erased is the first A nonvolatile semiconductor memory device having the same capacity as the basic memory block. A non-volatile semiconductor device,
The nonvolatile semiconductor device is
A first basic memory block as a unit of batch erasure;
A plurality of second basic memory blocks each having a smaller storage capacity than the first basic memory block and serving as a unit of batch erasure;
A first operation for erasing one of the plurality of second basic memory blocks in response to an erase command and a plurality of the second basic memory blocks in accordance with the erase command are simultaneously selected and erased. An erasing control circuit for performing the second operation,
The non-volatile semiconductor device switches between a type having at least one of a boot block and a parameter block and a type having no boot block and a parameter block by switching the first operation and the second operation. Done
The non-volatile semiconductor memory device, wherein the capacity of the plurality of second basic memory blocks to be simultaneously selected and erased is equal to the capacity of the first basic memory block.

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