GB2468051A - Verifying the programming of a cell array - Google Patents

Abstract

A semiconductor device includes a cell array, particularly a CAM cell array formed with non-volatile memory cells in preferred embodiments, which stores the operation setting information as to the semiconductor device, a write circuit and a verification circuit. The write circuit can perform simultaneous programming of memory cells in the cell array. Preferably the programming operation initially reads the data stored in the cells and compares this to the input data to identify cells which are in an erased state that the input data indicates should be programmed and then simultaneously programs only the identified cells. The verification circuit verifies memory cells which were programmed preferably by comparing the values read from those cells with the values expected based upon the input values. The verification circuit may return a pseudo-pass as the result of the verify operation for memory cells which were not programmed based upon a comparison of the input data with the data stored in the cell prior to programming.

Description

SEMICONDUCTOR DEVICE, ADDRESS ALLOYFIN METHOD, AND VERIfiCATION METHOD

CROSS-REFERENCES TO RELATED APPLICATIONS

This is a continuation application of International Application No. PCT/JP2005/00 1083 filed January 27, 2005, which was not published in English under

BACKGROUND OF THE INVENTTON

Field of the invention

The present invention generally relates to semiconductor devices, and more particularly, to a semiconductor device that includes a non-volatile memory. Even more specifically, the present invention relates to a technique of controlling the operation of a semiconductor device, using CAM (Contents Addressable Memory) IS data.

Description of the Related Art

Conventionally, two types of semiconductor device have been well known: one has a structure that determines whether the data stored in a non-volatile memory are equivalent to expected value data so as to automatically perform data checking at the time of programming or erasing the non-volatile memory; and the other one is a structure that has regular non-volatile memory cells to be used by users and CAM cells to control the operation of the semiconductor device. In recent years, so as to reduce the device size, a structure that has CAM cells formed with regular non-volatile memory cells. has been proposed. If the CAM cells have the same structures as the regular memory cells, the word lines and the bit lines to be connected to the CAM cells should preferably have the same structures as those to be connected to the regular memory cells.

The CAM data that are written in the CAM cells of the same structures as the regular memory cells are preferably read out and transferred to a volatile memory unit (a latch circuit) such as a SRAM (Static Random Access Memory) at the time of power on or resetting the hardware. By doing so, the operating speed at the time of read-access to the regular non-volatile memory cells is not reduced by the CAM data reading.

If the CAM cells have the same structures as the regular memory cells, the verif,'ing operation of the CAM cells should preferably be completed within the semiconductor device at the time of rewriting the CAM data, like the verif'ing operation of the regular memory cells. Japanese Unexamined Patent Publication No. 6-76586 discloses a verification circuit for programming regular memory cells.

When regular memory cells are to be programmed, the information "1" or "0" is input through IJOs by a user. A memory cell having the information "0" input thereto is a memory cell to be programmed, and a memory cell having the information "1" input thereto is a memory cell to be erased. The information of each I/O is used as an expected value at the time of verification.

In a semiconductor device, prior to actual programming, the data are read out from the memory cell connected to the word lines to be programmed. This process is referred to as "pre-rcading". The pre-read data are compared with the data input through the liDs. According to the comparison results, programming is performed only on the memory cells that are in the erased state (holding the information "1") and are to be programmed through the IiOs (having the information "0" input thereto).

Programming is not performed on the already programmed memory cells (holding the information "0"), because additional programming results in stress. If the information that is input to the already programmed memory cells (holding the information 11") through the I/Os is "I", an error signal is returned to the controller.

This is because the memory cells are non-volatile memories that physically perform writing operations, and have irreversibility. Therefore, an erasing operation is independent of a programming operation, and erasing is collectively performed on one sector, If the information that is input through the JJOs to the already erased memory cells (holding the information "1") is "1", no operations are performed.

Programming of CAM cells should preferably be performed in the same manner as the programming of regular memory cells, For programming CAM cells, there is a method that involves two different interfaces from the programming interface for regular memory cells. Input setting is performed in accordance with the information "1" and the information "0" input through the liOs, so as to determine CAM cells to be programmed and CAM cells not to be programmed (see Japanese Unexamined Patent Publication No. 10-106275). The programming interface for the input selling is referred to as "interface 1". In the case of the interface 1, a user inputs the information "1" and the information "0" through the respective lbs. The information "I" indicates a memory cell to be programmed, while the information "0" indicates a memory cell for which no operation is performed (not to be programmed).

For programming CAM cells, there is not only the method involving the interface 1, but also a method of designating only the CAM cells to be programmed through command input. The programming interface used in this method is referred to as "interface 2". In the ease of using the interface 2, the addresses of CAM cells are designated, and the address-designated CAM cells are to be programmed.

Each CAM cell should preferably have a user block in which users can rewrite information, and a factory block in which the vender maker writes information in advance. If the CAM data in the user block are rewritten in this structure, it is necessary to protect the memory cells in the factory block from disturb caused by cell information. The "disturb" is a phenomenon in which charge loss or charge gain is caused in the memory cells due to electric influence from the word lines and bit lines to which the memory cells arc connected at the time of programming the designated memory cells.

In a case where the CAM data in the user block is to be rewritten, it is necessary to protect the memory cells in the factory block from disturb caused by the cell information. However, there is not a technique for satisfying this requirement,

which is the first problem with the prior art.

The second problem lies in that proper verification cannot be performed after programming CAM cells. The following is a description of this problem.

The problem is caused when a verifying operation is performed simultaneously on the CAM cells located on the same word line in an array structure having more than one CAM cell connected onto one word line.

Fig. IA illustrates CAM cells that are connected onto one word line and are iii a programmed state. The CAM cells of"!" in Fig. 1A are erased cells and have not been programmed. The CAM cells of"0" are programmed cells and have already been programmed.

In Fig. IB, I/O input by the interface 1 is performed on the CAM cells on the word line shown in Fig. 1A. Here, the CAM cells with "1" are to be programmed, and the cells with "0" are not to be programmed and remain in the current state.

In the semiconductor device, the data that are prc-read from the CAM cells on the same word line are compared with the data that are input through the I/Os.

According to the comparison results, programming is performed only on the memory cell that is in the erased state (with the information "1" being stored) and is to be 110-programmed (with the information "1" being input). In this example, programming is performed on the rightmost CAM cell on the word line, as shown in Fig. JC.

Verification is performed after the programming. The data that are read out from the CAM cells after the programming are compared with the I/O-input data as expected values (see Fig. lD). At this point, if an I/O-input expected value indicates "non-programming" for an already programmed CAM cell, the comparison result is "fail", and the verifying operation ends in failure.

In the case where the above described designation method involving the interface 2 is employed, only the CAM cells to be programmed are designated through command input. Therefore, the expected values corresponding to the CAM cells not programmed on the same word line cannot be caused, and a verifying operation cannot be realized.

SUMMARY OF THE INVENTION

it is therefore an object of the present invention to provide a semiconductor device, an address allocation method, and a verification method in which the above disadvantages are eliminated.

A more specific object of the present invention is to provide a sen1ieonductor device having CAM cells on which data rewrite and verification can be properly performed, an address allocation method, and a verification method.

To achieve the above object of the present invention, a semiconductor device of the present invention includes: a cell array that stores the operation selling information as to the semiconductor device; and a control unit that controls read and write operation to be performed on the cell array. The control unit allocates different row addresses for respective functions of the operation setting information. As the different row addresses are allocated to the respective functions of the operation setting information, stress (gate disturb) is not caused in the cell array of unselected functions at the time of programming.

In the above semiconductor device, the control unit allocates different column addresses for the respective functions of the operation setting information. As the different column addresses are allocated to the respective functions of the operation setting information, stress (drain disturb) is not caused in the cell array of unselected functions at the time of programming.

In the above semiconductor device, the control unit allocates continuous column addresses for the respective functions of the operation selling information.

As the continuous column addresses are allocated for the respective functions, the data can be read out successively, and the reading time can be shortened.

In the above semiconductor device, the control unit allocates the operation setting information to column addresses selected by one of the row addresses.

Alternatively, the control unit allocates the operation setting information to all JJOs of an arbitrary column selected by the row address. In this manner, the number of reading cycles can be minimized, and the reading time can be shortened.

In the above semiconductor device, memory cells accessed by different row addresses are isolated from each other. Since the line pattern of local bit lines is cut off betcveen the memory cells of different row addresses, the data can be read out simply by switching column addresses, with a word line being selected between memory cells of respective functions.

In the above semiconductor device, memory cells are connected to switches for selectively connecting the memory cells to bit lines arranged on a column correspondence. With this structure, the data can be read out simply by switching column addresses, with a word line being selected between memory cells of respective functions.

in the above semiconductor device, the cell array includes cells for each column, and memory cells not storing the operation setting information are isolated from bit lines arranged on a column correspondence. Accordingly, stress is not caused in the cell array of unselected functions at the time of programming.

In the above semiconductor device, the control unit selects all word lines on the cell array, and reads the operation setting information from the cell array while successively changing the column addresses. With this structure, the data can be read out simply by switching column addresses, without switching word lines, and the reading time can be shortened.

In the above semiconductor device, the control unit includes a table that converts the number of a designated memory cell into an address of a corresponding memory cell. Since a designated memory cell number can be converted into the address of the designated cell, programming can be performed on the desired cell.

The present invention also provides a method of allocating addresses to a cell array that stores operation setting information as to a semiconductor device. This method includes the step of allocating different row addresses to respective functions of the operation setting information. Since the different row addresses are allocated to the respective functions of the operation setting information, stress is not caused in the cell array of unselected functions at the time of programming. Also, erasing can be performed for each function.

This method further includes the step of allocating different column addresses for the respective fUnctions of the operation setting information. By this method, the data can be read out with different column addresses for the respective functions of the operation setting information, This method further includes the step of allocating continuous column addresses for the respective functions of the operation setting information. By this method, the operation setting information of respective functions can be readily read out.

This method further includes the step of selecting all word lines on the cell array and successively changing the column addresses to read data from the cell array.

Accordingly, the operation setting information can be read out simply by switching the column addresses, without switching word lines.

The present invention also provides a semiconductor device that includes: a cell array that stores the operation setting information as to the semiconductor device; a write circuit that simultaneously programs memory cells in the cell array; and a verification circuit that verifies a programming result of only a memory ccli that is actually programmed. In this manner, only the programming results of the actually programmed cell can be verified.

In the above semiconductor device, the verification circuit includes: comparator circuits that compare expected value data obtained by normal programming with data that are read from the memory cells after programming: and a control unit that makes a pseudo-pass for comparator outputs related to programming results of memory cells that are not programmed. In this manner, a control operation is performed to make a pseudo-pass for the programming results from the comparator circuits allocated to unprogrammed cells Accordingly, the programming result of the programmed cell can be reflected in the verification.

In the above semiconductor device, the control unit identifies a memory cell in an erased state prior to the programming, the memory cell being designated as being to he programmed by an external input, and the semiconductor device further includes a circuit that generates expected value data obtained by normal programming in response to an instruction from the control unit, and outputs the expected value data to one of the comparator circuits related to the designated memory cell. In this manner, the actually programmed cell is detected, and the expected value data is output to the comparator circuit allocated to the cell. Thus, the programming result of the programmed cell can be accurately determined.

The present invention also provides a semiconductor device that includes: a cell array that stores the operation setting information as to the semiconductor device; a write circuit that simultaneously programs memory cells in the cell array; a volatile memory circuit that stores data stored in the memory cells prior to programming; and a verification circuit that verifies, with the data stored in the volatile memory circuit, a memory cell that is not programmed, and verifies another memory cell that is actually programmed with expected value data obtained by normal programming. In this manner, verification is performed on unprogranimed cells, using the stored data. For an actually programmed cell, the programming result is verified using the expected value data obtained when programming is properly performed. Thus, the programming result of the programmed cell can be accurately verified.

In the above semiconductor device, the verification circuit includes: comparator circuits that compare expected value data obtained by normal programming with data that are read from the memory cells or a sense amplifier after programming: and a control unit that identifies the memory cell that is actually programmed and causes one of the comparator circuits related to the memory cell actually programmed to verify a programming result thereof with the expected value data obtained by normal programming. With this structure, the actually programmed cell is identified, and the programming result of the programmed cell can be accurately verified.

In the above semiconductor device, the control unit identifies a memory cell in an erased state prior to programming, the memory cell being designated as being to be programmed by an external input, and the semiconductor device fUrther includes a circuit that changes the expected value data stored in the volatile memory circuit and related to a memory cell in an erased state prior to programming to the expected value data obtained by normal programming, and outputs the expected data value thus changed to the one of the comparator circuits. With this structure, the actually programmed cell is identified, and the programming result of the programmed cell can be accurately verified.

In the above semiconductor device, the control unit externally receives an instruction signal indicating whether each memory cell should be programmed, and identifies a memory cell to be actually programmed by determining whether the memory cell to be programmed is in an erased state. With this structure, a cell to be programmed is identified by an external instruction signal, and programming is performed on the identified cell.

In the above semiconductor device, the control unit decodes address information externally supplied to identify a memory cell to be programmed, the control unit identifying a memory cell to be actually programmed by determining whether the memory cell to be programmed is in an erased state. With this structure, a cell to be programmed is identified with externally input address information, and programming is performed on the identified cell.

In the above semiconductor device, the control unit changes an interface that designates a memory cell to be programmed in response to a mode switching signal that is externally supplied. With this structure, a cell to be programmed can be designated in accordance with interfaces.

In the above semiconductor device, the verification circuit is shared between verification after programming of the cell array storing the operation setting information, and verification after programming of a regular cell array storing regular data. With this structure, the verification circuit can be shared. Accordingly, the circuit size can be reduced.

In the above semiconductor device, the comparator circuits compare the expected value data obtained by normal programming with data read from the memory cells after programming in response to a mode signal for switching an operation mode to programming of the cell array storing the operation setting information. With this structure, the comparator circuits operate only at the time of verification.

In the above semiconductor device, the comparator circuits use outputs of the volatile memory circuit at the time of programming of the cell array storing the operation setting information, and the comparator circuits use outputs of a circuit holding the expected value data obtained by normal programming of the memory cell at the time of programming a regular cell. With this structure, different control operations can be performed for verification between the programming on the cell array that stores the operation setting information and the programming on the regular cell array.

* The present invention also provides a method of verifying a. cell array that stores the operation setting information as to a semiconductor device+ This method includes the step of verifying a programming result of only a memory cell that is actually programmed among memory cells in the cell array. By this method, only the programming result of the actually programmed cell can be verified.

The present invention also provides a method of verifying a cell array that stores the operation setting information as to a semiconductor device. This method includes the steps of: verifying a memory cell that is not programmed with data stored in the memory cell prior to programming; and verifying another memory cell that is actually programmed with expected value data obtained by normal programming. By this method, verification is performed on unprogrammed cells, using the stored data.

As for an actually programmed cell, the programming result is verified using the expected value data that is obtained when programming is properly performed. Thus, the programming result of the programmed cell can be accurately verified.

With any of the above semiconductor devices each having a cell array that stores the operation setting information, data rewrite and verification can be properly performed.

BRIEF DESCRIPTION OF TIlE DRAWINGS

Other objects, features and advantages of the present invention will become more apparent from the follo;ving detailed description when read in conjunction with the accompanying drawings, in which: Figs. IA through ID illustrate the problems with the prior art; Fig. 2 illustrates the structure of a semiconductor device of the present invention; Fig. 3 illustrates an example bitmap of a CAM cell array; Fig. 4 illustrates an example bitmap of a CAM cell array; Fig. 5 shows the correspondence between the WP bit numbers and the addresses; Fig. 6 shows the conversion of the WP addresses into the addresses of the CAM cell array; Figs. 7A and 713 illustrate the memory cell structures of a CAM cell array and a regular cell array; Figs. 8A and 813 illustrate the memory cell structures of a CAM cell array and a regular cell array; Fig. 9 illustrates the structures of logic circuits that convert WI' addresses into CAM column addresses; Fig. 10 illustrates the structures of logic circuits that convert WP addresses into DQs; Fig. 11 illustrates the structures of a cell array and a verification circuit; Fig. 12 illustrates the structure of a VIP bit select circuit; Fig. 13 is a flowchart of the operation of the verification circuit in the 110 mode; Figs. 14A through 14D illustrate the procedures to be carried out by the verification circuit in the I/O mode; Fig, 15 is a flowchart of the operation of the verification circuit in the address mode; Fig. 16 illustrates the procedures to be carried out by the verification circuit in the address mode; Fig. 17 illustrates the structure of the verification circuit in greater detail; Fig. 18 illustrates the structures of a cell array and a verification circuit; Fig. 19 illustrates the structure of a VIP bit select circuit; Fig. 20 is a flowchart of the operation of the verification circuit in the I/O mode; Fig. 21 illustrates the procedures to be carried out by the verification circuit in the I/O mode; Fig. 22 is a flowchart of the operation of the verification circuit in the address mode; Fig. 23 illustrates the procedures to be carried out by the verification circuit in the address mode; and Fig. 24 illustrates the structure of the verification circuit in greater detail.

DESCRIPTION OF TFIE PREFERRED EMBODIMENTS

The following is a description of preferred embodiments of the present invention, with reference to the accompanying drawings.

(First Embodiment) Referring first to Fig. 2, the structure of this embodiment is described. A semiconductor device I of this embodiment includes a regular cell array 3 that stores regular data and a CAM cell array 4 that stores CAM data. The regular cell array 3 and the CAM cell array 4 constitute a cell array unit 2. The CAM cell array 4 is formed with memory cell disposed on multiple rows and columns like regular cell array 3. The CAM cell array 4 stores the operation setting information (so-called CAM data) as to the semiconductor device I. For example, the write protect information as to the regular cell array 3, the internal voltage control information as to the semiconductor device I, the internal timing control information, the operation mode switch information, and the memory cell redundant bit information are stored.

The semiconductor device I also includes a peripheral circuit that performs data write, read, and erase on the cell arrays. As shown in Fig. 1, the peripheral circuit includes a row decoder 5, a column decoder 6, a command register 7, a controller 8, a program voltage generating circuit 9, a sense amplifier 10, a volatile memory unit 11, a determining unit 12, and a verification circuit 13, and a data input/output circuit 14.

The row decoder 5 selectively drives word lines WL, based on the respective addresses, at the time of writing, erasing, or reading data. A predetermined voltage is applied to the word line driver (not shown) from the program voltage generating circuit 9. The column decoder 6 selects a column from the cell array, i.e., a global bit line or a local bit line, based on an externally input address.

The command register 7 decodes an external command to an internal control signal. The controller 8 controls the inner operation, in response to the internal control signal decoded by the command register 7. The controller 8 is formed with a microprocessor, for example, and controls the program voltage generating circuit 9, a determining circuit 12, and a verification circuit 13.

The CAM data stored in the CAM cell array 4 are transferred to and stored in the volatile memory unit 11, at the time of switching on the semiconductor device I or resetting the hardware. With the CAM data being read into the volatile memory unit 11, a delay of a reading operation can be prevented when the CAM data are read out at the time of read-accessing the regular cell array 3. The reading operation period should preferably be short, because the activating period becomes longer unless the CAM data are transferred in a short time.

-10 -The data inputloutput circuit 14 includes an 1/0 terminal that inputs a program instruction from the outside, and outputs readout data. The data input/output circuit 14 performs data write (programming) and read on the CAM cell array 4.

Next, the structure of the CAM cell array 4 is described. Fig. 3 shows a bitmap illustrating the allocation of the CAM data to the CAM cell array 4. The CAM cell array 4 is divided into fUnction blocks of a user block and a factory block.

Data erase is performed in each function block.

A "user block" is a write region in which a user writes a write-protect bit (hereinafter also referred to as "WP bit") or the like. A "vrite protect" bit is a bit for controlling the programming or erasing of memory cells, and a unit write-protect bit is formed with an arbitrary number of sectors (hereinafter, the unit will be referred to as the "sector group"). In the example illustrated in Fig. 3, WP bits are preferably allocated to all the 1/Os DQO through DQ15. A word line (a row address) and four IS local bit lines (LBL), i.e., four column addresses (LBL0 through LBL3), are allocated to each one I/O, and a global bit line (GBL)(GBLO) is allocated to one 110. Here, the allocation of the WP bits to all the lbs DQO through DQI5 is to allocate data to all the memory cell of a column selected by a row address. If the number of WP bits is not an integer divisible by the number of IIOs, emphasis may be put on I/O allocation in column allocation, or emphasis may be put on column allocation in I/O allocation.

For example, if the number of WP bits is 60 and the number of I/Os is 16, I/Os (DQ) corresponding to the WP bits 60, 61, 62, and 63 of the last column address (000011) are not allocated, or the I/Os (DQ) corresponding to the WP bits 1, 2, 3, and 4 of the top column address (000000) are shifted and allocated, by the column allocation method, with emphasis being put on 110 allocation. By the I/O allocation method, with emphasis being put on column allocation, the IIOs (DQ) corresponding to the WP bits 15, 31, 47, and 63 are skipped.

The user block is formed with 64 WP bits 0 through 63, and are bit-allocated in accordance with the correspondence relation (a conversion table) shown in Fig. 5 and the conversion table shown in Fig, 6. As shown in Figs. 5 and 6, the V/P bits 0 through 63 correspond to the addresses A17 through A20 of the DQ terminals as I/Os, and the addresses A21 and A22 as column addresses.

The factory block is a fUnction block in which the vender maker performs rewrite, but users cannot perform rewrite, in this fUnction block, redundant data, internal voltage trimming data, and internal timing trimming data are to be written.

The factory block shown in Fig. 3 is formed with the 16 bits TRO through TRI 5 for trimming, the 32 bits of REDSECA through REDSECD for sector -11-j redundancy, and the 128 bits of REDCOL (0-0) through REDCOL(7-1) for column redundancy. Each 8 sector redundancy bits of REDSECA through REDSECD store one defect relief address. Each 8 column redundancy bits of REDCOL (0-0) through REDCOL (7-1) store one defect relief address.

The factory block is also allocated to DQO through DQ15, as shown in Fig. 3.

One word line and 11 local bit lines (LBL), i.e., eleven column addresses (LBL4 through LBL14), are allocated to each 110, and three global bit tines (GBL) (GBLI through GBL3) are allocated to each 1/0. As shown in Fig 4, the factory block is also formed with 64 bits, like the user block, and the 64 bits are allocated to DQ0 through DQ15.

Fig. 7A illustrates the structure of the CAM cell array 4 in detail, and Fig. 7B illustrates the structure of the regular cell array 3 in detail. In the CAM cell array 4 shown in Fig. 7A, the factory block and the user block have word lines that are independent of each other, so that the factory block is not adversely affected by the gate disturb in memory information due to rewrite in the user block. In other words, different row addresses are allocated to the factory block and the user block. The row decoder 5 shown in Fig. 2 allocates the CAM data of the respective function blocks to the different row addresses, based on externally input addresses. In Fig. 7A, the word line WLO allocated to the WP bits contained in the user block, and the word lines WL 1 allocated to the factory bits contained in the factory block are shown, Further, in one block (the user block or the factory block), the number of word lines to be allocated is restricted to the smallest possible number. This is because the structure is designed to be capable of collectively erasing the data in one unit function block. Here, the "gate disturb" is a phenomenon in which the bit lines are connected to the same word line to which the memory cells to be programmed are connected, and charge gain is caused due to a high voltage applied to the gates of unselected memory cells at the time of programming. Because of this phenomenon, the data of the unselected memory cells change from "I (the threshold value being low)" to "0 (the threshold value being high)" due to the charge gain.

Likewise, the column decoder 6 allocates the CAM data of the respective function blocks to different column addresses, based on externally input addresses, Also, address allocation is performed in such a manner that the allocated column addresses are continuous between the factory block and the user block.

So as to protect the factory block from drain disturb of the memory information due to rewrite or the like performed in the user block, the bit lines of the factory block and the user block are separated from each other,' as shown in Fig. 7A.

In other words, the column decoder 6 allocates column addresses that are independent of each other to the user block and the factory block. Further, the column decoder 6 allocates addresses in such a manner that the column addrçsses are continuous between the different function blocks Here, the "bit line separation" indicates both the physical separation and the electric separation of the local bit lines and the global bit lines. The "drain disturb" is a phenomenon in which the word line is connected to the same bit lines to which the memory cells to be programmed are connected, and charge loss is caused due to a high voltage applied to the drains of unselected memory cells at the time of programming. Because of this phenomenon, the data of the unselected memory cells change from "0 (the threshold value being high)" to "I (the threshold value being low)" due to the charge loss.

Also, with all the word lines (the word lines WL1 and WL2, for example) being selected, the same column addresses are not shared between the function blocks, and the column addresses are made.continuous between the function blocks, so that all the CAM data can be read out simply by switching the column addresses. In this manner, the time for switching the word lines can be saved, and CAM data can be transferred from the CAIvI cell array 4 to the volatile memory unit 11 in a short time.

In such a ease, when more than one word line is selected at the same time, the bit lines to which unnecessary cell data are connected are severed, so that the necessary cell data and the unnecessary cell data cannot be selected through the same bit line.

Taking advantage of the fact that the user block and the factory block do not share the same column addresses, the line pattern of the local bit lines (LBL) between the user block and the factory block is physically cut off, and the cut-off local bit lines (LBL) are not connected to the global bit lines (a contact via is not used, for example).

Alternatively, the user block and the factory block may be separated from each other as sectors, and column switches for connecting with the global bit lines are provided for the user block and the factory block, thereby electrically severing the user block and the factory block from each other.

With this structure, when the data are to be read from the CAM cell array 4 into the volatile memory unit II at the time of power supply or the like, the CAM data can be read out simply by switching the column addresses, with the word line of the user block and the word line of the factory block being simultaneously selected.

Since there is no need to switch the word lines, the total time required for reading all the bits of the CAM data can be shortened.

Fig. 9 illustrates the structures of conversion circuits that convert the address signals for programming/erasing operations into the column address signals for the respective banks. The conversion circuits are provided in the column decoder 6.

CAM program mode signals (CAMPGM) arc switched between an activated state and -13 -an inactivated state, so that switching can be performed between a column address of the regular cell array 3 and a column address of the CAM cell array 4.

The conversion circuits include: OR gates 121 to which address signals WA(0) or WA(1) for a programming/erasing operation and a CAMPGM signal are input; OR gates 123 to which the inverted output of the CAMPGM signal and address signals WA(21) or WA(22) are input; NAND gates 124 to which the outputs of the OR gates 1210 and 123 are input; and inverters 125 that invert the outputs of the NAND gates 124. The outputs of the inverters 125 are column addresses AA(0) and AA(1).

If the CAMPGM signal is in the inactivated state, the address signals WA(1) and WA(0) serve as the column addresses AA(1) and AA(0).

The conversion circuits also include; OR gates 131 to which address signals WA(2), WA(3), WA(4), and WA(S) are input; OR gates 133 to which the inverted outputs of CAMPGM signals and a power supply voltage VCC are input; NAND gates 134 to which the outputs of the OR gates 131 and 133 are input; and inverters 135 that identify the outputs of the NAND gates 134. The outputs of the inverters 135 serve as column addresses AA(2), AA(3), AA(4), and AA(5).

Fig. 10 illustrates conversion circuits that convert the address signals for programming/erasing operations into DQs. These conversion circuits are provided as switches in the data input/output circuit 14. The conversion circuit that generates DQO includes: a NOR gate 142 to which address signals WA(20), WA(19), WA(1 8), and WA(17) are input; a NAND gate 143 to which a CAMPGM signal and the output of the NOR gate 142 are input; and an inverter 144 that inverts the output of the NAND gate 143. The conversion circuits that generate DQ1 through DQI5 also have the same circuit structure as above.

If the CAMPOM signal is in the activated state, the address signals WA(0) through WA( 17) are allocated to CAM_DQ 15 through CAM_DQO. If the regular cell array 3 is in a selected state (i.e., the CAMPOM signal is in the inactivated state), CAM_DQ15 through CAM DQO are put into an inactivated state.

At the time of programming a write-protect bit, only the DQ to be programmed is activated, and applied stress, expected values, and identification signals are controlled through the conversion circuits shown in Fig. 10, so that the DQs not to be programmed are ignored.

Although the above described embodiment is a preferred embodiment, the present invention is not limited to that. For example, the factory block may include a one-time programmable ROM (OTP ROM). An OTP ROM is a functional memory a user can program only once. The OTP ROM differs from the factory block in terms of the function allowed to users, but is separated from the user block in which users -14 -can perform programming and erasing repeatedly, in view of the function that does not allow reprogramming. In short, it is required to avoid gate disturb and drain disturb.

It is also possible to form the user block with a read bit block, instead of a write bit block, In such a case, read control is performed for each desired sector.

In the above described embodiment, the physical separation among the local bit lines and the electric separation from the global bit lines between the factory block and the user block. However, the present invention is not limited to that structure, and it is also possible to physically or electrically separate the global bit lines between the factory block and the user block.

The regular cell array and the CAM cell array may be connected so as to share a data bus, or may be connected so as to share the global bit lines of the user block and the factory block.

Also, wells may be separated or shared between the user block and the factory block. If shared, the die size can be reduced. In such a case, floating control is performed on the word line of the factory block at the time of performing an erasing operation in the user block.

(Second Embodiment) Referring now to Fig. 11, the structure of this embodiment is described. Fig. 11 illustrates a cell array unit 2 (a regular cell array 3 and a CAM cell array 4) that store the data as to a semiconductor device I, a verification circuit 13 that confirms a data written state or a data erased state of the cell array 2, and expected value holding circuits 32 disposed in a data input/output circuit 14. In this embodiment, a 16-bit simultaneous write mode is also employed, so that programming can be performed through simultaneous access to the 16 memory cells of the regular cell array 3 or the CAM cell array 4.

A verification circuit 13 includes a WP bit select circuit 33 and data comparator circuits 34. The number of expected value holding circuits 32 and the number of data comparator circuits 34 disposed in the data input/output circuit 14 are 16, which is the same as the number of I/Os.

An interface mode setting signal, a signal input from each corresponding I/O, and an address signal (WP-CAM address designating signal) that designates a write-protect CAM (WP-CAM) are input to the WP bit select circuit 33.

There arc two methods of designating a CAM cell to be programmed. By one of the methods, the information "I" is input to the I/O corresponding to the CAM cell to be programmed, while the information "0" is input to the 1/Os not to be programmed ("I/O mode"). By the other method, the corresponding address is input to the CAM cell to be programmed ("address mode"). The interface mode selling -15 -signal is a signal for switching the method of designating a CAM cell to be programmed between the above two methods.

Fig. 12 illustrates the structure of the WP bit select circuit 33 in detail. As shown in Fig. 12, the WP bit select circuit 33 includes a decoder 51, AND gates 53, and switches 54. The number of AND gates 53 and the number of switches 54 are hoth 16, which is the same as the number of 1/Os. With this structure, the data comparator circuit 34 through which a pass is performed on pseudo verification is selected.

When the address mode is set by the interface mode setting signal, the switches 54-(0) through 54-(15) are turned OFF, and the WP-CAM address designating signal is decoded by the decoder 51, to generate a verification control signal. When the I/O mode is set by the interface mode setting signal, the decoder 51 is turned OFF by the interface mode setting signal input to the decoder 51 via the inverter 52, and the switches 54-(0) through 54-(15) are turned ON.

The signals I/O-(0) through 110(15) from the respective 1/Os and pre-read data (DAY) read out from the CAM cells in advance are input to the AND gates 53-(O) through 53-(15), which obtains the logic products of those signals. More specifically, if the data prior to the programming of the CAM cell and the data input from the 110 are both "1", a high-level signal is output as a verification control signal. In other cases, a low-level signal is output as a verification control signal.2 The expected value holding circuits 32-(0) through 32-(1 5) are provided for the respective 1/Os, as shown in Fig. II, and holds 110 input information. The held information is output as expected value data to the data comparator circuits 34 after programming of the regular cell array 3. The expected value holding circuits 32-(0) through 32-(15) also holds information that is I/O-input at the time of programming of the CAM cell array 4 in the I/O mode. The held information is output as expected value data to the data comparator circuits 34 after the programming of the CAM cell array 4. Further, the expected value holding circuits 32 generate expected values, having the verification control signal output from the WP bit select circuit 33, when the switches 35 are turned ON by the interface mode setting signal at the time of programming of the CAM cell array 4 in the address mode. The data are then output as expected value data to the data comparator circuits 34 after the programming of the CAM cell array 4.

The data comparator circuits 34-(0) through 34-(15) are also provided for the respective 1/Os, and compare the data read out from the regular cell array 3 or the CAM cell array 4 with the data (the expected values) stored in the expected value holding circuits 32-(0) through 32-(15). At the time of programming of the CAM cell array 4, the data comparator circuits 34 perform a pseudo-verification pass on the cells not to be programmed, using the verification control signal from the V/P bit select circuit 33.

Referring now to the flowchart of Fig. 13 and Fig. 14, the operation of programming the CAM cell array 4 set in the 1/0 mode in accordance with this embodiment is described. In this embodiment, the setting of "write protect" can be performed on each sector group consisting of sectors, and I/Os are allocated to each sector. When a sector group in which the "write protect" is to be set is selected, protection data are programmed in the WP-CAM cell in the selected sector group.

First, CAM program setting signals (1/0-0, I, ..., 15) for designating a WP-CAM cell to be programmed are input from the respective JJOs (step S 10). The information "1" for commanding programming is input to the 110 corresponding to the WP-CAM cell to be programmed, and the information "0" for prohibiting programming is input to the other I/Os (see Fig. 14B).

The data that are already stored in the \VP-CAM cells are read out (pre-read) in advance (step S 11). Judging from the pre-read data, each WP-CAM cell is determined to be in a data written state. If data have already been written and programming has already been performed the information "0" is held. If a V/P-CAM cell is in an erased state without written data, the information "1" is held in the I/O (see Fig. 14A).

Next, a V/P-CAM cell that is currently in an erased state and in which write is allowed by the I/O input signal is detected (step S 12). More specifically, a V/P-CAM cell having pre-read data of "1", which indicates an erased state, and also having the input of' l"is detected. In this detection, the expected value holding circuits 32 and the data comparator circuits 34 shown in Fig. 11 may be used.

Programming is then perfonned on the detected WP-CAM cell (step S13) (see Figs. 14C, for example). As the programming is performed, the verification circuit 13 determines whether the data have been certainly written in the WP-CAM cell. At this point, the switches 35-(0) through 35-(l 5) provided for the respective IIOs are turned OFF by the interface mode setting signals for setting the 110 mode. The interface mode setting signal is also input to the WP bit select circuit 33, so as to turn the switches 54-(0) through 54-(Il5) ON.

The V/P bit select circuit 33 obtains the logic products of the pre-read data read from the V/P-CAM cells and the I/O-input signals (110-U, 1, ..., 15) through the AND gates 53-(0) through 53-(15), to generate verification control signals. If the 110 input is "1" commanding programming, and the pre-read data is "1" indicating an erased eel], a high-level verification control signal is output to the corresponding data -17-comparator circuit 34, In other cases, a low-level verification control signal is output to the corresponding data comparator circuit 34.

The expected value holding circuits 32-(0) through 32-(15) latch the input signals l/O-(0), (I), ..., (15) as they are, and output the latched data as DINO through DIN 15 to the data comparator circuits 34-(0) through 34-( 15) at predetermined timing.

The data are referred to as the expected value data. The verification control signal is input from the WP bit select circuit 33 to each of the data comparator circuits 34-(0) through 34-(15).

The data comparator circuits 34-(0) through 34-(l 5) compare the data read out from the WP-CAM cells, i.e., the data read out after programming, with the expected values read out from the expected value holding circuits 32-(0) through 32- (15). At this point, in each data comparator circuit 34 to which a low-level verification control signal is input from the WP bit select circuit 33, comparison is not performed, but a high-level matching signal is output so as to make a pseudo-pass for the verification (see Fig. 14D). in each data comparator circuit 34 to which a high-level verification control signal is input from the WP bit select circuit 33, the expected value data that is input from the corresponding expected value holding circuit 32 is compared with the data after programming the WP-CAM ccli. if the I/O input is "1" commanding programming, and the data read from the WP-CAM cell after programming is "1" indicating an erased state, a low-level signal indicating "Fail" is output to the determining circuit 12. As shown in Fig. 14D, If the I/O input is "1", and the data read from the WP-CAM cell after programming is "0" indicating a programmed state, a high-level signal indicating verification pass is output to the determining circuit 12.

When all the matching signals that are output from the data comparator circuits 34-(0) through 34-( 15) are at the "H" level, the determining circuit 12 outputs a verification signal indicating data write success to the controller.

As described above, a pseudo-pass is performed on the comparison results of the data comparator circuits allocated to unprogrammed CAM cells in this embodiment. Accordingly, the programming results of the programmed CAM cell can be reflected in the verification.

Referring now to the flowchart of Fig. IS and Fig. 16, the operation to be performed in a case where a sector group address (SGA) is designated from the outside is described. As shown in Fig. 16, in accordance with the sequence for executing the program command of a WP-CAM cell, the procedures for command recognition are carried out in five cycles, and information is rewritten in the sixth cycle, in short, a SGAto be programmed is designated, and programming of the SGA is performed in six cycles in total.

First, a WP-CAM address designating signal for designating a WP-CAM cell to be programmed is input. The WP-CAM address designating signal is analyzed by the decoder (step 520), so as to generate an address corresponding to the WP-CAM cell to be actually programmed. In the verification circuit 13, the WP-CAM address designating signal is also decoded by the decoder 51, and a high-level verification control signaI is output to the expected value holding circuit 32 and the data comparator circuit 34 corresponding to the WP-CAM cell to be programmed. A low-level verification control signal is output to the other expected value holding circuits tO 32 and the other data comparator circuits 34.

Next, the data that are already stored in the VIP-CAM cell designated from the decoding result is pre-read (step 521). The pre-read data is analyzed to determine the data write state of the WP-CAM cell.

If the VIP-CAM cell is determined to be in an erased state ("YES" in step S22), data is written in the WP-CAM cell and is put into a programmed state (step S23). If the VIP-CAM cell is determined to be in a programmed state ("NO" in step 522), the operation comes to an end.

When the programming of the WP-CAM cell is finished, verification to determine whether the data has been certainly written in the VIP-CAM cell is performed by the verification circuit 13.

The VIP bit select circuit 33 and the data comparator circuits 34-(0) through 34-( 15) provided for the respective IIOs are connected with lines, and a verification control signal are output from the VIP bit select circuit 33. In the address mode, the switches 35-(0) through 35-(15) are tumed ON by the interface mode setting signal.

Accordingly, the verification control signal is input only to the expected value holding circuit 32 connected to the line through which a "FI"-level verification control signal is output. The expected value holding circuit 32 to which the "H"-level verification control signal is input generates the expected value "0" indicating that the subject VIP-CAM cell is programmed, and outputs the expected value "0" to the data comparator circuit 34 (step S24) (see Fig. 16). The other expected value holding circuits 32 to which a "L"-level verification control signal is input do not generate an expected value (step 524). Accordingly, an expected value is not output to the data comparator circuits 34.

The data comparator circuit 34 to which the expected value "0" is input from the expected value holding circuit 32 reads the data from the corresponding WP-CAM cell, and compares the data DAVi with the expected value "0" (denoted by!DINi in Fig. 16). Receiving the low-level verification control signal, the other data comparator circuits 34 forcibly output "H"-level matching signals. In short, a pseudo verification pass is performed (see Fig. 16).

When all the matching signals output from the data comparator circuits 34 are at the "I-I" level, the determining circuit 12 outputs a verification signal indicating data write success to the controller (step S25). The data comparison result of the actually programmed WP-CAM cell can be output as the verification result.

Fig. 17 illustrates the structures of each expected value holding circuit 32 and each data comparator circuit 34 shown in Fig. 11, and the structure of the determining circuit 12. As described above, the output of each data comparator circuit 34 is controlled by the verification control signal from the WP bit select circuit 33, and is output to the determining circuit 12. Also, each data comparator circuit 34 is controlled by a CAM mode signal for rewriting a CAM cell. Further, each expected value holding circuit 32 is controlled by the interface mode setting signal.

(Third Embodiment) Referring now to Fig. 18, a third embodiment of the present invention is described. The CAM data that is written in a CAM cell array 4 are read by switching ON a switch 61 at the time of power supply or resetting the hardware. The CAM data are then transferred to a volatile memory 11 such as a SRAM shown in Fig. 18.

The CAM data are read out from the volatile memory 11 so that read access to a regular cell array 3 is not delayed. In this embodiment, when programming is performed on the CAMs, the data stored in the volatile memory 11 arc used as expected value data, and data comparator circuits 34 compare the expected value data with the data that are read out from the CAM cell.

Other than the time at which verification is performed on the data that are programmed in the CAM cell array 4, a switch 62 is switched by a CAM mode signal, so as to connect the expected value holding circuits 32 to the data comparator circuits 34, By doing so, verification using the expected value holding circuits 32 can be performed at the time of verifying the regular cell array 3.

Fig. 19 illustrates the structure of the VIP bit select circuit 33. In this embodiment, the AND gates 53 of the second embodiment are not employed. When the I/O mode is set by the interface mode setting signal, the I/O-input signals I/O (0), (1), ..., (IS) are output as verification control signals as they are. In the address mode, the switches 54-(0) through 54-(I5) are turned OFF, and a decoded signal is output from the decoder 51. When the address mode is set, a WP-CAM address designating signal is input to the decoder Si, which then analyzes the signal so as to determine the VIP-CAM cell designated by the program. A high-level verification control signal indicating that the VIP-CAM cell is designated by the program is output

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to the volatile memory 11. The verification control signals that are output from the other WP-CAM cells (the WP-CAM cells that are not designated by the program) are at the low level, in the volatile memory 11, there are two memory regions that hold the data read out from CAM cells. A first memory region is a region holding the data that are proved to be certainly stored in the CAM cells through verification. In other words, the first memory region holds the data equivalent to the non-volatile memory information in the CAM cell array 4 after the programming (including verification) in the CAM cells, Accordingly, when there is a request for the data of the CAM cells from a circuit required in operations at the time of a regular operation of the regular cell array 3, the data stored in the first memory region are output. A second memory region is a region that is used as a temporary memory area and holds the data of CAM cells pre-read at the time of programming.

Receiving a verification control signal from the \VP bit select circuit 33, the volatile memory 11 outputs "0" as the expected value of the WP-CAM cell designated by the verification control signal, as shown in Fig. 18, instead of the data that are read in at the time of pre-reading. The volatile memory 11 also outputs (initial pass) the data stored in the second memory region at the time of pre-reading as the data of the other WP-CAM cells corresponding to low-level verification control signals.

Referring now to the flowchart of Fig. 20 and Fig. 21, the operation of programming the CAM cell array 4 set in the 110 mode in accordance with this embodiment is described. First, CAM program setting signals (T/0-0 through 1/0-15) for designating a V/P-CAM cell to be programmed are input from the respective I/Os (step S30), The information "1" for commanding programming is input to the 1/0 corresponding to the WP-CAM cell to be programmed, and the information "0" is input to the other IIOs.

The data are then pre-read from the V/P-CAM cells, and the data write state of each V/P-CAM cell is determined (step 831). If a V/P-CAM cell is in a programmed state with written data, the information "0" should be stored in the WP-CAM cell, If a WP-CAM cell is in an erased state without written data, the information "1" should be written in the WP-CAM cell, Next, the WP-CAM cell that is currently in an erased state and in which write is allowed by an I/O input signal is detected (step 832). More specifically, the WP-CAM cell having the pre-read data of"l" indicating an erased state and the I/O input of"i" is detected. In a case where the V/P-CAM cell designated for programming has already been programmed, the operation comes to an end, and an error signal is output. The procedures described so far are carried out by the controller 8.

Programming is performed on the detected WP-CAM cell (step 533). As the programming is performed, the verification circuit 13 determines whether the data have been certainly written in the \VP-CAM cell. At this point, the switches 54-(0) through 54-(1 5) provided for the I/Os are turned ON by the interface mode setting signal. The decoder 51 stops the operation upon receipt of the interface mode setting signal that is input via the inverter 52.

The WP bit select circuit 33 outputs the input signals I/0-(0) through 1/0-(1 5) as verification control signals to the volatile memory 11 as they are. More specifically, as "1" is P0-input to the WP-CAM cell designated by the program, the V/P-bit select circuit 33 outputs a high-level signal as the verification control signal.

The verification control signals corresponding to the other WP-CAM cells are at the low level.

The volatile memory 11 outputs the expected value "0" as the data of the WP-CAM cell designated by the high-level verification signal to the data comparator circuit 34 (see Fig. 21). The pre-read data stored in the second memory region are output as the expected value data of the other V/P-CAM cells (see Fig. 21).

The data comparator circuits 34-(0) through 34-(1 5) compare the data read from the WP-CAM cells after programming with the expected values read from the volatile memory 11 (step S34). Since the data read from a unprogrammed VIP-CAM cell is always the same as the expected value of the V/P-CAM cell, verification is performed by determining whether the data of each programmed WP-CAM is equal to the expected value. If the data read from the WP-CAM cell is not equal to the expected value ("NO" in step 835), the operation returns to the programming procedure (step S33). If the data read from the WP-CAM cell is equal to the expected value ("YES" in step 535), a matching signal indicating the matching between the data and the expected value is output from the data comparator circuit 34 to the determining circuit 12. If all the matching signals from the data comparator circuits 34 indicate the matching, the determining circuit 12 outputs a verification pass signal to the controller (step S36). If the verification succeeds, the data are read from the WP-CAM cell or the sense amplifier, and are stored as the authorized data of the WP-CAM cell in the first memory region of the volatile memory 11 (step 537).

In this embodiment, control is performed so as to perform a pseudo pass on the comparison results of the data comparator circuits allocated to the unprogrammed CAM cells, Accordingly, the programming result of the programmed CAM cell can be reflected in the verification.

Referring now to the flowchart of Fig. 22 and Fig. 23, the operation to be performed in the address mode is described. First, a VIP-CAM address designating -22 -signal for designating a WP-CAM cell to be programmed is input. The V/P-CAM address designating signal is analyzed by a decoder (step 840), so as to generate an address representing the WP-CAM cell to be actually programmed. In the verification circuit 13, the WP-CAM address designating signal is decoded by the decoder 5!. A verification control signal for designating the WP-CAM cell to be programmed is then output to the volatile memory 11.

Next, the data that have already been stored in the WP-CAM cell selected by the decoding result are read out through pre-reading (step S41). Using the pre-read data, the data write state of the V/P-CAM cell is determined.

If the V/P-CAM cell is determined to be in an erased state ("YES" in step 842), data is written in the V/P-CAM cell, which is thus put into a programmed state (step 843). If the WP-CAM cell is determined to be in a programmed state ("NO" in step 842), the operation comes to an end.

Thereafter, programming and verification are performed on the detected WP-CAM cell in the same manner as in the flowchart shown in Fig. 20. At the time of verification, the volatile memory 11 outputs the expected value "0" as the data of the V/P-CAM cell designated by the high-level verification control signal to the data comparator circuit 34 (see Fig. 23). The prc-read data stored in the second memory region are output as the expected value data of the other WP-CAM cells (see Fig. 23).

The data comparator circuits 34-(0) through 34-(l 5) compare the data read from the WP-CAM cells after programming with the expected values read from the volatile memory 11. If the data read from a V/P-CAM cell after programming is equal to the expected value of the WP-CAM, a verification pass signal is output to the controller 8, If the verification succeeds, the data are read from the WP-CAM cell or the sense amplifier, and are stored as the proper data of the WP-CAM cell in the first memory region of the volatile memory 11.

Fig. 24 illustrates the structure of the semiconductor device in detail. In the semiconductor device shown in Fig. 24, the inputs to each data comparator circuit 34 are switched by a CAM mode signal. More specifically, in a CAM mode, the output of the volatile memory IT is input to each data comparator circuit 34. In a regular operation, the outputs of the expected value holding circuits 32 are input to the data comparator circuits 34.

The above described embodiments are preferred embodiments of the present invention. However, the present invention is not limited to those embodiments, and various changes and modifications can he made without departing from the scope of the present invention.

For example, the volatile memory II may be formed with only one memory region (the first memory region). The CAM data written in the CAM cell array 4 are read by switching the switch 61 at the time of power supply or resetting the hardware.

Through pre-reading, the WP-CAM cell having the data of"l" indicating an erased state and the 110 input of"l" is detected by reading the information from the volatile memory 11. Programming is then performed on the detected VIP-CAM cell. As the programming is performed, the verification circuit 13 performs verification to determine whether the data have been certainly written in the VIP-CAM cell. The WP bit select circuit 33 outputs a high-level signal as a verification control signal to the WP-CAM cell designated by the program, and outputs low-level signals as the verification control signals to the other WP-CAM cells. The volatile memory ii outputs the expected value "0" to the data comparator circuits 34, regardless of the information stored as the data of the WP-CAM cell designated by the high-level verification control signal in the readout portion (not shown) of the first memory region. More simply, a clamp circuit that uses a verification control signal is attached to the readout portion of the first memory region, so as to clamp the outputs to "0" The information stored in the first memory region is output as the expected value data of the other WP-CAM cells, without an operation of the clamp circuit.

The data comparator circuits compare the data read from a WP-CAM cell after programming with the expected value read from the volatile memory 11. If the verification result indicates "matching", the data read from the WP-CAM cell or the sense amplifier by switching on the switch 61, and are stored as the proper data of the WP-CAM cell.

The device components of the volatile memory 11 may include a so-called static memory cell, or may be a latch circuit that is formed with logic elements applied to the peripheral circuits.

Although a few preferred embodiments of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.

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Claims (12)

1. CLMMS: I. A semiconductor device comprising: a cell array that stores operation setting information as to the semiconductor device; a write circuit that simultaneously programs memory cells in the cell array; a verification circuit that verifies a programming result of only memory cells that are actually programmed, wherein the verification circuit comprises: comparator circuits that compare expected value data obtained by normal programming with data that are read from the memory cells after programming: and a control unit that makes a pseudo-pass for comparator outputs relatcd to programming results of memory cells that are not programmed, wherein: the control unit identifies a memory cell in an erased state prior to the programming, the memory cell being designated as being to be programmed by an external input; and the semiconductor device further comprises a circuit that generates expected value data obtained by normal programming in response to an instruction from the control unit, and outputs the expected value data to one of the comparator circuits related to the designated memory cell.
2. 2. A semiconductor device comprising: a cell array that stores operation setting information as to the semiconductor device; a write circuit that simultaneously programs memory cells in the cell array; a volatile memory circuit that stores data stored in the memory cells prior to programming; and a verification circuit that verifies, with the data stored in the volatile memory circuit, memory cells that are programmed, using expected value data obtained by normal programming.
3. 3. The semiconductor device as claimed in claim 2, wherein the verification circuit comprises: comparator circuits that compare expected value data obtained by normal programming with data that are read from the memory cells or a sense amplifier afler programming; and a control unit that identifies the memory cell that is actually programmed and causes one of the comparator circuits related to the memory cell actually programmed to verify a programming result thereof with the expected value data obtained by normal programming.
4. 4. The semiconductor device as claimed in claim 3, wherein: the control unit identifies a memory cell in an erased state prior to programming, the memory cell being designated as being to be programmed by an external input; and the semiconductor device further comprises a circuit that changes the expected value data stored in the volatile memory circuit and related to a memory cell in an erased state prior to programming to the expected value data obtained by normal programming, and outputs the expected data value thus changed to the one of the comparator circuits.
5. 5. The semiconductor device as claimed in claim I or claim 3, wherein the control unit externally receives an instruction signal indicating whether each memory cell should be progranmed, and identifies a memory cell to be actually programmed by determining whether the memory cell to be programmed is in an erased state.
6. 6. The semiconductor device as claimed in claim 1 or claim 3, wherein the control unit decodes address information externally supplied to identify a memory cell to be programmed, the control unit identifying a memory cell to be actually programmed by determining whether the memory cell to be programmed is in an erased state.
7. 7. The semiconductor device as claimed in claim 1 or claim 3, wherein the control unit changes an interface that designates a memory cell to be programmed in response to a mode switching signal that is externally supplied.
8. 8. The semiconductor device as claimed iii claim 1 or claim 2, wherein the verification circuit is shared between verification after programming of the cell array storing the operation setting information, and verification after programming of a regular cell array storing regular data.
9. 9. The semiconductor device as claimed in claim 1 or claim 3, wherein the comparator circuits compare the expected value data obtained by normal programming with data read from the memory cells after programming in response to a mode signal for switching an operation mode to programming of the cell array storing the operation setting information.
10. 10. The semiconductor device as claimed in claim 3, wherein: the comparator circuits use output of the volatile memory circuit at the time of programming of the cell array storing the operation setting information; and the comparator circuits use outputs of a circuit holding the expected value data obtained by normal programming of the memory cell at the time of programming a regular cell.
11. 11. A method of verifying a cell array that stores operation setting information as to a semiconductor device, the method comprising the step of: simultaneously programming memory cells in the array; verifying a programming result of only memory cells that are actually programmed among memory cells in the cell array.
12. 12. A method of verifying a cell array that stores operation setting information as to a semiconductor device, the method comprising the steps of: simultaneously programming memory cells in the array, verifying memory cells that are actually programmed with expected value data obtained by normal programming.