JP2008293652A - Synchronous type semiconductor memory device and its test method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a synchronous type semiconductor memory device in which the number of observation pins can be reduced during a test, while output can be performed decreasing a data rate. <P>SOLUTION: The device includes a coincidence detecting circuit 250 which detects coincidence of data output to a plurality of data terminals in an input/output circuit part. Same results are written in latches 146, 148 during a test time and they are read out alternately in accordance with a clock signal. Therefore, the test result can be output from a terminal which outputs data with double data rate during normal operation decreasing the data rate. Observation can be performed by a tester having low performance also and a test cost can be reduced. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a synchronous semiconductor memory device and a test method thereof, and more particularly to an input / output circuit that inputs / outputs data in synchronization with a clock, a synchronous semiconductor memory device including the same, and a test method thereof.

  2. Description of the Related Art Conventionally, in a data input / output circuit used in a semiconductor device, for example, a semiconductor memory device, by shifting the phase of a plurality of data to be output with respect to an internal clock, the data is transferred from the semiconductor memory device to the outside of the semiconductor memory device at a rate higher than the clock frequency. And was transferring data.

  In addition, in order to reduce the inspection cost, there is an increasing number of cases where a BIST (Built-in Self Test) in which the chip itself has a function of performing a memory cell reading and writing test is employed.

  FIG. 67 is a block diagram showing a block configuration of a memory with a conventional BIST (built-in self test) function.

  Referring to FIG. 67, this memory includes a clock generation circuit CKG for generating an internal operation clock in response to control signals / RAS, / CAS, / WE, an address buffer ADB for receiving address signal AI from the outside, a clock In accordance with a clock generated by the generation circuit CKG, an X decoder XDEC and a Y decoder YDEC for decoding an address signal and a memory cell array MA for exchanging data with the outside are provided.

  The memory further includes a self test circuit STC. Self-test circuit STC includes a ROM for storing a coded test procedure, a program counter PC, an address counter AC, a data generation circuit DG, a data comparison circuit DC, and a test clock generation circuit TCG.

  During the self-test, the program counter PC reads a desired instruction from the mounted ROM, and therefore designates the address of the ROM storing the instruction. The ROM sequentially outputs a coded test procedure for controlling the program counter PC, the address counter AC, the data generation circuit DG, the data comparison circuit DC, and the test clock generation circuit TCG to advance the memory test.

  By incorporating such a self-test circuit in the semiconductor memory device, a high-performance test can be performed even with a simple tester device, and the test cost can be reduced.

  However, in the data input / output circuit, when a plurality of data are interleaved with the recent increase in the operation speed of the semiconductor device, when the circuit connected to the outside picks up, a collision between the data occurs, There was a problem of picking up incorrect data.

  When a huge synchronous semiconductor memory device having a memory capacity as large as 1 Gbit is used, the skew of an internal signal, particularly a clock for controlling the operation of the entire chip increases, and this skew limits the chip operating frequency. Become. In particular, after receiving a reference clock input from the outside with a clock buffer, when receiving addresses, data, and commands based on that clock, the received clock is input to each address, data, and command. The delay required to transmit this clock will limit the performance of the chip. At the same time, when the output buffer is controlled based on the clock, the output is delayed by the amount of clock skew, and the margin of output data received externally is impaired.

  As a second problem, with the increase in the operation speed of the semiconductor memory device, there are the following problems in the operation test during the manufacturing process or before the product shipment.

  That is, as the storage capacity of the semiconductor memory device increases, the time required for the test also increases, which in turn increases the cost required for the test and the manufacturing cost of the product itself.

  Conventionally, as a countermeasure against an increase in test time accompanying an increase in storage capacity of a semiconductor memory device, first, a plurality of semiconductor memory devices are tested in parallel to improve test efficiency. However, the increase in the storage capacity of the semiconductor memory device as described above results in, for example, an increase in the number of bits of the address signal given to the semiconductor memory device and an increase in the number of data input / output interfaces. As the number of control signal input pins and input / output pins increases, the number of semiconductor memory devices that can be tested simultaneously in parallel is limited.

  The number of semiconductor memory device chips that can be simultaneously measured in the tester device is determined by the relationship between the number of pins on the tester side and the number of pins required on the chip side, and is generally represented by the following equation.

(Number of pins of tester device) / (Number of pins required for chip)> (Number of chips that can be measured simultaneously)
Furthermore, if the operation speed of the tester device for testing the semiconductor memory device itself is improved as the operation speed of the semiconductor memory device itself is improved, an extremely expensive tester device is required. Increases costs.

  As a third problem, the synchronous semiconductor memory device employs a complicated system such as clock generation by BIST (built-in self test) or DLL (delay locked loop) to reduce costs and improve functions. This circuit has a problem that it is difficult to observe the operation state from the outside.

  An object of the present invention is to increase the number of chips that can be simultaneously measured by one tester device by reducing the number of terminals used at the time of inspection, and to reduce the data rate of output data to be observed, thereby reducing the data rate of output data to be observed. An object of the present invention is to provide a synchronous semiconductor memory device capable of reducing the inspection cost by enabling inspection without using the device.

  Another object of the present invention is to provide a synchronous type that facilitates inspection and evaluation of the internal circuit by enabling the state of the internal circuit that cannot be directly observed from the outside during operation to be observed from the outside via an input / output circuit. A semiconductor memory device is provided.

  In summary, the present invention is a synchronous semiconductor memory device, a memory array, a read circuit that reads first and second storage data from the memory array in response to an address signal, and first and second First and second data buses for receiving the two stored data, respectively, and a first input / output circuit for receiving the first and second stored data from the first and second data buses. The output circuit includes a data processing unit that receives both the first and second storage data and outputs the first and second output data. The data processing unit serves as the first and second output data during normal operation. First and second storage data are output, respectively, and a predetermined conversion process is performed on the first and second storage data during the test to generate first and second output data. First and second output data respectively received And a second data holding circuit and an output circuit for receiving the first and second output data held by the first and second data holding circuits and alternately outputting them in response to a clock signal, A first output node for receiving the output of the circuit is further provided.

  Preferably, the synchronous semiconductor memory device receives the third and fourth storage data that are read together with the first and second storage data from the memory array during normal operation, and outputs them alternately according to the clock signal. And a second output node that receives the output of the second input / output circuit during normal operation, and the data processing unit includes at least first storage data and third storage data The first degeneration circuit that outputs the first output data during the test according to the coincidence determination result, and the second output data according to the coincidence determination result between at least the second storage data and the fourth storage data And a second degeneration circuit that outputs during the test.

  More preferably, the synchronous semiconductor memory device receives the fifth and sixth storage data read together with the first and second storage data from the memory array during normal operation, and alternately according to the clock signal. A third input / output circuit for outputting and a third output node for receiving an output of the third input / output circuit during normal operation, wherein the first degeneration circuit includes at least the first storage data and the third output node; A first coincidence determination circuit for performing coincidence determination with stored data, a second coincidence determination circuit for performing coincidence determination between at least first storage data and fifth storage data, and first and second coincidence determinations A first gate circuit that activates the first output data during the test when both the circuits detect coincidence, and the second degeneration circuit includes at least the second storage data and the fourth storage data. Match with When the third coincidence determination circuit, the fourth coincidence determination circuit that performs coincidence determination between at least the second storage data and the sixth storage data, and the third and fourth coincidence determination circuits both detect coincidence. And a second gate circuit for activating the second output data during the test.

  Preferably, the synchronous semiconductor memory device receives the third and fourth storage data that are read together with the first and second storage data from the memory array during normal operation, and outputs them alternately according to the clock signal. And a second output node that receives the output of the second input / output circuit during normal operation, and the data processing unit has at least the first to fourth storage data match. And a first coincidence determination circuit that outputs the determination results as first and second output data during the test.

  More preferably, the output circuit outputs first and second output data in response to activation and inactivation of the clock signal, respectively.

  A synchronous semiconductor memory device according to another aspect of the present invention controls a memory array, execution of a self test for the memory array, provides an address signal and a command signal to the memory array, and transmits / receives stored data. (Built-in Self Test) A control circuit and a first terminal for outputting a test result of the preliminary test in a preliminary test mode for executing a preliminary test for testing whether the self test can be executed.

  Preferably, the synchronous semiconductor memory device has a second terminal to which a first predetermined potential exceeding the first power supply potential is applied in order to designate execution of a self test, and a predetermined potential is applied to the second terminal. A detection circuit that detects the occurrence of the failure, a BIST execution flag that is set according to the output of the detection circuit, a flag holding unit that outputs the BIST execution flag to the BIST control circuit, and a preliminary detection that the detection circuit has detected And an output circuit for outputting to the first terminal in the test mode.

  Preferably, the BIST control circuit includes a RAM unit that stores test data corresponding to a self-test procedure, and a pattern generation unit that performs self-test control based on the test data stored in the RAM unit. Includes test data stored in the RAM unit, and the RAM unit includes first to n-th group storage units (n is a natural number) which is a unit selected by the pattern generation unit when the self-test is executed, The storage units of the group are selected at a time when the self-test is executed, output test data to the pattern generation unit, and have m storage units each serving as a shift register connected in series in the preliminary test mode. (M is a natural number) In the preliminary test mode, the first group of storage units is tested from the first terminal. In the preliminary test mode, the storage unit in the i-th group (i is a natural number of 2 to n-1) sends the test data to the storage unit in the (i + 1) -th group. In the preliminary test mode, the nth group of storage units outputs test data to the first terminal.

  Preferably, when a defective part is found in the memory array during the self test, the BIST control circuit suspends the self test and sequentially outputs each bit of the defective address corresponding to the defective part. The semiconductor memory device further includes a second terminal that receives each bit and outputs it to the outside.

  More preferably, the synchronous semiconductor memory device holds a flag that detects a coincidence of a plurality of read data from the memory array and outputs a suspend flag that suspends the self-test in response to an output of the defect detection circuit. , A third terminal for outputting a recognition signal for executing a defective address output operation in accordance with the suspend flag, and a completion signal indicating that reception of the defective address is completed from the outside. And a completion detection circuit for outputting a suspend flag reset signal to the flag holding unit in response to the completion signal.

  Preferably, the memory array includes a plurality of normal memory cells arranged in a matrix, a plurality of redundant rows made of redundant memory cells, and a plurality of redundant columns made of redundant memory cells, and a synchronous semiconductor memory device Receives a defect detection circuit for detecting coincidence of a plurality of read data from the memory array, receives a defect address corresponding to a defect location in accordance with an output of the defect detection circuit, performs address processing, holds corresponding information, and An address processing unit for determining a replacement row address and a replacement column address respectively corresponding to a row to be replaced with a redundant row and a column to be replaced with a redundant column in response to a test end signal output from the control circuit; In response to the output of the defect detection circuit, a suspend flag for temporarily suspending the self test is output, and a processing completion signal indicating the end of address processing is received from the address processing unit. Further comprising a flag holding unit for resetting the suspend flag Te.

  More preferably, the address processing unit includes a first number of address holding units that is the sum of the number of redundant rows and the number of redundant columns, and each address holding unit stores a row address register that holds a row address of a defective address. And a row counter that is provided corresponding to the row address register and counts the number of detections of the row address stored in the row address register, and is provided corresponding to the row address register and stored in the row address register. A row flag setting unit that holds that the row address has been determined to be replaced, a column address register that holds the column address of the defective address, and a column address that is provided corresponding to the column address register and is stored in the column address register Column counter that counts the number of detections and column address stored in the column address register corresponding to the column address register And a column flag setting unit which holds that it has been determined substituted, address processing unit determines the row address replacement and column address replacement based on the count value of the column address counter and a row address counter.

  More preferably, the synchronous semiconductor memory device receives the replacement address determined by the address processing unit in response to the test end signal output from the BIST control circuit, holds the replacement address, and the designated address at the normal read of the memory array is A replacement address setting unit that outputs a replacement instruction signal when it matches the replacement address is further included, and the replacement address setting unit includes a nonvolatile memory element that receives and holds the replacement address in response to the test end signal.

  More preferably, the synchronous semiconductor memory device receives the replacement address determined by the address processing unit in response to the test end signal output from the BIST control circuit, holds the replacement address, and the designated address at the normal read of the memory array is A replacement address setting unit that outputs a replacement instruction signal when matched with the replacement address is further included, and the replacement address setting unit includes a plurality of fuse elements whose conduction state is changed corresponding to the address in response to the test end signal. .

  Preferably, the synchronous semiconductor memory device is provided with a first data group, a data group provided between the memory array and the first input / output terminal group, and activated when the self-test is performed to indicate the state of the internal circuit. And a data transmission circuit for outputting to one input / output terminal group, and the data group includes command data, address data, and test output data corresponding to the storage data, both of which are used for the storage operation of the memory array.

  More preferably, the synchronous semiconductor memory device further includes a degeneration circuit that degenerates any of command data, address data, and storage data and outputs test output data.

  In yet another aspect, the present invention provides a method for testing a synchronous semiconductor memory device, wherein the synchronous semiconductor memory device controls execution of a memory array and a built-in self test (BIST) for the memory array. The preliminary test is performed in the preliminary test mode in which the BIST control circuit for supplying the address signal and the command signal to the memory and transferring the stored data and the preliminary test for testing whether the built-in self test (BIST) can be executed. A BIST control circuit including a RAM unit storing test data corresponding to a self-test procedure, and a pattern for performing self-test control based on the test data stored in the RAM unit. Test results stored in the RAM section. The RAM unit includes first to n-th groups of storage units (n is a natural number) that is a unit selected by the pattern generation unit when the self-test is executed. Each having m storage units (m is a natural number), each of which is a shift register connected in series in the preliminary test mode. The first step of inputting the test data from the first group to the first group to the nth group of storage units and sequentially storing the data in the first group to the nth group of storage units, and the test data from the nth group of storage units through the first terminal Or a second step of sequentially shifting and reading the test data set in the storage unit of the nth group.

  A synchronous semiconductor memory device according to still another aspect of the present invention includes a memory array, and a first coincidence detection circuit that receives a plurality of storage data read from the memory array in response to a clock signal and detects a coincidence. And a shift register receiving the output of the coincidence detection circuit, the shift register including first to nth holding circuits connected in series for taking stored data and outputting held data in response to a clock signal. (N is a natural number greater than or equal to 2), the synchronous semiconductor memory device further includes a second coincidence detection circuit that determines whether or not the outputs of the first to nth holding circuits all coincide.

  The synchronous semiconductor memory device of the present invention can reduce the number of data input / output terminals necessary for monitoring the data output, and can reduce the number of channels used by the tester in the inspection of the semiconductor memory device. Therefore, the inspection cost of the semiconductor memory device can be reduced.

  Further, the synchronous semiconductor memory device of the present invention can greatly improve the defect detection rate.

  In addition, the data rate of the data to be observed can be reduced, and even a tester device that is not so high in performance can be inspected.

  In addition, before the BIST test is performed, the operation of the circuit that controls the BIST can be confirmed in advance.

  In addition, it can be seen whether or not the BIST RAM section operates normally. In addition, the number of pins required for the RAM test can be reduced.

  Since another synchronous semiconductor memory device of the present invention can output a defective address detected internally to a tester device or the like connected to the outside even when executing BIST, the result of BIST Redundant replacement can be performed using the output address.

  Further, since the defective address detection and redundant replacement can be executed by the chip itself without an expensive test apparatus, the cost can be further reduced.

  In addition, when the BIST is executed, the internal state can be monitored by the test apparatus, so that the result of the operation confirmation can be further ensured, and the cause of the occurrence of the trouble can be easily clarified.

  Further, the test method for the synchronous semiconductor memory device can determine whether or not the BIST RAM section operates normally. In addition, the number of pins required for the RAM test can be reduced.

  In addition, the non-defective / defective product of the synchronous semiconductor memory device can be discriminated even when the number of test result output signals is small, and the non-defective / defective product of the synchronous semiconductor memory device can be discriminated even in a tester with low performance. When a failure is determined, it is possible to obtain a clue to know the address where the failure has occurred by observing the output signal of the shift register.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

[Embodiment 1]
FIG. 1 is a schematic block diagram showing the overall configuration of a synchronous semiconductor memory device 1000 of the present invention.

  Referring to FIG. 1, synchronous semiconductor memory device 1000 is a double data rate synchronous dynamic random access memory (hereinafter referred to as DDR SDRAM) having a capacity of 1 Gbit.

  Synchronous semiconductor memory device 1000 has terminals P1 and P2 that receive complementary clock signals CLK and / CLK serving as a reference for the entire operation given from the outside, and a terminal P3 that receives enable signal CKE enabling input to the chip. A terminal P4 that receives a signal / CS for identifying an input of a command, a terminal P5 that receives a signal / RAS indicating that a row-related command has been input, and a signal / that indicates that a column-related command has been input A terminal P6 that receives CAS, a terminal P7 that receives a signal / WE that is a read / write identification signal, a terminal P8 that inputs and outputs data mask signals DM0 to DM3 that identify invalidity of data at the time of reading or writing, and a read Or a terminal group P9 for inputting / outputting data strobe signals QS0 to QS3 for identifying the timing of data at the time of writing, and an input A terminal P10 to which a reference potential Vref for determining the H level / L level of the signal is input, a terminal group P11 to which address signals A0 to A12 are input, and a 3-bit bank address BA0 to eight built-in memory banks. A terminal group P12 for receiving BA2 and a terminal group P13 for inputting / outputting 32-bit data input / output signals DQ0 to DQ31.

  The synchronous semiconductor memory device 1000 does not operate while the enable signal CKE is not activated. During the inactive period, the synchronous semiconductor memory device is in a standby state or a self-refresh state.

  While the signal / CS is activated, the command is recognized at the rising edge of the clock. The data mask signals DM0 to DM3 are transmitted from the semiconductor memory device side to the controller IC when data is invalid at the time of reading. On the other hand, when data invalidity is indicated at the time of writing, the data mask signals DM0 to DM3 are transmitted from the controller IC side to the semiconductor memory device. Is transmitted to. One data mask signal DM is assigned to every eight data input / output signals DQ.

  Similarly, the data strobe signal QS transmits the data timing from the semiconductor memory device side to the controller IC at the time of reading, and from the controller IC side to the semiconductor memory device side at the time of writing. One data strobe signal QS is assigned to every eight data input / output signals DQ.

  In the address signals A0 to A12, all 13 bits are used as row address inputs, and 10 bits out of 13 bits are used as column address inputs. A part of the address signal is also used for writing to the mode register.

  The synchronous semiconductor memory device 1000 further includes a mode decoder 2 for recognizing an input command, a mode register 16 for holding an operation mode, a row address latch 8 for fetching a row address from an address terminal, and a column from an address terminal. A column address latch 12 for fetching an address, a bank address latch 18 for fetching a bank address signal from the bank address, and a bank decoder 20 for activating a corresponding bank by decoding a bank address output from the bank address latch 18 Including.

  The synchronous semiconductor memory device 1000 further outputs a self-refresh timer 4, a refresh address counter 6 and an address output from the row address latch 8 and a refresh address counter 6 provided together to generate a refresh address during a refresh operation. A multiplexer 24 for selecting one of the addresses, a row predecoder 10 that receives an address output from the multiplexer 24 and outputs a corresponding signal to the row decoder RD, and a burst address counter 28 that generates a continuous column address during a burst operation. And column predecoder 14 which receives an address output from burst address counter 28 and outputs a corresponding signal to column decoder CD.

  The synchronous semiconductor memory device 1000 further includes a delay-locked loop (hereinafter referred to as DLL) circuit 30 that generates a clock CLK (in) that is in phase with the clock CLK input from the outside, and a data input / output terminal group P13. Further included is a data conversion unit 22 that converts the data rate with the global input / output line GI / O to exchange data.

  Global input / output line GI / O exchanges data with eight memory banks BANK0 to BANK7.

  FIG. 2 is a schematic diagram showing an arrangement example of each block in the synchronous semiconductor memory device 1000 according to the first embodiment of the present invention.

  Referring to FIG. 2, synchronous semiconductor memory device 1000 receives and decodes external control signals / RAS, / CAS, / WE, / CS, etc. applied through external control signal input terminal group 60. A control circuit 70 for generating an internal control signal, command data buses 53a and 53b for transmitting an internal control signal output from the control circuit 70, and a memory cell array 100 in which memory cells are arranged in a matrix.

  As shown in FIG. 2, the memory array 100 is divided into a total of 16 memory cell blocks 100a to 100p. For example, when the storage capacity of synchronous semiconductor memory device 1000 is 1 Gbit, each memory cell block has a capacity of 64 Mbits. Each block is configured to be able to operate independently as a bank.

  Synchronous semiconductor memory device 1000 further receives an external clock signal CLK applied to clock signal input terminal 66, is controlled by control circuit 70 to start a synchronous operation, and outputs internal clock signal CLK (in). A signal generation circuit 18 is included.

  The internal synchronization signal generation circuit 18 generates an internal clock signal CLK (in) synchronized with the external clock signal CLK by using, for example, a DLL circuit.

  External address signals A0 to A12 and BA0 to BA2 applied through address signal input terminal group 62 are synchronized with internal clock signal CLK (in) under the control of control circuit 70, and are stored in semiconductor memory device 1000. It is taken in.

  External address signals BA0-BA2 are applied to bank decoder 72 via address bus 51a. Decoded bank addresses B0 to B7 are transmitted from bank decoder 72 to each memory cell block via address buses 51b and 51c.

  The bank addresses B0 to B7 are the sum of any one of the memory cell blocks provided corresponding to the data input terminals DQ0 to DQ15 and any one of the memory cell blocks provided corresponding to the data input / output terminals DQ16 to DQ31. Two memory cell blocks are activated.

  On the other hand, other external address signals applied to address signal input terminal group 62 are transmitted to address driver 52 through address buses 50a and 50b. Further, an address signal is transmitted from the address driver 52 to each memory cell block via the address bus 50c.

  The synchronous semiconductor memory device 1000 is further provided for each pair of memory cell blocks. Under the control of the control circuit 70, the synchronous semiconductor memory device 1000 latches the row address transmitted by the address bus 50c and predecodes the row predecoder 36. A row decoder 44 for selecting a corresponding row (word line) of a memory cell block selected based on an output from the row predecoder 36, and provided for each memory cell block, under the control of the control circuit 70 The column predecoder 34 for latching and predecoding the column address transmitted by the address bus 50c, the column predecoder line 40 for transmitting the output from the column predecoder 34, and the output from the column predecoder line 40 are also provided. Select the corresponding column (bit line pair) of the selected memory cell block. And a column decoder 42.

  The synchronous semiconductor memory device 1000 is further arranged in an area along the long side direction at the center of the chip, outside the area where the external control signal input terminal group 60 and the address signal input terminal group 62 are provided. Data is input between data input terminals DQ0 to DQ15 and DQ16 to DQ31, input / output buffer circuits 64a to 64f provided corresponding to data input / output terminals DQ0 to DQ31, respectively, and memory cell blocks corresponding to the input / output buffers. Data bus 54 for transmission and read / write amplifier 38 provided corresponding to each of memory cell blocks 100a to 100p and transferring data between data bus 54 and a selected memory cell column are included.

  Signal / RAS applied to external control signal input terminal group 60 is a row address strobe signal that starts internal operation of synchronous semiconductor memory device 1000 and determines the active period of internal operation. In response to the activation of signal / RAS, a circuit related to the operation of selecting a row of memory cell array 100 such as row decoder 44 is activated.

  Signal / CAS applied to external control signal input terminal group 60 is a column address strobe signal, and activates a circuit for selecting a column in memory cell array 100.

  Signal / CS applied to external control signal input terminal group 60 is a chip select signal indicating that synchronous semiconductor memory device 1000 is selected. Signal / WE is a write operation of synchronous semiconductor memory device 1000. Is a signal for instructing.

  Signal / CS, signal / RAS, signal / CAS and signal / WE are fetched in synchronization with internal clock signal CLK (in).

  The address signal applied to address signal input terminal group 62 is also fetched in synchronization with internal clock signal CLK (in).

[Description of asynchronous concept]
The present invention enables the inside and outside of the input / output circuit to operate asynchronously. Before describing a specific configuration, the asynchronous concept will be briefly described.

FIG. 3 is an operation waveform diagram for explaining the asynchronous concept.
Referring to FIG. 3, an externally input clock CLK serves as a reference for reading / writing data from / to the memory array in the synchronous semiconductor memory device.

At time t1, a write command is input from the outside.
At the time of writing, the synchronous semiconductor memory device takes in data according to the timing of a signal DQS inputted in synchronization with data from the outside. At time t2, in response to the rise of signal DQS, data D1 input to data input / output terminal DQ is taken and written to a write latch provided in the input / output circuit portion. Similarly, at times t3, t4, and t5, the data D2, D3, and D4 are taken into the write latch at the timing when the signal DQS changes.

  At time t6, the data D1 and D2 taken in the write latch are written into the memory array in response to the rise of the clock CLK. Next, at time t7, the data D3 and D4 taken in the write latch are written into the memory array.

At time t8, the burst write ends and the write latch is reset.
Similarly, at time t8, a read command is input from the outside. Data D5 and D6 written in the memory array portion are transmitted to the read latch of the input / output circuit portion according to the internal clock generated internally based on the clock CLK between times t8 and t9. Subsequently, at times t9 to t10, the data D7 and D8 written in the memory array according to the internal clock generated internally based on the clock CLK are transmitted to the read latch of the input / output circuit section. . At the time of reading, the data held in the latch of the input / output circuit section is output at a timing when the system connected to the outside of the semiconductor memory device needs the data, and the signal DQS corresponding to this timing is output to the synchronous semiconductor memory. The device sends out to an external system.

  Data D5 to D8 are sequentially output to the outside in accordance with the change of the signal DQS between times t11 and t15.

  In this case, as shown in FIG. 3, the timing of outputting data is not always synchronized with the clock CLK input from the outside.

At time t15, the burst read is completed and the read latch is reset.
As described above, the synchronous semiconductor memory device reads / writes data from / to the memory array according to the internal clock generated internally based on the clock CLK input from the outside. On the other hand, when exchanging data with the outside, the synchronous semiconductor memory device takes in the data into the latch unit in response to the signal DQS indicating the timing according to the specifications of the system connected to the outside, and the latch unit To send data.

[Detailed configuration of input / output circuit section]
FIG. 4 is a schematic diagram for explaining the connection between each bank and each input / output circuit.

  FIG. 4 shows the connection between the banks 100a to 100d of the synchronous semiconductor memory device described in FIG. 2 and the input / output circuits of the data input / output terminals DQ0 to DQ15. The area for bits is enlarged. Referring to FIG. 4, banks 100a and 100b are divided into an area 100ab corresponding to an even address and an area 100abo corresponding to an odd address, respectively, across main word driver MWD.

  In the double data rate method, it is necessary to output data at a frequency twice that of the internal clock. By dividing in this way, it is possible to simultaneously access data corresponding to odd addresses and even addresses, facilitating data output operation at twice the frequency.

  However, this is not necessarily a requirement. It can also be realized by making the access timing of the corresponding area early if the address of the data to be output first is an odd number or even and delaying the access timing of the area to be accessed second. This method can also prevent a large current peak from occurring. However, since the phase of the access timing must be changed depending on whether the first address to be accessed is an even number or an odd number, the operation control is complicated.

  The data from the even address area and the data from the odd address area in one bank are input to the same DQ portion.

  For example, the input / output circuit 64a provided corresponding to the data input / output terminal DQ0 is connected to the read amplifier 102 for reading data from the even address regions 100be and 100cde and the write amplifier 122 for writing data. The input / output circuit 64a is further connected to a read amplifier 104 for reading data from the odd address areas 100abo and 100cdo and a write amplifier 124 for writing data.

  Corresponding data input / output terminals DQ1 to DQ15 are also provided with input / output circuits, and read / write amplifiers for odd address areas and even address areas are connected to the respective input / output circuits.

  FIG. 5 is a diagram for explaining the flow of data output from the memory bank to the data input / output terminal DQ0.

  When data in an odd area of a bank is read, the data read from the memory cell array by read amplifier 104 is output to read data bus RDBO. This data is selected by the multiplexer 110, temporarily held in the latch 112, and then output to the terminal via the multiplexer 114 and the output buffer 116. When data is read from the even area, data is supplied from the read amplifier 102 to the multiplexer 110 via the read data bus RDBE.

  FIG. 6 is a diagram for explaining the flow of writing data from the data input / output terminal DQ0 to the bank.

  Referring to FIG. 6, when data is written to an odd address, the data input from the terminal is output to write data bus WDBO via input buffer 136, demultiplexer 134, latch 132, and demultiplexer 130, and written. The signal is transmitted to the memory array by the amplifier 124. Similarly, when writing data to even addresses, data is transmitted from the demultiplexer 130 to the write amplifier 122 via the write data bus WDBE, amplified and transmitted to the memory array.

FIG. 7 is a diagram schematically showing the configuration of the data input / output terminals DQ0 to DQ15.
Referring to FIG. 7, data input / output terminals DQ0 to DQ15 are arranged in order, and an input / output circuit including a latch is provided corresponding to each. A read data bus RDB and a write data bus WDB are connected to the input / output circuit. The read data bus and the write data bus may be shared.

  Although not shown, input / output circuits are similarly provided for the data input / output terminals DQ16 to DQ31.

  FIG. 8 is an enlarged view of a portion corresponding to data input / output terminals DQ0 to DQ3 shown in FIG.

  Referring to FIG. 8, an input / output circuit provided corresponding to a data input / output terminal receives receivers 142 and 143 that receive data on read data bus RDB, and receives data from receivers 142 and 143, and sends data from either receiver first. The multiplexer 144 that distributes data according to whether the data is output to the data, the data from the multiplexer 144, the latch 148 for four data that outputs data at odd clock edges after CAS latency, and the data from the multiplexer 144, It includes a latch 146 for four data that outputs data at even clock edges after CAS latency, and an output buffer 150 that amplifies the data output from the latches 148 and 146 and outputs the amplified data to the terminal.

  The input / output circuit further includes an input buffer 152 for amplifying data externally applied to the input / output terminal DQ0, a latch 156 for four data for latching data output from the input buffer 152 at the rising edge of the clock, A latch 154 for four data that captures the data output from the input buffer 152 at the falling edge of the clock, and an even number according to the address when the data captured by the input data latches 154 and 156 is transmitted internally. A multiplexer 158 for distributing data to either the address data bus or the odd address data bus is included. The output of the multiplexer 158 is connected to a write data bus WDB including a write data bus for even addresses and a write data bus for odd addresses.

  FIG. 9 is a diagram for explaining an outline in which the synchronous semiconductor memory device 1000 exchanges data through the input / output circuit unit.

  Referring to FIG. 9, signal CLK is an externally applied clock signal, and signal CLK (ctr) is an internal clock that is generated internally based on clock signal CLK and serves as a reference for the operation of the memory array. / CS, / RAS, / CAS, / WE are control signals for causing the synchronous semiconductor memory device 1000 to recognize commands.

  The signal L-DQ is a data signal input / output to / from the lower bit side of the data input / output terminal, that is, the data input / output terminals DQ0 to DQ15, and the signal U-DQ is the upper bit of the data input / output terminal, that is, the data input / output terminal. Data signals input to and output from DQ16 to DQ31 are shown.

  A signal 64-ARRAY indicates a signal on the data bus for inputting / outputting data between the input / output circuit unit and the internal memory array. Here, the signal L-Even indicates data from the area corresponding to the even address on the lower bit side of the data, and the signal L-Odd indicates data from the area corresponding to the odd address on the lower bit side of the data.

  At time t1, an active command (ACT) is input, and at time t2, a write command (WRITE) is input.

  After time t3, continuous data having a burst length of 8 is input to the data input / output terminals DQ0 to DQ31 at a data rate twice that of the clock CLK.

  Two data are taken into the input / output circuit at the rising edge and the next falling edge of the clock at time t3, and sequentially output to the memory array after time t4. At this time, 32 bits of data input from the outside is reduced to a half of the frequency and becomes 64 data in which the number of bits is doubled. The 64 data is written into the memory array at a time. The 32-bit data having a burst length of 8, that is, 4-bit 64-bit data synchronized with the internal clock CLK (ctr) is written to the internal memory array.

  At time t5, a read command is input and 64-bit data is simultaneously read from the internal memory array, and 32-bit double data rate data is output to the outside from the semiconductor memory device after time t6.

FIG. 10 is a circuit diagram showing a configuration of input / output circuit 64 used in the first embodiment.
Referring to FIG. 10, address bus EVEN0 is a data bus connected to the even address areas of bank 0 to bank 3, and address bus ODD0 is a data bus connected to the odd address areas of bank 0 to bank 3. It is. The address bus EVEN1 is a data bus connected to the even address areas of the banks 4 to 7, and the address bus ODD1 is a data bus connected to the odd address areas of the banks 4 to 7.

  The input / output circuit 64 selects one of the address buses EVEN0, ODD0, EVEN1, and ODD1 according to the selected bank and the even and odd addresses corresponding to the first data to be output, and is transmitted from the address bus. Receivers 142 and 143 that output data in response to the receiver activation signal R-EN, a shift register 162 that performs a shift operation with the read clock RCLK (ctr) and outputs a select signal, and a select signal that the shift register 162 outputs Correspondingly, latches 146 and 148 for receiving data output from receivers 142 and 143 are included.

  The input / output circuit 64 further receives the thinned clocks DLLe and DLLo generated based on the clock DLL generated by the DLL circuit, and inputs them as data output clocks CK1 and CK2 in accordance with the CAS latency and the mode register settings. It includes a switch 166 that transmits to the inside of the output circuit, a shift register 164 that shifts data according to the output clock CK2, and a shift register 172 that shifts data according to the output clock CK1. The latches 146 and 148 select and output the latched data according to the outputs of the shift registers 172 and 164, respectively.

  The input / output circuit 64 further includes an output buffer 150 that is activated by the enable signal OE and outputs data to the terminal DQ0, and a switch 168 that provides the output of the latch 148 to the output buffer 150 in response to the activation of the output clock CK1. And a switch 170 for supplying the output of the latch 146 to the output buffer 150 in response to the activation of the output clock CK2.

  The input / output circuit 64 further receives the data input from the outside to the terminal DQ0 as an input and amplifies it according to the enable signal WE, and is internally generated according to the strobe signal input from the outside. Switches 176 and 178 that transmit the output of the input buffer 152 in response to the signals FETCHe and FETCHo, a shift register 174 that receives the signal FETCHo as a shift clock and outputs a select signal, and a select signal that receives the signal FETCHe as a shift clock. , A latch 156 that captures a signal transmitted through the switch 176 in response to a select signal output from the shift register 174, and a switch 178 in response to a select signal output from the shift register 180. introduce And a latch 154 for taking the issue.

  The input / output circuit 64 further receives a write clock WCLK (loc) as a shift clock and outputs a select signal, and receives data output from the latches 154 and 156 according to the select signal output from the shift register 182. And a bus driver 158. The bus driver 158 sends data to the data buses EVEN0, ODD0, EVEN1, and ODD1 depending on whether the bank to which the received data is written and the address (first address) to which the first received data is written is an even number or an odd number. Are distributed and output.

  The operation will be briefly described. Data from the even address area and the odd address area of the bank 0 to the bank 3 or data from the even address area and the odd address area of the bank 4 to the bank 7 are input to the receivers 142 and 143. It is distinguished and captured by a 4-point switch portion provided in the section.

  Here, a signal for discriminating between upper (4-7) / lower (0-3) of the bank and a signal indicating whether the first address at the time of burst reading is an even address or an odd address are input. The path provided with the receiver 143, the latch 148, and the switch 168 is a path for data to be output first, and the path provided with the receiver 142, the latch 146, and the switch 170 is a path for output of the second data. is there. Data that has passed through the switches of the input parts of the receivers 143 and 142 is amplified by an amplifier and transferred to the selector part of the input parts of the latches 148 and 146. Here, the selector selects one of the four paths included in the latch. The selection of this path is sequentially shifted in accordance with a read internal clock RCLK (ctr) applied to a shift register 162 that inputs a select signal to the latch, and the input data is sequentially latched.

  The data stored in the latch is output on the basis of a clock different from the clock when it is input to the latch. The selection path on the output side of the latch is sequentially shifted by the select signal output from the shift registers 164 and 172 that perform the shift operation in accordance with the clocks DLLe and DLLo on the output side. Of the output data, odd-numbered data is stored in the latch 148, and even-numbered data is stored in the latch 146. Therefore, the latency from the read clock RCLK (ctr) that recognized the read command to the output of data to the outside determines which of the clock DLLe and the clock DLLo is input to the switch 168 as a control signal. The other clock is input as a control signal. For example, if the latency is 1.5, the clock DLLo is input as a control signal to the switch 168, and the clock DLLe is input as a control signal of the switch 170.

  At the time of writing, the first input data from the outside is unconditionally transferred to the latch 156, the next input data is unconditionally transferred to the latch 154, and thereafter the data is alternately transferred to the latches 156 and 154. .

  The latched data is transmitted to the bus driver 158 in accordance with the write internal clock WCLK (loc). The bus driver 158 outputs data to the corresponding data bus according to the bank address and the first address of the burst data.

  Although the circuit configuration of the input / output circuit is shown in FIG. 10, it is also conceivable that the data input portion used as a data mask at the time of writing is operated with the same margin using the same type circuit. In this case, only the circuit on the data input side may be used. However, in order to balance the capacitance, the output system circuit is not operated, but may be arranged in a dummy manner.

  The same applies to the strobe terminals related to data output. In this case, only the circuit on the data output side may be used. However, in order to balance the capacitance, the input system circuit is not operated, but may be arranged in a dummy manner.

  In some cases, both may be combined. When the output data strobe and the write mask data input do not collide, the same bus can be used. In this case, with the same circuit configuration as the input / output circuit used for the data input / output terminal DQ, an output data strobe circuit can be assigned to the output side, and a write mask data circuit can be assigned to the input side.

  FIG. 11 is a circuit diagram showing a configuration of latch 148 that holds data at the time of reading shown in FIG.

  Referring to FIG. 11, latch 148 includes four latches 148a to 148d that receive and hold data RIN read from the memory array and output it as output signal ROUT. Latch 148a has a P-channel MOS transistor 192 for applying input signal RIN to internal node N1 in response to activation of select signal SELA, a source coupled to a power supply potential, a gate connected to node N1, and a drain connected to node N2. P-channel MOS transistor 194, N-channel MOS transistor 196 having a gate connected to node N1, a source connected to node N3, and a drain connected to node N2, and the potential of node N2 in response to activation of select signal SELB Is output to the outside of the latch as an output signal ROUT, and a NOR circuit 200 having nodes N2 and N4 connected to inputs and an output connected to node N1.

  Since latches 148b, 148c and 148d have the same configuration as 148a, description thereof will not be repeated.

  Latch 148 further includes an N-channel MOS transistor 202 provided in common with latches 148a to 148d for coupling node N3 to the ground potential in response to activation of read flag READ (FLAG), and read flag READ (FLAG). Further included is an inverter 204 which outputs a reset signal and applies it to node N4 when inverted.

  Transistors 194 and 196 used in the latch have a low threshold voltage to operate at a high speed with a low voltage. In order to suppress a subthreshold current flowing through the transistors 194 and 196 when a read operation is not performed. The N channel MOS transistor 202 is a transistor having a high threshold voltage.

  Since latch 146 in FIG. 10 has the same configuration as latch 148, description thereof will not be repeated.

  FIG. 12 is a circuit diagram showing a configuration of latch circuit 156 that holds data at the time of data writing shown in FIG.

  Referring to FIG. 12, latch circuit 156 includes four latches 156a to 156d that receive and hold data signal WIN input to the data input / output terminal and further output as an output signal WOUT toward the memory array.

  Latch 156a has a P-channel MOS transistor 212 for applying input signal WIN to node N5 in response to activation of select signal SELC, node N5 connected to the gate, source coupled to the power supply potential, and drain connected to node N6. P channel MOS transistor 214, N channel MOS transistor 216 having a gate connected to node N5 and a drain and source connected to nodes N6 and N7, respectively, and the potential of node N6 in response to activation of select signal SELD are output signals. N channel MOS transistor 218 provided as WOUT. Latch 156a further includes a NOR circuit 220 having nodes N6 and N8 connected to the inputs and an output connected to node N5.

  Since latches 156b, 156c, and 156d have the same configuration as latch 156a, description thereof will not be repeated.

  Latch 156 is further provided in common with latches 156a to 156d, and includes N channel MOS transistor 222 that couples node N7 to the ground potential in response to activation of write flag WRITE (FLAG), and write flag WRITE (FLAG). Inverter 224 is provided which is inverted when deactivated and applied to node N8 as a reset signal.

  Transistors 214 and 216 used in the latch have a low threshold voltage for high-speed operation at a low voltage, and suppress a subthreshold current flowing in the transistors 214 and 216 when a write operation is not performed. The N channel MOS transistor 222 is a transistor having a high threshold voltage.

  Since latch 154 in FIG. 10 has the same configuration as latch 156, description thereof will not be repeated.

  Referring to FIGS. 11 and 12, when latches 148 and 156 are not operated by a reset signal, the input side of the latch is reset to L level and the output side is reset to H level. For this reason, the conductivity type of the MOS transistor used as the transfer gate is changed.

  A transfer gate MOS transistor having a low threshold voltage is used to increase the operation speed. Since the input node is at the L level, a P-channel type transistor is used on the input side of the latch, and since the output node is at the H level, an N-channel type transistor is used on the output side. At this time, since the gate potential with respect to the node potential of the latch at the time of standby, that is, the gate-source voltage becomes negative, each transistor hardly generates a leak current even though the threshold voltage is low (not shown) The output node and the input node at the time of resetting are controlled by the circuit unit.)

  As described above, the latch is reset at the end of the burst operation at the time of reading and writing data, and the ground potential and the inverter are set by the N-channel MOS transistor having a high threshold voltage provided in common on the ground side of the inverter section. By separating these, the subthreshold current during standby can be kept small.

  11 and 12 show an example in which the input node of the inverter is reset to L (low) level by the NOR circuit, but may be reset to H (high) level. In that case, a P channel MOS transistor having a large absolute value of the threshold voltage is provided on the power supply node side of the inverter, and the conductivity type of the MOS transistor of the transfer gate for inputting / outputting data to / from the latch is selected according to the reset logic.

FIG. 13 is a circuit diagram showing a configuration of shift register 162 shown in FIG.
Referring to FIG. 13, shift register 162 receives a read flag READ (FLAG), a reset signal RESET, an internal signal CO2, and an internal signal CO11, and receives pulse signal generation circuit 501 for generating internal signal CO1 and internal signal CO1. A flip-flop 514 that receives the internal signal CO2 from the output node Q received at the node D, a flip-flop 516 that receives the internal signal CO2 from the output node Q and outputs the internal signal CO3 from the output node Q, and an internal signal CO3 as the input node D Flip-flop 518 that outputs internal signal CO4 from receiving output node Q, flip-flop 512 that receives internal signal CO4 at input node D and outputs internal signal CO11 from output node Q, and internal signals CO1, CO2, CO3, CO4 And select clock signal SCLK And an output circuit 519 for outputting a signal C1, C2, C3, C4.

  A clock signal SCLK is input to the clock node CK of the flip-flops 512, 514, 516, and 518 as a shift clock, and a reset signal RESET is input to the reset input node R.

  A pulse generation circuit 501 receives a read flag READ (FLAG) at one input, a NOR circuit 502, an output from the NOR circuit 502, a reset signal RESET, and an internal signal CO2 as inputs, and inputs to the other input node of the NOR circuit 502. A three-input NOR circuit 504 that outputs a negative sum, an inverter 506 that receives and inverts the output of the NOR circuit 502, a NOR circuit 508 that receives the output of the inverter 506 and the internal signal CO11, and an output of the NOR circuit 508 And an inverter 510 that inverts and outputs an internal signal CO1.

  Output circuit 519 includes an NAND circuit 520 that receives internal signal CO1 and clock signal SCLK, an inverter 522 that receives and inverts the output of NAND circuit 520 and outputs select signal C1, and a NAND that receives internal signal CO2 and clock signal SCLK. Circuit 524, inverter 526 which receives and inverts the output of NAND circuit 524 and outputs select signal C2, NAND circuit 528 which receives internal signal CO3 and clock signal SCLK, and receives and inverts and selects the output of NAND circuit 528 An inverter 530 that outputs signal C3, a NAND circuit 532 that receives internal signal CO4 and clock signal SCLK, and an inverter 534 that receives and inverts the output of NAND circuit 532 and outputs select signal C4.

FIG. 14 is a circuit diagram showing a configuration of flip-flop 512 shown in FIG.
Referring to FIG. 14, flip-flop 512 includes an inverter 570 having clock node CK connected to the input, an inverter 572 that receives and inverts the output of inverter 570, and an inverter 542 that has input node D connected to the input. P-channel MOS transistor 544 and N-channel MOS transistor 546 connected in parallel between the output node of inverter 542 and node NF1, NOR circuit 548 where node NF1 and reset input node R are connected to the input, Inverter 550 receives and inverts the output of NOR circuit 548, and includes a P-channel MOS transistor 554 and an N-channel MOS transistor 552 connected in parallel between the output node of inverter 550 and node NF1.

  The gate of P channel MOS transistor 544 and the gate of N channel MOS transistor 552 receive the output of inverter 570. The gate of N channel MOS transistor 546 and the gate of P channel MOS transistor 554 receive the output of inverter 572.

  Flip-flop 512 further includes a P-channel MOS transistor 556 and an N-channel MOS transistor 558 connected in parallel between the output node of NOR circuit 548 and node NF2, an inverter 560 having node NF2 connected to the input, NOR circuit 562 having the output node of inverter 560 and reset input node R connected to the input, P channel MOS transistor 564 and N channel MOS transistor connected in parallel between the output node of NOR circuit 562 and node NF2 566 and an inverter 568 that receives and inverts the output of inverter 560 and outputs the inversion result to output node Q.

  The gate of P channel MOS transistor 556 and the gate of N channel MOS transistor 566 receive the output of inverter 572. N channel MOS transistor 558 and P channel MOS transistor 564 both receive the output of inverter 570.

  Since flip-flops 514, 516, and 518 shown in FIG. 13 have the same configuration as flip-flop 512, description thereof will not be repeated.

Next, the operation of the shift register 162 will be briefly described.
First, in the initial state, the data held in the flip-flops 512 to 518 is cleared by the reset signal RESET. Next, when read flag READ (FLAG) is input, internal signal CO1 rises to H level.

  When clock signal SCLK is input, internal signal CO1 is taken into flip-flop 514 and internal signal CO2 rises to the H level. At the same time, the pulse generation circuit 501 is reset by the internal signal CO2, and the internal signal CO1 falls to the L level. Thereafter, the H level of the internal signal CO2 is sequentially transmitted by the flip-flops 516, 518, 512, and 514. That is, any one of the internal signals CO1, CO2, CO3, and CO4 is at the H level, and the signal that has become the H level is sequentially shifted in synchronization with the edge of the clock signal SCLK.

  Since the internal signals CO1, CO2, CO3, and CO4 are pulses having a width of one clock cycle, the select signals C1, C2, C3, and C4 receive the clock signal SCLK by performing an AND operation with the clock signal by the output circuit 519. A signal having a pulse width is output, and this signal is sequentially shifted.

  Since shift registers 164, 172, 174, 182, and 180 shown in FIG. 10 have the same configuration as shift register 162, description thereof will not be repeated.

[Read Test in Embodiment 1]
Data reading at the time of the operation test in the case where the input / output circuit described in Embodiment 1 is provided will be described.

  If the number of observation terminals connected to the tester device during the operation test can be reduced and the observation data rate can be reduced, it is possible to perform measurement even with a low-performance tester device, thereby reducing the inspection cost.

  FIG. 15 is a conceptual diagram for explaining the concept of the data read test in the first embodiment.

  Referring to FIG. 15, the input / output circuit portion includes a coincidence detection circuit MAT1 that receives data from the odd address area of the memory array, a latch L1 that receives the output of coincidence detection circuit MAT1, and an even address area of the memory array. A coincidence detection circuit MAT2 that receives the data of the data, a latch L2 that receives the output of the coincidence detection circuit MAT2, and a multiplexer MPX that receives the outputs of the latches L1 and L2 and alternately outputs the data from the latches L1 and L2 according to the clock signal; A buffer circuit OBUF that receives and amplifies the output of the multiplexer MPX and outputs the amplified signal to the terminal DQi.

FIG. 16 is a circuit diagram showing a more detailed configuration of input / output circuit 641 corresponding to FIG.
Referring to FIG. 16, input / output circuit 641 further includes a coincidence detection circuit 230 that receives the outputs of receivers 143 and 142 and outputs the results to latches 148 and 146, respectively, and tests the outputs of latches 156 and 154, respectively. It differs from the input / output circuit 64 shown in FIG. 10 in that it further includes an output circuit 232 that is sometimes provided to an input / output circuit provided corresponding to another terminal. Since other configurations are similar to those of input / output circuit 64, description thereof will not be repeated.

  The coincidence detection circuit 230 includes an EXOR circuit 234 that receives the signals ODQ0a to ODQ3a, a switching circuit 236 that provides the signal ODQ0a to the latch 148 during normal operation, and an output of the EXOR circuit 234 to the latch 148 during test operation, and signals ODQ0b to ODQ3b. The EXOR circuit 238 receives the signal ODQ0b in the normal operation and the switching circuit 240 supplies the latch 146 with the output of the EXOR 238 during the test. Here, the signals ODQ0a to ODQ3a are output signals of the receiver 143 of the input / output circuit 64 provided corresponding to the data terminals DQ0 to DQ3, respectively. The signals ODQ0b to ODQ3b are output signals of the receiver 142 included in the input / output circuit 64 provided corresponding to the data terminals DQ0 to DQ3, respectively.

  Output circuit 232 includes switch circuits 242 to 244 that provide signal IDQ0a as signals IDQ1a to IDQ3a during testing, and switch circuits 246 to 248 that provide signal IDQ0b as signals IDQ1b to IDQ3b.

  Here, the signal IDQ0a is an output signal of the latch 156 of the input / output circuit 641 provided corresponding to the data terminal DQ0, and the signals IDQ1a to IDQ3a are input / output circuits provided corresponding to the data terminals DQ1 to DQ3, respectively. 64 is an input signal of the bus driver 158. The signal IDQ0b is an output signal of the latch 154 included in the input / output circuit 641 provided corresponding to the data terminal DQ0, and the signals IDQ1b to IDQ3b are input / output circuits provided corresponding to the data terminals DQ1 to DQ3, respectively. 64 is an input signal of the bus driver 158.

  FIG. 17 is an operation waveform diagram for illustrating the operation of the data read test of the first embodiment.

  Referring to FIG. 17, at time t1, a read command is input, and data read from data input / output terminals DQ0, DQ4, DQ8, DQ12, DQ16, DQ20, DQ24, and DQ28 are output.

  At time t3, data DLE0 in the even address area read to data input / output terminals DQ0 to DQ3 during normal operation is output from data input / output terminal DQ0 after being degenerated by the matching circuit.

  After 0.5 clocks, the data input / output terminal DQ0 similarly outputs the data DLO0 in the odd address area normally output to the data input / output terminals DQ0 to DQ3 by the match detection circuit. Similarly, data that is normally output to the data input / output terminals DQ (4i + 1), DQ (4i + 2), and DQ (4i + 3) is degenerated and output from the other data input / output terminals DQ (4i) (i Is a natural number of 1-7. Thereafter, the data in the odd address area and the even address area are read alternately.

  With such a configuration, the number of data input / output terminals necessary for monitoring data output can be reduced, and the number of channels used by the tester in the inspection of the semiconductor memory device can be reduced. Therefore, the inspection cost of the semiconductor memory device can be reduced.

  FIG. 18 is a conceptual diagram showing a configuration in which the defect detection rate is further improved in the read test in the first embodiment.

  Referring to FIG. 18, the first embodiment is different from the configuration shown in FIG. 15 in that match detection circuits MAT11 and MAT12 are included instead of match detection circuits MAT1 and MAT2. Other configurations are similar to those shown in FIG. 15, and description thereof will not be repeated.

  FIG. 19 is a circuit diagram showing a configuration of coincidence detection circuits MAT11 and MAT12 shown in FIG.

  Referring to FIG. 19, coincidence detection circuit MAT11 includes an EXOR circuit E111 that receives signals ODQ0a to ODQ3a, an EXOR circuit E112 that receives signals ODQ0a, ODQ4a, ODQ8a, and ODQ12a, and an OR circuit that receives the outputs of EXOR circuits E111 and E112. E113. The output of the OR circuit E113 is output to the latch L1 shown in FIG.

  Match detection circuit MAT12 includes an EXOR circuit E121 that receives signals ODQ0b to ODQ3b, an EXOR circuit E122 that receives signals ODQ0b, ODQ4b, ODQ8b, and ODQ12b, and an OR circuit E123 that receives the outputs of EXOR circuits E121 and E122. The output of the OR circuit E123 is output to the latch L2 shown in FIG.

  Here, the signal ODQia is an output signal of the receiver 143 included in the input / output circuit 64 provided corresponding to the data input / output terminal DQi, and the signal ODQib is an output signal of the receiver 142 (i = 0-12). ).

  In the coincidence detection circuit of the first embodiment, for example, when all of the data read from data input / output terminals DQ0 to DQ3 output an incorrect value, a coincidence is detected and normal reading is executed. Judgment is made as if

  In the circuit as shown in FIG. 19, the coincidence result of the data output to the adjacent data input / output terminals (DQ0 to DQ3) is confirmed, and further, the non-adjacent data terminals (DQ0, DQ4, DQ8, DQ12). A match of the data output to is also checked, and if both match, the L level is output. Therefore, the probability of erroneous determination is greatly reduced as compared with the coincidence detection circuit in the first embodiment.

[Variation 1 of Embodiment 1]
FIG. 20 is a conceptual diagram showing a concept of a read test in the first modification of the first embodiment.

  Referring to FIG. 20, in the first modification of the first embodiment, there is provided a coincidence detection circuit MAT3 that receives a plurality of read data from the memory array and detects a coincidence, and the output of the coincidence detection circuit MAT3 is Both are different from the configuration shown in FIG. 15 in that they are input to the latches L1 and L2. Other configurations are the same as those shown in FIG. 15, and description thereof will not be repeated.

  FIG. 21 is a circuit diagram showing a configuration of input / output circuit 642 in the first modification of the first embodiment.

  Referring to FIG. 21, input / output circuit 642 differs from input / output circuit 641 shown in FIG. 16 in that it includes a match detection circuit 250 instead of match detection circuit 230. Other points are similar to those of input / output circuit 641, and description thereof will not be repeated.

  The coincidence detection circuit 250 receives an EXOR circuit 251 that receives the signals ODQ0a to ODQ3a and ODQ0b to ODQ3b, a switching circuit 252 that supplies the signal ODQ0a to the latch 148 during normal operation, and provides the output of the EXOR circuit 251 to the latch 148 during a test. A switching circuit 254 is provided which provides the signal ODQ0b to the latch 146 during the operation and provides the output of the EXOR circuit 251 to the latch 146 during the test operation.

  FIG. 22 is an operation waveform diagram for describing the operation of the read test in the first modification of the first embodiment.

  Referring to FIGS. 21 and 22, data is read from data input / output terminals DQ0, DQ4, DQ8, DQ12, DQ16, DQ20, DQ24, and DQ28 after time t3 after a read command is input at time t11. Is output. This data is output by the EXOR circuit 251 in which all of the even address area data and odd address area data output corresponding to the data input / output terminals DQ0 to DQ3 are matched. Therefore, the data output rate is halved compared to the case described with reference to FIG.

  With the above configuration, the number of observation terminals connected to the tester device can be reduced. Therefore, the number of chips that can be measured by one tester device can be increased, and the inspection cost can be reduced. In addition, the data rate of the data to be observed can be reduced, and it is possible to perform inspection even with a tester device that is not so high in performance.

[Modification 2 of Embodiment 1]
In the configuration of the input / output circuit 641 of the first embodiment shown in FIG. 16, the data output to the data input / output terminals DQ0 to DQ3 during normal operation is determined by EXOR during a test and output. However, since the comparison is not made with the expected value, but only with the mutual comparison of the read data, if all the read data is in error, the output of the EXOR circuit is the same value as in the normal state. Will be output.

  FIG. 23 is a conceptual diagram showing a concept of a data read test in the second modification of the first embodiment.

  A coincidence detection circuit MAT4 that receives a plurality of data from the memory array, latches L1 and L2 that receive both DOUT as an output signal of the coincidence detection circuit, a multiplexer MPX that alternately outputs the outputs of the latches L1 and L2, and a coincidence detection circuit An output buffer OBUF is provided that is inactivated when the output signal BEN of the MAT4 is at H level and amplifies the output of the multiplexer MPX and outputs it to the data input / output terminal DQi when it is at the L level. When executing the data read test, the data input / output terminal DQi is coupled to the power supply potential via the resistor R11 and the data input / output terminal DQi is grounded via the resistor R12 outside the semiconductor memory device. Combined with potential.

  Therefore, when the output of the output buffer OBUF is in a high impedance state, the potential level of the input / output terminal DQi is an intermediate potential level.

FIG. 24 is a circuit diagram showing a configuration of coincidence detection circuit MAT4 in FIG.
Referring to FIG. 24, coincidence detection circuit MAT4 receives signals ODQ0a to ODQ3a and ODQ0b to ODQ3b, and outputs an H level when they are all coincident, and outputs an L level otherwise. E41 and AND circuit E42 receiving signal ODQ0a and the output of gate circuit E41.

  The output signal of the AND circuit E42 is a signal DOUT. The output signal of the gate circuit E41 is the signal BEN.

  FIG. 25 is an operation waveform diagram for describing a read test in the second modification of the first embodiment.

  23 and 25, when a read command is input at time t1, a read result is output from data input / output terminal DQi after time t2. As a result of reading, when all the data from the memory array match, the data from the memory array is output by the match detection circuit MAT4, and the match detection circuit MAT4 does not detect the match of the data from the memory array. In this case, since the output buffer OBUF is in a high impedance state, the potential level of the data input / output terminal DQi becomes an intermediate level.

  Consider a case where the expected output values at times t2, t3, t4, t5, t6, and t7 are H, L, H, L, H, and L, respectively.

  At times t2, t3, t5, and t7, the output result matches the expected value, and it can be seen that the corresponding memory cell has read normally.

  At time t4, since the potential level of data input / output terminal DQi is an intermediate level, one of data signals ODQ0a to ODQ3a and ODQ0b to ODQ3b read from the array shown in FIG. 24 reads incorrect data. Can be observed.

  At time t6, although the expected value is H, the output result is L, and all of the signals ODQ0a to ODQ3a and ODQ0b to ODQ3b shown in FIG. 24 read the wrong data value (L level). Can be observed.

  By adopting such a configuration, the defect detection rate is further increased by performing the determination by the coincidence detection circuit between the read data and the determination of the comparison between the read data by the tester device and the expected value outside. be able to.

[Modification 3 of Embodiment 1]
In the third modification of the first embodiment, as in the second modification of the first embodiment, a configuration will be described in which the probability of erroneous determination is lowered and the defect detection rate is further increased.

  FIG. 26 is a conceptual diagram showing the concept of the data read test in the third modification of the first embodiment.

  Referring to FIG. 26, in modification 3 of the first embodiment, coincidence detection circuit MAT5 that receives a plurality of data from the memory array is provided, and coincides with latch L1 that receives output signal DOUT of coincidence detection circuit MAT5. An inverting switch circuit IVSW that receives the output signals DOUT and SINV of the detection circuit MAT5 and outputs corresponding values, a latch L2 that receives the output of IVSW, a multiplexer MPX that alternately outputs the outputs of the latches L1 and L2, and a multiplexer MPX An output buffer OBUF is provided for amplifying the output and outputting it to the data input / output terminal DQi.

  FIG. 27 is a circuit diagram showing the configuration of the coincidence detection circuit MAT5 and the inverting switch circuit IVSW.

  Referring to FIG. 27, match detection circuit MAT5 receives signals ODQ0a to ODQ3a, ODQ0b to ODQ3b, outputs an H level when all match, and outputs a L level when they do not match, AND circuit E52 which receives signal ODQ0a and output signal SINV of gate circuit E51 and outputs output signal DOUT.

  The inverting switch IVSW includes an inverter E53 that receives and inverts the output signal DOUT, an inverter E55 that receives and inverts the output signal SINV, and an N-channel MOS that provides the output of the inverter E53 to the latch L2 when the output signal SINV is at the H level. Transistor E54 and an N channel MOS transistor E56 that provides output signal DOUT to latch L2 when the output of inverter E55 is at the H level are included.

  FIG. 28 is an operation waveform diagram for illustrating a read test in the third modification of the first embodiment.

  Referring to FIGS. 26 and 28, a read command is given at time t0. Accordingly, a data read result is output from data input / output terminal DQi after time t1. Assume that the expected values of output data from the memory array corresponding to times t1a, t2a, t3a, t4a, t5a, and t6a are H, H, L, L, H, and H, respectively.

  When the data read value from the memory array is H level and the coincidence detection circuit MAT5 detects coincidence, H is read as data into the latch L1, and the data is inverted into the latch L2 by the inversion switch IVSW. Read as data. Accordingly, when observed externally, data is output to the data output terminal DQi in the order of the data of the latch L1 and the data of the latch L2, and therefore a falling edge falling from the H level to the L level is observed.

  If the coincidence detection circuit MAT5 detects a coincidence when the data from the memory array is at the L level, a rising edge rising from the L level to the H level is observed. Therefore, a falling edge is observed at times t1a and t2a, and a rising edge is observed at times t3a and t4a. By comparing this waveform with the output expected value, all results are paths.

  When the coincidence detection circuit MAT5 does not detect coincidence, the same data is written in the latches L1 and L2, so that the rising edge and the falling edge are not detected, and the determination is failed at time t5a.

  Further, when all the erroneous data is read as signals ODQ0a to ODQ3a and ODQ0b to ODQ3b, even when the coincidence detection circuit MAT5 detects a coincidence, for example, the rise of the comparison value and the edge as at time t6a It can be determined that the result is a failure.

  Therefore, in the third modification of the first embodiment, the defect detection rate can be further improved.

[Embodiment 2]
FIG. 29 is a circuit diagram showing a configuration of a test result output circuit TOC used in the synchronous semiconductor memory device of the second embodiment.

  Referring to FIG. 29, test result output circuit TOC is reset by EXOR circuit G1 receiving read result signals R0 to Rn read from the memory array and reset signal RESET, and synchronized with shift clock SCLK. In addition, flip-flops DF1 to DF9 connected in series for taking in data and outputting retained data, and an EXOR circuit G2 for receiving the outputs of flip-flops DF1 to DF9 and outputting test result output signal ROUT are included.

  The flip-flops DF1 to DF9 receive the output signal RR from the EXOR circuit G1, and constitute a shift register that shifts in synchronization with the shift clock SCLK. This shift register is composed of a number of flip-flops obtained by adding 1 to the burst length when the synchronous semiconductor memory device outputs data.

FIG. 30 is an operation waveform diagram for explaining the operation of the test result output circuit TOC.
Referring to FIGS. 29 and 30, clock signal CLK is a clock signal input from an externally connected test device to the synchronous semiconductor memory device, and shift clock SCLK is synchronous based on clock signal CLK. A clock signal generated by, for example, a phase-locked loop (PLL) circuit in the semiconductor memory device.

  Data output from the synchronous semiconductor memory device is normally performed in the cycle of the shift clock SCLK.

  At time t1, the reset signal RESET falls from the H level to the L level. Responsively, flip-flops DF1 to DF9 are released from reset and start taking in signal RR indicating the degenerated test result.

  Read result signals R0 to Rn are data read results respectively output to a plurality of data input / output terminals. However, for example, when a test mode is provided in which data is simultaneously written to a plurality of banks and data is read from the plurality of banks at the same time, the read results from the plurality of banks may be used.

  From time t1 to t5, the reading result (8 data in this case) corresponding to the burst length is continuously read.

  At this time, when a part of the memory cell is defective at time t2 to t3 and the read result signal R1 becomes an output different from the other read result signals, the degenerated signal RR becomes H level. However, in order to detect the change in the signal RR, a test apparatus (tester) that can cope with the frequency of SCLK that is an internal operation clock is required. In the case of a tester device with low performance, the output signal can be observed only at one point within one cycle of the clock signal CLK which is a basic clock given to the device by the tester device. For example, as indicated by arrows at times t1, t4, t5, and t6, the data signal can be observed only at the rising edge of the clock signal CLK.

  At time t3, the signal RR is taken into a shift register composed of flip-flops DF1 to DF9. Accordingly, the test result output signal ROUT observed externally becomes H level for a certain period. In the case of the circuit shown in FIG. 29, this fixed period is nine clocks of the shift clock SCLK. In this case, since the H level of the test result output signal ROUT can be observed at times t4 and t5, it is possible to detect that an abnormality has occurred in the read result even with a low-performance tester.

  If it is only necessary to determine whether the product is non-defective or defective, it is only necessary to observe that the test result output signal ROUT is at L level. Even in a low-performance tester, the synchronous semiconductor memory device is non-defective / non-defective. Good products can be identified.

  Further, when analysis is necessary for specifying a defective part of a defective product, the output signal RMON of the shift register is output to an external terminal in the test mode. By observing RMON, it is possible to analyze at which timing a read error has occurred in the read result signals R0 to Rn, and a clue to know the corresponding address can be obtained.

  In other words, in the synchronous semiconductor memory device of the second embodiment, when the result of reading from the memory array is continuously output in the operation check test, it is detected whether there is an error in reading halfway and the pulse width is widened. Output to the outside. The shift register is initially reset and stores data corresponding to the normal case, and read data from the memory array is degenerated and input to the shift register for each read cycle. As long as a normal value is input, the test result output signal ROUT is maintained at the L level. However, if a read error occurs, the test result output signal ROUT is at the H level.

  The observation of the test result output signal ROUT may be performed at least once with respect to the number of shift clock inputs corresponding to the burst length. Even with this small number of observations, it is possible to determine whether the synchronous semiconductor memory device is good or defective. Is possible. When a failure is determined, it is possible to obtain a clue to know the address where the failure has occurred by observing the output signal of the shift register.

[Embodiment 3]
In the third embodiment, an example of a synchronous semiconductor device incorporating a BIST (Built In Self Test) circuit will be described.

  FIG. 31 is a schematic block diagram showing the overall configuration of the synchronous semiconductor memory device 2100 of the third embodiment.

  Referring to FIG. 31, synchronous semiconductor memory device 2100 has the same structure as that of synchronous semiconductor memory device 1000 described in the first embodiment, from data conversion unit 303 in which data from data input / output terminal P13 is latched. Multiplexer 302 that multiplexes data input and data inputted from control-related terminals P4 to P7 and address terminal groups P11 and P12 and transmits them to the internal block, and a test having a shorter cycle than the external clock by receiving an external clock during the test 1 is different from the synchronous semiconductor memory device 1000 shown in FIG. 1 in that it further includes a PLL circuit 650 that generates a clock TCLK for use and a BIST circuit 649. Since other structures are similar to those of synchronous semiconductor memory device 1000, description thereof will not be repeated.

  When a test start command is input from the outside, the BIST circuit 649 automatically generates a command, address, data, and other signals necessary for the test, executes an operation test of the synchronous semiconductor memory device, and reads data, etc. Whether the test result is acceptable or not is determined from the output result and the determination is output to a predetermined output terminal.

  Therefore, the only pins necessary for the operation test of the synchronous semiconductor memory device incorporating the BIST circuit are the clock terminal for ensuring synchronization with the test device and the data terminal used for outputting the determination result. That is, in the case where the number is the smallest, the terminals used at the time of the test are a total of 2 pins including a clock terminal 1 pin and a data terminal 1 pin.

  FIG. 32 is a diagram for explaining data input through the input / output buffer when BIST of the synchronous semiconductor memory device 2100 is performed.

  Referring to FIG. 32, a pattern generation unit PG that executes BIST, a RAM unit BRAM that holds a test procedure for BIST, a clock gate circuit CKG that supplies a clock to the RAM unit BRAM, and a data bus to a RAM unit An input gate DIG for taking data into the BRAM, a detection circuit SVIHDEC for detecting an instruction to shift to the BIST mode, and an input / output circuit 64 for inputting data to be transferred to the RAM BRAM are provided. A circuit block for executing BIST is divided into a pattern generation unit PG and a RAM unit BRAM. The BIST is executed by reading and decoding data stored in advance in the RAM unit and generating a pattern according to the decoding result.

  Therefore, first, it is necessary to write data to the RAM BRAM before executing the BIST. This data is obtained by coding the content of the test sequence into a predetermined numerical value, and is expressed in a format called a vector format.

  When any input pins (DQj, DQk here) of the chip are in a predetermined combination, it is detected that a predetermined potential exceeding the power supply potential is applied to the specific pin (DQ0 here), and the pattern generation unit A detection circuit SVIHDEC is provided for outputting a BIST execution flag to the PG. Along with the setting of this flag, the operation of generating the test clock TCLK (synchronous clock generation) by the internal test clock generator is started (not shown). In accordance with this test clock, data serving as a BIST test vector is written into the RAM BRAM.

  The RAM unit BRAM constitutes a shift register as will be described later, and data inputted from the data input gate DIG is sequentially shifted internally. Therefore, when the period of the number of cycles of the shift clock SCK corresponding to the number of shift registers included in the RAM unit BRAM elapses, the input of data to the RAM unit is completed.

  This data writing is performed from a predetermined data input / output terminal DQi through the input / output circuit 64 through the data line DBLi included in the data bus DB. Since the configuration of input / output circuit 64 is similar to the configuration shown in FIG. 10, description thereof will not be repeated.

  During normal operation, data input from the data input / output terminal DQi is taken into the latches 156 and 154 in synchronization with the external clock, and the data is sent to the data bus DB in synchronization with the internal clock.

  However, when data is input to the initial RAM BRAM when executing BIST, the clock generation circuit that generates the internal clock is not sufficiently stable. This is because the external clock needs to be input to the clock generation circuit for a certain period in order to stabilize the internal clock.

  Therefore, when data is input to the RAM BRAM at the initial stage of BIST, data is sent from the latch circuits 156 and 154 of the input / output circuit 64 to the data path based on the external clock. The data output to the data bus is sequentially taken into a shift register in the RAM unit BRAM via the data input gate DIG in accordance with a shift clock generated based on the external clock.

  When the input of a series of data to the shift register in the RAM unit BRAM is completed, the data is read from the RAM unit BRAM according to the order of the program counter, decoded, and BIST is executed.

FIG. 33 is a circuit diagram showing a configuration related to the detection circuit SVIHDEC in FIG.
Referring to FIG. 33, a high voltage detection circuit 650 for detecting that the level of data input / output terminal DQ0 is equal to or higher than a predetermined voltage value and a signal input to data input / output terminals DQj to DQk are in a predetermined combination. Is received by the decode circuit 667 for decoding whether the signal is high, the output signal / SVCC0 of the high voltage detection circuit 650 and the output of the decode circuit 667, and receives and inverts the OR circuit 665 for outputting the signal / SVCC and the signal / SVCC0. The inverter 669 that outputs the signal SVCC0, the latch circuit 666 that is set by the signal / SVCC and reset by the signal TESTEND indicating that the test is completed, and starts counting according to the output of the latch circuit 666, and the signals QS1 and QS2 In addition to outputting, an enable signal STEN is output for a certain period after a predetermined time. Printer 682 is provided.

  High voltage detection circuit 650 includes N-channel MOS transistors 652 and 654 that are diode-connected in series between data input / output terminal DQ0 and node NVC, and an N-channel in which a source is connected to a ground node and a gate and a drain are connected. Constant current connected between MOS transistor 658, P channel MOS transistor 656 connected between the drain of N channel MOS transistor 658 and node NVC and having power supply potential Vcc applied to the gate, and between the power supply node and node NVD A source 662, an N-channel MOS transistor 660 connected between node NVD and the ground node and having a gate connected to the drain of N-channel MOS transistor 658, an inverter 663 having node NVD connected to the input, Receive output and invert And an inverter 664 which outputs a high voltage detection signal / SVCC0.

  Latch circuit 666 includes a NAND circuit 668 receiving signal / SVCC at one input node, and a NAND circuit 670 receiving the output of NAND circuit 668 and signal TESTEND. The output of NAND circuit 670 is connected to the other input of NAND circuit 668. The output of the NAND circuit 668 is a BIST flag BISTF.

FIG. 34 is a block diagram for explaining a configuration example of the RAM unit BRAM.
Referring to FIG. 34, RAM unit BRAM is connected to decoder IDEC included in pattern generation unit PG and read signal lines RL12 to RLn. Further, the program counter PC included in the pattern generation unit PG is connected to the selection signal lines PC0 to PCm.

  The input unit is provided with a clock gate circuit CKG that generates a clock when data is written to the RAM BRAM before the BIST starts. Clock gate circuit CKG receives external clock signal ext. An AND circuit CKG1 that receives the clock signal CLK and the enable signal STEN and outputs a clock signal GCK for taking in data, and an external clock signal ext. An AND circuit CKG3 that receives CLK and enable signal BRAMRE, and an OR circuit CKG2 that receives the output of AND circuit CKG3 and clock signal GCK are included. The output of the OR circuit CKG2 is a shift clock SCK for shifting a shift register included in the RAM unit BRAM.

  A data input gate DIG is provided between the data bus line DBLi and the RAM portion BRAM. Data input gate DIG takes in data in accordance with data take-in clock signal GCK.

  RAM unit BRAM includes n flip-flops R # 01 to R # 0n connected in series for receiving data input from data input gate DIG. Transfer gates TG # 01 to TG # 0n are provided corresponding to flip-flops R # 01 to R # 0n, respectively.

  Transfer gates TG # 01 to TG # 0n are activated by signal line PC0 to connect flip-flops R # 01 to R # 0n and read signal lines RL1 to RLn, respectively.

  The RAM portion BRAM is further activated by n flip-flops R # 11 to R # 1n connected in series for receiving the outputs of the flip-flops R # 0 to R # n and the signal line PC1, and the flip-flop R # 11. To R # 1n and read signal lines RL1 to RLn, respectively, transfer gates TG # 11 to TG # 1n.

  Similarly, in the RAM unit BRAM, n flip-flops connected in series for receiving the output of the flip-flop at the final stage in the i-1 row are provided corresponding to the i-th row.

  There are m rows. The output of the flip-flop R # mn, which is the final stage of the shift register, can be read externally as a signal RAMOUT.

With such a configuration, a RAM test can be executed with a small number of terminals.
FIG. 35 is a circuit diagram showing structures of flip-flop R # mn and transfer gate TG # mn in FIG.

  Flip-flop R # mn is connected between inverter IV1 that receives and inverts input signal IN, inverter IV2 that receives and inverts and outputs the output of inverter IV1, and is connected between the output of inverter IV1 and node ND0. P channel MOS transistor MP1 receiving shift clock / SCK at its gate, N channel MOS transistor MN1 receiving shift clock SCK at its gate connected between the output of inverter IV1 and node ND0, and its input connected to node ND0 Inverter IV3, inverter IV4 that inverts the output of inverter IV3 and outputs it to node ND0, P-channel MOS transistor MP connected between the output of inverter IV3 and output node Nout and receiving shift clock SCK at its gate When connected between the output of the inverter IV3 and the output node Nout, and an N-channel MOS transistor MN2 which receives the shift clock / SCK to the gate.

  Transfer gate TG # mn includes an N-channel MOS transistor MN3 connected between the output of inverter IV3 and read signal line RLn and supplied with signal PCm at its gate.

  Data set in the RAM BRAM is input from the data input terminal also serving as a data bus used for normal data input. The enable signal STEN is generated by the counter 682. This input enable signal gives clock pulses corresponding to the number of shift registers included in the RAM BRAM to the data input gate. The data is taken in by the number of times of the counter and sequentially shifted to complete the data storage in the RAM BRAM.

  Referring again to FIG. 34, shift clock SCK is input by OR circuit CKG2 also when a read test is performed because it is necessary to take out data when a test for confirming the operation of RAM unit BRAM is performed.

  Data in the RAM section is selected by signals PC0 to PCm output from the program counter PC and sent to the decoder IDEC via the read signal lines RL1 to RLn. The decoder IDEC decodes the sent data and executes a corresponding operation.

[Test of BIST execution circuit itself]
FIG. 36 is a diagram illustrating a sequence relating to a test of a circuit for executing BIST.

  Referring to FIG. 36, in step ST1, a check of a circuit that performs BIST starts. Next, in step ST2, an entry check for entering a mode for carrying out BIST is performed. Next, in step ST3, the BIST is terminated and a check for exiting the test mode is performed.

  Next, in step ST4, the RAM BRAM in which the BIST test contents are stored is checked. Next, in step ST5, the pattern generation unit PG of the circuit for performing BIST is checked.

  If all of the above steps are satisfactory, the test of the test circuit for performing BIST is completed in step ST6.

  After such a test is performed, the BIST is performed using a circuit for performing the BIST.

  First, a configuration for performing the entry check and the check for exiting from the mode executed in step ST2 and step ST3 will be described.

FIG. 37 is a block diagram for explaining a configuration for performing an entry test.
Referring to FIG. 37, in order to perform the entry test, an N channel MOS transistor MN4 is provided which receives detection signal SVCC0 output from SVIH detection circuit SVIHDEC and is connected between data input terminal DQi and the ground node. It is done. When a predetermined voltage value equal to or higher than the power supply potential is applied to data input / output terminal DQ0, detection signal SVCC0 is activated and N channel MOS transistor MN4 is rendered conductive. Since the data input / output terminal DQi is normally connected to the load resistor LR and pulled up during the test, it is normally at the H level, but the data input / output terminal DQ0 has a predetermined potential exceeding the power supply potential. While being applied, the level of data input / output terminal DQi is at L level.

  By observing this level externally, it is possible to determine whether or not the detection circuit SVIHDEC is operating normally.

  Further, the BIST flag is written to the output data latch unit in the input / output circuit 64 in order to check whether or not the BIST flag selected by the detection circuit SVIHDEC has been set normally by detecting the high voltage. It is. By reading the data written in the latch, it can be determined whether or not the BIST flag is set normally.

  FIG. 38 is an operation waveform diagram for explaining entry test and data writing to the RAM portion.

  Referring to FIGS. 37 and 38, at time t1, an arbitrary combination of terminals (here, data input / output terminals DQj to DQk are all at L level) is set, and the potential of data input / output terminal DQ0 is set to power supply potential Vcc. If the constant potential is set to exceed a certain level, the detection circuit SVIHDEC detects a high voltage. Accordingly, detection signal SVCC0 goes to L level, BIST flag BISTF is set, and N-channel MOS transistor MN4 connected to data input / output terminal DQi is turned on. Accordingly, the potential of data input / output terminal DQi becomes L level. If it is observed from the outside that the data input / output terminal DQi has become L level, it can be confirmed that the operation of the voltage detection unit of the detection circuit SVIHDEC is normal.

  At time t2, the counter included in the detection circuit SVIHDEC starts counting in response to the setting of the BIST flag BISTF, and the enable signal STEN becomes H level. In response to the enable signal STEN becoming H level, the external clock signal ext. Capture clock signal GCK and shift clock signal SCK are generated from CLK.

  Based on these clocks, test data written to the RAM BRAM is input from the data input / output terminal DQi.

  When the shift clock SCK having a predetermined number of clocks is input at time t3, the enable signal STEN becomes L level. Accordingly, the generation of the shift clock SCK is stopped and the data in the RAM BRAM is fixed. The clock input to the pattern generation unit PG is switched from an external clock to a high-speed clock generated internally by a PLL circuit or the like, and BIST is executed.

  When the self refresh mode or the mode register set cycle is set from the outside at time t4, the BIST flag BISTF is canceled and the BIST is terminated.

FIG. 39 is a block diagram for explaining a test of the RAM BRAM.
Referring to FIG. 39, after setting the test contents, switch SW01 is turned on, and a path for transmitting the data in RAM portion BRAM to the data output latch in input / output circuit 64 is formed. This path is formed after external data is input to the RAM unit BRAM.

  Even after the BIST flag is set and the predetermined combination of the data input / output terminals DQj to DQk is released, if the application of the high voltage to the data input / output terminal DQ0 is continued, the application of the high voltage is continued. During this period, the enable signal BRAME becomes H level, the switch SW01 is turned on, and a path is formed. During this period, the input / output circuit 64 performs an output buffer operation.

FIG. 40 is a flowchart for explaining a test of the RAM unit BRAM.
Referring to FIG. 40, first, in step SR1, a test of RAM unit BRAM is started, and in step SR2, data is written into RAM unit BRAM as described with reference to FIG.

  Next, in step SR3, the written data is read out to the outside. Externally, it is compared whether the read data is the same as the written data. It can be seen that the RAM BRAM operates normally if the written data is read normally. Therefore, BIST can be executed.

  In step SR4, the RAM test is completed, and in step SR5, data corresponding to the procedure for performing the BIST test is written. In step SR6, BIST is performed. Based on the data corresponding to this procedure, for example, a test such as a checker pattern or a march pattern is performed.

FIG. 41 is an operation waveform diagram for explaining execution of a read test of the RAM unit BRAM.
Referring to FIGS. 39 and 41, first, it is assumed that the writing of test data to RAM BRAM is completed before time t11.

  When data input / output terminals DQj to DQk are set to a predetermined combination and data input / output terminal DQ0 is set to a predetermined potential exceeding power supply potential Vcc at time t11, detection signal / SVCC is at L level and data is input accordingly. The output terminal DQi is at L level.

  Even if a predetermined combination of data input / output terminals DQj to DQk is released, if data input / output terminal DQ0 is applied with a predetermined high potential level, a read test of RAM unit BRAM is executed. At this time, the enable signal BRAME attains an H level at time t12, and accordingly, the shift clock signal is converted to the external clock signal ext. Generated based on CLK. When the shift clock SCK is input, the data set in the RAM unit BRAM is read from the data input / output terminal DQi.

  When the high potential level of the data terminal DQ0 is released at time t13, the enable signal BRAMRE falls to the L level, and the data reading from the RAM unit BRAM ends. Then, the counter in the detection circuit SVIHDEC starts counting, and the predetermined clock number enable signal STEN becomes H level. In response, the test data is written to the RAM BRAM until time t14.

  After the time t14, the BIST is executed, and when the self refresh or mode register set cycle is reached at the time t15, the BIST flag BISTF is canceled and the BIST ends.

[Monitoring internal data during BIST execution]
During BIST execution, it is normal that only the test result is output to the outside, so it may be unclear whether BIST is being executed normally. It is convenient if the internal data can be output to the outside even during BIST execution.

  FIG. 42 is a diagram showing a configuration in which internal data is output to the outside during BIST execution.

  Referring to FIG. 42, a degeneration circuit RDC that degenerates commands and addresses such as CS and / RAS, inspection data, expected value data, and the like, and an output of degeneration circuit RDC in response to test signal TEBX is input to data input / output terminal DQi. A switch SW02 provided as output data for output is provided.

Other configurations are the same as those described with reference to FIG. 39, and therefore description thereof will not be repeated.
FIG. 43 is an operation waveform diagram for explaining a state in which the test execution status is output to the outside from the data input / output terminal.

  When executing BIST, the BIST circuit 649 in FIG. 31 automatically generates a command, an address and data internally. These pieces of information are output so that they can be monitored externally.

  Referring to FIG. 43, it is assumed that the setting for starting the BIST operation is made before time t1. When the active command ACT is executed internally at BIST at time t1, the data of the command and address that are internally set correspondingly are output as data string D11 from each data input / output terminal.

  At time t2, the write command is executed internally. In response, the command being executed and the data of the used address are output as the data string D12.

  When a read command is executed internally at time t3, data corresponding to the command and address used internally is output from the data input / output terminal accordingly.

  After time t4, data read from the internal memory array is output from each data input / output terminal.

  As described above, even in the BIST mode, if the internal information is read out from the data input / output terminal, the internal state can be observed even in the BIST mode. In other words, whether or not all test results are acceptable, that is, only judgment results are not output, but for example, comparison is made in units of relief by redundant memory arrays to confirm whether or not the relief by the spare memory array is correctly performed. It is also possible to output the result.

  When outputting data representing the internal state to the synchronous semiconductor memory device, the test device can recognize the data output period by outputting the strobe signal QS.

  Therefore, when the BIST is executed, the internal state can be monitored by the test apparatus, so that the result of the operation check can be further ensured, and the cause of the occurrence of the trouble can be easily clarified.

  FIG. 44 is a circuit diagram showing a configuration of a degeneration circuit RDC used when outputting internal information of BIST.

  This data degeneration circuit is used to reduce the period of output data or reduce the number of pins when outputting the internal state during BIST.

  Referring to FIG. 44, signals indicating internal commands, address data, and the like are applied to signals SIG1 to SIGn. This data degeneration circuit includes switching circuits 684, 685,..., 686, 687 respectively provided corresponding to signals SIG1, SIG2,..., SIGn-1, SIGn, and a sense amplifier 688 that receives and amplifies the output of the switching circuit 687. including.

  A power supply potential and a ground potential are applied to the input nodes NI1 and NI2 of the switching circuit 684, respectively.

  Output nodes NO1 and NO2 of switching circuit 684 are connected to input nodes NI1 and NI2 of switching circuit 685, respectively. Similarly, output nodes NO1 and NO2 of switching circuit 686 are connected to input nodes NI1 and NI2 of switching circuit 687, respectively. A plurality of switching circuits are connected in series between the switching circuits 685 and 686, and each of the input nodes NI1 and NI2 of the switching circuit provided corresponding to the m (natural number) input signal SIGm is m. Output nodes NO1 and NO2 of a switching circuit provided corresponding to the −1st input signal are connected.

  The output nodes NO1 and NO2 of the switching circuit 687 connected to the nth, which is the final stage, are connected to the input / output nodes NOA and NOB of the sense amplifier 688, respectively.

  Switching circuit 684 receives an inverter 690 that receives and inverts signal SIG1, an N-channel MOS transistor 691 connected between input node NI1 and output node NO1 and receiving signal SIG1 at its gate, input node NI2 and output node NO2. N channel MOS transistor 692 connected between and receiving signal SIG1 at the gate, N channel MOS transistor 694 connected between input node NI1 and output node NO2 and receiving the output of inverter 690 at the gate, and input node NI2 N channel MOS transistor 693 connected between output node NO1 and receiving the output of inverter 690 at its gate is included.

  Since switching circuits 685 to 687 have the same configuration as switching circuit 684, description thereof will not be repeated.

  Sense amplifier 688 is connected in series between N channel MOS transistors 696 and 697 connected in series between input / output node NOA and input / output node NOB, and between input / output node NOA and input / output node NOB. N-channel MOS transistors 695 and 699, N-channel MOS transistors 695 and 699 connected between the connection nodes of N-channel MOS transistors 696 and 697 and the ground node and receiving logic determination signal LJS at their gates, and P-channel MOS transistors 698 and 699 P channel MOS transistor 700 connected between the connection node and the power supply node and receiving at its gate the logic determination signal / LJS.

  The gates of N channel MOS transistor 697 and P channel MOS transistor 699 are both connected to input / output node NOA. The gates of N channel MOS transistor 696 and P channel MOS transistor 698 are both connected to input / output node NOB.

  The operation of the data degeneration circuit will be briefly described. If the number of signals whose logic level is H level among the input signals SIG1 to SIGn is an even number, the output signal OUTA becomes H level and the output signal OUTB becomes L level. Become. On the other hand, if the number of signals whose logic level is H among the input signals SIG1 to SIGn is an odd number, the output signal OUTA becomes L level and the output signal OUTB becomes H level.

  This is because H level and L level data are respectively applied to the input nodes NI1 and NI2 of the first switching circuit 684, and when the input signal SIG1 is at the H level, the data is directly output to the corresponding output nodes NO1 and NO2. When input signal SIG1 is at the L level, the data applied to input node NI1 is output to output node NO2, and the data applied to input node NI2 is output to output node NO1.

  That is, the switching circuits 684 to 687 output the input data as they are to the corresponding output node when the input signal SIGn is at the H level, and the data applied to the input nodes NI1 and NI2 when the input signal SIGn is at the L level. They are exchanged and output to the output nodes NO1 and NO2. For this reason, it is possible to determine the even / odd number of signals having the H level among the input signals SIG1 to SIGn.

  A signal representing a command, an address signal, or the like can be input to the signals SIG1 to SIGn.

  Therefore, for example, if signals for 4 cycles are held in a latch and output through the degeneration circuit RDC, the data output in 4 cycles as shown in the data string D11 in FIG. 43 is output as 1 cycle. It is possible.

  FIG. 45 is an operation waveform diagram for explaining an operation when a command or address data is used in a degenerated state.

  Referring to FIG. 45, internal data information D111 corresponding to active command ACT is output at time t1. By using the circuit shown in FIG. 44, the data string D11 in FIG. 43 can be compressed and output in this way. Similarly, at times t2 and t3, data corresponding to the command or the like is compressed and output. In addition, after time t4, the output data can be checked at a data rate half that in the case of FIG. 43 by similarly compressing and outputting the data.

  As the data determination result, 64 data in each cycle are distributed to 4DQ and output. The resulting output is output during the period when the strobe signal QS is at L level. In this way, the number of data pins of output data can be reduced, and the data rate of output data can be reduced, so that even an inexpensive tester with low performance can monitor the output.

[Retention of defective address in BIST]
FIG. 46 is a block diagram showing a configuration for reading out a defective address to the outside during BIST execution.

  Referring to FIG. 46, this synchronous semiconductor memory device includes a BIST control unit 649 that automatically generates commands, data, and addresses, and a data read / write operation that receives commands, data, and addresses generated by BIST control unit 649. A memory array MA that performs a write operation and a failure detection circuit 801 that detects a match between a plurality of data read from the memory array MA and performs failure determination are provided.

  Defect detection circuit 801 includes coincidence detection circuits 802 to 808 that detect coincidence of a plurality of read signals read simultaneously from memory array MA, gate circuit 810 that receives the outputs of coincidence detection circuits 802 and 804, and coincidence detection circuit 806. , 808, and a gate circuit 812 for receiving the output of 808.

  The coincidence detection circuit has the configuration described with reference to FIG. 19, and the defect detection rate is improved. The outputs of the gate circuits 810 and 812 are ANDed by the gate circuit 814, and when no defective memory cell is found, the output of the gate circuit 814 holds the H level.

  Although not shown, a coincidence detection circuit and a gate circuit included in the defect detection circuit 801 are appropriately added according to the number of data read from the memory array MA at a time.

  When a defective memory cell is found, the output of the gate circuit 814 changes to L level. Defect detection circuit 801 further includes an edge detection circuit 816 that detects this change and generates a one-shot pulse.

  The synchronous semiconductor memory device detects which output of the gate circuits 810 to 812 has changed in response to the one-shot pulse, and outputs an address signal of the corresponding memory array MA to the pre-DQ latch unit 826. Further included is an address selection circuit.

  This synchronous semiconductor memory device is connected to a flag holding unit 818 that receives the output of the edge detection circuit 816 and outputs a suspend flag, and conducts in response to the suspend flag, and connects a data input / output terminal DQm that is an output node of the output buffer 828. N channel MOS transistor 830 for fixing to L level is further included.

  This synchronous semiconductor memory device is held in an input buffer 832 that receives a signal from an input / output terminal DQn that designates reading of an address from the outside, and an output signal ADRD of the input buffer 832 in a pre-DQ latch unit 826. And an output control circuit 824 for outputting the address to the output buffer 834. Defective address data is output from data terminal DQl in accordance with clock signal ADOUT.

FIG. 47 is an operation waveform diagram for explaining address output.
Referring to FIGS. 46 and 47, at time t1, a memory cell defect is detected during the BIST test execution, and the detection signal DETA changes. In response, suspend flag SUSPEND rises to H level. The potential of the data input / output terminal DQm is at the L level.

  When the tester device detects the change of the suspend flag by the change of the data input / output terminal DQm, the tester device connected to the outside at time t2 sets the potential of the data input / output terminal DQn to H so that an address is output to the chip. Launch to level.

  Accordingly, when signal ADRD changes to H level at time t3, output control circuit 824 changes signal ADOUT as an address output clock. In response, an address signal is output from data input / output terminal DQl.

  When the tester device finishes reading the address, the tester device lowers the potential of the data input / output terminal DQn from the H level to the L level. In response, signal ADRD falls to the L level, and suspend flag SUSPEND is released.

  At time t5, the BIST control unit 649 detects that the suspend flag SUSPEND is released, and restarts BIST.

  Even when the BIST is executed in this way, it is possible to output a defective address detected internally to a tester device or the like connected to the outside, so that redundant replacement is performed using the output address. It becomes possible to execute.

Furthermore, the case where automation of redundant replacement is advanced will be described below.
FIG. 48 is a diagram showing a first configuration in which redundant replacement is performed by itself based on a defective address detected at the time of BIST execution.

  Referring to FIG. 48, this configuration includes an address processing unit 842 that receives the output of the address selection circuit 822, an edge detection circuit 846 that detects an edge of a signal indicating the end of BIST output from the BIST control unit 649, an edge A gate circuit 844 that outputs an address set in the address processing unit 842 according to the output of the detection circuit 846, and an address program latch 848 provided in a redundancy determination circuit unit that latches an address output from the gate circuit 844. However, the configuration is different from that shown in FIG. Other configurations are similar to those shown in FIG. 46, and therefore description thereof will not be repeated.

  When a defective address is detected and received, the address processing unit 842 executes predetermined address processing. In the meantime, an H level signal is output to the edge detection circuit 820.

  The edge detection circuit 820 detects that the address processing of the address processing unit is completed and the output signal falls to the L level, and releases the suspend flag held by the flag holding unit 818. Then, the BIST control unit 649 continues to execute BIST.

  When the BIST ends, the BIST control unit 649 outputs a signal indicating the end to the edge detection circuit 846. In response to the end signal detected by the edge detection circuit 846, the gate circuit 844 transmits the defective address held in the address processing unit to the address program latch of the redundancy determination circuit unit, and the defective address is used as a replacement address in the address program latch. Entered. For the address program latch, for example, an electrically rewritable nonvolatile memory is used.

FIG. 49 is a block diagram showing a second configuration for performing redundant replacement after the BIST is completed.
Referring to FIG. 49, edge detection circuit 854 that has detected the BIST end signal output from BIST control unit 649 outputs signal HBREAK.

  The address processing unit 852 that receives and processes an address from the address selection circuit 822 has a built-in electric fuse, and the held address is fixed by inputting the signal HBREAK. The fixed address is transmitted to the address program latch 856 of the redundancy judgment circuit unit, and the defective address is replaced.

This configuration is different from the configuration shown in FIG. 48 in the above points.
FIG. 50 is a diagram showing a configuration for performing address fixing included in address processing unit 852 in FIG.

  Referring to FIG. 50, address processing unit 852 performs level conversion by receiving high voltage generation circuit 902 that generates a high voltage used to break the fuse when the address is fixed, and signal HBREAK0 at the end of BIST. Level conversion circuit 904 # 0, N-channel MOS transistor 908 # 0 receiving the output of level conversion circuit 904 # 0 at its gate, and high voltage when N-channel MOS transistor 908 # 0 is turned on receive a predetermined address signal AddB0 to AddBn. And an address fixing unit 906 that performs address fixing according to the above. 49 includes signals HBREAK0 to HBREAKm corresponding to m address fixing units (m is a natural number), and FIG. 50 representatively shows a configuration related to signal HBREAK0.

  Address fixing unit 906 includes address fixing units 906 # 0 to 906 # n corresponding to address signal bits AddB0 to AddBn. Address fixing units 906 # 0 to 906 # n are directed to address program latch 856 in FIG. Signals OUB0 to OUBn indicating the replacement addresses are respectively output.

  Although not shown, address processing unit 852 further includes level conversion circuits 904 # 1 to 904 # m that receive signals HBREAK1 to HBREAKm and perform level conversion, and outputs of level conversion circuits 904 # 1 to 904 # m are N-channel MOSs. This is applied to transistors 908 # 1 to 908 # m. Although not shown, a circuit similar to the address fixing unit 906 is provided corresponding to each of the N-channel MOS transistors 908 # 1 to 908 # m.

  Level conversion circuit 904 # 0 receives signal HBREAK0 at its gate, N channel MOS transistor 914 whose source is connected to the ground node, inverter 918 that receives and inverts signal HBREAK0, and the output of inverter 918 at its gate, N channel MOS transistor 916 having a source connected to the ground node, P channel MOS transistor 910 having a gate connected to the drain of N channel MOS transistor 916 and a gate connected to the drain of N channel MOS transistor 916 P channel MOS transistor 912 connected between the drain of N channel MOS transistor 916 and the power supply node, the gate connected to the drain of N channel MOS transistor 914, and the gate connected to the power supply node. And an N-channel MOS transistor 920 connected between the N-channel MOS transistor 916 of the drain and the level conversion circuit 904 # 0 of the output node.

  Although not shown, the level conversion circuits 904 # 1 to 904 # m have the same configuration as the level conversion circuit 904 # 0.

  Address fixing unit 906 # 0 is connected between node NY and node NX, N channel MOS transistor 922 connected between node NVg and node NY to which a high voltage is applied according to signal HBREAK0. Fuse element 924, N channel MOS transistor 926 that receives signal AddB0 at its gate and is connected between node NX and the ground node, and level conversion that receives signal AddB0 and converts it to the gate of N channel MOS transistor 922 A circuit 942 and a buffer circuit 928 that has node NX connected to the input and outputs signal OUB0 are included.

  The fuse element 924 is a capacitor, and the electrodes are normally insulated from each other. However, when a high voltage is applied between the node NX and the node NY, the insulation is broken.

  Level conversion circuit 942 receives signal AddB0 at its gate, N channel MOS transistor 934 whose source is connected to the ground node, inverter 938 that receives and inverts signal AddB0, and the output of inverter 938 at its gate. N channel MOS transistor 936 connected to the ground node, P channel MOS transistor 930 connected between the drain of N channel MOS transistor 934 and the power supply node, and having its gate connected to the drain of N channel MOS transistor 936, N P channel MOS transistor 932 is connected between the drain of channel MOS transistor 936 and the power supply node, the gate is connected to the drain of N channel MOS transistor 934, and the gate is connected to the power supply node. And an N-channel MOS transistor 940 connected between the output node of the drain and the level converting circuit 942 of the OS transistor 936.

  FIG. 51 is a circuit diagram showing a configuration of address program latch 856 in FIG.

  Referring to FIG. 51, address program latch 856 latches switch 950 # 0 for transmitting signal OUB0 applied from address processing unit 852 in accordance with signal TG and signal OUB0 applied via switch 950 # 0. Latch circuit 952 # 0 for outputting signals R0 and / R0 and bit comparison unit 954 # 0 for connecting common node NZ to the ground node in accordance with the combination of signals R0, / R0, AddR0 and / AddR0 are included.

  The address program latch 856 further latches the signal OUBi transmitted from the address processing unit 852 in response to the signal TG and the signal OUBi applied via the switch 950 # i, and signals Ri, / Ri And a bit comparison unit 954 # i for connecting the common node NZ to the ground node according to the combination of the signals Ri, / Ri, AddRi, and / AddRi (where i is 1 to n) Natural number).

  The latch circuit 952 # 0 has an input connected to the switch 950 # 0 and outputs a signal / RO, an inverter 960 that receives and inverts the signal / R0 and applies it to the input node of the inverter 958, and a signal / R0. And an inverter 962 that inverts and outputs a signal RO.

  Latch circuits 952 # 1 to 952 # n receive signals OUB1 to OUBn through switches 950 # 1 to 950 # n, respectively, and output signals R1 to Rn. Since latch circuits 952 # 1 to 952 # n have the same configuration as latch circuit 952 # 0, description thereof will not be repeated.

  Bit comparison unit 954 # 0 includes N-channel MOS transistors 964, 966, and 968 connected in series between common node NZ and the ground node. The gates of N channel MOS transistors 964, 966, and 968 receive power supply potential, signal / RO, and signal / AddR0, respectively.

  Bit comparison unit 954 # 0 further includes N channel MOS transistors 974, 976, and 978 connected in series between common node NZ and the ground node. The gates of N channel MOS transistors 974, 976, and 978 receive power supply potential, signal RO, and signal AddR0, respectively.

  Since bit comparison units 954 # 1 to 954 # n have the same configuration as bit comparison unit 954 # 0, description thereof will not be repeated.

  Address program latch 856 further includes a latch circuit 956 that precharges common node NZ in accordance with precharge signal / PC and holds the potential of the common node.

  Latch circuit 956 receives precharge signal / PC as a gate, P channel MOS transistor 982 connected between common node NZ and the power supply node, and common node NZ connected to the input, and outputs replacement instruction signal REPL. Inverter 986 and a P-channel MOS transistor 984 connected between common node NZ and the power supply node and receiving substitution instruction signal REPL at its gate are included.

  FIG. 52 is an operation waveform diagram for explaining a state in which address fixing is performed in the address processing unit.

  Referring to FIGS. 50 and 52, address processor 852 determines redundant row and redundant column address AddB to be replaced based on accumulation of defective addresses detected by BIST in a circuit portion (not shown). The address fixing unit 906 is supplied with signals AddB0 to AddBn corresponding to each address bit of the address AddB. When BIST ends and signal HBREAK0 is applied to address processor 852, high voltage VPP is applied to node NY at time t1. At this time, if the corresponding signal AddB0 is at the H level, the potential of the node NX becomes the L level, the potential difference between the electrodes of the capacitor 924, which is a fuse element, increases, and dielectric breakdown occurs, so that the fuse element becomes conductive.

  When the address AddB0 is released at time t2, the node NX is brought into a predetermined potential because it is electrically connected to the node NY by the broken fuse (capacitor).

  At times t3 and t4, the address set by the destruction of the fuse is confirmed. A state in which an unset address is input as Add (ext) at time t3, and a case where the set address and address Add (ext) match at time t4 are shown. Here, the address Add (ext) is an address generated by the BIST circuit instead of the address input from the outside.

  By time t5, address setting and checking are repeated for the number of address fixing portions corresponding to N channel MOS transistors 908 # 1 to 908 # m. At time t5, the program cycle ends, and it is finally determined whether or not the address program has been normally performed. If the determination result indicates unprogrammed, there is a possibility that the fuse is not sufficiently destroyed. Repeat the program again.

FIG. 53 is an operation waveform diagram for explaining the operation after power-on after the address is fixed.
Referring to FIG. 53, after the address is fixed, command CKE is input at time t1 when a predetermined time elapses after the power is turned on. At this time, all the signals AddB0 to AddBn are once set to the H level to initialize the node NX to the L level.

  After time t2, replacement addresses held in the address processing unit 852 in FIG. 49 due to fuse destruction are sequentially transferred to and held in the address program latch 856. At time t2, the first replacement address is transferred from the address processing unit 852 to the address program latch 856 by the transfer instruction PRGREAD1. Subsequently, at time t3, the second replacement address is transferred from the address processing unit 852 to the address program latch 856 by the transfer instruction PRGREAD2.

  This transfer is performed a plurality of times using the set time of a clock recovery circuit such as a DLL circuit, but may be performed once if the number of redundant rows and redundant columns is small. When transferring at a time, a command register setting cycle or the like is used.

  As described with reference to FIGS. 48 to 53, if the configuration is such that redundant replacement is performed after the BIST is performed, detection of defective addresses and redundant replacement can be performed by the chip itself even without an expensive test device, thereby further reducing costs. Can be achieved.

[Bad address processing during BIST execution]
Hereinafter, a description will be given of a configuration in which defective addresses are retained and redundant replacement is performed inside the chip when BIST is executed.

  FIG. 54 is a diagram for explaining a test of memory cells in the memory array.

  Referring to FIG. 54, memory array MA # is provided with two redundant rows RRED and four redundant columns CRED.

  As shown by the arrow AR, the memory cells are sequentially inspected in the row direction, and when the inspection of the memory cells for one row is completed, the process proceeds to the next row. Now, this memory array has seven defective memory cells. If the address of each defective memory cell is called a defective address, the defective address is (row address, column address) = (Ra, Cb), (Ra, Cc), (Ra, Cd), (Ra, Ce). ), (Ra, Cf), (Rb, Ca), and (Rc, Ca).

  In the case where these defective addresses are replaced using redundant rows and redundant columns, conventionally, the tester device stores the defective addresses when performing an operation test on the tester device. The tester device can display bad bits in the fail bit memory. For example, when testing a 64 Mbit DRAM, the tester device can display a 64 Mbit space.

  When the BIST is performed by a test circuit built in the chip, it is impossible to arrange such a fail bit memory on the chip, so it is necessary to store defective addresses one by one.

  The difficulty in this case is that the combination of which defective memory cell is used for replacement of the redundant column and redundant row changes depending on the arrangement of the defective address.

  The simplest method is to assign a redundant row or redundant column one by one to the defective address that has occurred, but the maximum number of relief bits is only (number of redundant rows + number of redundant columns). ineffective.

  For example, since there are five defective memory cells on the row address Ra in FIG. 54, for example, when all the redundant columns are used for repair, five redundant columns are required. If the row address Ra is replaced, five defective memory cells can be repaired with one redundant column. It is necessary to devise how to determine such efficient relief.

  The semiconductor memory device according to the third embodiment makes this determination possible by providing a counter that holds the address and counts the number of occurrences of the defective address.

  FIG. 55 is a schematic diagram for explaining a schematic configuration of the address processing unit 842 shown in FIG.

  Referring to FIG. 55, address registers RA # 1-RA # 6 for storing a defective row address when a defective memory cell is found are provided corresponding to address registers RA # 1-RA # 6, respectively. If the row address stored in the address registers RA # 1 to RA # 6 and the inputted defective row address are compared and matched, the counters CR # 1 to CR # 6 incrementing the count value by 1 and the address register RA # 1 Flag holding portions FR # 1 to FR # 6 provided corresponding to .about.RA # 6 and indicating that it is decided to replace the redundant row with the stored row address are provided.

  Similarly, column addresses are provided corresponding to address registers CA # 1 to CA # 6 for storing defective column addresses corresponding to defective memory cells and address registers CA # 1 to CA # 6. If the column address stored in registers CA # 1-CA # 6 and the input defective column address are compared and matched, counters CC # 1-CC # 6 that increment the count value by 1 and address registers CA # 1-CA # 1- Flag holding units FC # 1 to FC # 6 provided corresponding to CA # 6 and indicating that it is decided to replace the redundant row with the stored row address are provided.

  In this way, by arranging the address register and the counter as a set, it is observed how many times an address that appears once overlaps. Then, when the count number exceeds a certain value, it is determined to replace the corresponding row or column address.

  Referring again to FIG. 54, if there are four redundant columns and five or more defective addresses in the column direction on the same row address Ra are found, it is impossible to rescue all of them with the redundant columns. Is possible. In such a case, there is no choice but to use redundant rows.

  In other words, the counter value is monitored, and for the appearance of the same row address, it is determined that the row address is relieved in the redundant row when the number of redundant columns, that is, the counter value exceeds 4. To do. Thereafter, when the same row address is confirmed, all of them are relieved by this redundant row. Therefore, the column address of the memory cell existing on the row address determined to be repaired by the redundant row is excluded from the address holding target thereafter.

  If it is decided to use redundant rows, then the available redundant rows will be reduced by one. Therefore, the limit value of the counter that counts the number of defects of the same column address is decreased by one. In FIG. 54, after it is determined that the row of the row address Ra is repaired with a redundant row, the number of usable redundant rows is (2-1 = 1), and the counter value of the defective column address Ca is set to 2. At that time, the column address Ca can be relieved only by using a redundant column.

  By repeating this operation, defective addresses are accumulated. When the test is completed, if a defective address is not observed exceeding the set of address registers (number of redundant rows + number of redundant columns), that is, (2 + 4 = 6) in FIG. The array is determined to be salvable. However, if different defective addresses are detected more than the repairable number during the test, it is determined that the repair is not possible at that time. Hereinafter, a change in address storage in the case of the arrangement of defective memory cells in FIG. 54 will be described.

FIG. 56 shows the state of the first stage of address storage.
54 and 56, no defect of the memory cell is detected until the address (Ra, Cb) is reached. If the memory cell corresponding to the address (Ra, Cb) is checked and the memory cell is defective, the row address Ra is stored in the address register RA # 1 of the row address, and the defective address count unit A count number of 1 is set in CR # 1. Similarly, column address Cb is stored in address register CA # 1 for storing a column address, and defective address count unit CC # 1 holds a count number of 1.

FIG. 57 shows the state of the second stage of address storage.
Referring to FIGS. 54 and 57, the memory cell corresponding to address (Ra, Cc) is checked and is defective. Therefore, row address Ra is stored in address register Ra # 2, and address register CA # 2 Stores a column address Cc. The count values of the defective address count units CR # 1 and CR # 2 are increased since the second occurrence of the row address Ra, and the count 2 is held.

  The count value of defective address count portion CC # 1 does not change, and 1 is held in defective address count portion CC # 2.

FIG. 58 shows the state of the third stage of address storage.
Referring to FIGS. 54 and 58, when a defect in the memory cell at address (Ra, Cd) is detected, row address Ra is stored in address register RA # 3, and column address Cd is stored in address register CA # 3. Is stored. Since the appearance of the row address Ra is the third time, the count number of the defective address count units CR # 1 to CR # 3 increases by 1 to 3. Further, count value 1 is held in defective address count unit CC # 3.

FIG. 59 shows the state of the fourth stage of address storage.
54 and 59, a defective memory cell at address (Ra, Ce) is detected, row address Ra is stored in address register RA # 4, and column address Ce is stored in address register CA # 4. Is done. The count value of defective address count units CR # 1-CR # 4 is 4, and count value 1 is held in defective address count unit CC # 4.

FIG. 60 shows the state of the fifth stage of address storage.
Referring to FIGS. 54 and 60, when a defective memory cell is detected at address (Ra, Cf), the number of detections of row address Ra is 5, which is not replaced even if all redundant rows CRED are assigned. Since it is possible, the row address Ra is determined to be replaced by any one of the redundant rows RRED.

  A flag is set in the flag holding unit FR # 1, and the address of the row address Ra stored in the address register RA # 1 is fixed. Thereafter, if the row address of the defective memory cell is Ra, it is not necessary to hold the column address. Therefore, address register CA # 1 is in an address free state. The addresses set in address registers RA # 2-RA # 4 and CA # 2-CA # 4 are cleared.

FIG. 61 is a diagram showing a state of the sixth stage of address storage.
Referring to FIGS. 54 and 61, a defective memory cell is found at address (Rb, Ca), row address Rb is set in address register RA # 2, and 1 is held in defective address count unit CR # 2. Is done. Further, column address Ca is stored in address register CA # 2, and count value 1 is held in defective address count unit CC # 2.

FIG. 62 shows the state of the seventh stage of address storage.
54 and 62, when a defective memory cell is detected at address (Rc, Ca), row address Rc is stored in address register RA # 1, and 1 is stored in defective address count unit CR # 3. Is retained. Further, the column address Ca is stored in the address register CA # 3, and the count value of the defective address count units CC # 2 and CC # 3 is 2.

FIG. 63 is a diagram showing a state of address storage after the inspection is completed.
Referring to FIGS. 54 and 63, when the count value exceeds 1 after completion of the inspection, both address registers CA # 2 and CA # 3 are finally stored in order to achieve efficient relief. Row address Ca is set as a replacement column, flag is set in flag holding unit FC # 2, and the row address set in address register RA # 2 is in a free state. The addresses set in address registers RA # 3 and CA # 3 are cleared.

  As described above, it is finally determined how redundant rows and redundant columns are replaced.

The operation of the address processing unit described above will be described again using a flowchart.
FIG. 64 and FIG. 65 are flowcharts showing the flow of storing defective addresses at the time of inspection and remedy determination after completion of the inspection.

  Referring to FIGS. 64 and 65, when a defective address is received from the suspend flag during BIST execution, address storage processing starts in step S01. Next, in step S02, a match between the free address and the defective address is determined. Here, the free address has a row address that is determined to be replaced by a row, and a column address of a defective memory cell that is found afterwards or a column that is determined to be replaced. It is a row address of a defective memory cell that has an address and is subsequently discovered.

  If the address does not apply to the free address, the process proceeds to step S03, and writing to the address register is performed.

  Next, in step S04, a coincidence comparison with the address already stored in the address register is performed. If they match, the process proceeds to step S07, and if they do not match, the process proceeds to step S05.

  In step S05, it is determined whether the address register in which the address is stored exceeds the number of redundant columns and redundant rows. If it exceeds, the process proceeds to step S15, and it is determined that the inspected chip cannot be relieved. And BIST is interrupted.

  When the number of address registers storing addresses does not exceed the number of redundant columns and redundant rows, the process proceeds to step S06.

  In step S06, 1 is added to the value of the counter provided corresponding to each address register. Then, the process proceeds to step S14 where the defective address storing process is completed and the BIST is continued.

  If a match with the free address is detected in step S02, it is determined that the defective address has already been relieved, so there is no need to store the address, and the process proceeds to step S14, where address storage processing is performed. Is terminated.

  In step S04, if the already stored defective address matches the row address or the column address, the process proceeds to step S07. In step S07, it is determined whether or not the matched address is a row address.

  If the matched address is a row address, the process proceeds to step S08, and the value of the counter corresponding to the matched row address is incremented.

Then, the process proceeds to step S09.
In step S09, it is determined whether or not the incremented counter value exceeds the column limit value (number of usable redundancy). When the limit value is exceeded, the process proceeds to step S10, where the repair of the row address is determined, the row address is fixed, and a flag is set in the corresponding flag holding unit. Then, the same register at the same address is cleared, and the contents of the address register are rearranged. That is, the address is filled in the cleared register part. The column address corresponding to the fixed row address is freed and the column limit value is decremented by one.

  If the result of step S09 is negative, the process proceeds to step S14 and the address storage process is terminated.

  In step S07, if the matched address is not a row address, the process proceeds to step S11.

  In this case, the matched address is a column address. In step S11, the value of the counter provided corresponding to the matching column address is incremented. Subsequently, in step S12, it is determined whether or not the incremented counter value exceeds the low limit value (the number of usable redundancy). If not, the process proceeds to step S14 and the address storing process is terminated.

  If the row limit value is exceeded, column address relief is determined, the column address is fixed, and a flag is set in the corresponding flag holding unit. Then, the register storing the same column address is cleared and the contents of the address register are rearranged. The rearrangement of the contents of the address register means that addresses that are not cleared are sequentially packed in a cleared register. The row address is freed and the row limit value is decremented by one. Then, the process proceeds to step S14, the address storing process is completed, and the BIST is continued.

  The address storage processing cycle from step S01 to step S14 is repeated. When the BIST is finally completed, a BIST end flag is output and the process proceeds to step S16. In step S16, the address is fixed. The fixing of the address is performed in the order of the count value of the corresponding counter. Then, in step S17, the repair determination ends. That is, the column address for replacing the redundant column and the row address for replacing the redundant row are determined. Then, the determined replacement address is transferred to the address program unit or proceeds to the stage of electric fuse destruction processing corresponding to the replacement processing.

  FIG. 66 is a diagram for explaining how the relief address is transferred from the address processing unit 842 to the program processing unit of each bank.

  66, the address processing unit 842 includes a flag holding unit FR as a row address processing system, a defective address count unit CR, a row address register RA, and a column address processing system as a flag holding unit FC and a defective address counting unit. CC and column address register CA are provided.

  Furthermore, a connection shift unit RSFT, address latches RLAT # 1 to RLAT # 4, and a demultiplexer RDEM that sequentially receive data related to row addresses from the address processing unit are provided, and row addresses for replacement corresponding to each bank. Is set, and an address comparison unit RCMP that determines whether or not the row address set in the setting unit RSET matches the row address input at the time of data reading is provided.

  Further, a connection shift unit CSFT for sequentially receiving data related to column addresses from the address processing unit, address latches CLAT # 1 to CLAT # 2, and a demultiplexer CDEM are provided.

  Corresponding to each bank, a setting unit CSET in which a column address to be replaced is set, and a column address set in the setting unit CSET and a column address input at the time of data reading are compared to detect a match. Are provided.

  Now, consider a case where BIST is completed and a flag is set in a portion corresponding to the row address RA in the flag holding unit FR and a flag is set in the flag holding unit FC corresponding to the column address CA. The connection shift unit RSFT transfers only the address flagged in the flag holding unit FR to the address latch RLAT # 1. The demultiplexer RDEM transfers the address held by the address latch to the corresponding bank when the BIST is performed for each bank. Along with the transmission of the address information, a high voltage is applied to the setting unit RSET by the signal HBREAK, the fuse corresponding to the set row address is destroyed, and the replacement address is fixed.

  When the setting of the replacement address is completed in this manner, when a match with the set replacement address is detected when the row address is input to the address comparison unit RCMP, the match detection signal RHIT11 is activated, and the defective memory The row containing the cell is deactivated and the redundant row is activated instead.

Similar operations are performed for column address processing.
As described above, the synchronous semiconductor memory device of the third embodiment can output internal information to the outside when performing BIST, and can use it for operation analysis or obtain an address for redundant replacement. is there. Furthermore, it is possible to retain the internal information of the inspection result and carry out redundant replacement by itself. Therefore, the inspection cost of the synchronous semiconductor memory device can be reduced.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a schematic block diagram showing an overall configuration of a synchronous semiconductor memory device 1000 of the present invention. FIG. 3 is a schematic diagram showing an example of arrangement of each block in the synchronous semiconductor memory device 1000 according to the first embodiment of the present invention. It is an operation | movement waveform diagram for demonstrating the asynchronous concept. It is the schematic for demonstrating the connection of each bank and each input-output circuit. It is a figure for demonstrating the flow from which data is output to the data input / output terminal DQ0 from a memory bank. FIG. 10 is a diagram for explaining a flow of writing data from a data input / output terminal DQ0 to a bank. It is a figure which shows the outline of a structure of the part of the data input / output terminals DQ0-DQ15. It is the figure which expanded and showed the part corresponding to the data input / output terminal DQ0-DQ3 shown in FIG. FIG. 3 is a diagram for explaining an outline in which a synchronous semiconductor memory device 1000 exchanges data through an input / output circuit unit. 3 is a circuit diagram showing a configuration of an input / output circuit 64 used in Embodiment 1. FIG. FIG. 11 is a circuit diagram showing a configuration of a latch 148 that holds data at the time of reading shown in FIG. 10. FIG. 11 is a circuit diagram showing a configuration of a latch circuit 156 that holds data at the time of data writing shown in FIG. 10. FIG. 11 is a circuit diagram illustrating a configuration of a shift register 162 illustrated in FIG. 10. FIG. 14 is a circuit diagram showing a configuration of a flip-flop 512 shown in FIG. 13. FIG. 3 is a conceptual diagram for explaining a concept of a data read test in the first embodiment. FIG. 16 is a circuit diagram showing a more detailed configuration of an input / output circuit 641 corresponding to FIG. 15. FIG. 6 is an operation waveform diagram for illustrating an operation of a data read test of the first embodiment. FIG. 6 is a conceptual diagram for explaining an operation of a read test in the first embodiment. FIG. 19 is a circuit diagram showing a configuration of coincidence detection circuits MAT11 and MAT12 shown in FIG. FIG. 11 is a conceptual diagram showing a concept of a read test in Modification 1 of Embodiment 1. FIG. 11 is a circuit diagram showing a configuration of input / output circuit 642 in Modification 1 of Embodiment 1. FIG. 11 is an operation waveform diagram for describing an operation of a read test in the first modification of the first embodiment. FIG. 11 is a conceptual diagram showing a concept of a data read test in a second modification of the first embodiment. FIG. 24 is a circuit diagram showing a configuration of a coincidence detection circuit MAT4 in FIG. FIG. 11 is an operation waveform diagram for describing a read test in Modification 2 of Embodiment 1. 12 is a conceptual diagram showing a concept of a data read test in Modification 3 of Embodiment 1. FIG. FIG. 3 is a circuit diagram showing configurations of a coincidence detection circuit MAT5 and an inverting switch circuit IVSW. FIG. 10 is an operation waveform diagram for illustrating a read test in Modification 3 of Embodiment 1. FIG. 6 is a circuit diagram showing a configuration of a test result output circuit TOC used in the synchronous semiconductor memory device of the second embodiment. FIG. 6 is an operation waveform diagram for explaining the operation of the test result output circuit TOC. FIG. 11 is a schematic block diagram showing an overall configuration of a synchronous semiconductor memory device 2100 according to a third embodiment. 6 is a diagram for explaining data input via an input / output buffer when performing BIST of the synchronous semiconductor memory device 2100. FIG. FIG. 33 is a circuit diagram showing a configuration related to a detection circuit SVIHDEC in FIG. 32. It is a block diagram for demonstrating the structural example of RAM part BRAM. FIG. 35 is a circuit diagram showing structures of flip-flop R # mn and transfer gate TG # mn in FIG. 34. It is a figure which shows the sequence regarding the test of the circuit for performing BIST. It is a block diagram for demonstrating the structure for implementing an entry test. FIG. 10 is an operation waveform diagram for explaining an entry test and data writing to a RAM unit. It is a block diagram for demonstrating the test of RAM part BRAM. It is a flowchart for demonstrating the test of RAM part BRAM. It is an operation waveform diagram for explaining execution of a read test of a RAM unit BRAM. It is a figure which shows the structure which outputs internal data with respect to the exterior at the time of BIST execution. FIG. 6 is an operation waveform diagram for explaining a state in which a test execution status is output to the outside from a data input / output terminal. It is a circuit diagram which shows the structure of the degeneracy circuit RDC used when outputting the internal information of BIST. FIG. 11 is an operation waveform diagram for explaining an operation when a command or address data is degenerated and used. It is a block diagram which shows the structure for reading a defective address outside at the time of BIST execution. It is an operation waveform diagram for explaining output of an address. It is a figure which shows the 1st structure which performs redundant replacement based on the defective address detected at the time of BIST execution. It is a block diagram which shows the 2nd structure which performs redundant replacement after BIST completion | finish. It is a figure which shows the structure for performing the address fixation contained in the address process part 852 in FIG. FIG. 50 is a circuit diagram showing a configuration of an address program latch 856 in FIG. 49. It is an operation | movement waveform diagram for demonstrating a mode that address fixation is performed in an address processing part. FIG. 10 is an operation waveform diagram for explaining an operation after power-on after address fixing. It is a figure for demonstrating the test of the memory cell in a memory array. FIG. 49 is a schematic diagram for explaining a schematic configuration of an address processing unit 842 shown in FIG. 48. It is a figure which shows the state of the 1st step of address storage. It is a figure which shows the state of the 2nd step of address storage. It is a figure which shows the state of the 3rd step of address storage. It is a figure which shows the state of the 4th step of address storage. It is a figure which shows the state of the 5th step of address storage. It is a figure which shows the state of the 6th step of address storage. It is a figure which shows the state of the 7th step of address storage. It is a figure which shows the state of address storage after completion | finish of a test | inspection. It is a flowchart showing a flow of storing a defective address at the time of inspection and remedy determination after completion of the inspection. It is a flowchart showing a flow of storing a defective address at the time of inspection and remedy determination after completion of the inspection. It is a figure for demonstrating a mode that the address for relief is selected from the address process part to the program process part of each bank. It is a block diagram which shows the block structure of the memory with the conventional BIST (built-in self test) function.

Explanation of symbols

  10 row predecoder, 14 column predecoder, RD row decoder, CD column decoder, 22 data converter, 30 DLL circuit, 64, 64a to 64f, 641, 642 input / output circuit, 102, 104 read amplifier, 122, 124 write Amplifier, RDB read data bus, WDB write data bus, 146, 148, 154, 156, L1, L2 latch, 142, 143 receiver, 158 bus driver, 162, 164, 172, 174, 180, 182 Shift register, 150 outputs Buffer, 152 input buffer, 302, MPX multiplexer, MAT1 to MAT4, MAT11 to MAT12, 230, 250 coincidence detection circuit, OBUF output buffer, DQi, DQj, DQk data input / output terminal, 234 38, E111, E112, E121, E122, 251, G1, G2 EXOR circuit, 236, 240, 252, 254 switching circuit, E113, E123 OR circuit, E41, E51 gate circuit, E42, E52 AND circuit, IVSW inversion switch, DF1 to DF9, R # 00 to R # mn flip-flop, 650 PLL circuit, 649 BIST circuit, PG pattern generation unit, BRAM RAM unit, SR1 to SR6 step, 666 latch circuit, 682 counter, IDEC decoder, TG # 00 TG # mn Transfer gate, MN4 N-channel MOS transistor, SVIHDEC detection circuit, SW01, SW02 switch circuit, RDC degeneration circuit, 801 failure detection circuit, 816, 820 edge detection circuit, RR ED redundant row, CRED redundant column, 842 address processing unit, 848 address program latch, FR # 1-FR # 6, FC # 1-FC # 6 flag holding unit, RA # 1-RA # 6, CA # 1-CA # 6 Address register, CR # 1-CR # 6, CC # 1-CC # 6 counter, 1000, 2000 Synchronous semiconductor memory device.

Claims (12)

A memory array;
A BIST (Built-in Self Test) control circuit that controls execution of a self-test for the memory array, provides an address signal and a command signal to the memory array, and exchanges storage data;
A synchronous semiconductor memory device comprising: a first terminal for outputting a test result of the preliminary test in a preliminary test mode for executing a preliminary test for testing whether the self test can be executed. A second terminal to which a first predetermined potential exceeding a first power supply potential is applied to designate execution of the self-test;
A detection circuit for detecting that the predetermined potential is applied to the second terminal;
A flag holding unit that sets a BIST execution flag according to the output of the detection circuit and outputs the BIST execution flag to the BIST control circuit;
2. The synchronous semiconductor memory device according to claim 1, further comprising: an output circuit that outputs to the first terminal that the detection circuit has performed the detection in the preliminary test mode. The BIST control circuit
A RAM unit for storing test data corresponding to the self-test procedure;
A pattern generation unit that controls the self-test based on the test data stored in the RAM unit,
The test result is
Including the test data stored in the RAM unit;
The RAM unit is
Including first to n-th group storage units (n is a natural number) which is a unit selected by the pattern generation unit during the self-test execution;
Each said group of storage units comprises:
Each of the m storage units is selected at a time when the self-test is executed, outputs the test data to the pattern generator, and becomes a shift register connected in series in the preliminary test mode. m is a natural number),
In the preliminary test mode, the first group of storage units receives the test data from the first terminal and outputs the test data to the second group of storage units;
In the preliminary test mode, the storage unit of the i-th group (i is a natural number of 2 to n-1) outputs the test data to the storage unit of the (i + 1) -th group,
The synchronous semiconductor memory device according to claim 1, wherein in the preliminary test mode, the n-th group of storage units outputs the test data to the first terminal. The BIST control circuit temporarily stops the self-test when a defective portion is found in the memory array during the self-test execution, and sequentially outputs each bit of a defective address corresponding to the defective portion;
The synchronous semiconductor memory device according to claim 1, further comprising a second terminal that receives and outputs each bit. A failure detection circuit for detecting coincidence of a plurality of read data from the memory array;
A flag holding unit that outputs a suspend flag that suspends the self-test in response to an output of the defect detection circuit;
A third terminal for outputting a recognition signal for executing the defective address output operation in response to the suspend flag;
A fourth terminal to which a completion signal indicating completion of reception of the defective address is input from the outside;
5. The synchronous semiconductor memory device according to claim 4, further comprising a completion detection circuit that outputs a suspend flag reset signal to the flag holding unit in response to the completion signal. The memory array is
A plurality of regular memory cells arranged in a matrix;
A plurality of redundant rows of redundant memory cells;
A plurality of redundant columns of redundant memory cells,
A failure detection circuit for detecting coincidence of a plurality of read data from the memory array;
In response to an output of the defect detection circuit, a defective address corresponding to the defective portion is received, address processing is performed, corresponding information is held, and the redundant row is output to the redundant row in accordance with a test end signal output by the BIST control circuit. An address processing unit for determining a replacement row address and a replacement column address respectively corresponding to a row to be replaced and a column to be replaced with a redundant column;
A flag holding unit that outputs a suspend flag that suspends the self-test in response to an output of the defect detection circuit, and that receives a processing completion signal indicating completion of the address processing from the address processing unit and resets the suspend flag; The synchronous semiconductor memory device according to claim 1, further comprising: The address processing unit
Including a first number of address holders that is the sum of the number of redundant rows and the number of redundant columns;
Each of the address holding units
A row address register that holds the row address of the defective address;
A row counter provided corresponding to the row address register and counting the number of detections of the row address stored in the row address register;
A row flag setting unit that is provided corresponding to the row address register and holds that the row address stored in the row address register is determined to be replaced;
A column address register that holds the column address of the defective address;
A column counter that is provided corresponding to the column address register and counts the number of column address detections stored in the column address register;
A column flag setting unit that is provided corresponding to the column address register and holds that the column address stored in the column address register is determined to be replaced;
The synchronous semiconductor memory device according to claim 6, wherein the address processing unit determines the row address replacement and the column address replacement based on count values of the column address counter and the row address counter. In response to a test end signal output from the BIST control circuit, the replacement address determined by the address processing unit is received and the replacement address is held. When the designated address at the normal reading of the memory array matches the replacement address A replacement address setting unit that outputs a replacement instruction signal;
The replacement address setting unit
The synchronous semiconductor memory device according to claim 6, further comprising a nonvolatile memory element that receives and holds the replacement address in response to the test end signal. In response to a test end signal output from the BIST control circuit, the replacement address determined by the address processing unit is received and the replacement address is held. When the designated address at the normal reading of the memory array matches the replacement address A replacement address setting unit that outputs a replacement instruction signal;
The replacement address setting unit
The synchronous semiconductor memory device according to claim 6, comprising a plurality of fuse elements whose conduction state is changed corresponding to an address in accordance with the test end signal. A first terminal group;
A data transmission circuit provided between the memory array and the first input / output terminal group, which is activated during the execution of the self-test and outputs a data group indicating the state of the internal circuit to the first input / output terminal group And further comprising
The data group is:
2. The synchronous semiconductor memory device according to claim 1, further comprising command data, address data, and test output data corresponding to the storage data used for the storage operation of the memory array.   The synchronous semiconductor memory device according to claim 10, further comprising a degeneration circuit that degenerates any one of the command data, the address data, and the storage data and outputs the test output data. A method for testing a synchronous semiconductor memory device, comprising:
The synchronous semiconductor memory device includes:
A memory array;
A BIST control circuit that controls execution of a built-in self-test (BIST) for the memory array, provides an address signal and a command signal to the memory array, and exchanges storage data;
A first terminal for outputting a test result of the preliminary test in a preliminary test mode for executing a preliminary test for testing whether the built-in self-test (BIST) can be executed;
The BIST control circuit
A RAM unit for storing test data corresponding to the self-test procedure;
A pattern generation unit that controls the self-test based on the test data stored in the RAM unit,
The test result is
Including the test data stored in the RAM unit;
The RAM unit is
Including first to n-th group storage units (n is a natural number) which is a unit selected by the pattern generation unit during the self-test execution;
Each said group of storage units comprises:
Each of the m storage units is selected at a time when the self-test is executed, outputs the test data to the pattern generator, and becomes a shift register connected in series in the preliminary test mode. m is a natural number),
A first step of inputting the test data from the first terminal and sequentially shifting and storing the data in the first to n-th storage units;
A second step of sequentially reading out the test data set in the first to n-th group storage units from the n-th group storage unit via the first terminal. Test method for synchronous semiconductor memory device.

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