JP2008293096A - Memory interface and system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory interface and a memory system for managing memory access to a memory module, in which replacement of the memory module is facilitated. <P>SOLUTION: The memory interface 3 includes a programmable logic part 11, a storage means 12 which stores configuration data for configuring a unique memory controller function for managing memory access to memory modules 2-A and 2-B, a configuration means 13 which executes configuration processing by developing the configuration data on the programmable logic part 11 and configuring the memory controller function, and a control means 14 which reads configuration data corresponding to the kind of the installed memory modules 2-A and 2-B from the storage means 12 and controls the configuration means 13 to execute the configuration processing using the read configuration data. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a memory interface for managing memory access to a memory module on which a semiconductor memory chip is mounted, and a memory system including the memory module and the memory interface.

  Memory modules (also referred to as “expansion memory”, “memory board”, or “expansion memory board”) that are installed in computers will be used in the future, such as those with larger memory capacity and memory access speeds. In consideration of replacement, it is modularized, and in recent years, various types of memory modules are on the market. A plurality of semiconductor memory chips of the same specification are mounted on the memory module, and connection terminals for connecting to a computer are provided. The memory module is used by being attached to a memory socket (also referred to as “memory slot”) provided on the motherboard of the computer main body. Such a memory module is generally called DIMM (Dual Inline Memory Module) and is used as a memory of a personal computer or a printer.

  Synchronous memory modules are mainly used in today's personal computers, such as SDR (Single Data Rate) SDRAM (Synchronous DRAM), DDR (Double Data Rate) SDRAM, DDR2 SDRAM, and DDR3 SDRAM, Various memory modules have been developed in response to the demand for faster memory access. Each of these memory modules has been developed mainly to achieve high speed, and is not compatible.

  Memory access is managed and controlled by the memory controller corresponding to the interface specification of the memory module. For example, DDR SDRAM, DDR2 SDRAM, and DDR3 SDRAM each employ an interface specification called SSTL (Stub Series Terminated Logic). However, since the DIMMs of the DDR SDRAM, DDR2 SDRAM, and DDR3 SDRAM have different power supply voltage values, these memory modules are not compatible.

  FIG. 5 is a circuit diagram showing a basic configuration of SSTL (Stub Series Terminated Logic). Table 1 shows interface specifications of DDR SDRAM, DDR2 SDRAM, and DDR3 SDRAM that employ SSTL.

  “SSTL 2” is adopted as the interface for the DDR SDRAM, “SSTL 18” is adopted as the interface for the DDR2 SDRAM, and “SSTL 15” is adopted as the interface for the DDR3 SDRAM. The power supply voltage of the DDR SDRAM is 2.5 volts, the power supply voltage of the DDR2 SDRAM is 1.8 volts, and the power supply voltage of the DDR3 SDRAM is 1.5 volts, and the voltage decreases as the generation progresses.

  For the purpose of facilitating the replacement of the memory module and increasing the degree of freedom thereof, there is a technology for mounting a memory controller corresponding to the interface specification of the memory module on a memory module on which a plurality of semiconductor memory chips are mounted (for example, Patent Document 1). In this technology, a memory controller corresponding to the specifications of a semiconductor memory chip is programmed into a programmable device such as an FPGA mounted on a memory module.

JP 2001-290696 A

  As described above, when the types of memory modules are different, the corresponding memory controllers and power supply voltages are different. Therefore, for example, when replacing a memory module mounted on a computer with another memory module in order to increase the speed, not only the memory controller but also the power supply voltage must be changed.

  For example, each DIMM of a DDR SDRAM, a DDR2 SDRAM, and a DDR3 SDRAM has a voltage key or an architecture key to prevent destruction of a semiconductor memory chip mounted on the memory module or a motherboard on which the memory module is mounted. It has a so-called structure and cannot be attached to a memory socket of a computer that is not compatible. For this reason, when the memory module is to be mounted on a non-supported computer, a large-scale modification around the memory socket of the computer is required.

  In addition, the technique described in Japanese Patent Application Laid-Open No. 2001-290696 (that is, Patent Document 1) cannot electrically recognize the specifications of the semiconductor memory chip, and thus cannot rewrite the programmable device. . In addition, the value of the power supply voltage cannot be changed automatically.

  Accordingly, in view of the above problems, an object of the present invention is to provide a memory interface for managing memory access to a memory module, which facilitates replacement of a memory module on which a semiconductor memory chip is mounted, and the memory module and the memory interface. A memory system is provided.

  In order to achieve the above object, in the present invention, configuration data for constructing a memory controller function for managing memory access to the memory module corresponding to the type of the memory module mounted in the memory socket is stored as a program. Expand on possible logic part and build memory controller function in programmable logic part.

  That is, according to the present invention, the memory interface having a memory socket for mounting a memory module on which a semiconductor memory chip is mounted, and managing the memory access to the mounted memory module is provided with a programmable logic. Configuration data is expanded on a programmable logic unit, storage means for storing configuration data for constructing a memory controller function unique to the memory module for managing memory access to the memory module, and the programmable logic unit. Configuration means for executing a configuration process for constructing a memory controller function based on configuration data, and storage means for storing configuration data corresponding to the type of memory module installed in the memory socket. Read, and, and a control means for controlling to perform the configuration process described above using the configuration data to the configuration device.

In addition, the memory system according to the present invention includes:
A memory module in which a semiconductor memory chip is mounted, and a memory module in which identification information unique to the memory module is stored in a PROM mounted on the memory module;
A memory interface for managing memory access to a memory module, a memory socket for mounting the memory module, a programmable logic unit, and a memory controller specific to the memory module for managing memory access to the memory module The configuration data is expanded on the storage means for storing the configuration data for constructing the function and the programmable logic unit, and the memory controller function is constructed based on the configuration data. Read configuration data corresponding to the configuration means and the type of memory module installed in the memory socket from the storage means, and Using Activation data and a memory interface and a control means for controlling to perform the configuration process described above.

  According to the present invention, a memory interface for managing memory access to a memory module, and a memory system including the memory module and the memory interface, which facilitates replacement of a memory module on which a semiconductor memory chip is mounted, are realized. be able to.

  According to the present invention, even if the types of memory modules to be installed in the memory interface are different, the memory controller and the power supply environment corresponding to the memory module are automatically constructed by recognizing the type of the memory module, and the memory module It is equipped with a mechanism for preventing incorrect mounting so that it can be inserted into the memory socket without making a mistake in the front and back, so that the user can easily replace the memory module without having to pay special attention to its specifications. This eliminates the need for extensive modifications around the computer's memory socket. For example, even a user unfamiliar with a computer can easily perform a task of replacing a DDR SDRAM memory module mounted on the computer with a DDR2 SDRAM memory module.

  As an embodiment of the present invention, a case where two memory modules are mounted in a memory slot of a memory interface will be described below. The number of memory modules to be mounted is not limited to the present invention and may be other numbers.

  FIG. 1 is a diagram showing a configuration of a memory system according to a first embodiment of the present invention. Hereinafter, components having the same reference numerals in different drawings mean components having the same functions. The memory system 1 according to the first embodiment of the present invention manages memory access to the memory modules 2-A and 2-B on which the semiconductor memory chips are mounted and the memory modules 2-A and 2-B. A memory interface 3 is provided. The memory interface 3 is configured on a predetermined board (for example, a mother board) in a computer to which the memory modules 2-A and 2B are to be mounted.

  In the memory system 1 of the present invention, the memory modules mounted on the memory interface 3 must be DIMMs having the same specifications. For example, in FIG. 1, if the memory module 2-A is a DDR SDRAM, the memory module 2-B must be a DDR SDRAM, and if the memory module 2-A is a DDR2 SDRAM, the memory module 2-B is also a DDR2 SDRAM. If the memory module 2-A is a DDR3 SDRAM, the memory module 2-B must also be a DDR3 SDRAM. For example, the memory module 2-A mounted on the memory interface 3 cannot be a DDR SDRAM and the memory module 2-B cannot be a DDR2 SDRAM.

  FIG. 2 is a diagram illustrating a memory module in the memory system according to the first embodiment of the invention. 2A illustrates a memory module when a DDR SDRAM is mounted, FIG. 2B illustrates a memory module when a DDR2 SDRAM is mounted, and FIG. 2C illustrates a DDR3. The memory module when SDRAM is mounted is illustrated.

  In the present embodiment, in the memory modules 2-A and 2-B, a plurality of semiconductor memory chips having the same specification of DDR SDRAM, DDR2 SDRAM or DDR3 SDRAM are mounted, and a PROM (reference numeral 21) is provided. Implemented. In this PROM, identification information unique to the memory module in which the PROM is mounted is stored in advance. In addition, the memory modules 2-A and 2-B are provided with a plurality of connection terminals 22 for electrically connecting to a memory socket provided on, for example, a motherboard in the computer. Of these connection terminals 22, at least the terminals necessary for accessing the PROM 21, the power supply terminals for the PROM, and the GND terminals are the same regardless of the specifications of the semiconductor memory chip. is there.

  In addition, the memory modules 2-A and 2-B include a notch portion 23 for preventing erroneous mounting that defines the correct mounting direction of the memory module to the memory socket. The notch 23 in the embodiment of the present invention is not for specifying the specifications of the memory module such as the voltage key and the architecture key in the conventional DIMM, and is used as a memory socket so as not to mistake the front and back of the memory module. It has a role of a so-called erroneous mounting prevention key for enabling mounting. The memory socket on the side where the memory module is mounted is provided with a convex portion that fits into the notch portion 23. According to the present embodiment, the memory socket can be mounted regardless of the type of the memory module. Therefore, as shown in FIGS. 2A to 2C, the notch 23 has the type of the memory module. Even if they are different, they are provided at the same position on the main body of the memory module.

  The memory interface 3 shown in FIG. 1 includes a memory socket (not shown) for mounting the memory modules 2-A and 2-B, a PLD (reference numeral 11) that is a programmable logic unit, and a memory module 2 -ROM (reference numeral 12) which is a storage means for storing configuration data for constructing a memory controller function specific to the memory module that manages memory access to -A and 2-B, and a programmable logic unit On the PLD 11, configuration means 13 for executing configuration processing for expanding configuration data and constructing a memory controller function based on the configuration data, and memory modules 2-A and 2- Con that corresponds to the type of B CPU (reference numeral 14) as control means for reading the migration data from the ROM 12 as storage means and controlling the configuration means 13 to execute configuration processing using the read configuration data .

  In this embodiment, the configuration data stored in the ROM 12 is, for example, configuration data for constructing a memory controller function unique to the DDR SDRAM for managing the memory access to the memory module in which the DDR SDRAM is mounted, DDR2 SDRAM. Configuration data for constructing a memory controller function specific to a DDR2 SDRAM for managing memory access to a memory module on which DDR3 is mounted, and memory access to a memory module on which a DDR3 SDRAM is mounted This is configuration data for constructing a memory controller function unique to the DDR3 SDRAM.

  In addition to storing the configuration data for constructing the memory controller function unique to the memory module, the ROM 12 stores a software program that defines the operation procedure of the CPU 14 as the control means. The operation of the CPU 14 is controlled in accordance with a software program stored in the ROM 15, and this control will be described later with reference to FIG. The RAM indicated by reference numeral 15 is used by the CPU 14 as necessary, and a work area for that purpose is secured.

  The CPU 14 determines the type of the memory modules 2-A and 2-B installed in the memory socket, the identification information unique to the memory module stored in the PROM 21 mounted on the memory module, and an SPI (Serial Peripheral Interface). ) To identify by reading through (reference numeral 16).

  The memory interface 3 of FIG. 1 further includes a programmable power supply 17 that supplies a power supply voltage having a value instructed by the CPU 14 to the memory module mounted in the memory socket. As described above, DDR SDRAM, DDR2 SDRAM, and DDR3 SDRAM have different power supply voltage values. Therefore, the CPU 14 instructs the programmable power supply 17 to output a power supply voltage having a value corresponding to the type of the memory module mounted in the memory socket based on the identification result. The programmable power supply 17 has output switches SW1, SW2, and SW3 that turn on or off the voltage values Vtt, Vref, and Vdd as outputs, and set Vtt, Vref, and Vdd according to instructions from the CPU 14, respectively. And output. The programmable power supply may have any configuration as long as it can output a set voltage, such as a linear power supply or a switching power supply. As a method for setting the output voltage of the linear power supply or the switching power supply, a method of dividing the output voltage with a resistor and comparing it with a reference voltage is generally used. Therefore, the output voltage can be freely changed by changing the ratio of the resistors that divide the output voltage. The output voltage can be controlled from the CPU 14 by using a digital potentiometer or the like for this resistor.

  The memory interface 3 includes a fixed power source 18 in addition to the programmable power source 17. The fixed power supply 18 supplies a constant voltage to necessary elements in the memory interface 3.

  Further, the CPU 14 performs control to read configuration data corresponding to the type of the memory module mounted in the memory socket from the ROM 12 based on the identification result, and executes configuration processing using the read configuration data. The configuration means 13 is instructed.

  A PLD (Programmable Logic Device) indicated by reference numeral 11 is a device that can be configured many times. The configuration means 13 expands the configuration data read from the ROM 12 on the PLD 11 in accordance with an instruction from the CPU 14 and constructs a memory controller function based on the configuration data. As a result, the PLD 11 operates as a memory controller corresponding to the type of the memory module attached to the memory socket of the memory interface 3.

  FIG. 3 is a flowchart showing an operation flow of the control means in the memory system according to the first embodiment of the present invention. As described above, the ROM 12 in FIG. 1 stores a software program that defines the operation procedure of the CPU 14 as the control means. The operation flow of this software program is shown as a flowchart in FIG. The operation of the CPU 14, which is the control means in the memory system according to the first embodiment of the present invention, will be described below by taking as an example the case where the memory modules 2-A and 2-B are DDR2 SDRAMs.

  When the power of the memory interface 3 is turned on, the fixed power source 18 is mounted on the PLD 11, the ROM 12, the CPU 14, the RAM 15 and the SPI 16, and the memory modules 2 -A and 2 -B installed in the memory socket of the memory interface 3. A voltage is supplied to each PROM 21, and each of these components is activated. At this time, the voltage output from the programmable power supply 17 is not set, and the output switches SW1, SW2, and SW3 in the programmable power supply 17 are off. Therefore, no voltage is applied to the PLD 11 and the address / control data lines of the memory modules 2-A and 2-B.

  When the voltage is supplied to the CPU 14, the CPU 14 reads out and executes a software program that defines the operation procedure of the CPU 14 from the ROM 12. First, in step S101, the CPU 14 identifies the types of the memory modules 2-A and 2-B installed in the memory socket, and identification information unique to the memory module stored in the PROM 21 mounted on the memory module. It is identified by reading through the SPI 16. In the example of FIG. 3, based on the identification information stored in the PROM mounted on the installed memory modules 2-A and 2-B, the memory modules 2-A and 2-B are DDR2 SDRAMs. recognize.

  Next, in step S102, the CPU 14 reads configuration data dedicated to the DDR2 SDRAM from the ROM 12 based on the identification result in step S101, and expands the configuration data on the PLD 11 to the configuration unit 13 based on this. To instruct the memory controller function. The configuration means 13 expands the configuration data on the PLD 11 in accordance with an instruction from the CPU 14 and constructs a memory controller function based on the configuration data. As a result, a memory controller function corresponding to the DDR2 SDRAM is realized on the PLD 11.

  Next, in step S103, the CPU 14 sets the programmable power supply 17 so as to output a power supply voltage having a value corresponding to the type of the memory module mounted in the memory socket. In the example of FIG. 3, since the installed memory modules 2-A and 2-B are recognized as DDR2 SDRAM, Vtt is 0.9 volts, Vref is 0.9 volts, and Vdd is 1.. Set each to 8 volts. In this example, the memory modules 2-A and 2-B are described as being DDR2 SDRAMs. However, for example, in the case of DDR SDRAMs and DDR3 SDRAMs, voltages may be set as shown in Table 1.

  Next, in step S104, the CPU 14 checks the status of the programmable power supply 17 as to whether the voltages Vtt, Vref, and Vdd of the programmable power supply 17 are set correctly, and when it is confirmed that the voltage is set correctly, the programmable power supply output switch SW1. , SW2 and SW3 are turned on.

  Next, in step S105, the CPU 14 initializes the memory controller built on the PLD 11 and the memory chips mounted on the memory modules 2-A and 2-B based on the configuration data read from the ROM 12.

  Through the above processes, the PLD 11 can operate as a memory controller dedicated to the DDR2 SDRAM. As a result, memory access to the memory modules 2-A and 2-B can be managed through the memory interface 3. Further, after the memory controller function is constructed on the PLD in step S102, power is supplied to the memory module in steps S103 and S104, so that the memory module and the memory interface are not destroyed.

  FIG. 4 is a diagram showing the configuration of a memory system according to the second embodiment of the present invention. In the first embodiment described above, the CPU, RAM, configuration means, and SPI are configured as individual devices. In the second embodiment of the present invention, these components are constructed on the PLD. Is. That is, on the PLD 11 ′, configuration means 13 ′, CPU 14 ′, RAM 15 ′, and SPI 16 ′ corresponding to the functions of the configuration means 13, CPU 14, RAM 15, and SPI 16 in the example of FIG. 1 are constructed. Also in the second embodiment, as in the first embodiment, a memory controller corresponding to the type of the memory modules 2-A and 2-B mounted on the memory interface 3 is built in the PLD 11 ′. 4, a memory controller constructed on the PLD 11 ′ is indicated by reference numeral 20. In the second embodiment, a programmable power supply interface 19 is constructed on the PLD 11 ′ as an interface to the programmable power supply 17. The programmable power supply interface 19 is configured on the PLD 11 'before step S101 of FIG. 3 is executed. The other circuit components are the same as those shown in FIG. 1, and therefore, the same circuit components are denoted by the same reference numerals, and detailed description of the circuit components is omitted. . According to the second embodiment of the present invention, it is possible to realize a smaller memory interface than the memory interface in the first embodiment.

  The present invention can be applied to a memory interface and a memory system for managing memory access to a memory module that employs an interface specification called SSTL (Stub Series Terminated Logic).

  According to the first and second embodiments of the present invention, even if the type of the memory module to be mounted on the memory interface is different, the type of the memory module is recognized and the memory controller and the power supply environment corresponding to the memory module are automatically set. Built-in, and has a mechanism for preventing erroneous insertion of the memory module so that the memory module can be inserted into the memory socket without making a mistake in its front and back. They can be easily replaced without the need for care, and no major modifications around the computer's memory socket are required. For example, even a user unfamiliar with a computer can easily perform a task of replacing a DDR SDRAM memory module mounted on the computer with a DDR2 SDRAM memory module. Further, according to the second embodiment of the present invention, a memory interface smaller than the memory interface in the first embodiment can be realized, so that the memory system according to the present invention can be used as a mobile terminal or the like. It is easy to incorporate into a small terminal.

It is a figure which shows the structure of the memory system by 1st Example of this invention. 1 is a diagram illustrating a memory module in a memory system according to a first embodiment of the invention. FIG. 3 is a flowchart showing an operation flow of the memory system according to the first embodiment of the present invention. It is a figure which shows the structure of the memory system by the 2nd Example of this invention. It is a circuit diagram which shows the basic composition of SSTL (Stub Series Terminated Logic).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Memory system 2-A, 2-B Memory module 3 Memory interface 11 Programmable logic part 12 Memory | storage means 13, 13 'Configuration means 14, 14' Control means 15, 15 'RAM
16, 16 'SPI
17 Programmable Power Supply 18 Fixed Power Supply 19 Programmable Power Supply Interface 20 Memory Controller 21 PROM
22 Connection terminal 23 Notch

Claims (10)

A memory interface having a memory socket for mounting a memory module on which a semiconductor memory chip is mounted, and managing memory access to the mounted memory module,
A programmable logic part;
Storage means for storing configuration data for constructing a memory controller function unique to the memory module for managing memory access to the memory module;
Configuration means for expanding the configuration data corresponding to the type of the memory module mounted in the memory socket on the programmable logic unit and constructing a memory controller function based on the configuration data;
A memory interface comprising: A memory interface having a memory socket for mounting a memory module on which a semiconductor memory chip is mounted, and managing memory access to the mounted memory module,
A programmable logic part;
Storage means for storing configuration data for constructing a memory controller function unique to the memory module for managing memory access to the memory module;
Configuration means for executing configuration processing for expanding the configuration data on the programmable logic unit and constructing a memory controller function based on the configuration data;
Reading the configuration data corresponding to the type of the memory module installed in the memory socket from the storage unit, and executing the configuration process on the configuration unit using the configuration data Control means for controlling;
A memory interface comprising:   The control means identifies the type of the memory module mounted in the memory socket by reading identification information unique to the memory module stored in a PROM mounted on the memory module. Memory interface as described in A power supply for supplying a power supply voltage of a value instructed by the control means to the memory module mounted in the memory socket;
The memory interface according to claim 2, wherein the control unit instructs the power supply to output a power supply voltage having a value corresponding to a type of the memory module mounted in the memory socket.   The memory interface according to claim 2, further comprising a notch portion for preventing erroneous mounting that defines a correct mounting direction of the memory module to the memory socket. A memory module in which a semiconductor memory chip is mounted, and a memory module in which identification information unique to the memory module is stored in a PROM mounted on the memory module;
A memory interface for managing memory access to the memory module, a memory socket for mounting the memory module, a programmable logic unit, and a memory specific to the memory module for managing memory access to the memory module The configuration data corresponding to the type of the memory module mounted in the memory socket is expanded on the programmable logic unit and storage means for storing configuration data for constructing the controller function, and the configuration data Configuration means for executing configuration processing for constructing a memory controller function based on the configuration data, and a memory interface,
A memory system comprising: A memory module in which a semiconductor memory chip is mounted, and a memory module in which identification information unique to the memory module is stored in a PROM mounted on the memory module;
A memory interface for managing memory access to the memory module, a memory socket for mounting the memory module, a programmable logic unit, and a memory specific to the memory module for managing memory access to the memory module Configuration processing for expanding the configuration data on the programmable logic unit and building the memory controller function based on the configuration data on the storage means for storing the configuration data for building the controller function A configuration means for executing the configuration, and reading out the configuration data corresponding to the type of the memory module mounted in the memory socket from the storage means, and the configuration A memory interface and a control means for controlling to perform the configuration process of the using the configuration data to the device,
A memory system comprising:   8. The control means identifies the type of a memory module mounted in the memory socket by reading identification information unique to the memory module stored in a PROM mounted on the memory module. The memory system described in. The memory interface further comprises a power supply for supplying a power supply voltage of a value instructed by the control means to a memory module mounted in the memory socket,
The memory system according to claim 7, wherein the control unit instructs the power supply to output a power supply voltage having a value corresponding to a type of the memory module mounted in the memory socket.   8. The memory system according to claim 7, wherein the memory socket and the memory module of the memory interface each have a notch for preventing erroneous mounting that defines a correct mounting direction of the memory module to the memory socket. 9.

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