JP2008293094A - Pattern forming device and pattern forming method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily insert an optimum correction pattern to a semiconductor. <P>SOLUTION: An arithmetic processing part 102 generates a correction gate polysilicon layer from the positional relation between a diffusion layer and an original gate polysilicon layer which constitute a transistor, based on original data for transistor configuration input from an input part 101 and a design reference stored in a storage part 103, and an output part 104 outputs the generated correction gate polysilicon layer, together with the original data. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a lithography technique for manufacturing a semiconductor integrated circuit for forming a fine pattern on a substrate to be exposed, and more particularly to a pattern forming apparatus and a pattern forming method for forming a mask pattern with controlled shape control during etching.

  In conventional semiconductor products, even when there is a variation error in pattern formation, the variation error does not affect the transistor operation. However, in recent years, with the progress of miniaturization of patterns inside semiconductors, there is a concern that conventional variation errors may affect the operation of transistors. Therefore, there is a need for a measure that does not cause a variation error.

  The gate length of the transistor is most affected by the pattern formation. Changing the gate length makes it impossible to obtain originally intended transistor operating characteristics. One of the causes of the variation error in the gate length is that the etching amount due to the density of the gate poly changes. This etching amount is not regarded as a problem when the ratio to the gate length is several percent or less, but becomes a problem when miniaturization progresses to reach several tens of percent. As a supplement, etching is a physical phenomenon and one of the problems is that there is no connection with miniaturization of the optical system.

  Therefore, it is required to make the etching amount uniform regardless of the pattern.

  FIG. 11 is a diagram showing a configuration example of a conventional transistor configuration in which three transistors are arranged.

  In a plurality of gates arranged in a row as in the transistor configuration shown in FIG. 11, coarse / dense due to the difference in the surrounding gate arrangement occurs between the row-like end arrangement and the center arrangement. In such a case, a difference in performance occurs between the end transistors 1001 and 1003 and the central transistor 1002, which is different from the required circuit operation. In order to correct this, a method of inserting a correction pattern has been considered (see, for example, Patent Document 1).

  FIG. 12 is a diagram showing an example of a transistor configuration in which a correction pattern is inserted in parallel with a channel formation gate poly.

  As shown in FIG. 12, the correction pattern is generally inserted in parallel with the gate poly layer that forms the channel of the transistor.

  FIG. 13 and FIG. 14 are diagrams showing an example of a transistor configuration in which a correction pattern is inserted in parallel with a gate formation gate poly so as not to share a transistor diffusion layer.

  As shown in FIGS. 13 and 14, the correction pattern can be inserted in parallel with the channel formation gate poly so as not to share the diffusion layer of the transistor.

  As another method, it is conceivable that a transistor whose etching amount greatly affects the gate length is corrected in size by the influence. However, if the surrounding transistors are similarly corrected after the correction, the influence is newly added. If the influence is added again, the correction is repeated semipermanently and the final plan is not determined.

Further, when the 3D structure is simulated from the layout pattern inside the semiconductor and the resistance / capacitance is extracted, if the calculation is performed only from the data, it may be estimated to be larger by the correction amount. In that case, there is a problem that it cannot be calculated accurately.
JP 2004-004941 A

  In recent years, semiconductors such as LSIs have millions of transistors, and all transistors are formed in various configurations. Therefore, it is not sufficient to simply insert a correction pattern as described above. In other words, there are a variety of conditions for locations to be arranged, and there is a problem that it is necessary to manually understand the configuration of all conditions and insert them. Even if it is designed manually, if the correction pattern specifications are changed, it is necessary to recreate all the correction patterns from the beginning. There is a problem of becoming.

  The present invention has been made in view of the problems of the conventional techniques as described above, and provides a pattern forming apparatus and a pattern forming method capable of easily inserting an optimal correction pattern into a semiconductor. For the purpose.

In order to achieve the above object, the present invention provides:
A pattern forming apparatus for generating a correction gate poly layer to form a semiconductor layout pattern composed of transistors,
An outer peripheral edge of a diffusion layer constituting the transistor, which is parallel to the channel width direction of the transistor, is extracted, and a first reference pattern generation pattern for correction is generated in parallel with the extracted outer peripheral edge. Among the reference patterns for generating the correction pattern, the one having a predetermined design standard for the distance from the diffusion layer or the original gate poly layer is used as the correction gate poly layer, and the first correction pattern is used. Among the standard patterns for pattern generation, the second standard pattern generation pattern for correction, which is widened by an interval based on the design standard for the gate poly layer from the overlapped part, is overlapped with the original pattern for the gate poly layer. A pattern obtained by removing the reference pattern for generating the second correction pattern from the reference pattern for generating the first correction pattern is used as a correction gate poly layer, and the first correction is performed. Of the first pattern generation pattern and the gate poly layer, the first pattern generation reference pattern and the gate poly layer corresponding to the pattern generation reference pattern of the first correction pattern generation pattern that does not satisfy a predetermined interval. A replenishment pattern is generated between portions that do not satisfy the interval, and a third correction pattern generation reference pattern is generated from the replenishment pattern by an interval based on a preset design standard in the gate poly layer. A pattern obtained by removing the reference pattern for generating the third correction pattern from the reference pattern for generating the first correction pattern is used as a correction gate poly layer, and is set in advance from the correction gate poly layer. A fourth correction pattern generation reference form widened by an interval based on the design standard in the original gate poly layer is generated, and the first correction pattern generation A pattern obtained by removing the reference pattern for generating the fourth correction pattern from the quasi-form and the original gate poly layer as a first additional correction gate poly layer, and the first additional correction gate poly layer; A pattern forming apparatus in which the replenishment pattern is integrated to form a second additional correction gate poly layer.

  Further, the size or shape of the correction gate poly layer or the first or second additional correction gate poly layer is corrected based on the design criteria for a portion where the size or shape does not satisfy the design criteria. It is characterized by.

  Further, the present invention is characterized in that it has an input section that allows the design criteria to be input from the outside.

A pattern forming method for generating a correction gate poly layer to form a semiconductor layout pattern composed of transistors,
A process of extracting the outer peripheral edge of the diffusion layer constituting the transistor, which is parallel to the channel width direction of the transistor;
Processing for generating a reference pattern for generating a first correction pattern in parallel with the extracted outer periphery;
Among the first correction pattern generation reference forms, a process that secures a preset design standard with respect to the diffusion layer or the gate poly layer is used as a correction gate poly layer;
Of the reference pattern generation pattern for the first correction, the second correction extended from the overlapping part by an interval based on the design standard in the gate poly layer with respect to the reference pattern overlapping the original gate poly layer. Processing to generate a standard pattern generation pattern for
A process in which a pattern obtained by excluding the second correction pattern generation reference form from the first correction pattern generation reference form is used as a correction gate poly layer;
Among the first correction pattern generation reference forms, the first correction pattern generation reference form for the first correction pattern generation reference form that does not satisfy a predetermined interval. A process of generating a replenishment pattern between portions that do not satisfy the gap with the gate poly layer;
A process of generating a reference pattern for generating a third pattern for correction, which is expanded by an interval based on a design standard in a gate poly layer set in advance from a supplementary pattern in the previous period;
A process in which a pattern obtained by removing the reference pattern for generating the third correction pattern from the reference pattern for generating the first correction pattern is used as a correction gate poly layer;
A process of generating a reference pattern for generating a fourth correction pattern that is widened by an interval based on a preset design criterion in the original gate poly layer from the correction gate poly layer;
A process in which a pattern obtained by removing the fourth correction pattern generation reference form and the original gate poly layer from the first correction pattern generation reference form is used as a first additional correction gate poly layer; ,
A process of integrating the first additional correction gate poly layer and the replenishment pattern into a second additional correction gate poly layer.

  In addition, a process for correcting the size or shape of the correction gate poly layer or the first or second additional correction gate poly layer that does not satisfy the design standard based on the design standard It is characterized by having.

  In the present invention configured as described above, the outer peripheral edge of the diffusion layer constituting the transistor, which is parallel to the channel width direction of the transistor constituting the semiconductor, is extracted, and the first outer periphery is parallel to the extracted outer peripheral edge. A reference pattern generation pattern for correction is generated, and among the first correction pattern generation reference patterns, a design standard in which a distance from the diffusion layer or the original gate poly layer is set in advance is secured. The gate poly layer is a correction gate poly layer, and the reference pattern generation pattern for the first correction, which overlaps the original gate poly layer, is based on the design standard of the gate poly layer from the overlapping portion. A reference pattern for generating the second correction pattern generated by the interval is generated, and the reference pattern for generating the second correction pattern is removed from the reference pattern for generating the second correction pattern. The first pattern is a correction gate poly layer, and among the first correction pattern generation reference shapes, the first gate poly layer does not satisfy a predetermined interval with respect to the original one. A replenishment pattern is generated between the reference pattern generation pattern for correction and a portion of the gate poly layer that does not satisfy the interval, and an interval based on a design standard in the gate poly layer set in advance from the replenishment pattern A reference pattern for generating a third corrected pattern is generated, and a pattern obtained by removing the reference pattern for generating the third correction pattern from the reference pattern for generating the first correction pattern is corrected. Generation of a fourth correction pattern which is a gate poly layer and is expanded from the correction gate poly layer by an interval based on a design standard of the original gate poly layer set in advance. A reference form is generated, and a pattern obtained by removing the fourth correction pattern generation reference form and the original gate poly layer from the first correction pattern generation reference form is the first additional correction pattern. The first additional correction gate poly layer and the supplementary pattern are integrated to form a second additional correction gate poly layer.

  Thereby, the optimal correction pattern can be easily inserted into the semiconductor.

  As described above, in the present invention, the outer peripheral edge of the diffusion layer constituting the transistor, which is parallel to the channel width direction of the transistor constituting the semiconductor, is extracted, and the first correction is performed in parallel with the extracted outer peripheral edge. The reference pattern generation pattern is generated, and among the first correction pattern generation reference forms, a design standard having a predetermined interval between the diffusion layer and the original gate poly layer is secured. As the correction gate poly layer, the reference pattern generation pattern for the first correction, which overlaps the original gate poly layer, is expanded from the overlapping portion by an interval based on the design standard of the gate poly layer. The second correction pattern generation reference form is generated, and the second correction pattern generation reference form is removed from the first correction pattern generation reference form. The first correction is applied to the reference pattern generation pattern for the first correction that does not satisfy a predetermined interval among the reference patterns for generating the first correction pattern, the turn being a correction gate poly layer. A replenishment pattern is generated between a portion of the reference pattern generation pattern and the gate poly layer that does not satisfy the interval, and the replenishment pattern is expanded by an interval based on a preset design criterion in the gate poly layer. A third correction pattern generation reference form is generated, and a pattern obtained by removing the third correction pattern generation reference form from the first correction pattern generation reference form is corrected as a gate poly layer. The fourth correction pattern generation basis expanded from the correction gate poly layer by an interval based on the design criteria of the original gate poly layer set in advance. A pattern obtained by removing the reference pattern for generating the fourth correction pattern and the original gate poly layer from the reference pattern for generating the first correction pattern, and generating the first correction pattern. Since the first additional correction gate poly layer and the replenishment pattern are integrated into a second additional correction gate poly layer, an optimum correction pattern can be easily inserted into the semiconductor. can do.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing an embodiment of a pattern forming apparatus 100 of the present invention.

  As shown in FIG. 1, this embodiment includes an input unit 101, an arithmetic processing unit 102, a storage unit 103, and an output unit 104.

  The input unit 101 is used by a user who uses the pattern forming apparatus 100 to input information from the outside.

  The arithmetic processing unit 102 performs an operation based on information input from the input unit 101 and a processing program stored in advance in the storage unit 103, and outputs the operation result to the output unit 104.

  The storage unit 103 stores a processing program for forming a semiconductor pattern in advance.

  The output unit 104 outputs the result output from the arithmetic processing unit 102 to the outside (semiconductor). That is, semiconductor pattern information is output.

  FIG. 2 is a diagram illustrating a configuration example of the processing program stored in the storage unit 103 illustrated in FIG.

  As shown in FIG. 2, the processing program stored in the storage unit 103 shown in FIG. 1 includes a file name, a generation condition or size correction condition, and an arithmetic processing part. The file name or the like may include unique identification information that can identify the processing program in addition to the file name. The generation condition or the size correction condition is easily changed by inputting information from the input unit 101 and changing the description part. The arithmetic processing part is a part that performs arithmetic processing based on the generation condition or the size correction condition.

  A semiconductor pattern forming method using the pattern forming apparatus 100 shown in FIG. 1 will be described below.

  FIG. 3 is a flowchart for explaining a pattern forming method of a transistor configuration using the pattern forming apparatus 100 shown in FIG.

  First, when original data of a target transistor configuration is input from the input unit 101 (step S1), the input original data is subjected to graphic calculation processing by the calculation processing unit 102 (step S2). A pattern is generated (step S3).

  FIG. 4 is a plan view of a transistor configuration input to the input unit 101.

  As shown in FIG. 4, the target transistor configuration includes a diffusion layer 401 constituting the transistor, a gate poly layer 402 for channel formation, and a gate poly layer 403 for other than channel formation.

  A correction pattern is formed in the transistor configuration shown in FIG. 4 by the processing of step S2 and step S3. The process will be described below.

  FIG. 5 is a diagram showing a first stage of processing for forming a correction pattern in the transistor configuration shown in FIG.

  As shown in FIG. 5, as the first stage process, the outer peripheral edge 501 of the diffusion layer 401 parallel to the channel width direction of the transistor shown in FIG. 4 is extracted, and the first peripheral process 501 is parallel to the extracted outer peripheral edge 501. A reference pattern 502 for generating a correction pattern is generated.

  FIG. 6 is a diagram showing a second stage of processing for forming a correction pattern in the transistor configuration shown in FIG.

  As shown in FIG. 6, as the second stage process, the distance from the diffusion layer 401 or the gate poly layer 403 other than the channel formation in the reference pattern 502 for generating the first correction pattern generated in FIG. A gate poly layer 601 for correction is provided with a predetermined design standard set in advance.

  FIG. 7 is a diagram showing a third stage of processing for forming a correction pattern in the transistor configuration shown in FIG.

  As shown in FIG. 7, when the reference pattern 502 for generating the first correction pattern overlaps with the original gate poly layer (here, the gate poly layer 403 other than the channel formation) as the third stage of processing, the overlap occurs. A reference pattern 701 for generating a second correction pattern, which is widened by an interval in accordance with a predetermined design standard in the gate poly layer from a predetermined portion, is generated. A pattern obtained by removing the second correction pattern generation reference form 701 from the first correction pattern generation reference form 502 is defined as a correction gate poly layer 702.

  If the distance between the reference pattern 502 for generating the first correction pattern and the original gate poly layer (here, the gate poly layer 403 other than the channel formation) does not satisfy a predetermined distance, the first correction pattern A supplementary pattern is generated between the pattern generation reference form 502 and the portion of the gate poly layer 403 other than the channel formation that does not satisfy the interval. Then, a reference pattern 703 for generating a third correction pattern, which is widened by an interval in accordance with a preset design standard in the gate poly layer, is generated from the generated supplementary pattern. After the third correction pattern generation reference form 703 is generated, a pattern obtained by removing the third correction pattern generation reference form 703 from the first correction pattern generation reference form 502 is corrected. 704.

  FIG. 8 is a diagram showing a fourth stage of processing for forming a correction pattern in the transistor configuration shown in FIG.

  As shown in FIG. 8, as a fourth stage process, the corrected gate poly layers 601, 702, and 703 generated in the steps so far are expanded by an interval in accordance with a predetermined design standard in the gate poly layer. A reference pattern 801 for generating a correction pattern 4 is generated. A pattern obtained by removing the first correction pattern generation reference form 502 from the fourth correction pattern generation reference form 801 and the gate poly layer 403 other than the channel formation is used as the first additional correction gate poly layer. 802. Further, the portion of the first additional correction gate poly layer 802, the reference pattern 502 for generating the first correction pattern generated in the third stage, and the gate poly layer 403 other than the channel formation do not satisfy the interval. The replenishment pattern between them is integrated to form a second additional correction gate poly layer 803.

  Where the size or shape of the correction gate poly layer 601, 702, 703 or the first additional correction gate poly layer 802 or the second additional correction gate poly layer 803 thus formed does not satisfy the design criteria In step S4, the shape is corrected by the graphic correction process.

  FIG. 9 shows a figure where the size and shape of the correction gate poly layers 601, 702 and 703, the first additional correction gate poly layer 802 and the second additional correction gate poly layer 803 do not satisfy the design criteria. It is a top view of the transistor structure by which the shape was corrected by the correction process.

  As shown in FIG. 9, among the correction gate poly layers 601, 702, and 703, the first additional correction gate poly layer 802, and the second additional correction gate poly layer 803, a process whose size and shape are design criteria. The first additional correction gate poly layer 802 and the second additional correction gate poly layer 803 that do not satisfy the program generation condition or the size correction condition are corrected. This design criterion (generation condition or size correction condition) is automatically input by inputting it beforehand from the input unit 101 shown in FIG. In addition, since desired correction is performed simply by inputting various design criteria from the input unit 101, flexible correction can be performed.

  FIG. 10 is a diagram showing a corrected gate poly layer when the shape of the gate poly layer 403 other than the channel formation is changed.

  As shown in FIG. 10, even when the shape of the gate poly layer 403 other than the channel formation shown in FIGS. 4 to 9 changes, additional correction gate poly is formed in accordance with the changed gate poly layer other than the channel formation. A figure correction process is performed at a location where the size and shape of the layer do not satisfy the design standard, and the shape is corrected.

  The pattern corrected in this way is output from the output unit 104 together with the original data (step S5).

  Thus, it is not necessary to insert a correction pattern at the time of design, and a correction pattern can be generated any number of times by changing the generation condition or the pattern correction condition. Therefore, the optimum solution can be found in the stage prior to product creation by trying etching simulation each time.

  Furthermore, since the data is different from the original data, it is easy to determine the correction location, and it is easy to recognize it as a check required location in the etching simulation.

It is a figure which shows one Embodiment of the pattern formation apparatus of this invention. It is a figure which shows the example of 1 structure of the processing program memorize | stored in the memory | storage part shown in FIG. 2 is a flowchart for explaining a pattern forming method of a transistor configuration using the pattern forming apparatus shown in FIG. It is a top view of the transistor structure input into an input part. FIG. 5 is a diagram illustrating a state of a first stage process of forming a correction pattern in the transistor configuration illustrated in FIG. 4. FIG. 5 is a diagram illustrating a second stage of processing for forming a correction pattern in the transistor configuration illustrated in FIG. 4. FIG. 5 is a diagram illustrating a third stage of processing for forming a correction pattern in the transistor configuration illustrated in FIG. 4. FIG. 5 is a diagram illustrating a process of a fourth stage of correction pattern formation in the transistor configuration illustrated in FIG. 4. It is a top view of the transistor structure by which the shape was corrected by the figure correction process in the location where the size and shape of the correction gate poly layer and the additional correction gate poly layer do not satisfy the design standard. It is a figure which shows the correction | amendment gate poly layer when the shape of gate poly layers other than channel formation changes. It is a figure which shows one structural example of the conventional transistor structure in which three transistors were arranged. It is a figure which shows an example of the transistor structure by which the correction pattern was inserted in parallel with the gate poly of channel formation. It is a figure which shows an example of the transistor structure by which the correction pattern was inserted in parallel with the gate poly of channel formation so that the diffusion layer of a transistor might not be shared. It is a figure which shows an example of the transistor structure by which the correction pattern was inserted in parallel with the gate poly of channel formation so that the diffusion layer of a transistor might not be shared.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Pattern formation apparatus 101 Input part 102 Arithmetic processing part 103 Memory | storage part 104 Output part 401 Diffusion layer 402 Gate poly layer of channel formation 403 Gate poly layer other than channel formation 501 Outer periphery 502 Reference form 601 of pattern generation for the first correction 702, 704 correction gate poly layer 701 second correction pattern generation reference form 703 third correction pattern generation reference form 801 fourth correction pattern generation reference form 802 first additional correction The gate poly layer 803 of the second additional correction gate poly layer

Claims (5)

A pattern forming apparatus for generating a correction gate poly layer to form a semiconductor layout pattern composed of transistors,
An outer peripheral edge of a diffusion layer constituting the transistor, which is parallel to the channel width direction of the transistor, is extracted, and a first reference pattern generation pattern for correction is generated in parallel with the extracted outer peripheral edge. Among the reference patterns for generating the correction pattern, the one having a predetermined design standard for the distance from the diffusion layer or the original gate poly layer is used as the correction gate poly layer, and the first correction pattern is used. Among the standard patterns for pattern generation, the second standard pattern generation pattern for correction, which is widened by an interval based on the design standard for the gate poly layer from the overlapped part, is overlapped with the original pattern for the gate poly layer. A pattern obtained by removing the reference pattern for generating the second correction pattern from the reference pattern for generating the first correction pattern is used as a correction gate poly layer, and the first correction is performed. Of the first pattern generation pattern and the gate poly layer, the first pattern generation reference pattern and the gate poly layer corresponding to the pattern generation reference pattern of the first correction pattern generation pattern that does not satisfy a predetermined interval. A replenishment pattern is generated between portions that do not satisfy the interval, and a third correction pattern generation reference pattern is generated from the replenishment pattern by an interval based on a preset design standard in the gate poly layer. A pattern obtained by removing the reference pattern for generating the third correction pattern from the reference pattern for generating the first correction pattern is used as a correction gate poly layer, and is set in advance from the correction gate poly layer. A fourth correction pattern generation reference form widened by an interval based on the design standard in the original gate poly layer is generated, and the first correction pattern generation A pattern obtained by removing the reference pattern for generating the fourth correction pattern from the quasi-form and the original gate poly layer as a first additional correction gate poly layer, and the first additional correction gate poly layer; A pattern forming apparatus in which the replenishment pattern is integrated to form a second additional correction gate poly layer. The pattern forming apparatus according to claim 1,
The size or shape of the correction gate poly layer or the first or second additional correction gate poly layer is corrected based on the design criteria for a portion where the size or shape does not satisfy the design criteria. A pattern forming apparatus. The pattern forming apparatus according to claim 2,
A pattern forming apparatus, comprising: an input unit that allows the design criteria to be input from the outside. A pattern formation method for generating a correction gate poly layer to form a semiconductor layout pattern composed of transistors,
A process of extracting the outer peripheral edge of the diffusion layer constituting the transistor, which is parallel to the channel width direction of the transistor;
Processing for generating a reference pattern for generating a first correction pattern in parallel with the extracted outer periphery;
Among the first correction pattern generation reference forms, a process that secures a preset design standard with respect to the diffusion layer or the gate poly layer is used as a correction gate poly layer;
Of the reference pattern generation pattern for the first correction, the second correction extended from the overlapping part by an interval based on the design standard in the gate poly layer with respect to the reference pattern overlapping the original gate poly layer. Processing to generate a standard pattern generation pattern for
A process in which a pattern obtained by excluding the second correction pattern generation reference form from the first correction pattern generation reference form is used as a correction gate poly layer;
Among the first correction pattern generation reference forms, the first correction pattern generation reference form for the first correction pattern generation reference form that does not satisfy a predetermined interval. A process of generating a replenishment pattern between portions that do not satisfy the gap with the gate poly layer;
A process of generating a reference pattern for generating a third pattern for correction, which is expanded by an interval based on a design standard in a gate poly layer set in advance from a supplementary pattern in the previous period;
A process in which a pattern obtained by removing the reference pattern for generating the third correction pattern from the reference pattern for generating the first correction pattern is used as a correction gate poly layer;
A process of generating a reference pattern for generating a fourth correction pattern that is widened by an interval based on a preset design criterion in the original gate poly layer from the correction gate poly layer;
A process in which a pattern obtained by removing the fourth correction pattern generation reference form and the original gate poly layer from the first correction pattern generation reference form is used as a first additional correction gate poly layer; ,
A pattern forming method comprising: processing for integrating the first additional correction gate poly layer and the replenishment pattern into a second additional correction gate poly layer. In the pattern formation method of Claim 4,
A process of correcting the size or shape of the correction gate poly layer or the first or second additional correction gate poly layer that does not satisfy the design criteria on the basis of the design criteria. The pattern formation method characterized by the above-mentioned.

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