JP2008288286A - Semiconductor testing device - Google Patents

Semiconductor testing device Download PDF

Info

Publication number
JP2008288286A
JP2008288286A JP2007129876A JP2007129876A JP2008288286A JP 2008288286 A JP2008288286 A JP 2008288286A JP 2007129876 A JP2007129876 A JP 2007129876A JP 2007129876 A JP2007129876 A JP 2007129876A JP 2008288286 A JP2008288286 A JP 2008288286A
Authority
JP
Japan
Prior art keywords
probe card
electrical connection
probe
region
suction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007129876A
Other languages
Japanese (ja)
Other versions
JP5343278B2 (en
Inventor
Katsuhiko Sato
佐藤勝彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Electronic Materials Corp
Original Assignee
Japan Electronic Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Electronic Materials Corp filed Critical Japan Electronic Materials Corp
Priority to JP2007129876A priority Critical patent/JP5343278B2/en
Publication of JP2008288286A publication Critical patent/JP2008288286A/en
Application granted granted Critical
Publication of JP5343278B2 publication Critical patent/JP5343278B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor testing device dividing the function of a probe card into a common element and an exclusive element, simplifying the exclusive element and using the probe card having a simple configuration by analyzing the function of the probe card because there is the point at issue of the requirement of time for a manufacture since structures at every one substrate are formed in precise ones for improving a performance in the conventional probe cards. <P>SOLUTION: The semiconductor testing device is configured so as to have the probe card provided with a suction region and an electrical connecting region on one surface and fitting a probe corresponding to a substance to be inspected on the other surface. The semiconductor testing device is configured so as to further have a suction means sucking the probe card to the suction region and fixing the probe card and an electrical connecting means being connected to the electrical connecting region and transmitting and receiving an electric signal. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、プローブカードを用いた半導体試験装置に関する。   The present invention relates to a semiconductor test apparatus using a probe card.

近年の半導体試験装置に用いられているプローブカードには、基板と補強板が標準仕様として装備されている。   Probe cards used in recent semiconductor test equipment are equipped with a substrate and a reinforcing plate as standard specifications.

そして、アドバンストプローブカードにおいては、上述の基板と補強板を残しながら、さらに、プローブの実装、信号のファインアウト等のための基板を備える構造となっている。   The advanced probe card has a structure further including a substrate for mounting a probe and fine-out a signal while leaving the above-described substrate and a reinforcing plate.

このような構造のアドバンストプローブカードは、複数の基板から構成され、これらの基板は一部同じ機能を有しているので、その結果、プローブカードは非常に冗長で複雑な構造となっている。 The advanced probe card having such a structure is composed of a plurality of substrates, and some of these substrates have the same function. As a result, the probe card has a very redundant and complicated structure.

また、これらの基板はそれぞれが精密な構造を必要としており、そのために各基板の製作に手間が掛かり、製造コストが高くなる原因となっている。   In addition, each of these substrates requires a precise structure, which makes it troublesome to manufacture each substrate and causes a high manufacturing cost.

このように、必要な性能を満たすために次々と基板を増やしていくような構造のプローブカードでは、製造工程、製造コストでの無駄が生じ、またプローブカードが複雑でサイズが大きくなることにより、このようなプローブカードを用いる半導体検査装置全体も大きくなるという問題が生じている。   In this way, in a probe card with a structure that increases the number of substrates one after another in order to satisfy the required performance, waste in the manufacturing process and manufacturing cost occurs, and the probe card is complicated and large in size, There is a problem that the entire semiconductor inspection apparatus using such a probe card also becomes large.

上述のような問題点から、低コストでよりシンプルな構造のプローブカードを用いた半導体試験装置が求められている。 In view of the above problems, there is a demand for a semiconductor test apparatus using a probe card having a simpler structure at a lower cost.

そのために、本発明は、従来のプローブカードの機能を分析することによって、共通要素と専用要素に分けて、専用要素の簡素化を図り、簡易な構成のプローブカードを、汎用要素の構成の装置に真空吸着を用いて接続する半導体試験装置を提供することを目的とする。   Therefore, the present invention analyzes the function of a conventional probe card to divide it into a common element and a dedicated element, simplify the dedicated element, and convert the probe card with a simple configuration into a device with a general-purpose element configuration. An object of the present invention is to provide a semiconductor test apparatus which is connected to a semiconductor device using vacuum suction.

本発明の半導体試験装置は、一方の面に吸着領域と電気的接続領域が設けられ、他方の面に検査対象物に応じたプローブが設けられたプローブカード、上記吸着領域に吸着して上記プローブカードを固定する吸着手段、および上記電気的接続領域に接続されて電気信号の授受を行う電気的接続手段を備えたことを特徴とする。   The semiconductor test apparatus according to the present invention has a probe card in which an adsorption region and an electrical connection region are provided on one surface and a probe corresponding to an inspection object is provided on the other surface, and the probe adsorbed on the adsorption region It is characterized by comprising an adsorbing means for fixing the card, and an electric connecting means connected to the electric connecting area for transmitting and receiving electric signals.

本発明の半導体試験装置は、一方の面に吸着領域と電気的接続領域が設けられ、他方の面に検査対象物に応じたプローブが設けられたプローブカード、上記吸着領域に吸着して上記プローブカードを固定する吸着手段、および上記電気的接続領域に接続されて電気信号の授受を行う電気的接続手段を備えたことにより、より簡単な構成のプローブカードを用いることが可能となり、半導体検査装置の製造コストを低くすることができ、さらに、簡単な構成のプローブカードであっても変形を抑制することができ、十分な検査精度を確保することが可能となる。   The semiconductor test apparatus according to the present invention has a probe card in which an adsorption region and an electrical connection region are provided on one surface and a probe corresponding to an inspection object is provided on the other surface, and the probe adsorbed on the adsorption region By providing the suction means for fixing the card and the electrical connection means connected to the electrical connection area for transmitting and receiving electrical signals, it becomes possible to use a probe card with a simpler configuration, and a semiconductor inspection apparatus The manufacturing cost can be reduced, and even a probe card with a simple configuration can suppress deformation and ensure sufficient inspection accuracy.

本発明を実施するための最良の形態BEST MODE FOR CARRYING OUT THE INVENTION

以下に図を用いて本発明の半導体試験装置について詳しく説明する。   The semiconductor test apparatus of the present invention will be described in detail below with reference to the drawings.

図１が半導体試験装置１の概略断面図、図２がプローブカード２の平面図である。   FIG. 1 is a schematic sectional view of the semiconductor test apparatus 1, and FIG. 2 is a plan view of the probe card 2.

本発明の半導体試験装置１は、一方の面に吸着領域５と電気的接続領域６が設けられ、他方の面にプローブ４が設けられたプローブカード２、上記吸着領域５に吸着して上記プローブカード４を固定する吸着手段７、および上記電気的接続領域６に接続されて電気信号の授受を行う電気的接続手段８を備える。   The semiconductor test apparatus 1 according to the present invention has a probe card 2 provided with an adsorption region 5 and an electrical connection region 6 on one surface and a probe 4 provided on the other surface, and adsorbs on the adsorption region 5 and the probe A suction means 7 for fixing the card 4 and an electrical connection means 8 connected to the electrical connection area 6 for transmitting and receiving electrical signals are provided.

上記プローブカード２の上記吸着領域５と上記電気的接続領域６は、図２（ａ）、（ｂ）に示すような様々な配置が可能となっている。この吸着領域５と電気的接続領域６は一体的に構成する場合と、それぞれ別の構成とする場合がある。   The adsorption area 5 and the electrical connection area 6 of the probe card 2 can be arranged in various ways as shown in FIGS. The adsorption region 5 and the electrical connection region 6 may be configured integrally or may be configured separately.

一体的に構成する場合は、電気的接続領域６には、ポゴ座と呼ばれているランドが領域内に複数配置されている。このランドに上記電気的接続手段８が接触して電気的な接続を行う。   In the case of an integral structure, a plurality of lands called pogo seats are arranged in the electrical connection region 6 in the region. The electrical connection means 8 comes into contact with the land to make an electrical connection.

別に構成する場合は、プローブカード２における図２に示す電気的接続領域６の部分は窓となっており、この窓を通して別に構成された電気的接続領域６に上記電気的接続手段８が接続される。   In the case of another configuration, the portion of the electrical connection area 6 shown in FIG. 2 in the probe card 2 is a window, and the electrical connection means 8 is connected to the electrical connection area 6 separately configured through this window. The

また、上記吸着領域５は、吸着手段７によって吸着される範囲であるので、空気漏れが生じないように表面を平滑に仕上げるか、オーリングなどのパッキンを設ける必要がある。特に、表面を平滑な平面に仕上げて吸着手段と密着させるようにすれば、表面の位置を基準として、プローブの先端を高精度に位置決めすることができる。   Moreover, since the said adsorption | suction area | region 5 is the range adsorb | sucked by the adsorption | suction means 7, it is necessary to finish the surface smoothly or to provide packing, such as an O ring, so that an air leak may not arise. In particular, if the surface is finished into a smooth flat surface and brought into close contact with the suction means, the tip of the probe can be positioned with high accuracy based on the position of the surface.

上記プローブカード２としては、セラミック基板あるいは同等の基板が用いられる。形状としては、図２に示すような角型、あるいは丸型とすることができる。   As the probe card 2, a ceramic substrate or an equivalent substrate is used. The shape may be a square shape or a round shape as shown in FIG.

上記吸着手段７としては、ウエハチャックに用いられるような真空吸着装置を用いる。図３に示すように、真空吸着装置は吸着面に多数の孔１３が設けられ、この孔１３が排気装置１１に接続されており、排気装置１１によって排気することによって、上記吸着領域５を吸着する。   As the suction means 7, a vacuum suction device used for a wafer chuck is used. As shown in FIG. 3, the vacuum suction device is provided with a large number of holes 13 on the suction surface, and the holes 13 are connected to the exhaust device 11. To do.

上記電気的接続手段８としては、ポゴタワーを用いる。上記ポゴタワーは、複数のポゴピン９が配置されており、このポゴピン９が上記プローブカード２の電気的接続領域６に接触して、電気的に接続される。   A pogo tower is used as the electrical connection means 8. In the pogo tower, a plurality of pogo pins 9 are arranged, and the pogo pins 9 come into contact with the electrical connection region 6 of the probe card 2 and are electrically connected.

プローブカード２を吸着手段７によって固定する手順を、図４を用いて説明する。まず、図４（ａ）のホルダー１０にプローブカード２を保持させ、図４（ｂ）の状態にする。そして、排気装置１１によって排気を行い真空吸着装置（吸着手段７）によってプローブカード２の吸着領域５を吸着し、上記プローブカード２を固着する。 A procedure for fixing the probe card 2 by the suction means 7 will be described with reference to FIG. First, the probe card 2 is held in the holder 10 of FIG. 4A to be in the state of FIG. Then, the exhaust device 11 is evacuated and the suction region 5 of the probe card 2 is sucked by the vacuum suction device (suction means 7), and the probe card 2 is fixed.

上記プローブカード２の固定が完了したら、上記ホルダー１０による上記プローブカード２の保持を解除する（図４（ｃ））。上記プローブカード２は吸着手段７によって固着されているので、ホルダー１０の保持を解除しても問題は無いが、不測の事態に備えて、安全装置として、上記プローブカード２の係り止めを設けることも可能である。 When the fixing of the probe card 2 is completed, the holding of the probe card 2 by the holder 10 is released (FIG. 4C). Since the probe card 2 is fixed by the adsorbing means 7, there is no problem even if the holder 10 is released. However, in the event of an unexpected situation, the probe card 2 is provided with a lock as a safety device. Is also possible.

次に、プローブカード２が吸着手段７によって固着される時に同時に行われる電気的接続がどのように行われるか図５を用いて説明する。 Next, how electrical connection that is performed simultaneously when the probe card 2 is fixed by the suction means 7 will be described with reference to FIG.

上記プローブカード２が吸着手段７によって固着されるまではポゴピン９の先端が真空吸着装置（吸着手段７）の表面よりも突出しており（図５（ａ）の状態）、吸着装置によってプローブカード２が吸着されるときに、上記電気的接続領域６が上記ポゴピン９の先端に押し付けられ、電気的接続が確保される（図５（ｃ）の状態）。 Until the probe card 2 is fixed by the suction means 7, the tip of the pogo pin 9 protrudes from the surface of the vacuum suction device (suction means 7) (state of FIG. 5A). Is attracted, the electrical connection region 6 is pressed against the tip of the pogo pin 9 to ensure electrical connection (state shown in FIG. 5C).

この時、吸着手段７による吸着力（Ｆｖａｃ）と電気的接続手段８による押し圧力（Ｆｐｏｇｏ）との関係は、Ｆｖａｃ＞Ｆｐｏｇｏとなるようにする。これによって、電気的接続手段８の接触圧力に抗してプローブカード２が吸着手段７により固着され、同時に電気的接続手段８と電気的接続領域６との電気的接続がなされる。 At this time, the relationship between the suction force (F vac ) by the suction means 7 and the pressing force ( Fpogo ) by the electrical connection means 8 is set so that F vac > Fpogo . As a result, the probe card 2 is fixed by the suction means 7 against the contact pressure of the electrical connection means 8, and at the same time, the electrical connection means 8 and the electrical connection region 6 are electrically connected.

ただし、このような電気的接続は、プローブカード２において吸着領域５と電気的接続領域６が一体的に形成されている場合の接続手順であり、吸着領域５と電気的接続領域６が別に構成されている場合は、吸着手段７によりプローブカード２が吸着された後に、プローブカード２に形成された窓を通して電気的接続領域６と電気的接続手段８との接続を行う。 However, such an electrical connection is a connection procedure when the suction area 5 and the electrical connection area 6 are integrally formed in the probe card 2, and the suction area 5 and the electrical connection area 6 are configured separately. In the case where the probe card 2 is sucked by the suction means 7, the electrical connection region 6 and the electrical connection means 8 are connected through the window formed in the probe card 2.

このように、本願発明の半導体試験装置１では、吸着手段７によりプローブカード２を固着することにより、プローブカード２の平面度が維持され、プローブカードの補強効果をもたらす事が可能となる。   Thus, in the semiconductor test apparatus 1 of the present invention, by fixing the probe card 2 by the adsorbing means 7, the flatness of the probe card 2 is maintained, and the probe card can be reinforced.

これにより、従来の補強板等を用いた複雑な構造のプローブカードをより簡単な構造のプローブカードを用いることが可能となり、半導体試験装置の製造コストを低く抑えることが可能となる。 As a result, a probe card having a simple structure can be used instead of a probe card having a complicated structure using a conventional reinforcing plate or the like, and the manufacturing cost of the semiconductor test apparatus can be kept low.

そして、補強板等の複数の基板を用いた複雑な構造のプローブカードを使用せずに、吸着手段が補強効果を有することにより、プローブカードの変形が抑制され、半導体試験装置の検査精度を高めることが可能となる。   And since the adsorption | suction means has a reinforcement effect without using the probe card of a complicated structure using several board | substrates, such as a reinforcement board, a deformation | transformation of a probe card is suppressed and the test | inspection precision of a semiconductor testing apparatus is raised. It becomes possible.

本発明の半導体検査装置を用いることにより、φ３００ｍｍの半導体ウエハを一括で試験する場合でも、プローブカード２の大きさは、プローブカード２を保持する機構および半導体ウエハを保持する機構よりも若干大きい程度で済むことから、半導体検査装置全体を小型化することが可能となる。   By using the semiconductor inspection apparatus of the present invention, the probe card 2 is slightly larger in size than the mechanism for holding the probe card 2 and the mechanism for holding the semiconductor wafer, even when a semiconductor wafer having a diameter of 300 mm is collectively tested. Therefore, the entire semiconductor inspection apparatus can be reduced in size.

本発明の半導体試験装置の概略断面図。1 is a schematic sectional view of a semiconductor test apparatus of the present invention. 本発明の半導体試験装置に使用するプローブカードの平面図であり、（ａ）が角型のプローブカードの平面図、（ｂ）が丸型のプローブカードの平面図である。It is a top view of the probe card used for the semiconductor testing apparatus of this invention, (a) is a top view of a square-shaped probe card, (b) is a top view of a round-shaped probe card. 吸着手段および電気的接続手段の斜視図である。It is a perspective view of an adsorption | suction means and an electrical connection means. プローブカードを吸着手段によって吸着する手順を（ａ）から（ｃ）に順番に示す概略断面図である。It is a schematic sectional drawing which shows the procedure which adsorb | sucks a probe card by an adsorption | suction means in order from (a) to (c). ポゴピンの先端とプローブカードの電気的接続領域とが接触し電気的接続がなされる順序を（ａ）から（ｃ）に順番に示す概略断面図である。It is a schematic sectional drawing which shows the order in which the front-end | tip of a pogo pin and the electrical connection area | region of a probe card contact, and an electrical connection is made in order from (a) to (c).

符号の説明Explanation of symbols

１ 半導体試験装置
２ プローブカード
３ テスターインターフェース
４ プローブ
５ 吸着領域
６ 電気的接続領域
７ 吸着手段
８ 電気的接続手段
９ ポゴピン
１０ ホルダー
１１ 排気装置
１２ ウエハチャック
１３ 孔 DESCRIPTION OF SYMBOLS 1 Semiconductor test device 2 Probe card 3 Tester interface 4 Probe 5 Suction area 6 Electrical connection area 7 Suction means 8 Electrical connection means 9 Pogo pin 10 Holder 11 Exhaust device 12 Wafer chuck 13 Hole

Claims (1)

一方の面に吸着領域と電気的接続領域が設けられ、他方の面に検査対象物に応じたプローブが設けられたプローブカード、上記吸着領域に吸着して上記プローブカードを固定する吸着手段、および上記電気的接続領域に接続されて電気信号の授受を行う電気的接続手段を備えたことを特徴とする半導体検査装置。   A probe card provided with an adsorption area and an electrical connection area on one side and a probe corresponding to the object to be inspected on the other side; an adsorption means for adsorbing to the adsorption area and fixing the probe card; and A semiconductor inspection apparatus comprising an electrical connection means connected to the electrical connection region for transmitting and receiving electrical signals.
JP2007129876A 2007-05-15 2007-05-15 Semiconductor test equipment Active JP5343278B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007129876A JP5343278B2 (en) 2007-05-15 2007-05-15 Semiconductor test equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007129876A JP5343278B2 (en) 2007-05-15 2007-05-15 Semiconductor test equipment

Publications (2)

Publication Number Publication Date
JP2008288286A true JP2008288286A (en) 2008-11-27
JP5343278B2 JP5343278B2 (en) 2013-11-13

Family

ID=40147749

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007129876A Active JP5343278B2 (en) 2007-05-15 2007-05-15 Semiconductor test equipment

Country Status (1)

Country Link
JP (1) JP5343278B2 (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63299354A (en) * 1987-05-29 1988-12-06 Tokyo Electron Ltd Mechanism for movement
JPS6481242A (en) * 1987-09-24 1989-03-27 Hitachi Ltd Probe inspection device
JP2000286313A (en) * 1999-01-29 2000-10-13 Tokyo Electron Ltd Holding mechanism and automatic replacement mechanism for contactor
JP2002033359A (en) * 2000-07-17 2002-01-31 Ando Electric Co Ltd Ic tester, reference position setting equipment for its test head, and connection position controlling method for its connection mechanism
JP2003324133A (en) * 2002-04-26 2003-11-14 Agilent Technol Inc Planarization device and method for obtaining planarity of probe card
JP2007005405A (en) * 2005-06-21 2007-01-11 Renesas Technology Corp Method for manufacturing semiconductor integrated circuit device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63299354A (en) * 1987-05-29 1988-12-06 Tokyo Electron Ltd Mechanism for movement
JPS6481242A (en) * 1987-09-24 1989-03-27 Hitachi Ltd Probe inspection device
JP2000286313A (en) * 1999-01-29 2000-10-13 Tokyo Electron Ltd Holding mechanism and automatic replacement mechanism for contactor
JP2002033359A (en) * 2000-07-17 2002-01-31 Ando Electric Co Ltd Ic tester, reference position setting equipment for its test head, and connection position controlling method for its connection mechanism
JP2003324133A (en) * 2002-04-26 2003-11-14 Agilent Technol Inc Planarization device and method for obtaining planarity of probe card
JP2007005405A (en) * 2005-06-21 2007-01-11 Renesas Technology Corp Method for manufacturing semiconductor integrated circuit device

Also Published As

Publication number Publication date
JP5343278B2 (en) 2013-11-13

Similar Documents

Publication Publication Date Title
TWI466205B (en) Methods and apparatus for bimodal wafer testing
US7489148B2 (en) Methods for access to a plurality of unsingulated integrated circuits of a wafer using single-sided edge-extended wafer translator
US7459924B2 (en) Apparatus for providing electrical access to one or more pads of the wafer using a wafer translator and a gasket
JP2014089121A (en) Inspection unit, probe card, inspection device, and control system for inspection device
JP6001326B2 (en) Probe device and wafer mounting table for probe device
JP2009526992A (en) Space transformer, manufacturing method of the space transformer, and probe card having the space transformer
US20080209720A1 (en) Method and Apparatus for Manufacturing a Probe Card
US9612278B2 (en) Wafer prober integrated with full-wafer contacter
JP2009541715A (en) Sewing the corner of the tile on the probe card board
JP2005265658A (en) Probe device adaptable to a plurality of types of testers
JP6490600B2 (en) Inspection unit
KR101641276B1 (en) Socket for testing semiconductor package and method for manufacturing the same
US7701232B2 (en) Rotational positioner and methods for semiconductor wafer test systems
JP2023102503A (en) Probe card and inspection system
JP2008134170A (en) Electrically connecting device
US7723980B2 (en) Fully tested wafers having bond pads undamaged by probing and applications thereof
JP5343278B2 (en) Semiconductor test equipment
JP2012163529A (en) Contactor and inspection device
JP6393542B2 (en) Contact inspection device
JP6266386B2 (en) Semiconductor test system
TWI618936B (en) Apparatus and method for testing semiconductor dies
KR20090075515A (en) Probe card and test apparatus comprising the same
JP4907513B2 (en) Wafer cassette device
KR101729850B1 (en) Apparatus for inspecting a compact electronic device
KR101627869B1 (en) Apparatus for inspecting a hi-fix board

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20100319

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110112

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120202

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120221

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120330

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20120515

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120725

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20120801

A912 Re-examination (zenchi) completed and case transferred to appeal board

Free format text: JAPANESE INTERMEDIATE CODE: A912

Effective date: 20120914

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130624

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130726

R150 Certificate of patent or registration of utility model

Ref document number: 5343278

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250