JP2008287578A5 - - Google Patents

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Publication number
JP2008287578A5
JP2008287578A5 JP2007132936A JP2007132936A JP2008287578A5 JP 2008287578 A5 JP2008287578 A5 JP 2008287578A5 JP 2007132936 A JP2007132936 A JP 2007132936A JP 2007132936 A JP2007132936 A JP 2007132936A JP 2008287578 A5 JP2008287578 A5 JP 2008287578A5
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JP
Japan
Prior art keywords
memory
transfer clock
clock
control unit
busy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2007132936A
Other languages
English (en)
Japanese (ja)
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JP2008287578A (ja
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Publication date
Application filed filed Critical
Priority to JP2007132936A priority Critical patent/JP2008287578A/ja
Priority claimed from JP2007132936A external-priority patent/JP2008287578A/ja
Publication of JP2008287578A publication Critical patent/JP2008287578A/ja
Publication of JP2008287578A5 publication Critical patent/JP2008287578A5/ja
Withdrawn legal-status Critical Current

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JP2007132936A 2007-05-18 2007-05-18 メモリコントローラ、情報処理装置及び電子機器 Withdrawn JP2008287578A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007132936A JP2008287578A (ja) 2007-05-18 2007-05-18 メモリコントローラ、情報処理装置及び電子機器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007132936A JP2008287578A (ja) 2007-05-18 2007-05-18 メモリコントローラ、情報処理装置及び電子機器

Publications (2)

Publication Number Publication Date
JP2008287578A JP2008287578A (ja) 2008-11-27
JP2008287578A5 true JP2008287578A5 (cg-RX-API-DMAC7.html) 2010-10-07

Family

ID=40147227

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007132936A Withdrawn JP2008287578A (ja) 2007-05-18 2007-05-18 メモリコントローラ、情報処理装置及び電子機器

Country Status (1)

Country Link
JP (1) JP2008287578A (cg-RX-API-DMAC7.html)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5746201B2 (ja) * 2009-11-05 2015-07-08 ラムバス・インコーポレーテッド インターフェースクロックマネージメント
JP7475380B2 (ja) * 2022-01-31 2024-04-26 キヤノン株式会社 撮像装置、デバイス、それらの制御方法及びプログラム

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3923715B2 (ja) * 2000-09-29 2007-06-06 株式会社東芝 メモリカード
JP3865629B2 (ja) * 2001-07-09 2007-01-10 株式会社ルネサステクノロジ 記憶装置
JP3552213B2 (ja) * 2001-08-31 2004-08-11 株式会社東芝 Ｓｄメモリカードホストコントローラ及びクロック制御方法

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