JP2008282515A - Semiconductor memory device and method of testing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To contribute to improvement in an accuracy of test, a product yield and a reliability, by attaining the test in the worst case, which activates word lines of first and second ports by a same timing at the test. <P>SOLUTION: The semiconductor memory device is disclosed in which cells are connected to the word lines (WLA, WLB) of at least first and second ports and timing control of activation of the word lines of the first and second ports is respectively performed based upon first and second clock signals (CLKA, CLKB), wherein first and second test control signals (TESTA, TESTB) are prepared in accordance with the first and second clock signals for respectively controlling the timings of activation of the word lines of the first and second ports, and one side of test control signal is masked at the test by the either one test control signal in the activated state, then the activation of the first and second word lines is simultaneously controlled by the other side of test control signals. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a configuration and a test method considering a test of a cell having a plurality of ports.

  First, the configuration of a dual port static memory circuit having SRAM (static random access memory) cells composed of eight transistors will be described with reference to FIG. Referring to FIG. 4, the memory cell includes a PMOS transistor Q2 (load) and NMOS transistor Q1 (driver transistor) connected between the first power supply VDD and the second power supply VSS, and a PMOS connected between VDD and VSS. The transistor Q4 (load) and the NMOS transistor Q3 (driver transistor) are provided. The common drain (N1) of the PMOS transistor Q2 and the NMOS transistor Q1 is connected to the common gate of the PMOS transistor Q4 and the NMOS transistor Q3. The common drain (N2) of the NMOS transistor Q3 is cross-connected to the common gate of the PMOS transistor Q2 and the NMOS transistor Q1. Between the node N1 and the bit lines DTA and DTB of the ports A and B, there are provided A port and B port access transistors Q5 and Q6 whose gates are connected to the word lines WLA and WLB, respectively, and the node N2 and the ports A and B Between the complementary bit lines DBA and DBB, there are provided A port and B port access transistors Q7 and Q8 whose gates are connected to the word lines WLA and WLB, respectively.

  In the dual port static memory circuit having the SRAM cell shown in FIG. 4, the ports A and B are used as I / O ports for reading and writing (in this case, simultaneous reading of the two ports is possible). However, port A may be used as a write-only port and port B as a read-only port (or vice versa). Regarding the multi-port memory circuit, the description in Patent Document 1 is also referred to.

JP-A-1-296486

  The dual port static memory circuit having the SRAM cell shown in FIG. 4 has a problem that the memory cannot be tested with the worst operating margin. Hereinafter, this point will be described (note that the following description is based on the results of studies by the present inventor).

  FIG. 4 shows how the currents Icell_A and Icell_B simultaneously flow from the bit lines DTA and DTB to the driver transistor Q1 in the SRAM cell as the operation of the memory cell when the ports A and B are read simultaneously. When ports A and B are simultaneously accessed on the same row, the word lines WLA and WLB of both ports A and B simultaneously rise to HIGH, so that the access transistors Q5 and Q7 of port A and the access transistors Q6 and Q8 of port B Are turned on at the same time. In the configuration shown in FIG. 4, it is assumed that the bit line pairs (DTA, DBA) and (DTB, DBB) of both ports are precharged to the HIGH potential before activation of the selected word line.

  Since the driver transistor Q1 in the SRAM cell has to pull the bit lines DTA and DTB of the ports A and B low, the bit line pulling is worse than when the bit line of one port is pulled low. For this reason, the value of the bit line difference potential (ΔVBL: difference potential between the bit line pair (DTA, DBA) and bit line pair (DTB, DBB)) read by the sense amplifier (not shown) decreases, and the operation margin decreases. As a result, the minimum operating voltage deteriorates.

  The degree of decrease in the value of the bit line difference potential ΔVBL becomes more conspicuous as the time during which the ON states of the access transistors Q5 and Q6 of the ports A and B overlap is longer. Therefore, when the rising edges of the word lines of both ports are at the same timing, the cell data read margin is the strictest and the lowest operating voltage is the worst point.

  FIG. 5A shows the difference Δt (= t (WLA−WLB)) between the rising timings of the word lines WLA and WLB of the ports A and B, and the bit line difference potential ΔVBL (V | DTA−DBA |, V | It is the graph which showed the relationship of DTB-DBB |). When the rising timings of the word lines WLA and WLB of the ports A and B overlap (see FIG. 5C), it can be seen that ΔVBL is minimum (see the valley of ΔVBL in FIG. 5A). .

  That is, the driver transistor of the SRAM cell discharges the other bit line of the bit line pair to the LOW side when one of the bit line pairs is HIGH based on the cell data. When pulling a bit line (for example, DTA, DTB) simultaneously with one driver transistor to LOW, as compared with the case of pulling only the bit line of one port from the point of current drive capability of the driver transistor, FIG. As shown, the opening between the bit line pairs becomes smaller and the opening speed becomes slower. On the other hand, when the activation (rising) timing of the word lines WLA and WLB of the ports A and B is shifted back and forth in time, the opening of the bit line difference potential ΔVBL is large (see FIG. 5B). ).

  It is desirable to perform the test in this state (worst case where ΔVBL is minimum) in a test before shipping the memory device.

However,
(A) skew (timing deviation) occurs between the ports in the path from the BIST (Built In Self Test) to the memory due to element variations in the chip;
(B) Internal clock skew for word line startup due to physical layout inside the memory occurs.
For example, the word lines of both ports cannot be driven at the same timing, and the operation margin is not worst. Hereinafter, this point will be described in more detail with reference to the drawings.

  FIG. 6 shows an example of a typical configuration of the word line control unit of the static memory circuit having the SRAM cell shown in FIG. FIG. 6 shows an example of the configuration of a clock-synchronous dual-port static memory circuit that controls the activation timing of the word line based on the input clock signal.

  Referring to FIG. 6, the clock signals CLKA and CLKB input to the clock terminals (A) and (B) are respectively input to the buffers 101 and 102, and the internal clock signals ICLA and ICLB are respectively input from the buffers 101 and 102. Is output.

  XKA and XEA of the address selection signal (A) (row address) for selecting the word line WLA of the port A are a main predecoder (not shown) and a sub predecoder (not shown) of the X address decoder (row address decoder) for the port A. ) Output.

  XKB and XEB of the address selection signal (B) (row address) for selecting the word line WLB of the port B are outputs of a main predecoder (not shown) and a sub predecoder (not shown) of the port B X address decoder. .

  CMOS comprising NAND circuit 103 that receives address selection signals (A) XKA and XEA, a PMOS transistor that receives the output of NAND circuit 103 at the gate, and an NMOS transistor that receives the signal obtained by inverting the output of NAND circuit 103 by inverter 104 at the gate Since the output of the NAND 103 is LOW when both the XKA and XEA are HIGH, the CMOS transfer gate 105 is turned on and the input internal clock signal ICLA is transmitted and output, and the inverter 107, the inverting buffer (inverted type) is provided. The word line WLA is raised to a high potential. When both XKA and XEA are other than HIGH (when either one is LOW), the output of the NAND circuit 103 is HIGH, the NMOS transistor 106 is turned on, the input of the inverter circuit 107 is fixed LOW, and the word line WLA is LOW. Set to The activation period of the selected word line corresponds to the HIGH pulse period of the internal clock signal ICLA. The port B address selection signal (B) has the same configuration.

  FIG. 7 is a diagram for explaining a test of a static memory circuit by BIST. In FIG. 7, IOA and IOB each include a write amplifier (not shown), a sense amplifier (not shown), and the like that respectively write and read data in and from port A and port B of an SRAM cell array (SRAM CELL). The control units CNTA and CNTB receive the clocks CLKA and CLKB, respectively, and perform timing control of the selected word lines of the port A and the port B. WLDA / B includes an X address decoder that decodes the row addresses of port A and port B, and a word driver that drives the selected word lines of port A and port B, respectively. During the test, the clock signal from the BIST 202 is distributed through the clock distribution path (clock buffer groups 203 and 204), and reaches the clock terminals CLKA and CLKB of the port A and the port B of the memory circuit 201.

  In this case, clock skew occurs between port A and port B due to element variations between the BIST 202 and the memory circuit 201.

  In addition, due to a physical layout in the memory circuit 201, internal clock skew occurs between ports. For example, the clock path from the clock terminal CLKA to the word line WLA has a path length different from that of the clock path from the clock terminal CLKB to the word line WLB, so that a skew occurs between the internal clocks ICLA and ICLB.

  For this reason, it is difficult to realize a test performed by starting up the word line WLA of the port A and the word line WLB of the port B at the same time.

  In addition, when a memory device is tested with a tester in which pin-to-pin skew is calibrated without using BIST, the internal clock skew between the ports due to the physical layout in the memory circuit, the clock terminal (external clock) A similar problem occurs due to the skew between the clock terminals of the ports A and B of the memory circuit 201 in the semiconductor device in the semiconductor device.

  As described above, in a conventional memory device having a cell having a plurality of ports, it becomes difficult to control the word lines of the plurality of ports to be activated at the same time during testing, and the test in the worst state cannot be performed. . As a result, accuracy (measurement accuracy) such as pass / fail judgment is limited, and it is a cause of suppressing improvement in product yield, reliability, and the like.

  In order to solve the above-described problems, the invention disclosed in the present application is generally configured as follows. In the following description, the reference numerals in parentheses are shown as an example in order to clarify the present invention, and of course should not be construed to limit the present invention.

  A semiconductor memory device according to a first aspect (aspect) of the present invention is a semiconductor memory device including cells having a plurality of ports, each of which controls a plurality of activation timings of word lines of a plurality of ports. For a cell having a plurality of test control signals corresponding to the timing signal, and a plurality of ports selected, one test control signal among the plurality of test control signals respectively corresponding to the plurality of selected ports is When in the active state and the remaining test control signals are in an inactive state, a timing signal corresponding to the test control signal in the inactive state is masked, and one test control signal corresponding to one test control signal in the active state is masked. A circuit is provided for controlling to activate the word lines of the selected plurality of ports in response to a timing signal.

  In the semiconductor memory device according to the present invention, when all of the plurality of test control signals corresponding to the selected plurality of ports are inactive, the semiconductor memory device responds to a plurality of timing signals respectively corresponding to the plurality of test control signals. Thus, activation of word lines of a plurality of ports is performed independently.

A semiconductor memory device according to another aspect of the present invention includes cells connected to word lines (WLA, WLB) of at least first and second ports, and includes first and second clock signals (CLKA, CLKB). The first and second port word line activation timing control is performed based on the first, second port word line activation timing control, and the first and second port word line activation timings are respectively controlled. First and second test control signals (TESTA and TESTB) are provided corresponding to the first and second clock signals. The second clock signal when the first test control signal is in an active state and the second test control signal is in an inactive state for a cell in which the first and second ports are selected. And controlling to activate the first word line and the second word line in response to the first clock signal,
When the second test control signal is in an active state and the first test control signal is in an inactive state, the first clock signal is masked, and the second clock signal is responsive to the second clock signal. Control is performed so as to activate the first word line and the second word line.

  In the semiconductor memory device according to the present invention, when both the first and second test control signals are inactive for the cell in which the first and second ports are selected, the first and second The activation control of the first and second word lines is independently performed by the clock signal.

In the semiconductor memory device according to the present invention, the first clock signal and the second test control signal are input, and when the second test control signal is inactive, the first clock signal is First output as a first internal clock signal, and when the second test control signal is in an active state, the first clock signal is not transmitted and the first internal clock signal is fixed in an inactive state. Circuit (11, 12),
Inputting the second clock signal and the first test control signal, and outputting the second clock signal as a second internal clock signal when the first test control signal is in an inactive state; A second circuit (13, 14) for fixing the second internal clock signal to an inactive state without transmitting the second clock signal when the first test control signal is in an active state;
When the first internal clock signal (ICLA) from the first circuit (11, 12) is received and the address selection signal (XKA, XEA) of the first port indicates a selected state, it is turned on. A first switch (transfer gate) (17) for transmitting and outputting one internal clock signal;
When the second internal clock signal (ICLB) is received from the second circuit (13, 14) and the address selection signal (XKB, XEB) of the second port indicates a selected state, the second circuit (13, 14) is turned on. A second switch (24) for transmitting and outputting two internal clock signals;
The second test control signal (TESTB) and the output signal of the second switch (transfer gate) (24) are input, and when one or both of the inputs are inactive, a signal in an inactive state is output. A first logic circuit (19) that outputs an active signal when both inputs are active;
The second logic circuit (20) that receives the output signal of the first logic circuit (19) and the output signal of the first switch (17) and outputs the other when one of the inputs is inactive. )When,
A first word driver (21) for receiving an output signal of the second logic circuit (20) and driving a word line of a first port;
The first test control signal (TESTA) and the output signal of the first switch (17) are input, and when one or both of the inputs are inactive, a signal in an inactive state is output, A third logic circuit (26) that outputs an active signal when both are active;
The fourth logic circuit (27) which receives the output signal of the third logic circuit (26) and the output signal of the second switch (24) and outputs the other when one of the inputs is inactive. )When,
A second word driver (28) for receiving an output signal of the fourth logic circuit and driving a word line of a second port;
It has.

  In the present invention, the first logic circuit and the third logic circuit are two-input AND circuits, the second logic circuit and the fourth logic circuit are two-input NOR circuits, The one word driver and the second word driver are inverting drivers.

  In the present invention, the cell has two inverters (Q1, Q2), (Q3, Q4) whose inputs and outputs are cross-connected at the first and second nodes (N1, N2 in FIG. 4), Inserted between the first node (N1) and the bit lines (DTA, DTB) of the first and second ports, the control terminals are connected to the word lines of the first and second ports, respectively. 1, inserted between the second access transistor (Q5, Q6), the second node (N2) and the bit lines complementary to the bit lines of the first and second ports (DBA, DBB), The static cell includes third and fourth access transistors (Q7, Q8) having control terminals connected to the word lines of the first and second ports, respectively.

In the present invention of the first aspect, an input clock signal is used as the timing signal, and the selected word line is activated in response to the clock signal,
When the test control signal of one of the first and second ports is activated at the rise of the word line on the same row, the word line of the other port is also the word line on the one port side. It is driven at the same timing as the rising edge.

According to still another aspect of the present invention, there is provided a method for testing a semiconductor memory device including cells connected to at least first and second port word lines.
First and second test control signals corresponding to the first and second clock signals for controlling the activation timing of the word lines of the first and second ports, respectively, are prepared.
For cells for which the first and second ports are selected,
When the first test control signal is in an active state and the second test control signal is in an inactive state,
The second clock signal is masked, the first and second word lines are started at the same timing in response to the first clock signal, and a cell is formed from the bit lines of the first and second ports. Read data simultaneously,
When the second test control signal is in an active state and the first test control signal is in an inactive state, the first clock signal is masked, and the second clock signal is responsive to the second clock signal. The first and second word lines are started at the same timing, and cell data are simultaneously read from the bit lines of the first and second ports.

  According to the present invention, a memory cell having a plurality of word lines corresponding to a plurality of ports and a control for activating the word lines corresponding to each of the plurality of ports by a timing signal corresponding to each of the plurality of ports. A semiconductor memory device in which the control circuit activates the plurality of word lines by one of the timing signals in accordance with an input test control signal.

  Alternatively, according to the present invention, at least memory cells connected to the first and second word lines corresponding to the first and second ports, respectively, and the first clock signal corresponding to the first port. And a control circuit that activates the first word line and activates the second word line by a second clock signal corresponding to the second port. A semiconductor memory device is provided that activates the first word line and the second word line by the first clock signal or the second clock signal in accordance with a control signal.

  According to the present invention, at the time of testing, the word lines of a plurality of ports can be activated at the same timing, thereby enabling a worst-case test. This improves test accuracy and contributes to product yield and reliability.

  The above-described present invention will be described with reference to the accompanying drawings in order to explain in more detail. The semiconductor memory device of the present invention includes a cell having a plurality of ports, and further corresponds to a plurality of timing signals (for example, clock signals, CLKA, CLKB) that respectively control activation timings of word lines of the plurality of ports. For a cell having a plurality of test control signals (TESTA, TESTB) and a plurality of ports selected, one of the plurality of test control signals corresponding to the plurality of selected ports is activated. When the remaining test control signal is in an inactive state (disabled), the timing signal corresponding to the inactive test control signal is masked, and one active test control signal In response to one timing signal corresponding to the word lines of the selected ports (for example, WLA, and controls to activate WLB). When the present invention is applied to a dual-port type clock synchronous static memory circuit in which each port functions as an I / O port, the first and second ports are turned on when the word lines on the same row are raised. When the test control signal of one port is activated (enabled), the word line of the other port is also driven at the same signal transition timing as the rise of the word line on the one port side.

  In the present invention, when the test control signal of one port is activated (enabled), the internal clock of the other port is not raised. With such a configuration, the test can be performed under the condition that the operation margin is the strictest during the memory test by BIST or the like. That is, when the same row is accessed at ports A and B at the same time and the word lines of ports A and B rise at the same time, the data read margin is the smallest and the lowest drive voltage is the worst. For example, due to the configuration in which the word lines of ports A and B are driven at the same timing using only the clock of port A, the clock skew between the ports from BIST to the memory and the physical layout inside the memory Without considering the influence of the internal clock skew, it is possible to realize a state where the operation margin is always the worst. In the following, an embodiment in which the present invention is applied to a clock synchronous static memory circuit in which the memory cell comprises the dual port SRAM cell shown in FIG. 4 and the activation of a word line is controlled based on a clock signal will be described. To do.

  FIG. 1 is a diagram showing a configuration of a circuit (X address decoder and word driver) for controlling activation of a word line according to an embodiment of the present invention.

  Referring to FIG. 1, a clock terminal (A) for inputting a clock signal CLKA, a two-input NAND circuit 11 whose input is connected to a TEST terminal (TESTB) of a port B, and an inverting buffer for receiving the output of the NAND circuit 11 12 and the inversion buffer 12 outputs the internal clock ICLA.

  The operation of this circuit will be described. When the test control signal TESTB for the port B is LOW (the input of the test control signal TESTB is active at LOW in the NAND circuit 11), the NAND circuit 11 receives the clock signal CLKA for the port A. The inverted signal is output, and an internal clock signal (A) ICLA in phase with the clock signal CLKA is output from the inverting buffer 12. When the test control signal TESTB for port B is HIGH, the output of the NAND circuit 11 is fixed HIGH (the clock signal CLKA is masked) regardless of the value of the clock signal CLKA, and the internal clock signal ICLA from the inverting buffer 12 is output. Is fixed LOW.

  A clock terminal (B) for inputting the clock signal CLKB, a 2-input NAND circuit 13 whose input is connected to the TEST terminal (TESTA) of the port A, and an inverting buffer 14 for receiving the output of the NAND circuit 13 are provided. The internal clock ICLB is output from the buffer 14.

  The operation of this circuit will be described. When the test control signal TESTA for port A is LOW (input of the test control signal TESTA is active LOW in the NAND circuit 13), the NAND circuit 13 receives the clock signal CLKB for port B. The inverted signal is output, and the inversion buffer 14 outputs the internal clock signal (B) ICLB in phase with the clock signal CLKB. When the test control signal TESTA for port A is HIGH, the output of the NAND circuit 13 is fixed HIGH (the clock signal CLKB is masked) regardless of the value of the clock signal CLKB, and the internal clock signal ICLB from the inverting buffer 14 is set. Is fixed LOW.

  Further, as a circuit for controlling the driving of the word line WLA of the port A, a 2-input NAND circuit 15 that receives the XKA and XEA that are the address selection signals (A) of the port A, and a PMOS transistor that receives the output of the NAND circuit 15 at the gate And a CMOS transfer gate 17 composed of an NMOS transistor receiving the signal obtained by inverting the output of the NAND circuit 15 by the inverter 16, a drain connected to the output of the CMOS transfer gate 17, a source connected to the power supply VSS, and a gate connected to the NAND circuit. An NMOS transistor 18 connected to 15 outputs is provided. Further, the test control signal TESTB for port B, a 2-input AND circuit 19 whose input is connected to the output of a CMOS transfer gate 24 described later, and a 2-input NOR circuit for receiving the output of the CMOS transfer gate 17 and the output of the AND circuit 19 20 and an inversion type word driver 21 that receives the output of the NOR circuit 20. Note that XKA and XEA of the address selection signal (A) are address selection signals output as a result of decoding the X address in a predecoder (not shown).

  The operation of this circuit will be described. When both XKA and XEA are HIGH, the output of the NAND circuit 15 becomes LOW, the CMOS transfer gate 17 is turned on, and the input internal clock signal ICLA is transmitted and output. When at least one of XKA and XEA is LOW (when the address of port A of the cell is not selected), the output of the NAND circuit 15 is HIGH, the CMOS transfer gate 17 is turned off, the NMOS transistor 18 is turned on, and the CMOS transfer is turned on. The output of the gate 17 is set to the LOW level.

  For example, when the test control signal TESTB of port B is LOW, the output of the AND circuit 19 becomes LOW, and the NOR circuit 20 supplies a signal obtained by inverting ICLA, which is the output of the CMOS transfer gate 17, to the inverting type word driver 21. .

  On the other hand, when the test control signal TESTB of port B is HIGH (ICLA is fixed LOW at this time), the NOR circuit 20 supplies a signal obtained by inverting the output of the AND circuit 19 to the inverting word driver 21. The inverting type word driver 21 receives the LOW pulse (signal having a phase opposite to ICLB) from the NOR circuit 20 and drives the word line WLA.

  Further, as a circuit for controlling the driving of the word line WLB of the port B, a 2-input NAND circuit 22 that receives the XKB and XEB that are the address selection signals (B) of the port B, and a PMOS transistor that receives the output of the NAND circuit 22 And a CMOS transfer gate 24 comprising an NMOS transistor receiving the signal obtained by inverting the output of the NAND circuit 22 at the inverter 23, a drain connected to the output of the CMOS transfer gate 24, a source connected to the power supply VSS, and a gate connected to the NAND circuit The NMOS transistor 25 connected to the output of 22 is provided. Furthermore, a test control signal TESTA for port A, a 2-input AND circuit 26 whose input is connected to the output of the CMOS transistor 17, a 2-input NOR circuit 27 receiving the output of the CMOS transfer gate 24 and the output of the AND circuit 26, And an inversion type word driver 28 that receives the output of the NOR circuit 27. Note that XKB and XEB of the address selection signal (B) are address selection signals output as a result of decoding the X address in a predecoder (not shown).

  The operation of this circuit will be described. When both XKB and XEB are HIGH, the output of the NAND circuit 22 becomes LOW, the CMOS transfer gate 24 is turned on, and the input internal clock signal ICLB is transmitted and output. When at least one of XKB and XEB is LOW (when the address of the port B of the cell is not selected), the output of the NAND circuit 22 becomes HIGH, the CMOS transfer gate 24 turns off, the NMOS transistor 25 turns on, and the CMOS transfer The output of the gate 24 is set to the LOW level.

  For example, when the test control signal TESTA for port A is LOW, the output of the AND circuit 26 becomes LOW, and the NOR circuit 27 supplies a signal obtained by inverting ICLB, which is the output of the CMOS transfer gate 24, to the inverting driver 28.

  On the other hand, when the test control signal TESTA of port A is HIGH (ICLA is fixed LOW at this time), the NOR circuit 27 supplies a signal obtained by inverting the output of the AND circuit 26 to the inverting word driver 28. The inverting type word driver 28 receives the LOW pulse (signal having a phase opposite to ICLB) from the NOR circuit 27 and drives the word line WLB.

  Note that the test control signals TESTA and TESTB are both set to the LOW level except for the case where the simultaneous READ test of the ports A and B is performed during the normal operation or the test, and the ICLA, the CMOS transfer gate 17 and the NOR circuit 20 are set. The activation timing of the word line WLA is controlled via the ICB, and the activation timing of the word line WLB is controlled via the ICLB, the CMOS transfer gate 24 and the NOR circuit 27 (controlled independently of the WLA). ) It is prohibited to set both the test control signals TESTA and TESTB to HIGH.

  FIG. 2 is a diagram for explaining the timing operation of the present embodiment shown in FIG. The operation of the circuit of FIG. 1 will be described below with reference to FIG.

<Independent operation>
When both TESTA and TESTB are LOW (see “Independent operation” in FIG. 2), the NAND circuits 11 and 13 output signals obtained by inverting CLKA and CLKB, respectively, and ICLA and ICLB have the same phase as CLKA and CLKB. The internal clock signal is output.

  Since TESTB is LOW, the output of the AND circuit 19 is fixed LOW, and when XKA and XEA are HIGH, the NOR circuit 20 outputs an inverted signal of ICLA output from the CMOS transfer gate 17 and The word line (A) WLA is activated in synchronization with the clock ICLA, and hence CLKA.

  Since TESTA is LOW, the output of the AND circuit 26 is fixed LOW, and when XKB and XEB are HIGH, the NOR circuit 27 outputs an inverted signal of ICLB output from the CMOS transfer gate 24, and the port B The word line (B) WLB is activated in synchronization with the clock ICLB, and hence CLKB. That is, the word lines of port A and port B are controlled independently of each other.

<Simultaneous READ: A port test>
When TESTA is HIGH and TESTB is LOW (see “A port test” in FIG. 2), the output of the NAND circuit 13 is HIGH regardless of the value of the clock terminal CLKB, and ICLB is fixed LOW. Since the output of the AND circuit 19 is fixed to LOW, when XKA and XEA are HIGH, the NOR circuit 20 outputs an inverted signal of ICLA output from the CMOS transfer gate 17 and the word line (A) WLA of the port A Are activated in synchronism with the clock ICLA, and hence CLKA. ICLB is fixed to LOW. When XKB and XEB are HIGH, the NOR circuit 27 outputs an inverted signal of the AND circuit 26. When ICLA is HIGH, the AND circuit 26 is HIGH, and the word driver 28 sets the word line WLB to HIGH. That is, WLB rises simultaneously with WLA, and read data is simultaneously output to the bit line pair DTA / DBA of the A port and the bit line pair DTB / DBB of the B port. This is the worst case condition of the simultaneous READ described with reference to FIG.

<Simultaneous READ: B port test>
When TESTB is HIGH and TESTA is LOW (see “B port test” in FIG. 2), the output of the NAND circuit 11 is HIGH regardless of the value of the clock terminal CLKA, and ICLA is fixed LOW. Since the output of the AND circuit 26 is fixed to LOW, when XKB and XEB are HIGH, the NOR circuit 27 outputs an inverted signal of ICLB output from the CMOS transfer gate 24 and the word line (B) WLB of the port B Are activated in synchronism with the clock ICLB, and hence CLKB. ICLA is fixed LOW. When XKA and XEA are HIGH, the NOR circuit 20 outputs an inverted signal of the AND circuit 19, and when ICLB is HIGH, the AND circuit 19 becomes HIGH, and the word driver 21 sets the word line WLA to HIGH. That is, WLA rises simultaneously with WLB, and read data is simultaneously output to the bit line pair DTB / DBB of the B port and the bit line pair DTA / DBA of the A port. This is the worst case condition of simultaneous READ described with reference to FIG.

  Thus, in this embodiment, in the control of the rise of the word lines on the same row, the logic of the test control signal of one port and the word line rise signal of the other port is added, and one port is When the test control signal is enabled, the word line on the other port side is also driven at the same signal transition timing as the rise of the word line on one port side. The logic of the test control signal of one port and the clock signal of the other port inputted from the outside is taken so as not to disturb the driving of the other word line, and the test control signal of one port is enabled (HIGH) In this case, the internal clock of the other port is not output.

  FIG. 3 is a diagram for explaining the operation of the embodiment of the present invention, and corresponds to the configuration shown in FIG. The test control signal for the target port is activated (enabled), a clock is input to the target port, and the word line of the other port on the same row is driven at the same timing as the target port word line is driven. Perform the read operation. At this time, the internal clock signal at the other port is fixed at LOW so that the driving of the word line at the other port is not hindered even if a clock is input to the other port.

  Referring to FIG. 3, the clock signal CLKA and the test control signal TESTA are supplied from the BIST 2 to the terminals CLKA and TESTA of the port A of the memory circuit 1 through the clock buffer 4 and the signal buffer 6, and the test is performed with the clock signal CLKB from the BIST 2. The control signal TESTB is supplied to the terminals CLKB and TESTB of the port B of the memory circuit 1 through the clock buffer 3 and the signal buffer 5. In the example shown in FIG. 3, when the ports A and B of the selected cell are started at the same timing, the TESTA is set to HIGH, the TESTB is set to LOW, and the port A and B word lines WLA are used by using the clock A for the port A. , WLB is started up simultaneously. Since the same clock (clock from the clock terminal CLKA of the port A) is supplied to a circuit (see FIG. 1) that controls the driving of the word lines WLA and WLB, the ports between the ports according to the physical layout in the memory circuit 1 Even if there is a skew of the internal clock in FIG. 5, the word lines WLA and WLB can be raised at the timing shown in FIG.

  That is, since the word lines of the ports A and B are driven with the same clock in the simultaneous READ of both ports, the clock skew between the ports A and B does not pose a problem due to element variations between the BIST 2 and the memory circuit 1. Further, the physical layout in the memory circuit 1 does not affect the skew of the internal clock between the ports.

  FIG. 8 is a block diagram showing the configuration of an embodiment of the present invention. Referring to FIG. 8, the memory circuit 1 includes an internal clock B output circuit 42, an internal clock A output circuit 44, an X address decoder 30, a word driver control circuit 46, and a word driver 48. Of course, the word driver control circuit 46 and the word driver 48 may be configured as one circuit block.

  A clock signal of boat A and boat B is supplied from a BIST (Built In Self Test) circuit 2 to the memory circuit 1 via a clock buffer 3 and a clock buffer 4, respectively. Further, the test signals of the port A and the port B are supplied from the BIST circuit 2 to the memory circuit 1 via the signal buffer 5 and the signal buffer 6, respectively.

  The clock signal CLKA of port A and the test signal TESTB of port B are input to the internal clock A output circuit 44, and the internal clock A output circuit 44 outputs the internal clock ICLA of port A.

  The port B clock signal CLKB and the port A test signal TESTA are input to the internal clock B output circuit 42, and the internal clock B output circuit 42 outputs the port B internal clock ICLB.

  Of the addresses output from the BIST circuit 2, the X address is input to the X address decoder 30, and address selection signals XKA, XEA, and XKB, XEB are output from the X address decoder 30. Of the addresses output from the BIST circuit 2, the Y address is input to a column decoder (not shown).

  The word driver control circuit 46 receives the internal clock signals ICLA and ICLB, the test signals TESTA and TESTB, and the address selection signals XKA, XEA, XKB, and XEB, and outputs a signal that controls the activation of the word driver 48. .

  The word driver 48 drives the word line WLA of the port A and the word line WLB of the port B of the memory cell array 32 based on the output from the word driver control circuit 46, respectively.

  In FIG. 8, the internal clock A output circuit 44 includes the NAND 11 and the inverter 12 shown in FIG. The internal clock B output circuit 42 includes the NAND 13 and the inverter 14 shown in FIG. The word driver control circuit 46 includes the NAND 15, the inverter 16, the CMOS transfer gate 17, the NMOS transistor 18, the AND 19, the NOR 20, the NAND 22, the inverter 23, the CMOS transfer gate 24, the NMOS transistor 25, the AND 26, and the NOR 27 in FIG. Is done. Further, the word driver 48 includes inversion type drivers (inverters) 21 and 28 for driving the word lines WLA and WLB, respectively, in FIG.

  This embodiment has the following effects.

-By testing this memory circuit under conditions that have the strictest operating margin in testing before product shipment, the failure rate after product shipment is reduced.

-Improve yield by setting appropriate test standards in tests before product shipment.

  Note that by setting the test control signals TESTA and TESTB to LOW, a phase difference is given to the rising edges of CLKA and CLKB, and the test is performed under the condition that the word lines WLA and WLB do not overlap as shown in FIG. Of course it is good.

  In the above embodiment, the clock synchronous static memory circuit having the dual port SRAM cell described with reference to FIG. 4 (ports A and B are used as I / O ports for reading and writing, However, the static memory circuit may use port A as a write-only port and port B as a read-only port (or vice versa). Of course. Further, the present invention is not limited to the two port configurations of ports A and B, and can be similarly applied to cells having more than two ports.

  It should be noted that the disclosures of the above patent documents are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

It is a figure which shows the structure of one Example of this invention. It is a timing diagram for demonstrating operation | movement of one Example of this invention. It is a figure for demonstrating the test of one Example of this invention. It is a figure explaining simultaneous READ in an SRAM cell. It is a figure explaining the problem of simultaneous READ in an SRAM cell. It is a figure which shows the structure of the word driver control circuit of a 2-port type clock synchronous static memory circuit. It is a figure for demonstrating the test of a 2 port type clock synchronous static memory circuit. It is a figure which shows the structure of one Example of this invention.

Explanation of symbols

1 Memory circuit 2 BIST
3, 4 Clock buffer 5, 6 Signal buffer 11, 13 NAND circuit 12, 14 Inversion buffer 15, 22 NAND circuit 16, 23 Inverter 17, 24 CMOS transfer gate 18, 25 NMOS transistor 19, 26 AND circuit 20, 27 NOR circuit 21, 28 Inverted word driver (inverter)
30 X address decoder 32 Memory cell array 42 Internal clock B output circuit 44 Internal clock A output circuit 46 Word driver control circuit 48 Word driver 101, 102 Buffer 103, 109 NAND circuit 104, 110 Inverter 105, 112 CMOS transfer gate 106, 113 NMOS Transistor 107, 107 Inverter 108, 115 Inverted word driver 201 Memory circuit 202 BIST
203, 204 clock buffer

Claims (11)

A memory cell having a plurality of word lines corresponding to a plurality of ports;
A control circuit that activates a word line corresponding to each of the plurality of ports by a timing signal corresponding to each of the plurality of ports;
With
The semiconductor memory device, wherein the control circuit activates the plurality of word lines by one of the timing signals in accordance with an input test control signal. A semiconductor memory device including a cell having a plurality of ports,
A plurality of test control signals corresponding to a plurality of timing signals for controlling activation timings of word lines of a plurality of ports,
For cells with multiple ports selected
When one of the plurality of test control signals corresponding to the plurality of selected ports is in an active state and the remaining test control signals are in an inactive state,
Masking a timing signal corresponding to the test control signal in an inactive state;
A semiconductor comprising: a circuit for controlling to activate word lines of the plurality of selected ports in response to one timing signal corresponding to one test control signal in an active state Storage device.   When the plurality of test control signals corresponding to the selected plurality of ports are all inactive, activation of word lines of the plurality of ports is performed based on a plurality of timing signals respectively corresponding to the plurality of test control signals. 3. The semiconductor memory device according to claim 2, wherein each of the steps is performed independently. Memory cells connected to the first and second word lines corresponding to at least the first and second ports, respectively.
A control circuit for activating a first word line by a first clock signal corresponding to the first port and activating a second word line by a second clock signal corresponding to the second port; ,
With
The control circuit activates the first word line and the second word line by the first clock signal or the second clock signal in accordance with an input test control signal. A semiconductor memory device. A semiconductor memory device comprising at least cells connected to word lines of first and second ports,
First and second test control signals corresponding to the first and second clock signals used for controlling the activation timing of the word lines of the first and second ports, respectively.
For cells in which the first and second ports are selected,
When the first test control signal is in an active state and the second test control signal is in an inactive state, the second clock signal is masked and in response to the first clock signal, Controlling to activate the first word line and the second word line;
When the second test control signal is active and the first test control signal is inactive, the first clock signal is masked and in response to the second clock signal, A circuit for controlling to activate the first word line and the second word line;
A semiconductor memory device comprising:   When the first and second test control signals are both inactive for the cells for which the first and second ports are selected, the first and second clock signals are used to determine the first and second clock signals. 6. The semiconductor memory device according to claim 5, wherein activation of the second word line is controlled independently. The first clock signal and the second test control signal are input, and when the second test control signal is in an inactive state, the first clock signal is output as a first internal clock signal, A first circuit that does not transmit the first clock signal and fixes the first internal clock signal to an inactive state when the second test control signal is in an active state;
Inputting the second clock signal and the first test control signal, and outputting the second clock signal as a second internal clock signal when the first test control signal is in an inactive state; A second circuit for fixing the second internal clock signal to an inactive state without transmitting the second clock signal when the first test control signal is in an active state;
A first switch that inputs the first internal clock signal from the first circuit, turns on when the address selection signal of the first port is in a selected state, and transmits and outputs the first internal clock signal When,
A second switch that inputs the second internal clock signal from the second circuit, turns on when the address selection signal of the second port is in a selected state, and transmits and outputs the second internal clock signal When,
When the second test control signal and the output signal of the second switch are input, when one or both of the inputs are inactive, an inactive signal is output, and when both inputs are active A first logic circuit for outputting an active signal;
A second logic circuit that receives the output signal of the first logic circuit and the output signal of the first switch, and outputs the other when one of the inputs is inactive;
A first word driver for receiving an output signal of the second logic circuit and driving a word line of a first port;
When the first test control signal and the output signal of the first switch are input, when one or both of the inputs are inactive, an inactive signal is output, and when both inputs are active A third logic circuit for outputting an active signal;
A fourth logic circuit that inputs an output signal of the third logic circuit and an output signal of the second switch, and outputs the other when one of the inputs is inactive;
A second word driver for receiving an output signal of the fourth logic circuit and driving a word line of a second port;
The semiconductor memory device according to claim 6, further comprising: Each of the first logic circuit and the third logic circuit comprises a logical product (AND) circuit;
Each of the second logic circuit and the fourth logic circuit comprises a NOR circuit (NOR),
8. The semiconductor memory device according to claim 7, wherein each of said first word driver and said second word driver comprises an inverting driver. The cell is
Two inverters whose inputs and outputs are cross-connected at the first and second nodes;
First and second access transistors inserted between the first node and the bit lines of the first and second ports, respectively, and having control terminals connected to the word lines of the first and second ports, respectively. When,
A third node is inserted between the second node and a bit line complementary to the bit line of the first and second ports, and a control terminal is connected to the word line of the first and second ports, respectively. A fourth access transistor;
3. The semiconductor memory device according to claim 2, comprising a static type cell including As the timing signal, an input clock signal is used,
The selected word line is activated in response to the clock signal,
When the test control signal of one of the first and second ports is activated at the rise of the word line on the same row, the word line of the other port is also the word line on the one port side. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is driven at the same timing as the rising timing of. A test method for a semiconductor memory device including a cell connected to a word line of at least first and second ports,
First and second test control signals corresponding to the first and second clock signals for controlling the activation timing of the word lines of the first and second ports, respectively, are prepared.
For cells for which the first and second ports are selected,
When the first test control signal is in an active state and the second test control signal is in an inactive state,
The second clock signal is masked, the first and second word lines are started at the same timing in response to the first clock signal, and a cell is formed from the bit lines of the first and second ports. Read data simultaneously,
When the second test control signal is in an active state and the first test control signal is in an inactive state, the first clock signal is masked, and the second clock signal is responsive to the second clock signal. The first and second word lines are started at the same timing, and cell data is read simultaneously from the bit lines of the first and second ports.
A test method for a semiconductor memory device, comprising a step.

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