JP2008281536A - Image processing apparatus, image processing program, and imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processing apparatus that can avoid increase of the circuit scale and suppress the reduction of using efficiency and the reduction of processing speed when a defect of a point and line of a display panel is detected. <P>SOLUTION: This image processing apparatus is provided with: a perpendicular memory address control circuit (for input) 23a for setting, every perpendicular direction cn, addresses where image data for one horizontal line is read from display panel image data of an image memory 12; a line buffer memory unit having v sets of h line buffer memories 24, as one set, for continuously storing each pixel data of ((h-1)×cm+1) of one horizontal line; an image memory control circuit 21 for sequentially reading image data of a plurality of horizontal lines from the image memory 12 line by line, and storing them in the line buffer memories 24; a comparing operation processing circuit 25 for performing comparison operation between pixels using pixel data for comparison operation output from the line buffer memories 24; and the image memory 12 for storing the operation result. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an image processing device, an image processing program, and an imaging device for detecting a defect in a display panel of a flat panel display device.

  Main defects of display devices using flat panels such as liquid crystal displays, plasma displays, and liquid crystal projectors are point defects, which are defects of each pixel of the flat panel, and short-circuiting, contact failure, and driving of adjacent signal lines. There is a line defect defect due to a driver element defect.

  In order to detect such defects, many methods for detecting a defective portion of a display device using image processing have been conventionally devised.

  As one method for detecting a point / line defect such as a flat panel using the above image processing, for example, a predetermined display pattern is imaged for one screen with a camera, and then shading correction is performed to obtain a predetermined first threshold value or more. There is a method of detecting a luminance of a black spot defect as a black spot defect.

  Here, the shading correction means correcting the entire image so that the average brightness is uniform, and the necessity of performing the shading correction is as follows.

  In order to perform image processing, it is first necessary to capture an image of a display state by capturing an image of a display device with an image capturing device such as a camera. Thus, when a large flat panel is imaged by an imaging device such as a camera, shading occurs due to the aberration of the camera lens and the difference in distance from the camera lens to the center and end of the large flat panel. That is, as shown by the solid line and the rough broken line in FIGS. 22A, 22B, and 22C, the amount of light decreases as the distance increases. In the case of imaging a transmissive liquid crystal panel, by arranging a plurality of backlights, as shown by fine broken lines in FIGS. 22A, 22B, and 22C, luminance unevenness of the entire liquid crystal panel occurs. Therefore, in order to improve the detection accuracy of the point / line defect, it is necessary to use shading correction or other correction means.

  Next, as another method for detecting a point / line defect such as a flat panel using the image processing, there is a method disclosed in Patent Document 1, for example. In the screen inspection apparatus disclosed in Patent Literature 1, after imaging two screens of a white lighting display pattern and a black lighting display pattern with a camera and calculating a difference image between the white lighting display pattern and the black lighting display pattern, A method is adopted in which a luminance equal to or higher than a predetermined first threshold is used as a bright spot defect, and a luminance equal to or lower than a predetermined second threshold is detected as a black spot defect.

  Specifically, as shown in FIG. 23, first, the image input unit 501 captures two screens of a fully lit (white lit) display pattern and a fully unlit (black lit) display pattern, The entire lighting pattern image memory 502 and the all lighting pattern image memory 503 are stored. Next, the image comparison circuit unit 504 performs subtraction processing on each pixel from the contents of each image stored in the all lighting pattern image memory 502 and all lighting pattern image memory 503, and smoothing processing 505 performs noise removal. Therefore, smoothing processing is performed.

  Next, a black point defect detection binarization circuit unit 506 for extracting a pixel having a low luminance value with respect to the black point detection threshold, and a pixel for extracting a pixel having a high luminance value with respect to the bright point detection threshold. It relays to the binarization circuit unit 507 for detecting bright spot defects, and the processing results of the binarization circuit unit 506 for detecting black spot defects and the binarization circuit unit 507 for detecting bright spot defects are transferred to the comparison circuit unit 508 for defect detection. To extract.

  Next, an AND process is performed on the image data of the mask pattern image memory 509 and the image data of the defect detection comparison circuit unit 508 that actually store the detection effective area, with respect to the result obtained by the defect detection comparison circuit unit 508. By performing the above, it is possible to obtain a defect image of only the detection effective area in the image cutout unit 511.

  Thereafter, the noise removal processing unit 511 performs noise removal processing on the defect image using an image filter such as expansion / contraction processing, and the region detection circuit unit 512 extracts the defective region from the feature amount of the defective portion, The determination circuit unit 513 determines pass / fail.

  FIG. 24 explains the above processing contents by taking image data as an example.

  As shown in the figure, when the black spot defects 550a and 550b exist for the all lighting display pattern 552 and the bright spot defect 550c exists for the all lighting display pattern 553, the all lighting display pattern 552 is completely turned off. The image data of the display pattern 553 is subtracted and smoothed, and binarization processing for black spot detection and binarization processing for bright spot detection are performed. Become. Next, the defect image 550a / 550b / 550c can be obtained on the image memory 556 by performing AND processing from the mask pattern 555 in which the detection area effective area 560 is stored in advance and the image 554 from which the defect portion is extracted. .

  Furthermore, as a conventional method for detecting another line defect, for example, there is a panel line defect detection method and apparatus disclosed in Patent Document 2.

  In this panel line defect detection method and apparatus, in order to perform shading correction on an image captured by a camera, first, a plurality of non-defective flat panel images are sampled in advance, and each pixel of the plurality of images is averaged. By flattening the average image with a smoothing filter, a reference image for performing shading correction is created. Thereafter, arithmetic processing such as subtraction of the reference image from the image to be inspected is performed to generate a corrected image. Next, edge correction filters (horizontal and vertical differential filters) in the horizontal direction and vertical direction are performed on the image to be corrected, and the filter calculation results in each direction are integrated. Then, in order to suppress the luminance gradation value fluctuation part caused by the difference in luminance value between the flat panel picture element part and the non-display part between the picture elements, filter processing such as moving average is performed on the integrated result Is used for planarization.

  Thereafter, the line defect is detected by calculating the feature amount of the portion where the peak occurs based on the calculation result.

  On the other hand, as an image filter processing method based on a threshold value indicating whether or not the pixel is defective after shading correction, for example, there is a method disclosed in Patent Document 3.

  This Patent Document 3 discloses an image processing apparatus that performs high-speed processing using a line buffer memory when performing arithmetic processing. In this type of image processing apparatus, when the entire display panel is composed of M × N (horizontal × vertical) pixels, as shown in FIG. 25, for example 3 × which is an adjacent m × n (horizontal × vertical) pixel region. When performing the image filter processing of the three-pixel region, as shown in FIG. 26, the gray image data of one horizontal scanning line is read from the image memory 601 storing the gray image data of the entire display panel, and the read one horizontal scan is performed. N line buffer memories 602 having an M pixel length for temporarily storing line grayscale image data ((n + 1) lines in Patent Document 3) are arranged, and the grayscale image data for one pixel from each of the line buffer memories 602a, 602b, and 602c. Are sequentially read out, whereby predetermined image filter processing is performed by pipeline processing.

  That is, conventionally, when performing image filter processing of image data of the entire display panel, when image filter processing is performed while reading data one pixel at a time in the horizontal direction of the image memory from the left end, The processing is performed up to the final image memory position while sequentially reading data from the left end image memory below one vertical line.

When calculating one pixel of an adjacent 3 × 3 image filter, for example, it is necessary to read image data for nine pixels from the image memory. However, every time image data for nine pixels is read, processing is performed. ineffective. Therefore, when the image data is read, the image data read from the image memory is sequentially stored in the line buffer memory, and the stored image data is sequentially read from the line buffer, thereby improving the access efficiency of the image memory, and Efficiency is improved by line processing.
JP 7-175442 A (published July 14, 1995) JP 2005-172559 A (published June 30, 2005) JP 61-62187 (published March 31, 1986) JP 2001-251636 A (published September 14, 2001) Japanese Patent Laying-Open No. 2005-123946 (published on May 12, 2005) Japanese Patent Laid-Open No. 10-271529 (released on October 9, 1998) Japanese Unexamined Patent Publication No. 2000-197065 (released on July 14, 2000) JP 2004-48709 A (published July 14, 2004)

  However, the conventional image processing apparatus has the following problems.

  That is, when defect detection is performed with image data for one screen in the conventional method, it is necessary to perform shading correction using a smoothing filter or the like with a large pixel size. The calculation accuracy of the image filter is lowered, and the shading correction tends to be incomplete. Further, when the binarization process is performed with the same threshold on the entire screen, the luminance result between the pixels of the flat panel varies, and the processing result is not stable.

  On the other hand, when performing defect detection processing after performing differential image calculation of two screens as in Patent Document 1, extra imaging time is required, resulting in a longer processing time. In particular, when imaging image data of a flat panel having a large pixel size, an area sensor type imaging apparatus needs to divide into a plurality of images in order to capture the entire flat panel. Further, in the line sensor type imaging apparatus, imaging is performed while moving the imaging apparatus or the flat panel with the stage mechanism, and image data is generated. Therefore, an imaging time of several seconds is required to generate the image data.

  Further, when the difference image is used, the shading amount is reduced but not eliminated as compared with the case where defect detection is performed using image data for one screen. As a result, in order to improve the detection accuracy, it is necessary to perform a shading correction process, which increases the processing time. Here, a large shading amount occurs for an image having a bright luminance gray value, whereas a shading amount tends to be small for an image having a low luminance gray value. As a result, even if the difference calculation is performed, the shading amount cannot be completely corrected.

  In addition, in the case of a method of performing correction using a reference image for shading correction as in Patent Document 2, a plurality of non-defective flat panel images are sampled in advance, each pixel of the plurality of images is averaged, and the average image is smoothed. It is necessary to generate a reference image by flattening with a conversion filter. In this case, when taking an image to be inspected, if the imaging conditions change due to changes over time such as backlight or external illumination, maintenance of the measuring device, etc., it is necessary to update the reference image again. It is necessary to take a plurality of sample images and update the database again.

  In addition, when line defect detection is performed using a differential filter for edge detection, a luminance grayscale value generated due to a difference in luminance value between the pixel portion of the flat panel and the non-display portion between pixels due to the characteristics of the filter. As a result, it is necessary to process using a smoothing filter in order to suppress the influence of the fluctuation part, which causes a reduction in detection accuracy of the defective part due to the smoothing.

  Further, in order to perform good imaging, it is necessary to perform imaging by assigning about 8 to 10 or more pixels of the imaging device in the horizontal direction and the vertical direction for one pixel of the flat panel. As the flat panel becomes larger, the number of allocated pixels of the imaging device tends to decrease due to processing speed and device cost factors. In this case, even when the adjacent pixels having the same luminance are imaged, the resolution of the image sensor is insufficient, so that moire such as interference fringes occurs and an image having the same luminance value can be obtained. Deterioration of defect detection accuracy occurs.

  In addition, in the hardware configuration, when the interval between the pixels to be subjected to the filter operation is large, if the conventional pipeline processing is used, the number of stages such as the line buffer memory is increased and the buffer length is increased. Becomes larger, which increases costs.

  On the other hand, when there is no line buffer memory, speeding up by pipeline processing cannot be expected. For example, in the case of a 3 × 3 image filter, the number of times image data is read in the pipeline processing is one, whereas the line buffer memory When there is no image data, the number of times of reading the image data is nine times, and the number of times of reading the image data is nine times, so that the processing speed is lowered.

  In addition, when processing a large image size by software processing, a large amount of cache memory is required. Therefore, when data does not fit in the cache memory, the processing capability decreases.

  That is, in order to perform a 3 × 3 image filter by pipeline processing, a temporary storage circuit for image data is usually formed by three line buffer memories each having a horizontal image size length and nine latch circuits as in Patent Document 3. Is often configured.

  However, unlike the adjacent 3 × 3 pixel size filter processing, when performing the filter processing at positions spaced apart at a constant interval in the horizontal and vertical directions, in the pipeline processing system using the line buffer memory, the line buffer memory However, the number of stages of the line buffer memory must be increased, and the circuit scale increases. For example, as shown in FIG. 4, which is an explanatory diagram of the present embodiment, the center and peripheral portions are effective at every three pixels (= cm) in the horizontal direction and every four pixels (= cn) in the vertical direction. When processing an image filter having an area of 3 × 3 pixels, an image filter having an apparent 7 × 9 pixel size ((2 × cm + 1 = 2 × 3 + 1 = 7) × (2 × cn + 1 = 2 × 4 + 1 = 9)) Therefore, nine line buffer memories having a horizontal image size length are required.

  For example, in Patent Document 4, for each RGB CCD pixel, based on the pixel data of three consecutive peripheral pixels of the same color as the inspection target pixel for each color, the median value of the peripheral pixel data and the inspection target pixel data To determine whether the pixel is defective.

  Also in Patent Document 5, detection determination of a defective pixel is performed based on the same color pixel that exists in a peripheral range of a certain range with the target pixel.

  However, in both Patent Document 4 and Patent Document 5, lines that are not related to the target pixel and a certain range of peripheral pixels are also read in order.

  The present invention has been made in view of the above-described conventional problems, and its purpose is to increase the circuit scale when pipeline processing is performed using a line buffer memory in order to detect a dot / line defect of a display panel. An object of the present invention is to provide an image processing apparatus, an image processing program, and an imaging apparatus that can prevent an increase and suppress a decrease in use efficiency and a decrease in processing speed.

  In order to solve the above problem, the image processing apparatus of the present invention uses the horizontal operation pixel count h for each number of pixels cm (cm is a positive integer) in the horizontal direction from the image data of the display panel stored in the image memory. (H is an integer equal to or greater than 2) A pixel composed of the number of pixels ((h−1) × cm + 1) in the horizontal calculation area having a pixel for comparison calculation, and every pixel number cn (cn is a positive integer) in the vertical direction Are composed of a pixel matrix with pixels composed of the number of pixels to be operated vertically ((v−1) × cn + 1) having the number v of pixels to be operated vertically v (v is an integer of 2 or more). Displayed by performing comparison calculation processing for each comparison calculation target pixel of the horizontal calculation pixel number h × vertical calculation pixel number v with respect to the comparison calculation target region (at least one of cm or cn is an integer of 2 or more). Detects point and line defects on panels A vertical memory for setting an address for reading image data for one horizontal line from image data of a display panel stored in the image memory so as to be every number of pixels cn in the vertical direction Address control means, and a line buffer memory of h number of horizontal operation pixels for storing each pixel data of at least the number of pixels ((h−1) × cm + 1) of the horizontal operation region in the horizontal line is 1 As a set, a line buffer memory unit provided with the above-mentioned number v of vertical operation pixels, and each pixel data of a horizontal line at an address set by the vertical memory address control means for a plurality of lines from the image memory for each line. Image memory input control means for sequentially reading and storing in the line buffer memory, and the plurality of line buffers. A comparison calculation processing means for performing inter-pixel comparison calculation using pixel data of the comparison calculation target pixels respectively output from the buffer memory, and a defect information storing image memory for storing calculation results by the comparison calculation processing means are provided. It is characterized by having.

  According to the above-described invention, the image processing apparatus uses the horizontal operation pixel number h (h is 2 for each pixel number cm (cm is a positive integer) in the horizontal direction from the image data of the display panel stored in the image memory. The number of pixels in the horizontal calculation area having (number of integers) comparison target pixels ((h−1) × cm + 1) and the vertical calculation for each number of pixels cn (cn is a positive integer) in the vertical direction. Comparison operation target area configured by a pixel matrix having pixels (v-1) × cn + 1) having a number v of pixels (v is an integer of 2 or more) comparison operation target pixels. (At least one of cm or cn is an integer greater than or equal to 2), by performing comparison calculation processing of each pixel to be compared of the number of horizontal calculation pixels h × vertical calculation pixel number v, Detect line defects.

  In this case, conventionally, when the pixel data is to be read into the line buffer memory, a line buffer memory having a number of pixels ((v−1) × cn + 1) in the vertical operation region is required. Therefore, it is necessary to increase the number of stages of the line buffer memory even though the utilization efficiency of the line buffer memory is lowered, and there is a problem that the circuit scale is increased.

  On the other hand, in the present invention, a line buffer memory having h number of horizontal operation pixels for continuously storing each pixel data of at least the number of horizontal operation region pixels ((h−1) × cm + 1) in one horizontal line. As a set, a line buffer memory unit is provided in which the above-mentioned number v of the vertical operand pixels is provided. Then, the vertical memory address control means sets an address for reading image data for one horizontal line from the image data of the display panel stored in the image memory so as to be every number of pixels cn in the vertical direction. Further, the image memory input control means reads each pixel data of the horizontal line at the address set by the vertical memory address control means from the image memory for a plurality of lines in order, and stores them in the line buffer memory in order. .

  As a result, each pixel to be compared can be extracted from each line buffer memory in the number h of horizontal operand pixels × the number of vertical operand pixels v, and the comparison calculation processing means can output each of the plurality of line buffer memories. The inter-pixel comparison calculation is performed using the pixel data of the comparison calculation target pixel. The calculation result is stored in the defect information storage image memory.

  As a result, when detecting a point / line defect on the display panel, since the comparison calculation processing is performed in a small area, the fluctuation portion of the luminance density value between pixels in the display panel, the lens characteristics of the camera, the illumination conditions, etc. The shading amount generated due to the factor can be removed at the same time, and the detection accuracy of defect detection can be improved.

  That is, since the comparison operation is performed in an area where the amount of shading is small, the shading is within a negligible range. In addition, since the detection is performed by relative comparison, the shading amount with a small amount of generation is removed by calculation.

  In addition, defect detection can be performed on a single image without using large-size filter processing, shading correction calculation, and processing by pipelining. Can be planned.

  In addition, the number of pixels in the horizontal operation region ((h−1) × cm + 1) and the number of vertical operation pixels v (v is an integer of 2 or more) for each pixel number cn (cn is a positive integer) in the vertical direction. ) At least one of (cm or cn) with respect to a comparison calculation target area configured by a pixel matrix with a number of vertical calculation target area pixels ((v−1) × cn + 1) having a comparison calculation target pixel. Is an integer greater than or equal to 2), and pipeline processing can be performed with the size of the number of horizontal operation pixels h × the number of vertical operation pixels v, so that the circuit scale can be reduced and the operation processing speed can be increased.

  Furthermore, in the present invention, since the comparison calculation process is performed in a small area, the fluctuation portion of the luminance gray value between the pixels of the display panel and the shading amount generated due to factors such as the lens characteristics of the camera and illumination conditions are simultaneously removed. This improves the detection accuracy of defect detection. In addition, since the defect detection is performed with one image without using a large-size filter process, the calculation process can be speeded up.

  A similar technique is disclosed in Patent Document 6, for example. However, Patent Document 6 is different from the present invention in which rearrangement is not performed in that, in order to reduce the line buffer memory, first, the same color is rearranged into blocks. Thus, the present invention does not require a rearranging memory and can avoid an increase in memory.

  Further, for example, Patent Document 7 has a description “read a signal from a color filter of the same color as the color filter of the horizontal line skipping (m + 2) horizontal line into a register”. Therefore, the point of inputting to the line buffer memory at a glance is the same as the present invention. However, the arrangement of the color filters is special, there are only two sets of GBGB and RGRG, and two sets of line buffer memories are provided for these two sets. Eventually, although it is input to the line buffer memory in a jump, it is different from the present invention in that all lines are written and read, and there is no consideration in the horizontal direction.

  Further, in Patent Document 8, there is a description that after determining whether or not a line needs to be stored in the buffer, the line determined to be unnecessary is skipped and input to the buffer.

  On the other hand, the invention of the present application skips without determining whether or not the line needs to be stored, and does not perform a thinning process, and all pixel data is an object of calculation. Different from 8.

  In the image processing apparatus of the present invention, it is preferable that the defect information storing image memory is an image memory storing image data of the display panel.

  As a result, the defect information storing image memory is used also as the image memory storing the image data of the original display panel, so that the memory can be reduced.

  In the image processing apparatus according to the present invention, the comparison calculation processing unit may include at least 2 × 2 horizontal calculation pixels for each comparison calculation target pixel of the horizontal calculation pixel count h × vertical calculation pixel count v. It is preferable to perform inter-pixel comparison calculation for each comparison calculation target pixel pattern of number h × vertical calculation target pixel number v.

  As a result, even if not all of the comparison target pixels of horizontal calculation pixel number h × vertical calculation pixel number v are prepared at the edge of the display panel, the comparison calculation processing means can perform comparison calculation target of at least 2 × 2 or more. An inter-pixel comparison operation can be performed using pixels.

  In the image processing apparatus of the present invention, it is preferable that buffer length changing means for changing the buffer length of each line buffer memory is provided.

  In this way, by providing the buffer length changing means for changing the buffer length of each line buffer memory, comparison calculation by each display pixel of an arbitrary display panel in the horizontal direction can be performed without adding and changing hardware. It can be carried out.

  In the image processing apparatus of the present invention, it is preferable that a pixel number cn changing unit for changing the pixel number cn at the address set by the vertical memory address control unit is provided.

  As described above, by providing the pixel number cn changing unit for changing the pixel number cn at the address set by the vertical memory address control unit, any display panel in the vertical direction can be provided without adding or changing hardware. A comparison operation by each display pixel can be performed.

  In the image processing apparatus of the present invention, it is possible to provide fixed length setting means for setting the buffer length of the line buffer memory to a fixed length.

  Thereby, the comparison calculation processing of each comparison calculation target pixel in only the vertical direction of the number of horizontal calculation pixels 1 × the number of vertical calculation pixels v can be performed. Therefore, the hardware configuration can be simplified.

  In the image processing apparatus of the present invention, the bus width of the line buffer memory is expanded to a bus width n times (n: an integer equal to or greater than 2) the bit length representing one pixel, and the comparison operation is performed. The processing means preferably includes n sets of comparison operation processing circuits that perform an inter-pixel comparison operation corresponding to the output of each pixel data by the line buffer memory having the bus width of n times.

  Note that, as described above, the bus width is n times (n: an integer equal to or greater than 2) the bit length representing one pixel because one pixel is not necessarily represented by one byte. For example, when one pixel is expressed by 1 byte, it is n times the bus width for 1 byte, but when 1 pixel is expressed by 8 bytes, it is n times the bus width for 8 bytes.

  As a result, the number of accesses to the image memory can be reduced to 1 / n times, and the comparison calculation processing speed is increased n times, so that high speed can be achieved by parallel processing.

  In the image processing device of the present invention, the comparison calculation target region corresponds to the image data in which the number of imaging pixels in the horizontal direction and the vertical direction of the imaging pixels by the imaging device is captured at an interval that is an integer multiple of the number of display pixels. Horizontal / vertical ratio setting means is provided for setting the number of pixels in the horizontal direction cm and the number of vertical pixels cn in the display panel to be integral multiples of the number of display pixels in the horizontal direction and the number of display pixels in the vertical direction. It is preferable that

  Thus, when detecting a point / line defect on the display panel, in order to perform good imaging normally, the pixels of the imaging device are usually arranged in the horizontal and vertical directions with respect to one pixel of the display panel. Although it is necessary to perform imaging by assigning 8 to 10 or more numbers, it is possible to detect defects even by assigning 2 to 3 pixels.

  In the image processing device according to the present invention, the number of pixels in the vertical direction of the image pickup pixels by the image pickup device corresponds to the image data picked up at an integer multiple interval of the number of display pixels, in the vertical direction in the comparison calculation target region. Preferably, there is provided a vertical direction ratio setting means for setting the number of pixels cn to be an integral multiple of the number of display pixels in the vertical direction of the display panel.

  As a result, when detecting a point / line defect on the display panel, for example, when the entire surface is the same pattern, such as a white display pattern, or the same pattern with respect to the vertical direction of the captured image, the comparison calculation process only in the vertical direction However, defect detection can be performed by assigning 2 to 3 pixels as the number of pixels of the imaging device.

  In order to solve the above problems, an image processing program of the present invention is an image processing program for operating the above-described image processing apparatus, and is characterized by causing a computer to function as each of the above-described means.

  As a result, when pipeline processing is performed using a line buffer memory to detect a dot / line defect of a display panel, an image that can avoid an increase in circuit scale and suppress a decrease in use efficiency and a decrease in processing speed A processing program can be provided.

  In order to solve the above problems, the image pickup apparatus of the present invention uses the horizontal operation pixel number h (h is 2 or more) for each pixel number cm (cm is a positive integer) in the horizontal direction from image data obtained by photographing the display panel. Of pixels) having the number of pixels in the horizontal calculation area ((h−1) × cm + 1) having the comparison target pixels, and the vertical calculation pixels for each number of pixels cn (cn is a positive integer) in the vertical direction. In a comparison calculation target region configured by a pixel matrix of pixels having a number v (v is an integer of 2 or more) comparison calculation target pixels and a vertical calculation target region pixel number ((v−1) × cn + 1) On the other hand (at least one of cm or cn is an integer greater than or equal to 2), by performing the comparison calculation process for each pixel to be compared of the number of horizontal calculation pixels h × vertical calculation pixel number v, the dot / line of the display panel An imaging device that detects defects A sensor composed of a line sensor or a TDI sensor arranged at equal intervals for storing image data of the photographed display panel for each line, and a plurality of sensors storing the image data for each pixel number cn in the vertical direction. A plurality of multiplexers to be selected, conversion means for digitally converting the image data of the sensors selected by the multiplexers, and a variable-length line buffer memory capable of setting the pixel data to be stored to the number of pixels cm A line buffer memory unit provided for the number of vertical arithmetic pixels v as one set (the number of horizontal arithmetic pixels h−1) and image data of the sensor selected by the multiplexer are sequentially converted through the conversion means. Timing control means for sequentially storing in the line buffer memory, and images converted by the conversion means. Comparison operation processing means for performing inter-pixel comparison using data and pixel data output from each line buffer memory, defect detection means for detecting a defective portion from a calculation result by the comparison operation processing means, and the defect An external output means for outputting the detection result of the detection means to the outside is provided.

  According to the above-described invention, the imaging apparatus can calculate the horizontal operation pixel number h (h is 2 or more) for each pixel number cm (cm is a positive integer) in the horizontal direction from the image data of the display panel stored in the image memory. Of pixels) having the number of pixels in the horizontal calculation area ((h−1) × cm + 1) having the comparison target pixels, and the vertical calculation pixels for each number of pixels cn (cn is a positive integer) in the vertical direction. In a comparison calculation target region configured by a pixel matrix of pixels having a number v (v is an integer of 2 or more) comparison calculation target pixels and a vertical calculation target region pixel number ((v−1) × cn + 1) On the other hand (at least one of cm or cn is an integer greater than or equal to 2), by performing the comparison calculation process for each pixel to be compared of the number of horizontal calculation pixels h × vertical calculation pixel number v, the dot / line of the display panel Detect defects.

  In this case, conventionally, when the pixel data is to be read into the line buffer memory, a line buffer memory having a number of pixels ((v−1) × cn + 1) in the vertical operation region is required. Therefore, it is necessary to increase the number of stages of the line buffer memory even though the utilization efficiency of the line buffer memory is lowered, and there is a problem that the circuit scale is increased.

  On the other hand, in the present invention, there is provided a sensor composed of a line sensor or a TDI sensor arranged at equal intervals for storing the image data of the photographed display panel for each line.

  In addition, a plurality of multiplexers are provided for selecting a plurality of sensors storing image data so that the number of pixels is cn in the vertical direction, and the image data of the sensors selected by each multiplexer is digitally converted. Conversion unit for performing the above operation and the number of pixels to be stored in the variable length line buffer memory capable of setting the number of pixels in cm (horizontal operation pixel number h-1) are set as one set, and the number of vertical operation pixels is set to v. And a line buffer memory unit.

  Accordingly, the timing control means sequentially stores the image data of the sensor selected by the multiplexer in the line buffer memory through the conversion means in order, so that the number of horizontal operation pixels from each conversion means and the variable length line buffer memory. Each comparison calculation target pixel of h × vertical calculation target pixel number v can be taken out, and the comparison calculation processing unit uses the image data converted by the conversion unit and the pixel data output from each line buffer memory. The pixel comparison operation is performed. Then, the defect detection means detects the defect portion from the calculation result by the comparison calculation processing means, and the external output means outputs the detection result by the defect detection means to the outside.

  As a result, when detecting a point / line defect on the display panel, since the comparison calculation processing is performed in a small area, the fluctuation portion of the luminance density value between pixels in the display panel, the lens characteristics of the camera, the illumination conditions, etc. The shading amount generated due to the factor can be removed at the same time, and the detection accuracy of defect detection can be improved.

  In addition, since defect detection can be performed on one image without performing shading correction calculation, and further processing by pipelining can be performed, the speed of defect detection processing can be increased.

  Further, the number of pixels in the horizontal calculation area ((h−1) × cm + 1) and the number of vertical calculation pixels v (v is an integer of 2 or more) for each pixel number cn (cn is a positive integer) in the vertical direction. ) At least one of (cm or cn) with respect to a comparison calculation target area configured by a pixel matrix with a number of vertical calculation target area pixels ((v−1) × cn + 1) having a comparison calculation target pixel. Is an integer greater than or equal to 2), and pipeline processing can be performed with the size of the number of horizontal operation pixels h × the number of vertical operation pixels v, so that the circuit scale can be reduced and the operation processing speed can be increased.

  In addition, even when the interval between pixels to be compared is large, the sensor substitutes for the line buffer memory, so that a large-sized line buffer memory (1 to 16 k pixels) is not required, and the circuit scale can be reduced. , Can reduce costs.

  Further, a variable-length line buffer memory capable of setting the pixel data to be stored to the number of pixels cm, and a plurality of multiplexers that are selected so as to be every number of pixels cn in the vertical direction are provided. The area can be set flexibly.

  In addition, since defect detection can be performed simultaneously with imaging within the imaging apparatus, arithmetic processing in real time is possible, and the circuit configuration can be simplified as compared with a configuration in which the imaging apparatus and the defect detection apparatus are combined.

  In addition, by making a self-diagnosis function for detecting a defect of the sensor element on the same chip as the sensor and the arithmetic processing circuit unit by a CMOS process, for example, the circuit can be easily downsized.

  In the imaging apparatus of the present invention, each of the sensors is a line sensor, a shift register that collectively stores pixel data of the line sensor, and whether to transfer the pixel data from the sensor to an adjacent sensor. It is preferable to include switching means for switching.

  As a result, by arranging a plurality of blocks adjacent to each other as a single block including a line sensor, a shift register, and a switching unit, each sensor block can be used as a function as a TDI sensor.

  As a result, the accumulation time for imaging can be shortened, and the influence of flicker caused by the lighting panel cycle can be reduced.

  In the image pickup apparatus of the present invention, it is preferable that selection control means for controlling the selection of the sensor in the multiplexer to be an arbitrary sensor is provided.

  As a result, the selection control means dynamically switches the multiplexer arbitrarily, thereby enabling detection of self-defects in the line sensor element and imaging as an area sensor.

  In the imaging apparatus of the present invention, the plurality of sensors are mounted on a plurality of support bases, respectively, an optical unit that projects the same captured image in the direction of the plurality of support bases, and the plurality of the plurality of sensors. It is preferable to include a moving means for moving the support base on which the sensor is mounted by an integral multiple of the imaging pixel pitch with respect to the vertical direction of the captured image.

  As a result, even if the interval between the comparison calculation areas is increased, the interval in the vertical direction can be arbitrarily set by, for example, a support stage such as a microstage, so that an increase in the number of sensors can be suppressed.

  Further, the resolution of the picked-up image can be improved by performing interpolation / synthesis of the image by, for example, pixel shifting from the pick-up of the plurality of sensors mounted on the support base.

  In the imaging apparatus according to the aspect of the invention, the moving unit may be configured such that a support base on which the plurality of sensors is mounted has an imaging pixel pitch only in a vertical direction of the captured image or in both a horizontal direction and a vertical direction of the captured image. It is preferable that inter-pixel interpolation means is provided for interpolating and synthesizing the acquired pixel data of a plurality of sensors as inter-pixel interpolation data while moving by a real value multiple.

  As a result, the resolution of the captured image can be improved by performing interpolation and synthesis of the image by, for example, pixel shifting from the imaging of the plurality of sensors mounted on the support base.

  In the imaging apparatus according to the present invention, the external output unit may include a binarized display generating unit that performs binarized display of the pixel data of the defective portion extracted from the defect detecting unit, and pixel data of the defective portion. Based on the highlight display generating means for highlighting the defect peripheral portion, the pixel data binarized and displayed by the binarized display generating means, and the pixel in the defect peripheral portion highlighted by the highlight display generating means It is preferable to have pixel data combining means for generating a display image by combining data and other pixel data.

  Thereby, the output of a captured image and the highlight display output of a defective part can be performed. Accordingly, the defect of the display panel can be detected by the image pickup device alone, and the defect portion can be directly highlighted, for example, on a monitor or the like, so that the defect position can be easily reconfirmed by an inspection operator or a visual inspector. Can do.

  As described above, the image processing apparatus of the present invention has an address for reading image data for one horizontal line from the image data of the display panel stored in the image memory so that the address is every cn in the vertical direction. A vertical memory address control means to be set, and a line with h number of horizontal operation pixels for continuously storing each pixel data of at least the number of pixels in the horizontal operation area ((h−1) × cm + 1) in the horizontal line. One set of buffer memory, the line buffer memory unit provided with the number v of the vertical operation pixels, and each pixel data of the horizontal line at the address set by the vertical memory address control means for a plurality of lines from the image memory. Image memory input control means for sequentially reading image data for each line and storing them in the line buffer memory in order, A comparison calculation processing unit that performs inter-pixel comparison calculation using pixel data of the comparison calculation target pixels output from the line buffer memory, and a defect information storage image memory that stores a calculation result of the comparison calculation processing unit. It is provided.

  Further, as described above, the image processing program of the present invention is an image processing program for operating the above-described image processing apparatus, and causes a computer to function as each of the above-described means.

  In addition, as described above, the image pickup apparatus of the present invention stores the image data of the display panel that has been photographed and stores the image data with a sensor composed of a line sensor or a TDI sensor arranged at equal intervals. A plurality of multiplexers for selecting a plurality of sensors so that the number of pixels is cn in the vertical direction, conversion means for digitally converting image data of the sensors selected by the multiplexers, and pixel data to be stored as pixels A line buffer memory unit provided with the number of the vertical operation pixels v as a set of (the number of horizontal operation pixels h−1) in the variable length line buffer memory which can be set to several centimeters, and the multiplexer Timing control for sequentially storing the image data of the selected sensor in the line buffer memory sequentially through the conversion means A comparison calculation processing means for performing a pixel-to-pixel comparison calculation using the image data converted by the conversion means and the pixel data output from each line buffer memory, and a calculation result by the comparison calculation processing means. Defect detection means for detecting a defective portion and external output means for outputting the detection result by the defect detection means to the outside are provided.

  Therefore, when pipeline processing is performed using a line buffer memory to detect a dot / line defect of a display panel, an image that can avoid an increase in circuit scale and suppress a decrease in use efficiency and a decrease in processing speed There is an effect of providing a processing device, an image processing program, and an imaging device.

[Embodiment 1]
An embodiment of the present invention will be described with reference to FIGS. 1 to 11 as follows.

  The overall system configuration of the image processing apparatus according to the present embodiment will be described with reference to FIG. FIG. 2 shows a system configuration for detecting a defect in the flat panel 1 as a display panel of the liquid crystal panel display device. The image processing apparatus 10 according to the present embodiment detects defects in the flat panel 1 by inputting image data obtained by capturing the displayed measurement pattern of the flat panel 1 with the imaging apparatus 5 and performing image processing. It has become.

  As shown in FIG. 1, the image processing apparatus 10 includes an image input unit 11, an image memory 12, an image processing unit 20, an overall management unit 14, a measurement control unit 15, a pattern generator 16, and a backlight. A control unit 17 and a panel drive control circuit 18 are provided. The image processing apparatus 10 can be installed as a single unit when the CPU is incorporated, but when the personal computer or the like is used for an interface terminal or integrated management, the personal computer and the image processing apparatus 10 Will be connected. When the image processing apparatus 10 is a substrate, it is connected to an expansion slot of a personal computer.

  In order to detect each pixel defect in the flat panel 1, first, the measurement control unit 15 performs output control of a video signal for displaying a measurement pattern on the flat panel 1 on the pattern generator 16. Next, a video pattern is displayed on the flat panel 1 by the panel drive control circuit 18 based on the video signal. When a transmissive liquid crystal panel is used for the flat panel 1, the panel control unit 17 simultaneously turns on the panel illumination.

  Next, the displayed measurement pattern of the flat panel 1 is picked up by the image pickup device 5, and the image pickup signal is stored in the image memory 12 as a digitized grayscale image through the image input unit 11.

  Next, based on the data stored in the image memory 12, the image processing unit 20 performs arithmetic processing for detecting a defective part, and extracts the feature amount of the defective part. A pass / fail judgment of 1 is performed.

  The configuration of the image processing unit 20 according to the present embodiment will be described in detail with reference to FIG. FIG. 1 is a block diagram illustrating a configuration of the image processing unit 20.

  As shown in FIG. 1, the image processing unit 20 of the present embodiment includes an image memory control circuit 21 serving as an image memory input control unit that reads image data from the image memory 12 and stores the image data in the image memory 12. Line buffer memory (1,1) 24a, line buffer memory (1,2) 24b, line buffer memory (1,3) 24c, which are line buffer memories 24 such as shift registers, are read from the image memory 12; Line buffer memory (2,1) 24d, line buffer memory (2,2) 24e, line buffer memory (2,3) 24f, line buffer memory (3,1) 24g, line buffer memory (3,2) 24h, And a line buffer memory (3, 3) 24i and a comparison calculation process as a comparison calculation processing means for performing image filter processing. It includes a circuit 25, and an output line buffer memory 26 for storing temporarily in the line memory output result of the comparison processing circuit 25. The group of line buffer memories 24 constitutes a line buffer memory unit.

  The image memory 12 stores image data of all the pixels in the flat panel 1 photographed by the imaging device 5 and also stores the result of image processing by the image processing unit 20. In the present invention, the result of image processing does not necessarily need to be stored in the image memory 12, and can be stored in another defect information storing image memory if there is room in the memory.

  The image memory 12 is composed of, for example, a DDR / DDR2 memory. The DDR / DDR2 memory has advantages such as a large capacity, a low cost per bit, and high speed continuous data access, and has recently been used for personal computers and image memories. However, the DDR / DDR2 memory has a disadvantage in that the random access of data in units of bytes extremely reduces the memory access efficiency. This is because one memory access control first sets addresses in the memory in two steps, and then performs access control with 4 or 8 burst length (4 or 8 times consecutively, memory is accessed sequentially). is there. For example, one memory access control with 8 burst lengths in a commonly used 64-bit bus length (8 byte length) memory module is in units of 8 (bytes) × 8 (times) = 64 (bytes). For this reason, even if only 1-byte data access is required, it is necessary to perform access control for 64 bytes. Therefore, random access less than 64 bytes extremely deteriorates transfer efficiency. For this reason, in order to improve the access efficiency of the DDR / DDR2 memory, it is necessary to perform memory access as continuously as possible and to access at an integral multiple of one memory access.

  In order to compensate for this disadvantage, a CPU that supports a DDR / DDR2 memory usually incorporates a cache memory to compensate for this disadvantage. Further, when using the DDR / DDR2 memory as an image memory, control is performed so that continuous memory access is performed in order to perform data transfer as fast as possible.

  Also, in order to improve the processing efficiency in hardware, when reading or writing image data from the image memory 12 using a buffer memory or the like (usually faster access speed than the image memory), Temporarily store data. As a result, the number of accesses to the image memory 12 can be reduced, and other arithmetic processing circuits can be operated in parallel even during periods when the image memory 12 cannot be accessed.

  Thus, a buffer memory or the like is indispensable in order to increase the overall processing speed and efficiency.

  Next, the image memory control circuit 21 performs control to read image data from the image memory 12 and control to write the result of image processing by the image processing unit 20 into the image memory 12.

  As an input system control circuit for reading the image data stored in the image memory 12 in the image memory control circuit 21 from the image memory 12, an input image memory address control circuit 22 is provided. The memory address control circuit 22 has a vertical memory address control circuit (for input) 23a and a horizontal memory address control circuit (for input) 23b as vertical memory address control means.

  In the horizontal memory address control circuit (for input) 23b, the horizontal position for reading image data from the image memory 12 is counted up by increment (+1) sequentially from 1 to the number of horizontal pixels, and the horizontal position is calculated. The vertical memory address control circuit (for input) 23a calculates a vertical position from 1 to the number of vertical pixels for reading the image data. However, as a method for calculating the vertical position, the basic operation is not counting as simple as the horizontal position calculation but counting up with the number of vertical pixels cn. For example, as shown in FIG. 4B described later, when the vertical interval cn = 4, first, 1, 5, 9,..., 4n + 1 (n: positive integer) in order from the first line. In this order, counting up is performed within the range of the number of vertical pixels. If this is one cycle, then, the second cycle of 2, 6, 10,..., 4n + 2 is executed in order from the second line, and then the third, seventh in order from the third line. , 11,..., (4n + 3) is executed in the third cycle, and then the fourth cycle of 4, 8, 12,..., (4n + 4) is executed in order from the fourth line. Complete a series of direction counts.

  By performing such calculation, there are pixels to be compared in the vertical direction at intervals of 4 pixels (4 lines) on the image data, but line buffer memories (1, 2) 24a to 24i to be described later. In the above, data for three continuous lines is stored in the vertical direction, and it is possible to improve the efficiency of arithmetic processing and reduce the circuit scale.

  The input image memory address control circuit 22 synthesizes the positions of the vertical memory address control circuit (for input) 23a and the horizontal memory address control circuit (for input) 23b to actually read the read address of the image memory 12. Perform conversion.

  On the other hand, an output image memory address control circuit 27 is provided as a control circuit for writing the result of image processing by the image processing unit 20 in the image memory control circuit 21 to the image memory 12, and this output image memory The address control circuit 27 includes a vertical memory address control circuit (for output) 28a and a horizontal memory address control circuit (for output) 28b.

  The output image memory address control circuit 27, vertical memory address control circuit (for output) 28a, and horizontal memory address control circuit (for output) 28b are input image memory address control circuit 22 for input system, vertical memory address control. It has the same function as the circuit (input) 23a and the horizontal memory address control circuit (input) 23b.

  The image memory control circuit 21 performs an arbitration operation in response to requests from the input system and the output system, and reads and stores image data in the image memory 12.

  Next, a line buffer memory (1,1) 24a, a line buffer memory (1,2) 24b, a line buffer memory (1,3) 24c, a line buffer memory (2,1) 24d, a line buffer memory (2,2 ) 24e, line buffer memory (2, 3) 24f, line buffer memory (3, 1) 24g, line buffer memory (3, 2) 24h, and line buffer memory 24 such as line buffer memory (3, 3) 24i explain.

  First, there are a plurality of methods for realizing the line buffer memory 24 by hardware. Here, a configuration example of the line buffer memory 24 using a shift register having a simple configuration is shown in FIG. Description will be made based on b) and (c). 3A and 3B show the line buffer memory length of 10 bytes, and FIG. 3C shows the 5-byte line buffer memory length in two stages.

  As shown in FIGS. 3A and 3B, for example, in the line buffer memory 24 in which the line buffer memory length is 10 bytes, “1”, “2”. Is stored. For example, FIG. 3A shows a case where there is data “11” to be stored next in the line buffer memory 24 on the left side of the line buffer memory 24, and the line buffer memory 24 on the right side. In this case, there is data “1” extracted from “1”.

  Here, by executing the transfer process of the line buffer memory 24, the image data in the line buffer memory 24 is shifted and transferred to the right by one byte. As shown in FIG. At the same time as storing the data “11” at the left end, the data “2” at the right end of the line buffer memory 24 can be taken out.

  This configuration is a basic configuration of the fixed-length line buffer memory. Here, when the variable-length line buffer memory is used, the variable-length line buffer memory can be realized by arbitrarily extracting the image data extraction position from the middle portion of the line buffer memory 24 using, for example, a multiplexer. . For example, in the example of FIG. 3A, the variable-length line buffer memory 24 extracted from the position “3” can be realized. When data is extracted from the position “3”, the line buffer memory 24 can be set to 8 bytes.

  Next, FIG. 3C shows an example in which the bus width is doubled. In general, image data is often used with a width of 8 bits. If the image data is 8 bits, a buffer memory with a width of 16 bits is obtained in FIG. In this case, the bus width is doubled, but the buffer capacity is the same as 10 bytes. As an advantage of doubling the bus width, it is possible to improve the transfer speed of image data by a factor of two, while having the same circuit scale.

  The reason why the CPU bus width has been expanded to 8 bits, 16 bits, 32 bits, etc. is that a large amount of data can be transferred / processed with a single memory access, improving the processing capability. It is a technique that is commonly used to A commercially available memory module having a 64-bit bus width is generally used to improve the transfer speed.

  As a method for realizing the variable-length line buffer memory 24 other than the shift register, a general dual port memory may be used.

  In the case of a dual port memory, it can be realized by performing address control with an address for storing image data and an address for retrieving data being separated from each other by a fixed interval. For example, when the buffer memory has a length of 10 bytes, for example, when the current data storage address is “15” and the data retrieval address is “5”, the difference is “10”, so the buffer length is 10 bytes. be able to. By incrementing (+1) the address each time image data is stored and retrieved, the buffer length of “10” intervals is always maintained. If it is desired to change the buffer length, it can be easily realized by changing the address difference.

  The necessity of the line buffer memory 24 is, as described with respect to the image memory 12, when image data from the image memory 12 is subjected to image data processing and comparison operation processing using image data for a plurality of pixels as needed. If processing is performed by reading data for a plurality of pixels, the processing efficiency is significantly reduced. For this reason, in the case of an operation such as image filter processing for reusing the image data read from the image memory 12 once, the image data is not read from the image memory 12, and the line buffer memory 24 having a high access speed is used. It is possible to speed up the arithmetic processing by reading the image data and performing pipeline processing.

  Next, image filter processing of the image processing unit 20 in the image processing apparatus 10 having the above configuration will be described.

  Conventionally, when image filter processing of image data of the entire display panel is performed, the image filter processing is performed while reading data one pixel at a time sequentially from the left end in the horizontal direction of the image memory. Processing is performed up to the final image memory position while sequentially reading data from the left end image memory one line below.

  When calculating one pixel of an adjacent 3 × 3 image filter, for example, it is necessary to read image data for nine pixels from the image memory. However, every time image data for nine pixels is read, processing is performed. ineffective. Therefore, when the image data is read, the image data read from the image memory is sequentially stored in the line buffer memory, and the stored image data is sequentially read from the line buffer, thereby improving the access efficiency of the image memory, and Efficiency is improved by line processing.

  Conventionally, in order to perform adjacent 3 × 3 image filters by pipeline processing, normally, as in Patent Document 3, three line buffer memories each having a horizontal image size length and nine latch circuits are used to store image data. In many cases, a temporary storage circuit is configured.

  However, unlike the adjacent 3 × 3 pixel size filter processing, when performing the filter processing at positions spaced apart at a constant interval in the horizontal direction and the vertical direction, in the pipeline processing method using the line buffer memory, the line buffer Despite the reduction in memory utilization efficiency, it is necessary to increase the number of stages of the line buffer memory, which increases the circuit scale.

  For example, as shown in FIG. 4B, the center pixel P (m, n) and eight peripheral portions are arranged every 3 pixels (= cm) in the horizontal direction and every 4 pixels (= cn) in the vertical direction. Pixel P (m-cm, n-cn), P (m, n-cn), P (m + cm, n-cn), P (m-cm, n), P (m + cm, n), P (m- When processing an image filter having an effective area of 3 × 3 pixels with cm, n + cn), P (m, n + cn), and P (m + cm, n + cn), an apparent 7 × 9 pixel size ((2 × cm + 1 = 2) Since (* 3 + 1 = 7) * (2 * cn + 1 = 2 * 4 + 1 = 9)) image filters are processed, nine line buffer memories are required. When cn is 5 or more, a line buffer memory of 2 × cn + 1 = 2 × 5 + 1 = 11 or more is required.

  Therefore, in the present embodiment, when filtering an image for which the effective area is a comparison operation having a 3 × 3 pixel size, for example, as shown in FIG. Three sets of 24 are arranged. That is, the first set of line buffer memory 24 is composed of three line buffer memories (1, 1) 24a, line buffer memories (1, 2) 24b, and line buffer memories (1, 3) 24c. The set of line buffer memories 24 is composed of three lines: a line buffer memory (2, 1) 24d, a line buffer memory (2, 2) 24e, and a line buffer memory (2, 3) 24f. Reference numeral 24 denotes a line buffer memory (3, 1) 24g, a line buffer memory (3, 2) 24h, and a line buffer memory (3, 3) 24i.

  This number does not change when cn is 5 or more. The total size of one set (three) of line buffer lengths is a horizontal image size length L. The horizontal image size length L is composed of a preset number of pixels.

  Here, out of the three line buffer memories 24 in one set, the two line buffer memories 24 are set to 3 pixels, and the remaining is set to “horizontal image size length L-6”. Filter processing can be performed for each pixel. That is, for example, the second and third line buffer memories (1, 2) 24b, line buffer memory (1, 3) 24c, line buffer memory (2, 2) 24e, line buffer memory (2) of each set , 3) 24f, line buffer memory (3, 2) 24h, and line buffer memory (3, 3) 24i have a horizontal image size length = 3 pixels, and the first line buffer memory (1, 1) 24a of each set, The line buffer memory (2, 1) 24d and the line buffer memory (3, 1) 24g have a horizontal image size length of L-6 pixels.

  On the other hand, in the vertical direction, the data of each pixel of the horizontal image size length L, which is the image data for one horizontal line in the image memory 12, is sequentially read out and stored sequentially from the line buffer memory (1, 1) 24a. However, in the case of reading out the image memory 12, for one line reading out of the image memory 12, reading is performed every four pixels (= cn) in the pixel interval in the vertical direction of the image filter, that is, in the example shown in FIG. , And sequentially stored from the line buffer memory (1, 1) 24a.

  As a result, apparently three lines are continuously stored in the line buffer memory 24 in the vertical direction. That is, it is not necessary to arrange an extra line buffer memory 24 in the middle.

  In this way, by controlling the memory access interval in the vertical direction, the pixel interval in the vertical direction can be arbitrarily set. The control of the memory access interval in the vertical direction can be performed by setting in the vertical memory address control circuit (for input) 23a.

  The movement of the pixel data in the line buffer memory 24 will be specifically described with reference to FIG. FIG. 5 shows a state in which the image data of each line buffer memory 24 is stored when the horizontal image size length L is, for example, 100 pixels.

  In FIG. 5, the number of horizontal imaging pixels is set to 100 pixels, that is, the horizontal image size length L = 100 pixels, and the number of horizontal pixels cm for comparison operation is set to 3 pixels. Therefore, line buffer memory (1, 2) 24b, line buffer memory (1, 3) 24c, line buffer memory (2, 2) 24e, line buffer memory (2, 3) 24f, line buffer memory (3, 2) The size of each of the six line buffer memories 24 of 24h and the line buffer memory (3, 3) 24i is set to a length of 3 pixels (3 bytes), and the line buffer memory (1, 1) 24a, the line buffer memory (2 , 1) 24d and line buffer memory (3, 1) 24g, the size of each of the three line buffer memories 24 is set to 94 pixels (horizontal image size length L-6 = 100-6 = 94 pixels). .

  The numbers in FIG. 5 indicate the numbers in which the image data is actually sequentially stored, and nine pieces of pixel data can be extracted from the output portion (right end portion) of each line buffer memory 24. By processing these nine pieces of pixel data by the comparison calculation processing circuit 25, it is possible to detect whether or not the pixel data portion “104” shown in the comparison calculation processing circuit 25 of FIG. 5 is defective.

  With this configuration, it is possible to store image data in each line buffer memory 24, retrieve image data, execute comparison operation processing, and store processing results by pipeline processing every clock. It becomes.

  Of the line buffer memory 24, the line buffer memory (1, 1) 24a is, for example, 94 bytes. However, the size of 94 bytes is not necessarily required, and the size (number) required for temporary storage from the image memory 12 is not necessary. (About 10 bytes). However, for the line buffer memory (2, 1) 24d and the line buffer memory (3, 1) 24g, it is necessary to match the pixel position in the vertical direction in the pipeline processing, so 94 bytes or more (in the case of variable length) is required.

  Next, a defect detection method by the comparison calculation processing circuit 25 in the comparison calculation target area in the flat panel 1 will be described with reference to FIG. FIG. 6 is a plan view showing the comparison calculation target region 3 in the display pixel 2 of the flat panel 1.

  As shown in FIG. 6, when the number of horizontal pixels (= cm) is, for example, 6 pixels and the number of vertical pixels (= cn) is, for example, 10, the comparison calculation target region 3 has 13 × 21 pixels ((2 × cm + 1 = 2). × 6 + 1 = 13) × (2 × cn + 1 = 2 × 10 + 1 = 21)). FIG. 6 is for detecting bright spots (white spots) and black spots for nine imaging pixels in each display pixel 2 in monochrome display. In the figure, the gray value in the central central imaging pixel 4a among the nine points is compared with the gray value of the peripheral peripheral imaging pixels 4b... At the eight peripheral points, so that the central imaging pixel 4a has a gray value higher than that of the peripheral imaging pixels 4b. When the center image pickup pixel 4a is darker than the peripheral image pickup pixels 4b..., The center image pickup pixel 4a is detected as a black point defect.

  As a simple calculation processing example, for example, when the average value of the gray values of the eight peripheral imaging pixels 4b... Is subtracted from the gray value of the central imaging pixel 4a, and the calculation result is equal to or greater than a predetermined positive threshold value. On the other hand, if it is a bright spot defect, but below a predetermined negative threshold, it is determined as a black spot defect.

  In addition, since line defects occur continuously, point defects can be detected by calculating the range of defect groups using a labeling process or the like.

  Next, the case where the comparison calculation target area 3 is expanded will be described with reference to FIG. FIG. 7 is a plan view showing a region in which the comparison calculation target region 3 is made larger than that in FIG. 6, and shows a case where comparison calculation processing is performed using all the 25 imaging pixels. That is, the comparison calculation processing is performed using an image filter of 5 × 5 pixels.

  As shown in FIG. 7, in the case where the comparison calculation process is performed using all the 25 image pickup pixels, the number of pixels to be compared is increased as compared with the case of nine positions, so that the stability of the comparison calculation process is further improved. Can be made. That is, since the average value of the gray values of the 24 peripheral imaging pixels 4b is compared with the gray value of the central imaging pixel 4a, the accuracy of the average gray value of the 24 peripheral imaging pixels 4b is compared. Is improved, the accuracy of determining whether or not the gray value of the center imaging pixel 4a is defective, and the stability of the comparison calculation process is increased.

  Thus, rather than performing defect detection by performing various image filter processes in a small area (for example, an adjacent 3 × 3 pixel area) of an inspection target pixel to be inspected, for example, the surrounding same color Defect detection can be performed more easily by image filter processing that performs comparison calculation with non-defective pixels for pixels (for example, green (G) display color pixels). That is, in general, the display pixels 2 of the flat panel 1 are arranged in the order of red (R), green (G), and blue (B). Therefore, in the adjacent 3 × 3 pixel regions, different display colors are used. Pixels are mixed.

  Further, when performing defect detection of the flat panel 1, when performing defect detection by lighting only display pixels of even lines or odd lines, a large pixel interval in the horizontal direction and the vertical direction as in the present embodiment. This is particularly effective when the comparison calculation process is performed.

  That is, since the signal lines for driving each pixel of the flat panel 1 are arranged in a matrix in the horizontal direction and the vertical direction, if adjacent signal lines are short-circuited, the lines of adjacent display pixels are simultaneously Defects that may or may not be displayed. In order to detect this defect, for example, a pattern of lighting display pixels only on even lines or odd lines is used. This is because such a defect cannot be completely detected when the patterns of adjacent lines are the same.

  Next, the contents of the pixel data in the comparison calculation target area 3 will be described.

  For example, in the processing of an image filter having an apparent 7 × 9 pixel size ((2 × cm + 1 = 2 × 3 + 1 = 7) × (2 × cn + 1 = 2 × 4 + 1 = 9)) shown in FIG. As described above, the pixel spacing in the vertical direction of the image filter, that is, every four pixels (= cn) is read and sequentially stored from the line buffer memory (1, 1) 24a. As a result, the comparison calculation process for the center pixel P (m, n) was completed.

  Next, in the present embodiment, the image memory control circuit 21 inputs the next pixel data to the line buffer memory 24. As shown in FIG. 5, for example, the pixel data of the pixel “301” is stored in the line buffer memory (1, 1) 24a. At the same time, the line buffer memory (1, 2) 24b, the line buffer memory (1, 3) 24c, the line buffer memory (2, 1) 24d, the line buffer memory (2, 2) 24e, the line buffer memory (2, 3 ) 24 f, line buffer memory (3, 1) 24 g, line buffer memory (3, 2) 24 h, line buffer memory (3, 3) 24 i, etc. At the same time, the data output value for one pixel is transferred as the input value for the next line buffer memory 24 as the data output value for the rightmost pixel in the line buffer memory 24. For example, pixel data “207”, which is the output of the line buffer memory (1, 2) 24b, transfers data as an input to the line buffer memory (1, 2) 24b, and the output of the line buffer memory (1, 2) 24b. Certain pixel data “204” is transferred as input to the line buffer memory (1, 3) 24c. Further, the pixel data “201” that is the output of the line buffer memory (1, 3) 24c is transferred as the input of the line buffer memory (2, 1) 24d.

  As a result, the pixel data “208” “205” “202” “108” “105” ““ 102 ”“ 8 ”“ 5 ”“ 2 ”is input to the comparison calculation processing circuit 25, so that the pixel data“ The comparison calculation process with “105” as the central imaging pixel 4a is performed.

  Here, the positional relationship between the pixel data stored in each line buffer memory 24 shown in FIG. 5 and each pixel having an effective area of 3 × 3 pixel size shown in FIG. 4B will be described.

  That is, the line buffer memory (1,1) 24a, the line buffer memory (1,2) 24b, and the line buffer memory (1,3) 24c shown in FIG. 5 are (n + cn) in the vertical direction shown in FIG. The line buffer memory (2, 1) 24d, the line buffer memory (2, 2) 24e, and the line buffer memory (2, 3) 24f are (n) lines in the vertical direction, and the line buffer memory (3 , 1) 24g, line buffer memory (3, 2) 24h, and line buffer memory (3, 3) 24i are in the positional relationship of the (n-cn) lines in the vertical direction.

  For the horizontal direction, the output of the line buffer memory (1, 1) 24a, the line buffer memory (2, 1) 24d, and the line buffer memory (3, 1) 24g corresponds to the position of (m + cm), The outputs of the line buffer memory (1, 2) 24b, the line buffer memory (2, 2) 24e, and the line buffer memory (3, 2) 24h correspond to the position (m), and the line buffer memory (1, 3) 24c The outputs of the line buffer memory (2, 3) 24f and the line buffer memory (3, 3) 24i correspond to the position (m-cm).

  Therefore, the output pixel data “1” of each line buffer memory 24 shown in FIG. 5 has the positional relationship of the peripheral pixel P (m-cm, n-cn) shown in FIG. 4B, and the output pixel data “4”. Is the positional relationship of the peripheral pixel P (m, n−cn) shown in FIG. 4B, and the output pixel data “7” is the data of the peripheral pixel P (m + cm, n−cn) shown in FIG. The output pixel data “101” has a positional relationship with the peripheral pixel P (m−cm, n) shown in FIG. 4B, and the output pixel data “104” has the central pixel shown in FIG. 4B. The output pixel data “107” has the positional relationship of the peripheral pixel P (m + cm, n) shown in FIG. 4B, and the output pixel data “201” has the positional relationship of P (m, n). ), The positional relationship of the peripheral pixel P (m-cm, n + cn) shown in FIG. The pixel data “204” has a positional relationship with the peripheral pixel P (m, n + cn) shown in FIG. 4B, and the output pixel data “207” has the peripheral pixel P (m + cm, n + cn) shown in FIG. The positional relationship is as follows. The positional relationship between FIG. 4B and FIG. 5 is an image rotated 180 degrees around the center pixel P (m, n).

  Next, in the above description, the memory access in the vertical direction in the comparison calculation target area 3 is accessed in order of 1, 5, 9,..., 4n + 1 (n is an integer of 0 or more) in order from the first line. It is carried out.

  When this is one cycle, in the present embodiment, the second cycle of 2, 6, 10,..., (4n + 2) is executed sequentially from the second line, and then the third line. The third cycle of 3, 7, 11,..., (4n + 3) is executed in order, and then the fourth cycle of 4, 8, 12,..., (4n + 4) is executed in order from the fourth line. The eye is executed to complete a series of memory accesses.

  Next, the movement position of the comparison calculation target area 3 after the series of cycles is completed will be described with reference to FIG. FIG. 4A shows the movement position of the comparison calculation target area 3 by the address control of the input image memory address control circuit 22.

  As shown in FIG. 4A, first, the comparison calculation target area 3 at the position 3-1 is started, and then the comparison calculation target area 3 is moved in the horizontal direction so that the central imaging pixel 4a moves by one pixel. To do. Similarly, after moving in the horizontal direction as shown by position 3-1 ′ and moving to the right end of the flat panel 1, it starts from the area of position 3-2 moved in the vertical direction by cn.

  Thereafter, in the same manner, the comparison calculation target region 3 is moved in the direction of the position 3-2 ′ so that the central imaging pixel 4 a moves one pixel at a time. After moving to the right end, similarly, starting from the comparison calculation target region 3 at the position 3-3 that has moved further in the vertical direction by cn, the processing is sequentially performed while horizontally moving the comparison calculation target region 3 as described above. .

  With this configuration, calculation is performed using the output pixels of each line buffer memory 24, so that even in the case of actually pixel data at a distant position, the pixel data of the adjacent 3 × 3 pixel region is obtained in the calculation processing part. Can be handled as.

  As described above, the comparison processing calculation result for defect detection of each center imaging pixel 4a obtained by the comparison calculation processing circuit 25 is transferred to the output line buffer memory 26 as shown in FIG. The image data is stored in the image memory 12 via the image memory control circuit 21.

  Note that the output line buffer memory 26 is installed for the purpose of continuously operating without waiting time in the entire processing even if the writing wait time in the image memory control circuit 21 occurs. If there is no problem with waiting, it can be omitted.

  The flow of the image processing will be described based on the flowchart shown in FIG.

  First, various initial settings such as the buffer length setting of each line buffer memory 24 are performed (S1), the cycle number S is initialized to 1 (S2), the vertical counter is set to the cycle number S (S3), and the horizontal counter is set. Is initialized to 1 (S4).

  Next, address calculation is performed by the horizontal counter and the vertical counter set in S3 and S4 (S5). Then, one pixel at the address obtained by the address calculation is read and stored in each line buffer memory 24 (S6). In this flowchart, as shown in FIG. 5, it is assumed that the pixel data “300” is stored in the line buffer memory (1, 1) 24a.

  As a result, the pixel data “1” “4” “7” “101” “104” “107” “201” “204” “207” shown in FIG. A comparison calculation process is performed with “104” as the central imaging pixel 4a (S7). By this comparison calculation process, the display is made to know whether one pixel data “104” as the central imaging pixel 4a is defective, and is output to the image memory 12 (S8).

  Next, the pixel data “301” is written in the line buffer memory (1, 1) 24a shown in FIG. 5 (S9). At this time, the horizontal counter is incremented by 1 (S10), and it is determined whether the horizontal counter is within the number of horizontal pixels which is the horizontal image size length L (S11). If the horizontal counter is within the number of horizontal pixels that is the horizontal image size length L, the process returns to S5 and S5 to S11 are repeated.

  On the other hand, when the horizontal counter exceeds the number of horizontal pixels which is the horizontal image size length L in S11, the vertical counter is replaced with the vertical counter + cn (S12), and whether or not the replaced vertical counter is within the number of vertical pixels. Determination is made (S13). If the replaced vertical counter is within the number of vertical pixels, the process returns to S4 and S4 to S13 are repeated.

  On the other hand, when the replaced vertical counter exceeds the number of vertical pixels in S13, the cycle number S is incremented by 1 (S14), and the increased cycle number S is compared with the vertical pixel number cn (S15). When the increased cycle number S is smaller than the vertical interval cn, the process returns to S3 and S3 to S15 are repeated.

  On the other hand, if the increased cycle number S is greater than or equal to the vertical pixel number cn in S15, the process ends.

  According to the above flowchart, defect detection can be performed for all the pixels of the flat panel 1.

  Note that the above-described processing has been described for the case where nine pieces of pixel data are prepared as shown in the comparison calculation target region 3e in FIGS. 9A and 9B. However, in actuality, as shown in FIG. 9A, in the end portion of the flat panel 1, nine pixel data are not aligned as shown in the comparison calculation target areas 3a to 3d and 3f to 3i. Exists.

  That is, similar to the generally used filter processing of the m × n pixel size, when the pixel data is not aligned in the line buffer memory 24 in the upper, lower, left, and right end portions, the image data of the specified size cannot be used. It is necessary to perform edge processing for this part.

  FIG. 10 shows a flowchart in which this end processing is added.

  That is, as shown in FIG. 10, a step of reading out pixels for one line indicated by the vertical counter between S3 and S4 in the flowchart shown in FIG. 8 and storing the pixels for one line in the line buffer memory 24. (S21) and a step of setting the vertical counter to the vertical counter + cn (S22) are additionally inserted. Further, S13 in the flowchart shown in FIG. 8 is changed to a step (S23) for determining whether the vertical counter is within (vertical pixel number + cn).

  The reason why S21 and S22 are added is that one line of image data necessary in the initial state is stored in the line buffer memory 24 in advance. The reason that S23 is changed is that the condition is changed in order to store the data.

  Further, with respect to the comparison calculation process in S7 of the flowchart shown in FIG. 8, as shown in FIG. 11, the comparison calculation target area 3 is positioned in the upper, lower, left and right end areas with respect to the memory area in which the image is stored. In this case, the comparison calculation is usually performed with a total of nine pixels, that is, the pixel P5 that is the central imaging pixel 4a and the eight pixels P1 to P4 and the pixels P6 to P9 that are the peripheral imaging pixels 4b shown in FIG. In the upper, lower, left and right end regions, all necessary pixels are not aligned. For this reason, the comparison calculation target area 3 is classified into nine types of comparison calculation target areas 3a to 3i, and then the comparison calculation processing is performed.

  Specifically, as shown in the flowchart of FIG. 11, it is determined whether or not it is the comparison calculation target area 3a (S31). If it is the comparison calculation target area 3a, the pixel P5 and the pixels P6, P8, and P9 Is compared (S41).

  In S31, it is determined whether or not the comparison calculation target area 3b is not the comparison calculation target area 3a (S32). If it is the comparison calculation target area 3b, the pixel P5 and the pixels P4, P6, P7, P8, and P9 are determined. Is compared (S42).

  In S32, it is determined whether or not the comparison calculation target area 3c is not the comparison calculation target area 3b (S33). If it is the comparison calculation target area 3c, the comparison calculation between the pixel P5 and the pixels P4, P7, and P8 is performed. (S43).

  In S33, it is determined whether or not the comparison calculation target area 3d is not the comparison calculation target area 3c (S34). If it is the comparison calculation target area 3d, the pixel P5 and the pixels P2, P3, P6, P8, and P9 are determined. Is compared (S44).

  In S34, it is determined whether or not the comparison calculation target area 3e is not the comparison calculation target area 3d (S35). If it is the comparison calculation target area 3e, the pixel P5 and the pixels P1, P2, P3, P4, and P6 are determined. A comparison operation with P7, P8, and P9 is performed (S45).

  In S35, it is determined whether it is the comparison calculation target area 3f if it is not the comparison calculation target area 3e (S36). If it is the comparison calculation target area 3f, the pixel P5 and the pixels P1, P2, P4, P7, P8 are determined. Is compared (S46).

  In S36, it is determined whether or not the comparison calculation target area 3g is not the comparison calculation target area 3f (S37). If it is the comparison calculation target area 3g, the comparison calculation of the pixel P5 and the pixels P2, P3, and P6 is performed. (S47).

  In S37, it is determined whether or not the comparison calculation target area 3h is not the comparison calculation target area 3g (S38). If it is the comparison calculation target area 3h, the pixel P5 and the pixels P1, P2, P3, P4, and P6 are determined. Is compared (S48).

  In S38, if it is not the comparison calculation target area 3h, it is the comparison calculation target area 3i, so that the comparison calculation between the pixel P5 and the pixels P1, P2, and P4 is performed (S49).

  With the above processing, the comparison calculation processing can be performed even when the comparison calculation target region 3 is located in the upper, lower, left, and right end regions.

  As described above, by using the image processing apparatus 10 according to the present embodiment, when the point / line defect of the flat panel 1 is detected, the comparison calculation process is performed in a small region. It is possible to simultaneously remove the fluctuation portion of the brightness gray value and the shading amount generated due to factors such as camera lens characteristics and illumination conditions, thereby improving the detection accuracy of defect detection.

  That is, shading is likely to occur when the entire flat panel 1 or an area with a large range is imaged, and it can be considered that the amount of shading generated is relatively small within the small area. For this reason, since the comparison operation is performed in an area where the amount of shading is small, shading is within a negligible range. In addition, since the detection is performed by relative comparison, the shading amount with a small amount of generation is removed by calculation.

  In addition, defect detection can be performed on a single image without using large-size filter processing, shading correction calculation, and processing by pipelining. Can be planned.

  That is, in order to perform shading correction, it is usually necessary to perform a large-size smoothing filter process. As shown in FIGS. 22A and 22B, when the entire imaging screen is viewed, a gentle curve is obtained. The reason why the large size is necessary is to reproduce a gentle state.

  Usually, several pixels are assigned to the imaging pixels for one display pixel of the flat panel 1. For this reason, since the actual imaging pixels also image non-display areas between the pixels and the like, the captured images are uneven. In order to eliminate the unevenness, it is necessary to perform the smoothing filter process in an imaging range of about 10 times or more as many as several pixels are allocated as imaging pixels. Therefore, in order to perform shading correction as preprocessing, the amount of data and the amount of calculation for calculation increase, resulting in a decrease in processing speed. The present embodiment is characterized in that defect detection is performed without performing this shading correction.

  In the present embodiment, the comparison calculation target area 3 can be set large. However, since the data amount and the calculation amount for performing the actual comparison calculation are small, the processing can be performed at high speed.

  In addition, since the ((h-1) × cm + 1) × ((v−1) × cn + 1) pixel region can be pipelined with the number of effective operation pixels h × v, the circuit scale can be reduced and the operation can be performed. Processing speed can be increased.

  Furthermore, as shown in FIG. 1, by making the line buffer memory 24 for horizontal lines variable length, the number of horizontal pixels cm can be arbitrarily set without adding or changing hardware. The size of the comparison calculation target area 3 can be flexibly changed.

  In addition, the horizontal memory address control circuit (for input) 23b and the vertical memory address control circuit (for output) 28a have a function of calculating the memory address by setting the number of vertical pixels cn to an arbitrary value instead of a fixed value. Accordingly, the vertical interval can be arbitrarily set without adding or changing hardware, and the size of the comparison operation target area 3 in the vertical direction can be flexibly changed.

  In this embodiment, since shading correction using the reference image is not performed, defect detection is not affected by changes in illumination conditions or changes in imaging conditions caused by maintenance factors of the measurement device. It can be performed.

  In addition, when using line defect detection, it is possible to remove the fluctuation part of the brightness gradation value caused by the difference in the brightness value of the non-display part between pixels without using a differential filter such as an edge detection filter. The S / N ratio between the portion and the normal portion is calculated to be large, and as a result, the line defect portion can be easily extracted.

  That is, a differential filter such as an edge detection filter generally has the following problems.

  For example, if a large number of imaging pixels are assigned to one pixel of the flat panel 1, an edge is always detected regardless of whether the liquid crystal is displayed (regardless of a non-defective product / defective product) (in particular, red (R), green In the case of (G) and blue (B) monochrome display patterns), it is necessary to perform another process for detecting a defective portion.

  On the contrary, when the number of imaging pixels allocated to one pixel of the flat panel 1 is too small, an imaging state in which the luminance value varies periodically is detected, so that an edge is always detected regardless of whether the product is non-defective or defective. The In addition, since the variation amount varies depending on the imaging position, the detection accuracy is extremely lowered.

  The edge detection filter system can detect even a small amount of fluctuation, but conversely, since it detects with a slight fluctuation, its stability is poor. For this reason, normally, in order to improve detection accuracy without performing detection only by edge processing, other arithmetic processing is often performed by tying together.

  The edge detection filter system may not be used, for example, as shown in FIG. 15 to be described later, with respect to the position of the display pixel of each flat panel 1 when the position of the imaging pixel targeted for the comparison operation is This is a case where the positions are relatively the same. In this case, stable defect detection can be performed even when the number of image pickup pixels is an allocation of a small number of pixels of 2 to 3 pixels with respect to the display pixels.

  In addition, it is separated from each display pixel of red (R), green (G), and blue (B) by a fixed interval rather than performing point defect detection by image filter processing in an adjacent small area of each display pixel of the flat panel 1. The point defect detection accuracy can be improved and stabilized by performing image filter processing that performs comparison operations with display pixels of similar colors, red (R), green (G), and blue (B).

  In addition, since a defect under an adjacent condition is unlikely to occur due to a comparison operation with a distant pixel, it is easy to compare a normal pixel with a defective pixel. That is, the defect under the adjacent condition refers to a defect that occurs when the wiring patterns of the upper, lower, left, and right pixels of the pixel that is the defect detection target of the flat panel 1 are short-circuited. When compared with adjacent pixels, the comparison calculation is performed in an area where many defective portions occur, so that the detection accuracy decreases. On the other hand, in the case of comparison at a distant position, it is possible to prevent a decrease in detection accuracy due to this defect.

  In addition, for example, in the case of dust adhesion, it becomes a pseudo defect under the adjacent condition. If dust adheres to the inside of the flat panel 1, it becomes a true defect. However, if it adheres to the outside of the flat panel 1, that is, only on the surface, it is not a defect but merely a dust adhering and not a defect. This determination is normally performed by switching a plurality of display patterns to detect a defect, and therefore can be determined based on the type of defect in the display pattern.

  The image processing apparatus 10 stores a CPU (Central Processing Unit), which is a calculation means for executing instructions of a program (control program, recording condition setting program) for realizing each function of the image processing unit 20, and the program. ROM (Lead Only Memory) as storage means, RAM (Random Access Memory) as storage means for expanding the program, and a storage device (storage medium) (not shown) such as memory as storage means for storing the program and various data Etc.

  An object of the present invention is to provide a recording medium in which a program code (execution format program, intermediate code program, source program) of a control program, which is software that realizes the functions described above, can be read by a computer, the image processing apparatus 10 and the computer (or CPU or MPU) reads out and executes the program code recorded on the recording medium. In this case, since the program code itself read from the recording medium realizes the above-described function, the recording medium on which the program code is recorded constitutes the present invention.

[Embodiment 2]
The following will describe another embodiment of the present invention with reference to FIG. Configurations other than those described in the present embodiment are the same as those in the first embodiment. For convenience of explanation, members having the same functions as those shown in the drawings of the first embodiment are given the same reference numerals, and explanation thereof is omitted.

  In the image processing unit 20 in the image processing apparatus 10 of the first embodiment, as shown in FIG. 2, all the line buffer memories 24 have a variable length, whereas the image processing apparatus 10 of the present embodiment. As shown in FIG. 12, the image processing unit 30 in FIG. 12 includes a line buffer memory (1, 3) 34c, a line buffer memory (2, 3) 34f, and a line buffer memory (3 3) A fixed-length line buffer memory 24 composed of only three 34i (the buffer length is the number of all horizontal pixels of the flat panel 1) is different.

  In the present embodiment, with this configuration, only a pixel comparison operation process at an arbitrary vertical interval in the vertical direction is performed to detect a defect. As a result, the circuit configuration can be greatly simplified.

  Further, in this configuration, as a display pattern on the flat panel 1 for performing defect detection, the entire screen is the same pattern on one side such as a white display pattern or the same pattern with respect to the vertical direction of the captured image. In this case, the defect detection can be sufficiently performed even by the comparison calculation process using only the pixels in the vertical direction without using the pixels in the horizontal direction.

  Further, when the imaging device 5 is a one-dimensional imaging device such as a line sensor or a TDI sensor (having several tens of line sensors arranged), a plurality of one line is used in order to speed up image data transfer. There are cases where the image data is divided (about 4 to 16 divisions) and the image data is transferred to the output end of each division section through each amplifier. In this case, there is a case where the amplification characteristics of the amplifiers do not match or a discontinuity of the image data occurs at the boundary portion between the divided portions. When processing such image data, a better result can be obtained if the comparison calculation process is performed using only the pixels in the vertical direction without using the pixels in the horizontal direction.

[Embodiment 3]
The following will describe still another embodiment of the present invention with reference to FIGS. The configurations other than those described in the present embodiment are the same as those in the first embodiment and the second embodiment. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiment 1 and Embodiment 2 are given the same reference numerals, and explanation thereof is omitted.

  The comparison operation processing circuit 25 of the first and second embodiments is one as shown in FIGS. 1 and 12, whereas the image processing in the image processing apparatus 10 of the present embodiment is one. As shown in FIG. 13, the unit 40 is different in that it uses two comparison operation processing circuits 45a and 45b.

  In other words, the image processing unit 40 according to the present embodiment performs two parallel processes as the comparison calculation process, and doubles the bus width of each line buffer memory 44 to generate two comparison calculation processing circuits 45 a. By providing 45b, the calculation processing speed and the image data transfer speed are doubled.

  In general, when performing image processing, as shown in FIGS. 3A and 3B, one pixel is often handled with a data length of 8 bits. However, in recent years, in order to improve the data transfer speed and processing capability, the bus width of the line buffer memory tends to be larger, such as 16 to 64 bits instead of 8 bits. In particular, commercially available memory modules having a 64-bit bus width are widely used.

  For example, in particular, since a memory module used for a personal computer or the like has a 64-bit width, it is possible to access 8 bytes by one access. For this reason, the memory access efficiency is improved by a factor of eight. Therefore, if the bus width of the line buffer memory 24 is the same in accordance with the bus width of the memory module, the memory transfer speed is improved even with the same buffer capacity.

  In the present embodiment, in order to simplify the description, the bus width is doubled to 16 bits, that is, extended to two pixels. The line buffer memory 44 has the configuration shown in FIG.

  Therefore, in the first embodiment and the second embodiment, the image memory control circuit 21 performs data transfer with an 8-bit width to each line buffer memory 24. In this embodiment, FIG. As shown, the image memory control circuit 41 includes a line buffer memory (1,1) 44a, a line buffer memory (1,2) 44b, a line buffer memory (1,3) 44c, and a line buffer memory (2,1) 44d. , Line buffer memory (2, 2) 44e, line buffer memory (2, 3) 44f, line buffer memory (3, 1) 44g, line buffer memory (3, 2) 44h, and line buffer memory (3, 3) Data transfer is performed with a bus width of 16 bits to each line buffer memory 44 such as 44i (indicated as (16b) in FIG. 13).

In this case, each line buffer memory 44 handles the lower 8 bits as the nth pixel and the upper 8 bits as the (n + 1) th pixel in the 16-bit data. Thus, specifically, as shown in FIG. 14, the comparison operation target region 3 _H near the imaging pixels 4b _H or comparison target region 3 _L of two adjacent pixels of the pixel data, such as surrounding imaging pixels 4b _L Are output at the same time. Therefore, the upper 8 bits of each line buffer memory 44 are input to the comparison operation processing circuit 45a, and the lower 8 bits of each line buffer memory 44 are input to the comparison operation processing circuit 45b. Thereby, the comparison operation can be performed in parallel.

  In the above description, the line buffer memory 44 has a 16-bit length that is twice that of the line buffer memory 24. However, the processing speed is increased to 8 times that of the line buffer memory 24 by corresponding to the 64-bit length. Can be easily realized.

  In general, the processing speed can be increased n times by multiplying the bus width of the line buffer memory 24 by n and providing n comparison operation processing circuits 25.

[Embodiment 4]
The following will describe still another embodiment of the present invention with reference to FIG. Configurations other than those described in the present embodiment are the same as those in the first to third embodiments. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiments 1 to 3 are given the same reference numerals, and descriptions thereof are omitted.

  In the image processing apparatus 10 according to the present embodiment, when each display pixel 2 of the flat panel 1 to be inspected is imaged by the imaging apparatus 5, the number of imaging pixels in the horizontal direction and the vertical direction of the imaging pixels is the display pixel. Defect detection is provided by means for imaging at intervals of integer multiples of the number and means for setting the horizontal and vertical intervals of the image filter to intervals of integer multiples of the number of display pixels.

  When detecting a point / line defect in the flat panel 1, in general, in order to perform good imaging, the number of pixels of the imaging device 5 is set to 8 in the horizontal direction and the vertical direction with respect to one pixel of the flat panel 1. It is necessary to perform imaging by assigning about -10 or more.

Therefore, in the present embodiment, as shown in FIG. 15, the ratio between the number of display pixels and the number of imaging pixels of the flat panel 1 is an integer such as 1: 2 in the horizontal direction and 1: 3 in the vertical direction. Enable double image input. This figure shows the comparison calculation target region 3 with cm = 6 and cn = 6. Also,
Further, FIG. 15 illustrates an example in which a color flat panel comparison operation is performed. That is, the flat panel 1 shown in FIG. 15 is of a stripe arrangement type (display pixels of each color of red (R), green (G), and blue (B) are arranged in the same color in the vertical direction). The display pixels are arranged in the order of red (R), green (G), and blue (B) display pixels in the horizontal direction.

  As for imaging pixels, 2 pixels in the horizontal direction and 3 pixels in the vertical direction are assigned to one display pixel.

  As shown in FIG. 15, the position of the image pickup pixel to be compared is compared with the relative position of the display pixels of the same color on the flat panel 1 (the upper right portion of the red (R) display pixel in FIG. 15). The intervals of cm and cn are set so that the calculation can be performed. In FIG. 15, the same relative value is obtained every six pixels in the horizontal direction, and the same relative position is obtained every three pixels in the vertical direction. For this reason, cm is an integral multiple of 6 and cn is an integral multiple of 3 for the setting. However, for cn, “6” is set instead of “3” in order to reduce accuracy degradation due to adjacent pixel defects. As a result, the comparison calculation target area 3 is set in a range of 13 × 13 pixels, and the imaging pixel at the center thereof becomes a target pixel for determination of defect detection. Judge whether it is a non-defective product.

  In the above description, the vertical direction is set at an interval of cn = 6 instead of cn = 3 because a defect in adjacent pixels on the upper, lower, left, and right sides to be compared is due to a short circuit pattern or the like. This is because defects may be continuous. In this case, if the comparison calculation is performed, the detection accuracy may decrease. Therefore, a position where one display pixel is skipped is designated. Thereby, it is possible to prevent a decrease in detection accuracy due to adjacent pixel defects.

  By using the above-described method, even if the number of imaging pixels is set to a small number of 2 to 3 pixels for one display pixel, the display pixel portion under the same conditions is relatively compared. Defect detection can be performed. In addition, when the number of assigned imaging pixels is small, the number of imaging pixels of the imaging device can be reduced, so that the cost of the imaging device can be reduced and the amount of captured image data is reduced, so the processing time for defect detection can be reduced. Can be shortened.

  As a method for realizing the input of the main image, the imaging device 5 shown in FIG. 2 is moved in the vertical direction UD, or a lens (not shown) attached to the imaging device 5 is used as a zoom lens, and the imaging magnification is adjusted. This can be easily realized.

  When the imaging device 5 is a one-dimensional type such as a line sensor, the imaging device 5 is moved in the horizontal direction HO at a constant speed to generate a captured image. At this time, the number of pixels in the vertical direction can be adjusted by adjusting the moving speed of the imaging device 5.

  In the above description, the ratio of the number of pixels is adjusted both in the horizontal direction and in the vertical direction. However, when a point / line defect of the flat panel 1 is detected, the same pattern on one side such as a white display pattern. Or when the pattern is the same with respect to the vertical direction of the captured image, defect detection can be performed by assigning 2 to 3 pixels as the number of pixels of the imaging device 5 even in the comparison calculation process only in the vertical direction.

  In all of the above embodiments, the processing is based on the hardware operation function, but part or all of the function can be detected by software processing by a computer.

[Embodiment 5]
The following will describe still another embodiment of the present invention with reference to FIGS. Configurations other than those described in the present embodiment are the same as those in the first to fourth embodiments. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiments 1 to 4 are given the same reference numerals, and descriptions thereof are omitted.

  In the first to fourth embodiments, as illustrated in FIG. 2, the imaging device 5 and the image processing device 10 are provided separately from each other.

  As shown in FIG. 16, the defect detection system 50 of the present embodiment includes a sensor camera 60 with a defect detection function, and the sensor camera 60 has a function in which an imaging device and a defect detection function are integrated. It has become a thing. FIG. 16 is a block diagram showing a configuration of the defect detection system 50 of the present embodiment.

  As shown in FIG. 16, the defect detection system 50 according to the present embodiment includes a sensor camera 60 supported by a stage 51, a monitor unit 52, a communication processing unit 53, a defect determination processing unit 54, and an overall control unit. 55, a stage control unit 56 and a stage driver unit 57 as moving means, a pattern generator 58, and a panel drive control circuit unit 59.

  In the defect detection system 50 described above, in order to detect each pixel defect in the flat panel 1, first, an image for displaying a measurement pattern on the flat panel 1 with respect to the pattern generator 58 by the overall control unit 55. Controls signal output. Thus, the video pattern is displayed on the flat panel 1 by the panel drive control circuit 59 based on the video signal.

  Next, the sensor camera 60 installed on the stage 51 capable of vertically moving the displayed measurement pattern vertically is moved at a constant speed in the upward or downward direction by the stage controller 56 and the stage driver 57. Imaging processing and defect detection processing are performed simultaneously. Here, the movement by the stage 51 is accompanied at the time of imaging because the sensor camera 60 has a line sensor or a TDI sensor (having several tens of arrayed line sensors) as a basic structure.

  The captured image output from the sensor camera 60 is displayed on the monitor unit 52, and the pixel defect information of the flat panel 1 is transferred to the defect determination processing unit 54 via the communication processing unit 53.

  The defect determination processing unit 54 performs comprehensive determination based on the pixel defect information, extracts the feature amount of the defective portion, and determines the quality of the entire flat panel 1.

  Next, a configuration for performing image filter processing in the sensor camera 60 will be described with reference to FIG. FIG. 17 is a block diagram showing a configuration in the case of filtering an image for which the effective area has a 3 × 3 pixel size comparison operation.

  As shown in FIG. 17, the sensor camera 60 of the present embodiment includes a sensor unit 70, a comparison calculation block 80, and a defect detection block 90.

  The sensor unit 70 has a sensor structure in which a plurality of line sensors 71 of horizontal M pixels (N in the figure) are arranged in the vertical direction, and has amplifiers 72a and 72b on both sides of the line sensor 71, respectively. Yes.

  The sensor unit 70 extracts pixel data from the end (pixel “1” or pixel “M” portion) of each line sensor 71 by a function of shifting the pixel data of the line sensor 71 from the captured image, and the amplifiers 72 a. 72b is relayed and transferred to each multiplexer 81 such as the multiplexer (MUX1) 81a, the multiplexer (MUX2) 81b, the multiplexer (MUX3) 81c in the comparison operation block 80.

  Since each multiplexer 81 can arbitrarily select the output position of the line sensor 71, the multiplexer (MUX1) 81a, the multiplexer (MUX2) 81b, and the multiplexer (MUX3) 81c are arranged in the number of cn pixels in the vertical direction. By selecting three vertical lines, the vertical interval of the comparison calculation target area 3 can be arbitrarily set.

  Further, in the comparison operation block 80, each multiplexer 81, an A / D converter 82 as conversion means, and two variable-length line buffer memories 84 are provided as one set, and three sets are provided. The thing of the circuit structure provided is arranged.

  When attention is paid to the first set of circuit configurations, first, analog image data from the vertical line selected by the multiplexer 81 is digitally converted by the A / D converter 82. Next, the digitized image data is input to the first variable length line buffer memory (1, 2) 84a. Next, the output of the line buffer memory (1, 2) 84a is input to the second variable length line buffer memory (1, 3) 84b. Next, the pixel data of the pixel P13, which is the output of the line buffer memory (1, 3) 84b, is input to the comparison operation processing circuit 85 as the comparison operation processing means. At the same time, the pixel data of the pixel P11 which is the output of the A / D converter 82 and the pixel data of the pixel P12 which is the output of the first variable length line buffer memory (1, 2) 84a are also compared. 25.

  Since there are three sets of these circuits, a total of nine pieces of image data are input to the comparison calculation processing circuit 85.

  Here, since the data length of each line buffer memory 84 can be changed, the horizontal pixel interval of the comparison calculation target region 3 is arbitrarily set by setting the horizontal interval in cm intervals (every six pixels in FIG. 6). It becomes possible.

  Therefore, by using the above function, it is possible to select image data in an apparent 13 × 13 pixel area as in the example of FIG. 6 described above.

  Note that the timing of the sensor unit 70 and the comparison calculation block 80 is controlled by the timing signal generator 61, and the sensor unit 70 is based on a control signal from the timing signal generator 61. The sensor driver 62 is driven.

  In the present embodiment, the position data and the like of the defective part by the comparison calculation in the comparison calculation processing circuit 85 are temporarily stored in the defect data storage unit 92 once through the defect detection unit 91 as defect detection means, and the communication processing unit 53. Then, defect data is transferred in real time to a defect determination processing unit 54 such as a PC (personal computer) installed outside, and a quality determination process is performed.

  In the present embodiment, the captured image itself can also be output to the outside simultaneously via the image data output unit 63 as an external output means in real time, so that a defect can be obtained without arranging a large-capacity image memory inside. Detection can be performed.

  The process flow described above will be specifically described based on the flowchart shown in FIG.

  First, the buffer length in each variable-length line buffer memory 84 is set (S51), the selection position of the multiplexer 81 is set (S52), and then the sensor camera 60 is moved at a constant speed (S53).

  Next, when defect detection is started (S54), imaging with the sensor camera 60 is performed (S55).

  Next, each line sensor 71 in the sensor unit 70 is shifted by one pixel, transferred to each multiplexer 81 of the comparison calculation block 80 (S56), and the A / D converter 82 digitally converts the image data (S57). The image data is transferred to the first variable length line buffer memory 84 (S58), the image data is transferred to the second variable length line buffer memory 84 (S59), and the image data is transferred to the comparison processing circuit 85. (S60).

  Next, the comparison calculation processing circuit 85 performs calculation processing of the image data to be compared (S61). In the defect detection block 90, the defect detection unit 91 detects a defect portion (S62), and the defect data storage unit 92 stores the defect data. The defect data is temporarily stored (S63), and the communication processing unit 53 transfers the defect data and the image data to the external device (S64).

  Thereafter, it is determined whether or not the processing for the horizontal line (M pixels) is completed (S65). If the processing for horizontal lines (M pixels) is not completed, the process returns to S56 and S56 to S65 are repeated.

  On the other hand, if the processing for the horizontal line (M pixels) is completed in S65, it is determined whether the processing for the vertical line (N pixels) is completed (S66). If the processing for the vertical line (N pixels) is not completed, the process returns to S55 and repeats S55 to S66.

  On the other hand, if the process for the vertical line (N pixels) is completed in S66, the movement of the sensor camera 60 is stopped (S67), and the process ends.

  As described above, in the defect detection system 50 configured as described above, when detecting a point defect on the flat panel 1, in order to perform a comparison calculation process in a small area, the fluctuation portion of the luminance gradation value between the pixels of the flat panel 1, In addition, the shading amount generated due to factors such as the lens characteristics of the sensor camera 60 and the illumination conditions can be removed at the same time, and the detection accuracy of defect detection is improved.

  In addition, since the shading correction calculation is not performed, the defect detection is performed with one image, and further, the processing by pipelining can be performed, so that the defect detection processing can be speeded up.

  In addition, since the ((h-1) × cm + 1) × ((v−1) × cn + 1) pixel region can be pipelined with the number of effective operation pixels h × v, the circuit scale can be reduced and the operation can be performed. Processing speed can be increased.

  Further, even when the interval between pixels to be compared is large, the line sensor 71 can be used as a substitute for the line buffer memory. Therefore, a large-sized line buffer memory (1 to 16 k pixels) is not necessary, and the circuit scale is reduced. As a result, costs can be reduced.

  Further, the comparison calculation target area 3 can be flexibly set by means for variably setting the buffer length of each line buffer memory 84 for horizontal lines and means for arbitrarily selecting the vertical position by the multiplexer 81.

  In addition, since defect detection can be performed simultaneously with imaging in the sensor camera 60, real-time arithmetic processing is possible, and the circuit configuration can be simplified compared to a configuration in which the imaging device and the defect detection device are combined. By making a CMOS process on the same chip as the sensor unit and the arithmetic processing circuit unit, the circuit can be easily downsized.

  Further, when displaying an image on the flat panel 1 or the like, since the image is displayed at a constant lighting cycle, the imaging time in the imaging device, that is, the accumulation time for imaging is an integral multiple of the lighting cycle. If is not set, it has been a factor that the image quality of the image pickup deteriorates due to the effect of flicker.

  In addition, when performing defect detection by combining an imaging device and a detection device, it is necessary to store the captured image in the image memory and then perform arithmetic processing for defect detection. The problem of not being able to do it can also be solved.

  In the above description, it is assumed that each multiplexer 81 that selects the output from each line sensor 71 is not changed when it is set once at the time of initial setting or model change. However, the present invention is not particularly limited to this, and it is also possible to control the multiplexer 81 by switching and using it sequentially during operation. In this way, by using a different control method for the multiplexer 81 or the like, a self-defect detection function of each line sensor 71 by self-diagnosis or a defect detection of a display device having an area sensor imaging function is performed. Is possible.

  Specifically, when self-defect detection of each line sensor 71 is performed, first, the selection positions of the multiplexers 81 such as the multiplexer (MUX1) 81a, the multiplexer (MUX2) 81b, the multiplexer (MUX3) 81c, and the like are determined based on the sensors (1) to (1). The selected position in the vertical direction is set to adjacent sensor positions as in the sensor (3), or to sensor positions having a constant interval in the vertical direction. Next, for each variable length line buffer memory 84 such as the line buffer memory (1, 2) 84a to the line buffer memory (3, 3) 84f, the line sensor 71 adjacent to the horizontal direction in the same manner as the vertical direction. Alternatively, the buffer length is set so as to be a constant interval in the vertical direction.

  In this state, when a single-surface gray pattern or the like is imaged by the sensor camera 60 of the present embodiment and one line of the line sensor 71 is calculated by the comparison calculation processing circuit 85, in the case of a non-defective product, a predetermined threshold range. However, if a defect occurs, a brighter or darker state than the surrounding line sensor 71 occurs, resulting in a processing result outside the predetermined threshold range. Can be detected.

  Next, when the calculation processing for one line is completed, each multiplexer 81 is switched to a position shifted by one line in the vertical direction, the same processing as described above is performed, and then defect detection for one line is performed. By repeatedly executing this process for all line sensors 71..., It is possible to detect defects in each line sensor 71.

  On the other hand, when performing defect detection of a display device as an area sensor, in the above example, imaging was performed for a specific pattern such as gray on one side, but when used as an area sensor, the display pattern of the display device is actually used. This can be realized by imaging and performing the same control as in the above control example.

  Here, differences between the image processing apparatus 10 according to the first to fourth embodiments, the defect detection system 50 according to the present embodiment, and the sensor camera 60 with a defect detection function will be described.

  The defect detection system 50 and the sensor camera 60 with a defect detection function of the present embodiment are different from the image processing apparatus 10 in that the image processing apparatus 10 continuously stores image data in the line buffer memory 24. In the sensor camera 60 with defect detection function, the vertical interval is temporarily set (which line sensor 71 is selected by the multiplexer 81). For example, imaging can be performed by moving the object to be imaged (flat panel 1) or the sensor camera 60 at a constant speed, and comparison calculation processing can also be performed at this interval.

  In the case of the sensor shown in FIG. 17, since the line sensor 71 and the shift register are shared, a shift register configuration is required. That is, in order to perform data transfer after imaging, it is necessary to perform imaging and transfer in a time division manner.

  In the case of the sensor shown in FIG. 19, since the shift register 112 is separately provided, data transfer and imaging can be performed simultaneously.

  For example, in the case of having a latch / shift register, if a multiplexer is added to the horizontal line, it is possible to access every 6 pixels. Since only about tens of lines are arranged in the vertical direction, multiplexers for tens of lines are selected. As a result, the circuit scale can be relatively small. However, since the arrangement is several thousand pixels per line in the horizontal direction, the circuit configuration becomes complicated when a multiplexer is arranged.

  Further, the line buffer memory (1, 1) 24a, the line buffer memory (2, 1) 24d, and the line buffer memory (3, 1) 24g are reduced as compared with the image processing apparatus 10. This is because the line sensor 71 itself functions as a shift register structure when transferring data sequentially. The remaining line buffer memory 84 is used for setting a horizontal interval. For this reason, the remaining line buffer memory 84 requires a buffer length for setting the horizontal interval in order to perform pipeline processing.

[Embodiment 6]
The following will describe still another embodiment of the present invention with reference to FIG. Configurations other than those described in the present embodiment are the same as those in the first to fifth embodiments. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiments 1 to 5 are given the same reference numerals, and descriptions thereof are omitted.

  As shown in FIG. 19, the sensor camera 100 according to the present embodiment has a function of arbitrarily setting the sensor unit 110 to a plurality of blocks of a TDI sensor structure (having a plurality of line sensors). .

  That is, the sensor unit 110 according to the present embodiment includes the TDI sensor blocks 111 of the TDI sensor blocks 111a to 111j. Each TDI sensor block 111 includes the line sensor 71, the shift register 112, and an analog as a switching unit. Each sensor including the switch 113 and the amplifiers 72a and 72b as a set includes a plurality of sets. That is, the TDI sensor blocks 111a, 111b, and 111j basically have a configuration such that i sets (i is an integer of 2 or more). However, the last TDI sensor block 111j may be a fraction because it may not be divisible for all N lines when line sensors are arbitrarily combined. However, when the comparison calculation process is performed, since all sensor blocks are not used, fractions may be generated. However, it is preferable to make settings so that fractions do not occur because all sensors can be used effectively.

  Each TDI sensor block 111 is provided with a shift register 112 for storing image data for one line at a time with respect to the line sensor 71, and an amplifier disposed on one side or both sides of the shift register 112. 72a and 72b amplify the image data sequentially transferred for each pixel from the shift register 112 and transfer the amplified image data to the comparison operation block 80.

  The shift register 112 has a function of temporarily storing image data of the line sensor 71 and outputting the image data while shifting the image data in a time division manner for each pixel. Normally, it is sufficient to provide a function of only one-way one-way shift, but the reference position for image output can be changed by arbitrarily switching between left shift and right shift. Thereby, the output position of the image can be reversed.

  An analog switch 113 is disposed between adjacent line sensors 71. The analog switch 113 has a function of setting whether to transfer image data captured by the line sensor 71 to the adjacent line sensor 71. By using this function, it is possible to sequentially accumulate and add image data of adjacent line sensors 71. That is, the function of the TDI sensor can be realized.

  Here, as a general control method of the TDI sensor, as shown in the figure, every time imaging is performed, imaging is repeated while moving the TDI sensor up or down by one sensor line in the vertical direction. At this time, image data is transferred while accumulating and adding to sensors arranged in the direction opposite to the moving direction. Here, the accumulation-addition imaging refers to imaging again in a state as it is without releasing the charge stored in the sensor. By performing this method, charges for a plurality of adjacent lines are accumulated, so that the characteristics equivalent to the conditions for imaging at a shutter speed for a plurality of lines are obtained.

  The analog switch 113 controls ON / OFF of the connection with the adjacent line sensor 71. Therefore, when the continuous line sensor 71 is desired to have a TDI sensor structure, the analog switch 113 is turned ON, and when it is desired to be separated, OFF control is performed, as shown in FIG. Can be set. In the figure, an example in which j TDI sensor blocks 111 are configured with i line sensors 71 as one TDI sensor block 111 is shown.

  In the sensor unit 110 according to the present embodiment, by arbitrarily setting the TDI sensor structure, accumulation and addition of imaging can be performed as compared with the line sensor structure. As a result, since the accumulation time can be shortened or the accumulation time can be increased in a pseudo manner, it is possible to reduce the influence on flicker or the like caused by the display cycle of the display device.

[Embodiment 7]
The following will describe still another embodiment of the present invention with reference to FIG. Configurations other than those described in the present embodiment are the same as those in the first to sixth embodiments. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiments 1 to 6 are given the same reference numerals, and descriptions thereof are omitted.

  In the sensor camera 120 of the present embodiment, as shown in FIG. 20, a plurality of the line sensors 71 are arranged in the sensor unit 70 mounted on the microstage 121, and the same captured image is distributed to each sensor by the optical unit 122. A projection structure is used, and the imaging position in the vertical direction is shifted by the microstage 121, whereby the interval of the comparison operation areas in the vertical direction is arbitrarily set.

  The configuration of the sensor camera 120 will be described with reference to FIG. FIG. 20 is a block diagram illustrating an example in which three sensor units 70 are arranged.

  As shown in FIG. 20, the sensor camera 120 of the present embodiment has a sensor unit 70 disposed on each microstage 121, and a captured image input through a lens 123 is used for each sensor using the optical unit 122. The same captured image is distributed and projected onto the sensor units 70 such as the units 70a, 70b, and 70c. At this time, with the imaging position of one sensor unit 70 as a reference, the remaining two sensor units 70 and 70 are each an integral multiple of the imaging pixel pitch in the vertical direction with respect to the vertical direction of the captured image by the microstage 121. Move.

  Accordingly, the horizontal direction of the line sensor 71 in each sensor unit 70 is the same position, but the imaging position in the vertical direction is shifted. That is, the same position of each sensor unit 70, for example, each image data output from the sensor 1 is output as image data at a position relatively shifted in the vertical direction.

  In the fifth embodiment, the vertical interval is set by the multiplexer 81 in the selection, but in the present embodiment, the vertical interval is set by the microstage 121.

  Thus, in the fifth embodiment, the multiplexer 81 is arranged for the input portion of the comparison operation block 80 as shown in FIG. 17, but in this embodiment, as shown in FIG. 20, the comparison operation block 80a. The multiplexer 81 can be omitted for the input portion.

  In addition, as the sensor unit 70, a line sensor having only one line or a normal TDI sensor can be used. Furthermore, even if the interval of the comparison calculation target region 3 is increased, the interval in the vertical direction can be arbitrarily set by the microstage 121. Therefore, this can be realized without increasing the number of sensors in the sensor unit 70.

  Note that the microstage 121 used in the present embodiment can be controlled by the microstage 121 using a piezo element or the like when the interval is controlled to be finer than the pixel pitch of the sensor.

  In the above description, the method of setting the vertical interval to an integral multiple of the imaging pixel pitch is used. However, the present invention is not limited to this, and the microstage 121 is used only in the vertical direction of the captured image, or in the horizontal and vertical directions. On the other hand, it is possible to move the imaging pixel pitch by a real value multiple (a value including a decimal point).

  As a result, it is possible to improve the resolution of the captured image by performing interpolation / synthesis of the image by pixel shifting or the like based on the plurality of image data output from the sensors of each sensor unit 70.

  As an example of this use, it is possible to realize an inspection method in which defect detection is performed with a normal resolution image, and the periphery of the defective portion is re-confirmed with respect to the peripheral portion of the defect by image synthesis such as pixel shifting again. it can.

[Embodiment 8]
The following will describe still another embodiment of the present invention with reference to FIG. Configurations other than those described in the present embodiment are the same as those in the first to seventh embodiments. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiments 1 to 7 are given the same reference numerals, and descriptions thereof are omitted.

  As shown in FIG. 21, the sensor camera 140 of the present embodiment is obtained by adding the function of the display output block 150 to the sensor camera 60 of the seventh embodiment, and binarizing the captured image and the defective portion. The image and the image highlighting the defective portion are combined and output to the monitor.

  As shown in FIG. 21, the display output block 150 of the sensor camera 140 includes an emphasis display generation unit 151 as an emphasis display generation unit, a binarization display generation unit 152 as a binarization display generation unit, and a switch 153. A pixel data synthesis output unit 154 as a pixel data synthesis unit, a display image generation unit 155, an image memory unit 156, and an image output unit 157.

  In the display output block 150, the binarized display generation unit 152 generates binary image data of the defective portion with respect to the image data extracted by the defect detection unit 91 of the defect detection block 90. Further, highlight display image data of the defect portion is generated by the highlight display generation unit 151 from the defect position information and the like stored in the defect data storage unit 92 of the defect detection block 90. As an example of highlighting, it is realized by a method of surrounding the defect portion with a square line or the like.

  The switch 153 selects display of the captured image, the binarized image of the defective portion, and the highlighted image. The switch 153 synthesizes the image data selected by the pixel data synthesis output unit 154, generates image data to be actually displayed by the display image generation unit 155, and stores it in the image memory unit 156. The image output unit 157 outputs a signal for outputting the display image data stored in the image memory unit 156 to the monitor unit 52, and displays an image in which the defective portion is highlighted on the monitor unit 52.

  With the above function, the defect of the display device can be detected and the defect portion can be directly highlighted on the monitor unit 52. Therefore, the defect position can be easily reconfirmed by the operator of the inspection apparatus or the visual inspector. .

  The present invention relates to an image processing apparatus, an image processing program, and an imaging apparatus for detecting point defects and line defects, which are main defective items of a display panel using a flat panel such as a liquid crystal display, a plasma display, and a liquid crystal projector. Can be applied to.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an embodiment of an image processing apparatus according to the present invention, and is a block diagram illustrating a configuration of an image processing unit. It is a block diagram which shows the structure of the said image processing apparatus. (A) (b) (c) is a figure which shows the structure of the line buffer memory in the said image processing part. (A) is a top view which shows the movement order of the comparison calculation object area | region in the said image processing part, (b) is a top view which shows a comparison calculation object area | region. It is a block diagram which shows a line buffer memory and a comparison arithmetic processing circuit in case a horizontal pixel number is 100 pixels. It is a top view which shows the center imaging pixel and peripheral imaging pixel in a comparison calculation object area | region of 13x21 pixel. It is a top view which shows the center imaging pixel and peripheral imaging pixel in the case of performing a comparison calculation process using a 5x5-pixel image filter in the comparison calculation object area | region of 13x17 pixel. It is a flowchart which shows the image processing operation | movement in the said image processing part. (A) is a top view which shows the position pattern of the comparison calculation object area | region in a flat panel, (b) is a top view which shows a comparison calculation object area | region. It is a main flowchart which shows the image processing operation | movement in the said image processing part including the time when the comparison calculation object area | region is located in the edge part of a flat panel. It is a subroutine flowchart which shows the comparison calculation process operation in the said image process part including the time when the comparison calculation object area | region is located in the edge part of a flat panel. FIG. 10 is a block diagram illustrating another embodiment of the image processing apparatus according to the present invention and illustrating a configuration of an image processing unit. FIG. 24 is a block diagram illustrating still another embodiment of the image processing device according to the present invention and illustrating a configuration of an image processing unit. It is a top view which shows the comparison calculation object area | region in the said image processing part. FIG. 29 is a plan view showing a comparison calculation target region in an image processing unit according to still another embodiment of the image processing device of the present invention. FIG. 24 is a block diagram illustrating still another embodiment of the image processing apparatus according to the present invention and illustrating a configuration of a defect detection system. It is a block diagram which shows the structure of the sensor camera in the said defect detection system. It is a flowchart which shows the image processing operation in the said sensor camera. FIG. 24 is a block diagram illustrating still another embodiment of the image processing apparatus according to the present invention and illustrating a configuration of a sensor camera in the defect detection system. FIG. 24 is a block diagram illustrating still another embodiment of the image processing apparatus according to the present invention and illustrating a configuration of a defect detection system. It is a block diagram which shows the structure of the sensor camera in the said defect detection system. (A) is a figure which shows the conventional image processing apparatus, Comprising: It is a figure which shows the lightness and darkness of the image in the XX cross section of the flat panel shown in (c), (b) is a figure of the flat panel shown in (c). It is a figure which shows the lightness and darkness of the image in a YY line cross section, (c) is a top view which shows the structure of a flat panel. It is a block diagram which shows the structure for performing the defect detection of a flat panel in the said conventional image processing apparatus. It is a figure which shows the other conventional image processing apparatus and shows the defect detection method of a flat panel. FIG. 15 is a plan view showing another filter processing area adjacent to a flat panel when a defect is detected in the image processing apparatus according to still another conventional image processing apparatus. It is a block diagram which shows the structure of the image process part in the said image processing apparatus.

Explanation of symbols

1 Flat panel (display panel)
3 Comparison calculation target area 5 Imaging device 10 Image processing device 12 Image memory (image memory for storing defect information)
14 General management section (buffer length changing means, pixel number cn changing means, fixed length setting means, horizontal vertical ratio setting means, vertical ratio setting means)
20 Image processing unit 21 Image memory control circuit (image memory input control means)
22 Image memory address control circuit for input 23a Vertical memory address control circuit (for input) (vertical memory address control means)
23b Horizontal memory address control circuit (for input)
24 line buffer memory (line buffer memory unit)
24a Line buffer memory (1, 1)
24b Line buffer memory (1, 2)
24c line buffer memory (1, 3)
24d line buffer memory (2,1)
24e Line buffer memory (2, 2)
24f line buffer memory (2, 3)
24g line buffer memory (3, 1)
24h Line buffer memory (3, 2)
24i line buffer memory (3, 3)
25. Comparison operation processing circuit (comparison operation processing means)
26 output line buffer memory 27 output image memory address control circuit 28a vertical memory address control circuit (for output)
28b Horizontal memory address control circuit (for output)
30 Image Processing Unit 40 Image Processing Unit 44 Line Buffer Memory 44a Line Buffer Memory (1, 1)
44b Line buffer memory (1, 2)
44c Line buffer memory (1, 3)
44d line buffer memory (2,1)
44e Line buffer memory (2, 2)
44f Line buffer memory (2, 3)
44g line buffer memory (3, 1)
44h Line buffer memory (3, 2)
44i line buffer memory (3, 3)
45a Comparison calculation processing circuit 45b Comparison calculation processing circuit 50 Defect detection system 51 Stage 54 Defect determination processing section 55 General control section (selection control means, inter-pixel interpolation means)
56 Stage controller (moving means)
57 Stage driver (moving means)
60 sensor camera 61 timing signal generator (timing control means)
63 Image data output unit (external output means)
70 Sensor Unit 71 Line Sensor 72a Amplifier 72b Amplifier 80 Comparison Operation Block 81a Multiplexer (MUX1)
81b Multiplexer (MUX2)
81c Multiplexer (MUX3)
82 A / D converter (conversion means)
84 Line buffer memory (line buffer memory unit)
84a Line buffer memory (1, 2)
84b Line buffer memory (1, 3)
84c Line buffer memory (2, 2)
84d line buffer memory (2, 3)
84e Line buffer memory (3, 2)
84f Line buffer memory (3, 3)
85 Comparison calculation processing circuit (Comparison calculation processing means)
90 Defect detection block 91 Defect detection unit (defect detection means)
92 Defect data storage unit 100 Sensor camera 110 Sensor unit 111 TDI sensor block 112 Shift register 113 Analog switch (switching means)
DESCRIPTION OF SYMBOLS 120 Sensor camera 121 Micro stage 122 Optical unit 140 Sensor camera 150 Display output block 151 Emphasis display production | generation part (emphasis display production | generation means)
152 Binarization display generation unit (binarization display generation means)
153 Switch 154 Pixel data composition output unit (pixel data composition means)
155 Display image generation unit 156 Image memory unit 157 Image output unit

Claims (16)

From the image data of the display panel stored in the image memory, the number of pixels to be compared (h is an integer equal to or greater than 2) is calculated for each pixel number cm (cm is a positive integer) in the horizontal direction. The number of pixels in the horizontal operation area ((h−1) × cm + 1) and the number of vertical operation pixels v (v is an integer of 2 or more) for each pixel number cn (cn is a positive integer) in the vertical direction. For a comparison calculation target region configured by a pixel matrix with a pixel composed of the number of vertical calculation target region pixels ((v−1) × cn + 1) having a comparison calculation target pixel, at least one of cm or cn is 2 An integer above), an image processing apparatus for detecting a point / line defect in a display panel by performing a comparison calculation process on each of the comparison calculation target pixels of the horizontal calculation pixel number h × vertical calculation pixel number v,
Vertical memory address control means for setting an address for reading image data for one horizontal line from the image data of the display panel stored in the image memory so as to be every pixel number cn in the vertical direction;
A set of line buffer memories having a horizontal calculation pixel number h that continuously stores each pixel data of at least the horizontal calculation region pixel number ((h−1) × cm + 1) in the horizontal line is used as the set. A line buffer memory unit having v sets of operation pixel numbers;
Image memory input control means for sequentially reading each pixel data of a horizontal line at the address set by the vertical memory address control means from the image memory for each of a plurality of lines, and storing them in the line buffer memory in order.
A comparison calculation processing means for performing a pixel-to-pixel comparison calculation using pixel data of the comparison calculation target pixels output from the plurality of line buffer memories, respectively.
An image processing apparatus comprising a defect information storing image memory for storing a calculation result obtained by the comparison calculation processing means.   2. The image processing apparatus according to claim 1, wherein the defect information storing image memory is composed of an image memory storing image data of the display panel.   The comparison calculation processing means has at least 2 × 2 to the number of horizontal calculation pixels h × the number of vertical calculation pixels v for each comparison calculation target pixel of the horizontal calculation pixel count h × vertical calculation pixel count v. The image processing apparatus according to claim 1, wherein an inter-pixel comparison calculation is performed for each comparison calculation target pixel pattern.   4. The image processing apparatus according to claim 1, further comprising buffer length changing means for changing a buffer length of each line buffer memory.   5. The image processing apparatus according to claim 1, further comprising a pixel number cn changing unit for changing a pixel number cn at an address set by the vertical memory address control unit.   6. The image processing apparatus according to claim 1, further comprising fixed length setting means for setting the buffer length of the line buffer memory to a fixed length. The bus width of the line buffer memory is expanded to a bus width n times (n: an integer of 2 or more) the bit length representing one pixel,
The comparison operation processing means includes n sets of comparison operation processing circuits for performing an inter-pixel comparison operation corresponding to the output of each pixel data by the line buffer memory having the n-times bus width. Item 7. The image processing apparatus according to any one of Items 1 to 6.   The number of pixels in the horizontal direction and the vertical direction of the image pickup pixels by the image pickup device corresponds to the image data picked up at integer multiple intervals of the number of display pixels, and the number of pixels in the horizontal direction cm and the vertical direction in the comparison calculation target region A horizontal / vertical direction ratio setting means is provided for setting the number of pixels cn of the display to be an integral multiple of the number of display pixels in the horizontal direction and the number of display pixels in the vertical direction of the display panel. The image processing apparatus according to 4 or 5. Corresponding to the image data in which the number of imaging pixels in the vertical direction of the imaging pixels by the imaging device is captured at an integer multiple interval of the number of display pixels, the number of vertical pixels cn in the comparison calculation target region is
7. The image processing apparatus according to claim 6, further comprising a vertical direction ratio setting means for setting to be an integral multiple of the number of display pixels in the vertical direction on the display panel. An image processing program for operating the image processing apparatus according to any one of claims 1 to 9,
An image processing program for causing a computer to function as each of the above means. A horizontal calculation region having a horizontal calculation pixel number h (h is an integer of 2 or more) for each pixel number cm (cm is a positive integer) in the horizontal direction from image data obtained by photographing the display panel. The number of pixels ((h-1) × cm + 1) and the number of pixels to be compared in the vertical direction v (v is an integer of 2 or more) for each pixel number cn (cn is a positive integer) in the vertical direction With respect to a comparison calculation target area configured by a pixel matrix with a pixel composed of the number of vertical calculation target area pixels ((v−1) × cn + 1) having pixels (at least one of cm or cn is an integer of 2 or more) An imaging device that detects a point / line defect in a display panel by performing a comparison calculation process on each comparison calculation target pixel of the number of horizontal calculation pixels h × the number of vertical calculation pixels v,
A sensor composed of a line sensor or a TDI sensor arranged at equal intervals for storing image data of a photographed display panel for each line;
A plurality of multiplexers for selecting the plurality of sensors storing the image data so as to be every number of pixels cn in the vertical direction;
Conversion means for digitally converting the image data of the sensor selected by each of the multiplexers;
A line buffer memory unit provided with (vertical operation pixel number h-1) as one set in the variable length line buffer memory capable of setting the pixel data to be stored in the number of pixels cm as one set. When,
Timing control means for sequentially storing the image data of the sensors selected by the multiplexer in the line buffer memory sequentially through the conversion means;
Comparison operation processing means for performing inter-pixel comparison using image data converted by the conversion means and pixel data output from each line buffer memory;
Defect detection means for detecting a defect portion from the calculation result by the comparison calculation processing means;
An image pickup apparatus comprising: an external output unit that outputs a detection result of the defect detection unit to the outside. Each sensor is
A line sensor;
A shift register that collectively stores the pixel data of the line sensor;
12. The imaging apparatus according to claim 11, further comprising switching means for switching whether to transfer pixel data from the sensor to an adjacent sensor.   The imaging apparatus according to claim 11 or 12, further comprising selection control means for controlling selection of the sensor in the multiplexer so as to be an arbitrary sensor. The plurality of sensors are respectively mounted on a plurality of support bases,
An optical unit that distributes and projects the same captured image in the direction of the plurality of support bases, and
14. A moving unit that moves the support base on which the plurality of sensors are mounted by an integral multiple of the imaging pixel pitch with respect to the vertical direction of the captured image. Imaging device. The moving means moves the support base on which the plurality of sensors are mounted only by a real value multiple of the imaging pixel pitch only in the vertical direction of the captured image or in both the horizontal direction and the vertical direction of the captured image,
The image pickup apparatus according to claim 14, further comprising an inter-pixel interpolation unit that interpolates and synthesizes the acquired pixel data of the plurality of sensors as inter-pixel interpolation data. The external output means includes
Binarized display generating means for performing binarized display of pixel data of the defective portion extracted from the defect detecting means;
Based on the pixel data of the defective portion, highlight generation means for highlighting the peripheral portion of the defect,
The pixel data binarized and displayed by the binarized display generating unit, the pixel data of the peripheral portion of the defect highlighted by the highlighted display generating unit, and other pixel data are combined to generate a display image. 16. The image pickup apparatus according to claim 11, further comprising pixel data synthesizing means.

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