JP2008278257A - Receiving circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the problem wherein the circuit area of the conventional receiving circuit becomes large. <P>SOLUTION: This receiving circuit comprises: first and second input terminals; a first comparator COMP1 connected to the first input terminal through a first capacitor C1 and connected to the second input terminal through a second capacitor C2; a second comparator COMP2 connected to the second input terminal through a third capacitor C3 and connected to the first input terminal through a fourth capacitor C4; a first bias voltage setting circuit for setting bias voltage of an input terminal of the first comparator COMP1; a second bias voltage setting circuit for setting bias voltage of an input terminal of the second comparator COMP2; and an output signal generation circuit for setting an output signal to a first logical level on the basis of a first pulse outputted by the first comparator COMP1 and setting the output signal to a second logical level on the basis of a second pulse outputted by the second comparator COMP2. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The receiving circuit of the present invention particularly relates to a receiving circuit that converts a differential signal into a single-ended signal.

  In communication performed between a transmitter and a receiver, in order to improve signal reliability (for example, noise resistance) against noise mixed in a communication line connecting the transmitter and the receiver, differential Signals are transmitted and received using signals. Further, when connecting the transmitter and the receiver, the transmitter and the receiver are connected via a coupling capacitor in order to cut off the DC component of the signal between the transmitter and the receiver. . Examples of receiving circuits used for such transmitters and receivers are disclosed in Patent Documents 1 and 2 (hereinafter referred to as Conventional Examples 1 and 2).

  FIG. 4 shows a circuit diagram of the receiving circuit RC according to the conventional example 1 and the interface circuit 100 added thereto. As shown in FIG. 4, in Conventional Example 1, differential signals output from the transmitter are input to the interface circuit 100 from input terminals B1 and B2, respectively. This differential signal is input to the comparators CMN and CMP via the capacitors C101 and C102 in the interface circuit 100. At this time, in the interface circuit 100, the DC voltage of the node connected to the comparators CMN and CMP of the capacitor C101 is converted into a resistance division ratio by a plurality of resistors connected in series between the power supply node VCC and the ground node GND. Set by. On the other hand, the DC voltage of the node connected to the comparators CMN and CMP of the capacitor C102 is set based on the voltage generated by the voltage source (in this example, VCC / 2 (half the power supply voltage)). With such a configuration, the comparators CMN and CMP generate a signal based on the input differential signal, and the receiving circuit RC receives this signal. In Conventional Example 1, the interface circuit 100 removes the DC component output from the transmitter.

FIG. 5 shows a circuit diagram of the receiving circuit 200 according to the second conventional example. In the example shown in FIG. 5, the receiver IC2 receives the differential signal output from the driver IC1 via the capacitors C201 and C202. At this time, the voltage at the receiver side node of the capacitors C201 and C202 is set to a value obtained by dividing the bias voltage (−5.2V in FIG. 5) and the ground voltage by a resistor. With this configuration, the receiver IC 2 generates a signal based on the differential signal. That is, in the conventional example 2, the DC component output from the driver IC1 is removed by the capacitors C201 and C202.
JP-A-3-216045 JP-A-6-97967

  However, when a differential signal having a binary signal such as a clock signal is input as an input signal, in conventional examples 1 and 2, input is performed according to the time constant determined by the capacitance value of the capacitor and the resistance value of the resistor. The rise and fall of the signal is dull. When the rise and fall of the input signal become dull, there is a problem that the comparators CMN and CMP in the conventional example 1 or the receiver IC 2 in the conventional example 2 cannot correctly reproduce the signal waveform of the differential signal. In order to solve this problem, it is necessary to increase at least one of the capacitance value and the resistance value to increase the time constant. However, when such measures are taken, the receiving circuits according to the conventional examples 1 and 2 have a problem that the element area of the capacitor or resistor increases.

  According to one embodiment of the present invention, first and second input terminals to which a differential signal is input, a non-inverting input terminal connected to the first input terminal via a first capacitor, and the second A first comparator comprising an inverting input terminal connected to the second input terminal via a second capacitor; a non-inverting input terminal connected to the second input terminal via a third capacitor; A second comparator comprising a first input terminal and an inverting input terminal connected via a fourth capacitor; and a non-inverting input terminal of the first comparator for a first threshold voltage A first bias voltage setting circuit that sets a bias voltage of the inverting input terminal of the first comparator to be high and a second bias voltage of the second comparator with respect to a second threshold voltage. The bias voltage of the non-inverting input terminal is set low so that the second comparator Based on the second bias voltage setting circuit that sets the bias voltage of the input terminal high, and the first pulse output from the first comparator, the output signal is set to the first logic level, and the second comparator And an output signal generation circuit that sets the output signal to a second logic level based on the second pulse to be output.

  According to the receiving circuit of the present invention, the output signal generation circuit inverts the logic of the output signal based on the first and second pulses, so that the output signal generation circuit is based on the logic inversion of the differential signal. Outputs a single-ended signal. Therefore, it is sufficient that the first and second comparators can generate the first and second pulses corresponding to the logic inversion timing in the differential signal. For this reason, even if the time constants at the input terminals of the first comparator and the second comparator are set to be small, the receiving circuit according to the present invention provides a single-ended signal based on the logical inversion of the differential signal. It is possible to output. In addition, since the time constants at the input terminals of the first comparator and the second comparator can be set small, it is necessary to connect the first and second bias voltage setting circuits to the non-inverting input terminal and the inverting input terminal. Even when a resistor for determining a constant is inserted, the resistance value of the resistor can be set small.

  According to the receiving circuit of the present invention, it is possible to reduce the circuit area by reducing the ratio of the capacitor or resistor to the circuit area.

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. A circuit diagram of the receiving circuit 1 according to the present embodiment is shown in FIG. As shown in FIG. 1, the receiving circuit 1 includes first to fourth capacitors (capacitors C1 to C4 in the figure), a first bias voltage generation circuit 10, a second bias voltage generation circuit 11, a first bias voltage generation circuit 11, and a first bias voltage generation circuit 11. The comparator COMP1, the second comparator COMP2, and the output signal generation circuit 12 are included. The receiving circuit 1 has a first input terminal BP and a second input terminal BM, and one of the differential signals is input from the first input terminal BP and the difference from the second input terminal BM. The other signal of the motion signals is input.

  The first comparator COMP1 has a non-inverting input terminal and an inverting input terminal. When the voltage at the non-inverting input terminal is higher than the voltage at the inverting input terminal, the first comparator COMP1 outputs a high level (for example, a power supply voltage). If the voltage at the inverting input terminal is lower than the voltage at the inverting input terminal, a low level (for example, ground voltage) is output. In the first comparator COMP1, the input voltage of the comparator whose logic level of the output signal is inverted is referred to as a first threshold voltage Vth1. The second comparator COMP2 has a non-inverting input terminal and an inverting input terminal, and outputs a high level (for example, power supply voltage) if the voltage at the non-inverting input terminal is higher than the voltage at the inverting input terminal. If the voltage at the terminal is lower than the voltage at the inverting input terminal, a low level (for example, ground voltage) is output. Note that, in the second comparator COMP2, the input voltage of the comparator at which the logic level of the output signal is inverted is referred to as a second threshold voltage Vth2.

  The capacitor C1 is connected between the first input terminal BP and the non-inverting input terminal of the first comparator COMP1. The capacitor C2 is connected between the second input terminal BM and the inverting input terminal of the first comparator COMP1. The capacitor C3 is connected between the second input terminal BM and the non-inverting input terminal of the second comparator COMP2. The capacitor C4 is connected between the first input terminal BP and the inverting input terminal of the second comparator COMP2.

  The first bias voltage generation circuit 10 applies different bias voltages to the non-inverting input terminal and the inverting input terminal of the first comparator COMP1. The first bias voltage generation circuit 10 generates a bias voltage such that the bias voltage at the inverting input terminal is higher than the first threshold voltage Vth1, and the bias voltage at the non-inverting input terminal is lower than the first threshold voltage Vth1. Generate. In the present embodiment, the first bias voltage generation circuit 10 generates a bias voltage based on a resistance ratio of resistors connected in series between the power supply node VCC and the ground node GND.

  The first bias voltage generation circuit 10 includes first to fourth resistors (resistors R11 to R14 in the drawing). The resistor R11 is connected between a power supply terminal (hereinafter referred to as a power supply node) VCC and a non-inverting input terminal of the first comparator COMP1. The resistor R12 is connected between a non-inverting input terminal of the first comparator COMP1 and a ground terminal (hereinafter referred to as a ground node) GND. The resistor R13 is connected between the power supply node VCC and the inverting input terminal of the first comparator COMP1. The resistor R14 is connected between the inverting input terminal of the first comparator COMP1 and the ground node GND. Here, the resistance value of the resistor R11 is set larger than the resistance value of the resistor R12, and the resistance value of the resistor R13 is set smaller than the resistance value of the resistor R14. By setting the resistance value as described above, the first bias voltage generation circuit 10 applies the bias voltage described above to the non-inverting input terminal and the inverting input terminal of the first comparator COMP1. In the following description, a connection point between the resistors R11 and R12 and the non-inverting input terminal of the first comparator COMP1 is referred to as a node Na, and the resistors R13 and 14 and the inverting input terminal of the first comparator COMP1 are connected to each other. The connection point is referred to as a node Nb.

  The second bias voltage generation circuit 11 applies different bias voltages to the non-inverting input terminal and the inverting input terminal of the second comparator COMP2. The second bias voltage generation circuit 11 generates a bias voltage such that the bias voltage at the inverting input terminal is higher than the second threshold voltage Vth2, and the bias voltage at the non-inverting input terminal is lower than the second threshold voltage Vth2. Generate. In the present embodiment, the second bias voltage generation circuit 11 generates a bias voltage based on the resistance ratio of a resistor connected in series between the power supply node VCC and the ground node GND.

  The second bias voltage generation circuit 11 has fifth to eighth resistors (resistors R15 to R18 in the drawing). The resistor R15 is connected between the power supply node VCC and the non-inverting input terminal of the second comparator COMP2. The resistor R16 is connected between the non-inverting input terminal of the second comparator COMP2 and the ground node GND. The resistor R17 is connected between the power supply node VCC and the inverting input terminal of the second comparator COMP2. The resistor R18 is connected between the inverting input terminal of the second comparator COMP2 and the ground node GND. Here, the resistance value of the resistor R15 is set larger than the resistance value of the resistor R16, and the resistance value of the resistor R17 is set smaller than the resistance value of the resistor R18. By setting the resistance value as described above, the second bias voltage generation circuit 11 applies the bias voltage described above to the non-inverting input terminal and the inverting input terminal of the second comparator COMP2. In the following description, a connection point between the resistors R15 and R16 and the non-inverting input terminal of the second comparator COMP2 is referred to as a node Nc, and the resistors R17 and R18 and the inverting input terminal of the second comparator COMP2 are connected to each other. The connection point is referred to as a node Nd.

  In this embodiment, the capacitance values of the capacitors C1 to C4 are the same, the combined resistance value of the resistors R11 and R12 (R11 × R12 / (R11 + R12)), and the combined resistance value of the resistors R13 and R14 (R13 × R14). / (R13 + R14)), the combined resistance value of the resistors R15 and R16 (R15 × R16 / (R15 + R16)) and the combined resistance value of the resistors R17 and R18 (R17 × R18 / (R17 + R18)) are the same. As a result, the time constant X set in the nodes Na to Nd becomes the same. Further, the bias voltage of the non-inverting input terminal and the bias voltage of the inverting input terminal in the first and second comparators are set so that their voltage waveforms cross each other due to the fluctuation of the node voltage according to the differential signal. . For example, when the first and second threshold voltages are set as the center voltage, and the bias voltage is set so that the difference from the first and second threshold voltages is equal to or less than the minimum value of the fluctuation of the node voltage according to the differential signal. good.

  The output signal generation circuit 12 inverts the logic level of the output signal SOUT based on the output signal of the first comparator COMP1 and the output signal of the second comparator COMP2. The output signal generation circuit 12 can use, for example, an SR latch. The SR latch has a set terminal S and a reset terminal R. The SR latch sets the output signal SOUT to the first logic level (for example, high level) when the rising edge of the pulse signal is input to the set terminal S, and outputs the output signal when the rising edge of the pulse signal is input to the reset terminal R. SOUT is set to the second logic level (for example, low level). In the present embodiment, the output of the first comparator COMP1 is connected to the set terminal S of the SR latch, and the output of the second comparator COMP2 is connected to the reset terminal R.

  Next, an example of a timing chart showing the operation of the receiving circuit 1 is shown in FIG. With reference to FIG. 2, the operation of the receiving circuit 1 according to the present embodiment will be described. In the example shown in FIG. 2, the level of the input signal is the ground voltage during the period before the timing T0. The voltages at the nodes Na to Nd are bias voltages. As for the voltages of the node Na and the node Nb, the voltage of the node Na is low and the voltage of the node Nb is high with the first threshold voltage Vth1 as the center. On the other hand, with regard to the voltages at the nodes Nc and Nd, the voltage at the node Nc is low and the voltage at the node Nd is high, centering on the second threshold voltage Vth2.

  At time T0, the signal rises and the level of the input signal becomes the bias level. At the rise of the signal at this timing T0, the signal levels input to the first input terminal BP and the second input terminal BM rise in the same way. Therefore, the voltage levels of the nodes Na to Nd change in the same direction and with the same fluctuation range. Further, the voltage relationship between the nodes Na to Nb at the timing T0 does not change the voltage relationship between the node Na and the node Nb and the voltage relationship between the node Nc and the node Nd, and therefore the outputs of the first comparator COMP1 and the second comparator COMP2. Maintains a low level.

  Subsequently, when the input signal becomes a differential signal that changes in opposite phase at the timing T1, the voltages at the nodes Na to Nd vary according to the change in the differential signal. At timing T1, the voltage at the node Na increases and the voltage at the node Nb decreases. At this time, the voltage relationship between the node Na and the node Nb is reversed. Accordingly, the voltage relationship between the non-inverting input terminal and the inverting input terminal of the first comparator COMP1 is reversed, and the output of the first comparator COMP1 is switched from the low level to the high level. Further, the voltages of the nodes Na and Nb change with the amplitude corresponding to the voltage fluctuation of the input signal, respectively, but after this voltage change reaches the apex, it returns to the bias voltage before the voltage fluctuation according to the time constant X. To do. That is, the voltage waveforms at the nodes Na and Nb intersect at the timing T2. As a result, the output of the first comparator COMP1 is switched from the high level to the low level. That is, the first comparator COMP1 outputs a first pulse signal that becomes a high level during the period from the timing T1 to the timing T2 in accordance with the change in the input signal at the timing T1. Then, the output signal generation circuit 12 switches the output signal from the low level to the high level according to the first pulse signal output from the first comparator COMP1 (timing T1).

  On the other hand, at the timing T1, the voltage at the node Nc decreases and the voltage at the node Nd increases. That is, the voltage difference between the node Nc and the node Nd increases. Therefore, the voltage relationship between the non-inverting input terminal and the inverting input terminal of the second comparator COMP2 is not reversed, and the output of the second comparator COMP2 maintains the low level.

  Subsequently, when the signal level of the input signal is reversed at the timing T3, the voltages at the nodes Na to Nd vary according to the change in the differential signal. At timing T3, the voltage at the node Na decreases and the voltage at the node Nb increases. At this time, the voltage difference between the node Na and the node Nb increases. Therefore, the voltage relationship between the non-inverting input terminal and the inverting input terminal of the first comparator COMP1 is not reversed, and the output of the first comparator COMP1 is maintained at a low level.

  On the other hand, at the timing T3, the voltage at the node Nc rises and the voltage at the node Nd falls. That is, the voltage relationship between the node Nc and the node Nd is reversed. Therefore, the voltage relationship between the non-inverting input terminal and the inverting input terminal of the second comparator COMP2 is reversed, and the output of the second comparator COMP2 is switched from the low level to the high level. Further, the voltages of the nodes Nc and Nd change with the amplitude corresponding to the voltage fluctuation of the input signal, respectively, but after this voltage change reaches the apex, the bias voltage before the voltage fluctuation is restored according to the time constant X. To do. That is, the voltage waveforms at the nodes Nc and Nd intersect at the timing T4. As a result, the output of the second comparator COMP2 is switched from the high level to the low level. That is, the second comparator COMP2 outputs a second pulse signal that becomes a high level during the period from the timing T3 to the timing T4 in accordance with the change of the input signal at the timing T3. Then, the output signal generation circuit 12 switches the output signal from the high level to the low level according to the second pulse signal output from the second comparator COMP2 (timing T3).

  The operations at timings T5 and T6 and the operations at timings T9 and T10 are substantially the same as the operations at timings T1 and T2, and the operations at timings T7 and T8 are substantially the same as the operations at timings T3 and T4. Therefore, description of these operations is omitted.

  From the above description, the receiving circuit 1 according to the present embodiment includes the first comparator COMP1 that detects the rising timing of the signal input to the first input terminal BP among the differential signals, and the differential signal. Based on the second comparator COMP2 that detects the falling timing of the signal input to the first input terminal BP, and the first pulse signal that is output from the first comparator COMP1, the output signal is set to the high level. The output signal generation circuit 12 sets the output signal to a low level based on the second pulse signal output from the second comparator COMP2. That is, the first comparator COMP1 and the second comparator COMP2 need only detect the timing at which the logic level of the differential signal switches. At this time, the pulse width of the pulse signal output from the comparator may be shorter than the switching period of the differential signal, and may be as long as the output signal generation circuit 12 can sufficiently recognize. As a result, the receiving circuit 1 can set the time constant set at the nodes Na to Nd so small that the comparator can generate a pulse signal based on voltage fluctuations at the nodes Na to Nd.

  Thus, in the receiving circuit 1, since the time constant can be made smaller than before, it is possible to reduce the capacitance values of the capacitors C1 to C4 or the resistance values of the resistors R11 to R18, for example. That is, the receiving circuit 1 can reduce the element area of the capacitor or the resistor. For example, in the case of an input signal having a frequency of 100 kHz, the time constant X necessary for correctly handling the waveform of this signal is 1/100 kHz = 0.01 msec. When this time constant X is realized in the conventional examples 1 and 2, the time constant X = C × R = 10 pF × 1 MΩ, the capacitance value of the coupling capacitor is about 10 pF, and the resistance value connected to the coupling capacitor The combined resistance value is about 1 MΩ. On the other hand, in the receiving circuit 1 according to the present embodiment, for example, there is no problem even if the time constant when handling an input signal having a frequency of 100 kHz is set to about 1/10 compared to the conventional one. For example, the resistance value can be set to 100 kΩ or less, and the capacitance value of the coupling capacitors (C1 to C4) can be set to 1 pF or less. Therefore, the receiving circuit 1 according to the present embodiment can reduce the circuit area as compared with the conventional circuit.

  In the receiving circuit 1 according to the present embodiment, the capacitors C1 to C4 are connected to the nodes Na to Nd, and the bias voltages of the nodes Na to Nd are the first bias voltage generation circuit 10 and the second bias voltage. These are set independently by the voltage generation circuit 11. Thereby, the time constants of the nodes Na to Nd can be set independently. It is also possible to set all the time constants of the nodes Na to Nd as the same value. In the present embodiment, the time constants of the nodes Na to Nd are all set to the same value. From this, the voltage fluctuations of the nodes Na to Nd all change at the same rate of change. That is, the voltages at the nodes Na to Nd change at the same timing with respect to the change in the differential signal. By setting the voltage fluctuations of the nodes Na to Nd in this way, the delay time between the fluctuation of the pulse signal output from the first comparator COMP1 and the second comparator COMP2 and the differential signal is at any timing. Be the same. Then, the output signal generation circuit 12 generates an output signal based on such a pulse signal, whereby the duty ratio of the differential signal and the duty ratio of the output signal can be made the same.

  Further, in Conventional Example 1 (see FIG. 4), the signal amplitude at nodes A and B decreases based on the resistance division ratio of resistors R101 to R104. Further, the signal amplitude at the node C decreases based on the resistance division ratio of the resistors R105 and R106. When such a decrease in signal amplitude occurs, the comparator may not be able to detect the switching of the input signal. However, in the receiving circuit 1 according to the present embodiment, since a signal is input from a connection point between resistors connected in series, the signal amplitude at the nodes Na to Nd does not decrease based on the resistance division ratio.

Embodiment 2
FIG. 3 shows a circuit diagram of the receiving circuit 2 according to the second embodiment. As illustrated in FIG. 3, the reception circuit 2 is a modification of the first bias voltage generation circuit 10 and the second bias voltage generation circuit 11 of the reception circuit 1. The receiving circuit 2 includes a first bias voltage generation circuit 20 and a second bias voltage generation circuit 21.

  The first bias voltage generation circuit 20 includes first and second resistors (resistors R21 and R22 in the drawing) and first and second voltage sources (voltage sources V1 and V2 in the drawing). Voltage source V1 is connected between ground node GND and resistor R21. The resistor R21 is connected between the voltage source V1 and the non-inverting input terminal of the first comparator COMP1. A connection point between the resistor R21 and the non-inverting input terminal of the first comparator COMP1 is referred to as a node Na. Voltage source V2 is connected between ground node GND and resistor R22. The resistor R22 is connected between the voltage source V2 and the inverting input terminal of the first comparator COMP1. A connection point between the resistor R22 and the inverting input terminal of the first comparator COMP1 is referred to as a node Nb.

  The second bias voltage generation circuit 21 includes third and fourth resistors (resistors R23 and R24 in the drawing) and third and fourth voltage sources (voltage sources V3 and V4 in the drawing). Voltage source V3 is connected between ground node GND and resistor R23. The resistor R23 is connected between the voltage source V3 and the non-inverting input terminal of the second comparator COMP2. A connection point between the resistor R23 and the non-inverting input terminal of the second comparator COMP2 is referred to as a node Nc. Voltage source V4 is connected between ground node GND and resistor R24. The resistor R24 is connected between the voltage source V4 and the inverting input terminal of the second comparator COMP2. A connection point between the resistor R24 and the inverting input terminal of the second comparator COMP2 is referred to as a node Nd.

  In the receiving circuit 2, the bias voltages of the nodes Na to Nd are set independently based on the voltages generated by the voltage sources V1 to V4. At this time, the setting values of the bias voltages of the nodes Na to Nd are the same as those in the first embodiment. The time constants at the nodes Na to Nd are set by the resistance values of the capacitors C1 to C4 and the resistors R21 to R24 corresponding to the capacitors. At this time, the method for setting the time constant is the same as in the first embodiment.

  From the above description, since the first comparator COMP1, the second comparator COMP2, and the output signal generation circuit 12 are used in the receiving circuit 2 according to the second embodiment, the node is the same as in the first embodiment. It is possible to reduce the time constant in Na to Nd.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

FIG. 3 is a circuit diagram of a receiving circuit according to the first exemplary embodiment; 3 is a timing chart illustrating the operation of the receiving circuit in the first embodiment. FIG. 4 is a circuit diagram of a receiving circuit according to a second exemplary embodiment. FIG. 6 is a circuit diagram of a receiving circuit in Conventional Example 1. FIG. 10 is a circuit diagram of a receiving circuit in Conventional Example 2.

Explanation of symbols

1, 2 Receiving circuits 10, 11, 20, 21 Bias voltage generating circuit 12 Output signal generating circuit BM, BP Input terminals C1-C4 Capacitors COMP1, COMP2 Comparator Na-Nd Nodes R11-R18, R21-R24 Resistors V1-V4 Voltage source VCC Power supply node GND Ground node Vth1, Vth2 Threshold voltage

Claims (6)

First and second input terminals to which a differential signal is input;
A first comparison comprising: a non-inverting input terminal connected to the first input terminal via a first capacitor; and an inverting input terminal connected to the second input terminal via a second capacitor. And
A second comparison comprising: a non-inverting input terminal connected to the second input terminal via a third capacitor; and an inverting input terminal connected to the first input terminal via a fourth capacitor. And
A first bias voltage for setting a bias voltage at the non-inverting input terminal of the first comparator lower than a first threshold voltage and setting a bias voltage at the inverting input terminal of the first comparator higher. A setting circuit;
A second bias voltage that sets a bias voltage of the non-inverting input terminal of the second comparator low with respect to a second threshold voltage and sets a bias voltage of the inverting input terminal of the second comparator high. A setting circuit;
The output signal is set to the first logic level based on the first pulse output from the first comparator, and the output signal is set to the second logic level based on the second pulse output from the second comparator. An output signal generation circuit;
A receiving circuit. The first bias voltage setting circuit includes: a first resistor connected between a power supply terminal and a non-inverting input terminal of the first comparator; a non-inverting input terminal of the first comparator; A second resistor connected between the terminal, a third resistor connected between the power supply terminal and the inverting input terminal of the first comparator, and an inverting input of the first comparator. A fourth resistor connected between the terminal and the ground terminal;
The second bias voltage setting circuit includes a fifth resistor connected between the power supply terminal and a non-inverting input terminal of the second comparator, and a non-inverting input terminal of the second comparator. A sixth resistor connected between the ground terminal, a seventh resistor connected between the power supply terminal and the inverting input terminal of the second comparator, and the second comparator. The receiving circuit according to claim 1, further comprising an eighth resistor connected between an inverting input terminal and the ground terminal. The time constant at the non-inverting input terminal of the first comparator is set by the capacitance value of the first capacitor and the combined resistance value of the first and second resistors,
The time constant at the inverting input terminal of the first comparator is set by the capacitance value of the second capacitor and the combined resistance value of the third and fourth resistors,
The time constant at the non-inverting input terminal of the second comparator is set by the capacitance value of the third capacitor and the combined resistance value of the fifth and sixth resistors,
The receiving circuit according to claim 2, wherein a time constant at an inverting input terminal of the second comparator is set by a capacitance value of the fourth capacitor and a combined resistance value of the seventh and eighth resistors. The first bias voltage setting circuit includes: a first voltage source that sets a voltage value of a non-inverting input terminal of the first comparator; and a non-inverting of the first voltage source and the first comparator. A first resistor connected between the input terminals; a second voltage source for setting a voltage value of an inverting input terminal of the first comparator; the second voltage source; and the first comparator. A second resistor connected between the inverting input terminals of
The second bias voltage setting circuit includes a third voltage source for setting a bias voltage of a non-inverting input terminal of the second comparator, and a non-inverting of the third voltage source and the second comparator. A third resistor connected to the input terminal; a fourth voltage source for setting a bias voltage of the inverting input terminal of the second comparator; and the fourth voltage source and the second comparison. The receiving circuit according to claim 1, further comprising a fourth resistor connected between the inverting input terminal of the amplifier. A time constant at a non-inverting input terminal of the first comparator is set by a capacitance value of the first capacitor and a resistance value of the first resistor;
A time constant at an inverting input terminal of the first comparator is set by a capacitance value of the second capacitor and a resistance value of the second resistor;
A time constant at a non-inverting input terminal of the second comparator is set by a capacitance value of the third capacitor and a resistance value of the third resistor;
The receiving circuit according to claim 4, wherein a time constant at an inverting input terminal of the second comparator is set by a capacitance value of the fourth capacitor and a resistance value of the fourth resistor.   The difference between the bias voltage of the non-inverting input terminal and the bias voltage of the inverting input terminal in the first and second comparators is such that the voltage waveforms cross each other due to the voltage fluctuation of the node according to the differential signal. The receiving circuit according to claim 1, wherein the receiving circuit is set.

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