JP2008277477A - Semiconductor substrate and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor substrate which is suitable for manufacturing a p-type transistor of high-speed operation and has a surface with a plane orientation [011], low manufacturing cost and sufficient bonding strength, and to provide a manufacturing method therefor. <P>SOLUTION: An epitaxial layer 41 is formed directly on a first substrate 40 whose surface having the plane orientation [011]. At this time, the epitaxial layer 41 is so formed that the edge rolloff of the substrate is offset, i.e., the thickness of the end portion of the epitaxial layer 41 is slightly thicker than that in the other region. Then, hydrogen ions are implanted into the epitaxial layer 41 and a second substrate (base substrate) 45 is bonded thereto. Thereafter, the epitaxial layer 41 is cleaved, at a portion having a high hydrogen concentration. As a result, a semiconductor substrate 46 wherein a [011] with monocrystalline layer 41 provided on the second substrate 45 is obtained. Meanwhile, the first substrate 40 left after cleavage is reused by polishing the surface thereof. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor substrate suitable for manufacturing a semiconductor device having a p-type field effect transistor and a manufacturing method thereof, and more particularly to a semiconductor substrate having a surface of {011} and a manufacturing method thereof.

  In recent years, information devices using computer technology tend to increase the amount of information handled. In particular, an information device having a moving image display function is required to process a large amount of information at high speed. In addition, information devices are required to improve information processing capability and to save power, and an n-type field effect transistor (hereinafter simply referred to as “n-type transistor”) and a p-type field effect transistor (hereinafter simply referred to as “p”). CMOS (Complimentary Metal Oxide Semiconductor) combined with a type transistor) is widely used.

  A general semiconductor device is manufactured using a silicon wafer having a surface of {001} (hereinafter referred to as a {001} silicon wafer). However, in such a semiconductor device, it is known that an n-type transistor operates at a high speed, but a p-type transistor operates at a low speed. For this reason, improvement of the operating speed of the p-type transistor is particularly demanded. The difference in operating speed between the n-type transistor and the p-type transistor in the semiconductor device using the {001} silicon wafer is due to the physical properties of the silicon crystal.

  In order to improve the operating speed of the p-type transistor, it has been proposed to introduce compressive strain in the channel length direction of the p-type transistor (for example, Patent Document 1). However, in order to form a higher-speed p-type transistor by this method, it is necessary to generate a large distortion. In this case, the following problem occurs.

  That is, in the technique disclosed in Patent Document 1, a silicon-germanium alloy (hereinafter referred to as “SiGe”) crystal is used for the source and drain, and this SiGe crystal has a larger lattice constant than Si (silicon) crystal. Is used to generate compressive strain in a channel made of Si crystal. However, a crystal lattice mismatch occurs at the interface between the SiGe crystal and the Si crystal, which causes a large number of dislocations in the operation region of the transistor, which increases the leakage current. Therefore, it is difficult to apply the technique disclosed in Patent Document 1 to, for example, a mobile device that requires a low standby current.

  The second problem is that the stress generated by the strain introduced by the SiGe crystal is as large as about 2 GPa. According to the material strength theory, the ideal fracture strength (ideal crystal fracture strength without distortion or wrinkles) is about 1/10 of Young's modulus, and the actual crystal fracture strength is even lower. It is about 1/100. In the case of a Si single crystal, the Young's modulus varies depending on the plane orientation, but is about 130-180 GPa. The stress that exceeds is generated. Although a high-purity silicon single crystal is used for the manufacture of the transistor, this stress state has a high risk from the mechanical point of view, and the crystal may be destroyed.

  In order to solve such a problem, Non-Patent Document 1 proposes to use a {011} silicon wafer. FIG. 1 shows the relationship between carrier density and hole mobility in (001) silicon wafer and (011) silicon wafer, where the horizontal axis represents carrier density and the vertical axis represents hole mobility. FIG. In FIG. 1, <011> and <001> indicate the channel length direction. Further, in this application, when a specific plane orientation is indicated, it is described as (001) or (011), and when equivalent plane orientations are collectively indicated, {001} or {011} is described.

  As can be seen from FIG. 1, when a {011} silicon wafer is used, about twice the hole mobility can be easily realized as compared with the case where a {001} silicon wafer is used, and high-speed operation is possible. A p-type transistor can be obtained. Patent Documents 2 and 3 describe a method of manufacturing an SOI (Silicon On Insulator) substrate (wafer) having a silicon layer having a surface of {011} and a semiconductor device using the substrate.

  However, silicon wafers with a surface of {011} have been produced on a small scale, but are currently difficult to mass-produce in terms of cost. The reason will be described below.

  In general, the Czochralski method (hereinafter referred to as “CZ method”) is used for industrial production of Si single crystals, and this is considered to remain unchanged in the future. In the CZ method, after a seed crystal is brought into contact with a silicon melt filled in a quartz crucible, the seed crystal is slowly pulled up while rotating the seed crystal to continuously grow a single crystal below the seed crystal. A single crystal is formed. The diameter of the ingot can be freely controlled by the pulling speed and the melt temperature. At present, a huge single crystal having a diameter of 300 mm, a length of 2 m, and a weight of 300 kg can be industrially produced.

  When a silicon single crystal is produced by the CZ method, an operation called necking is performed. As shown in FIGS. 2A and 2B, dislocations are introduced into the seed crystal 11 by thermal stress at the moment when the seed crystal 11 comes into contact with the melt 10. Therefore, if an ingot is produced by increasing the diameter as it is, a large number of dislocations remain in the ingot, and a high-quality single crystal cannot be obtained. Necking is performed in order to avoid such problems.

  That is, after bringing the seed crystal 11 into contact with the melt 10, the pulling speed and the melt temperature are adjusted so that the diameter of the crystal growing under the seed crystal 11 is about 4 to 5 mm. If the crystal growth is continued to some extent in this state, as shown in FIGS. 3A to 3C, the dislocations inherited from the seed crystal 11 move to the surface along with the crystal growth and are finally removed. It becomes a single crystal of dislocation. Thereafter, the pulling rate and the melt temperature are adjusted to grow the crystal thickly to a predetermined diameter as shown in FIG. Thereby, the ingot 13 which consists of a large diameter Si single crystal without a dislocation is obtained. A {001} wafer that is generally used at present is formed by processing an ingot made of a Si single crystal grown in the <001> direction.

  By the way, according to the dislocation theory of Si single crystal, the moving direction of the dislocation is <011>. Accordingly, when the Si single crystal 11 is grown in the <001> direction as shown in FIG. 5A, dislocations move to the surface side of the crystal by necking, and finally an ingot made of a dislocation-free Si single crystal. Can be formed. However, when the growth direction of the Si single crystal is <011>, the crystal grows in the direction of dislocation movement as shown in FIG. 5B, and it is difficult to eliminate the dislocation by necking.

  Even in the growth in the <011> direction, dislocations can be removed if the diameter of the crystal grown below the seed crystal is reduced to about 1 mm. According to the study by the inventors of the present application, it has been found that by reducing the diameter of the crystal to about 1 mm, the single crystallization rate becomes 90% or more even in the crystal growth in the <011> direction. However, in that case, since the mechanical strength of the necking portion is lowered, in consideration of work safety, only an ingot of 20 kg or less can be produced at the maximum, resulting in an increase in production cost.

  As described above, Patent Document 2 discloses an SOI substrate (wafer) having a silicon layer whose surface is {011}. However, this Patent Document 2 does not describe a specific method for forming the {011} silicon layer.

  The manufacturing method of the SOI substrate disclosed in Patent Document 3 has already been industrialized and is now called Smart Cut (registered trademark). A manufacturing method of an SOI substrate (semiconductor wafer) by Smart Cut will be described with reference to FIGS. Note that although a method for manufacturing an SOI substrate having a {011} silicon layer is described here, there are several variations of Smart Cut, and SOI substrates other than an SOI substrate having a {011} silicon layer are used. It is also used for production. Smart Cut is also described in Non-Patent Document 2.

  First, an Si crystal is grown in the <011> direction by a CZ method or the like to form an ingot made of a Si single crystal. Thereafter, the ingot is cut to obtain a first substrate 20 made of {011} silicon single crystal as shown in FIG.

Next, as shown in FIG. 6B, the surface of the first substrate 20 is oxidized to form a silicon oxide film 21. Thereafter, as shown in FIG. 6C, hydrogen ions (H ⁺ ) are implanted from one surface side of the first substrate 20. At this time, the position of the surface where hydrogen ions are most concentrated is determined by the acceleration voltage at the time of hydrogen ion implantation. Here, the surface having the highest concentration of hydrogen ions is indicated by reference numeral 22.

  On the other hand, as shown in FIG. 6D, a second substrate 25 is prepared as a base substrate (bonding substrate). As the second substrate 25, for example, a general {001} silicon substrate can be used. Then, as shown in FIG. 7A, the first substrate 20 on which the silicon oxide film 21 is formed is bonded onto the second substrate 25.

  Next, for example, when heat treatment is performed at a predetermined temperature, the first substrate 20 is cleaved on the surface where hydrogen ions are introduced as shown in FIG. 7B, and {011} silicon is formed on the second substrate 25. The single crystal layer 20a remains. Thereafter, heat treatment is performed to increase the bonding strength between the second substrate 25 and the silicon single crystal layer 20a.

  Next, the surface of the silicon single crystal layer 20a is polished and planarized. In this way, as shown in FIG. 7C, the SOI substrate 26 composed of the base substrate (second substrate 25), the silicon oxide film 21, and the {011} silicon single crystal layer 20a is completed. To do.

  On the other hand, after the cleaved surface of the first substrate 20 made of {011} silicon single crystal remaining in the step of FIG. 7B is polished and planarized, the silicon oxide film 21 is removed. The first substrate 20 is used again, and the steps shown in FIGS. 6A to 6D and FIGS. 7A to 7C are performed to form the SOI substrate 26.

  Thus, according to the method disclosed in Patent Document 3, a large number of SOI substrates can be manufactured using one {011} silicon single crystal substrate (first substrate 20). For this reason, even if an expensive {011} silicon single crystal substrate is used, the manufacturing cost per SOI substrate can be kept relatively low.

In addition, there exist some which were described in patent documents 4-7 and nonpatent literature 3-6 as a prior art considered to be related to this application.
US Pat. No. 6,621,131 Japanese Patent Laid-Open No. 03-19275 US Pat. No. 7,052,974 Japanese Patent Laid-Open No. 11-307413 JP 2004-79930 A JP 2004-214402 A JP 2004-79930 A M. Leong et al., Electrochem. Soc., PV 2004-1, 371 (2004) M. Bruel, Electron. Lett. 31, 1201 (1995) M. Kimura, Y. Saito, H. Daio, and K. Yakushiji, Jpn. J. Appl. Phys. Vol. 38, (1999), pp. 38. JEITA EMR-3001 "The Impact of Edge Roll-off on CMP Performance" published by JEITA. Oct. 2004 WS Capinski et al., Appl. Physs. Lett. 71, 2109 (1997) T. Fukuda et al., Procceedings of The 2ndSymp. On Defects in Si, edited by WM Bullis, U. Gosele, and F. Shimura (Electrochem. Soc., NJ, 1991), vol. 91-9, pp.173

  However, in the method described in Patent Document 3, since a single {011} silicon single crystal substrate is used many times, the {011} silicon single crystal substrate is brought into contact with a jig during heat treatment or transportation. The quality deteriorates due to wrinkles and crystal defects. For this reason, the number of SOI substrates that can be manufactured from a single {011} silicon single crystal substrate is limited, and it is difficult to further reduce the manufacturing cost of the SOI substrate.

  Patent Document 4 proposes that an epitaxial layer is formed on a silicon substrate, and an SOI substrate is manufactured by Smart Cut using the silicon substrate as a first substrate. In the method described in Patent Document 4, hydrogen ions are implanted into an epitaxial layer formed on a silicon substrate, bonded to a base substrate, and then cleaved at the epitaxial layer to produce an SOI substrate. The silicon substrate remaining after the cleavage can be used again as the first substrate by removing the silicon oxide film and then epitaxially growing a silicon layer thereon. In the method described in Patent Document 4, the silicon substrate can be used many times, and the manufacturing cost of the SOI substrate can be reduced.

  It is conceivable to manufacture an SOI substrate having a silicon layer whose surface is {011} using the technique described in Patent Document 4. However, when the semiconductor substrate having a surface of {011} is formed using the methods described in Patent Documents 3 and 4 based on experiments and research by the present inventors, the bonding strength between the base substrate and the silicon single crystal layer is low. It turned out to be insufficient.

  As described above, the object of the present invention is a semiconductor substrate having a surface orientation of {011}, low manufacturing cost, sufficient junction strength, and suitable for manufacturing a p-type transistor operating at high speed, and a manufacturing method thereof. Is to provide.

  According to one aspect of the present invention, in a semiconductor substrate having a base substrate and a silicon single crystal layer disposed above the base substrate, the surface orientation of the surface of the silicon single crystal layer is {011}, In addition, a semiconductor substrate is provided in which the silicon single crystal layer has a thickness distribution that cancels edge roll-off of the base substrate.

  In the present invention, the plane orientation of the surface of the silicon single crystal layer disposed above the base substrate is {011}. Therefore, the hole mobility is high, and the p-type transistor can be operated at high speed. In the present invention, the silicon single crystal layer has a thickness distribution that cancels the edge roll-off of the base substrate. For this reason, the bonding strength between the base substrate and the silicon single crystal layer is improved.

  According to another aspect of the present invention, a step of epitaxially growing a silicon single crystal layer on a first substrate made of a silicon single crystal whose surface plane orientation is {011}, and hydrogen ions are added to the silicon single crystal layer. A step of implanting, a step of bonding the first substrate on the second substrate with the silicon single crystal layer facing down, and a portion where the concentration of hydrogen in which the silicon single crystal layer is ion-implanted is high The silicon single crystal layer is formed by adjusting epitaxial growth conditions so as to have a thickness distribution that cancels edge roll-off of the first substrate or the second substrate. A method for manufacturing a semiconductor substrate is provided.

  In the present invention, a silicon single crystal layer is epitaxially grown immediately above a first substrate made of a silicon single crystal having a surface orientation of {011}. The silicon single crystal layer formed thereby has a surface orientation of {011} as in the first substrate. However, when the single crystal layer is formed, it is necessary to adjust the epitaxial growth conditions so that the thickness distribution cancels the edge roll-off of the first substrate or the second substrate described later.

  Next, hydrogen ions are implanted into the silicon single crystal layer. By this implantation of hydrogen ions, the silicon single crystal layer is easily cleaved.

  Next, a second substrate is prepared, and the first substrate is bonded onto the second substrate with the silicon single crystal layer on the lower side. In this case, since the silicon single crystal layer is formed so as to have a thickness distribution that cancels edge roll-off of the first substrate or the second substrate, the silicon single crystal layer and the second substrate The gap between them is reduced, and the silicon single crystal layer and the second substrate can be bonded with sufficient strength.

  Next, for example, by applying temperature, stress is generated in the portion where hydrogen ions are implanted to cleave the silicon single crystal layer. In this manner, a semiconductor substrate having a structure in which a {011} silicon single crystal layer is stacked on the second substrate is obtained. On the other hand, the first substrate after cleaving is made reusable by slightly polishing the surface.

  In the present invention, since the silicon single crystal layer and the second substrate can be bonded with sufficient strength, a highly reliable semiconductor device can be manufactured. Further, since the first substrate made of {011} silicon single crystal can be reused many times without being consumed, the manufacturing cost of the semiconductor substrate can be greatly reduced.

  Before explaining the embodiments of the present invention, the reason why a sufficient bonding strength cannot be obtained between the silicon single crystal layer and the base substrate by the methods described in Patent Documents 3 and 4 will be described below. Explain the results of the study.

  As shown in FIG. 8, the thickness of the peripheral portion of the wafer that becomes the substrate when manufacturing the semiconductor device is slightly reduced, and has a shape called edge roll-off. Edge roll-off occurs when the surface is polished by a CMP (Chemical Mechanical Polish) method during wafer manufacture. In the case of a standard 300 mm diameter wafer, a range from the wafer end to about 0.5 mm is called an edge portion, and a range from 2 mm from the wafer end is called an edge exclusion area (EEA). An area excluding the edge exclusion portion is called FQA (Fixed Quality Area). Usually, it is considered that the surface is flat in a region 3 mm or more away from the edge end. Here, an area 3 to 6 mm away from the edge end is referred to as a reference area. Ideally, the region excluding the edge portion (the region indicated by W in FIG. 8) is preferably flat (same thickness).

  Non-Patent Document 3 proposes to use ROA (Roll-Off Amount) as a parameter indicating the degree of edge roll-off. ROA is now an international standard as a parameter indicating the degree of edge roll-off. This parameter is defined as the amount of decrease in the thickness of the front surface at a position 1 mm from the wafer edge (the amount of decrease from the thickness of the reference region).

  FIG. 9A shows the results of ROA measurement performed by the inventors of the present invention on five wafers. As shown in FIG. 9A, as a result of measuring ROA of five wafers, there was a variation in the range of 0.07 μm to 1.25 μm, but the ROA of most wafers was less than 1 μm. . FIG. 9B shows the profile, FQA and W of the front surface of the fifth wafer with the largest ROA, together with the ROA.

  Non-Patent Document 4 describes that edge roll-off increases the variation in the film thickness removal amount in the peripheral portion of the wafer in the CMP process. This indicates that edge roll-off is a problem that directly leads to a decrease in device manufacturing yield. Substrates with a small edge roll-off have also been developed, but the cost of the substrate is significantly increased. Also, as long as the substrate is finally finished by polishing, it is impossible to completely eliminate edge roll-off.

  In the methods described in Patent Documents 3 and 4 described above, an SOI substrate is manufactured by bonding two substrates. In this case, since the edge roll-off exists in each substrate, as a result of bonding them so as to face each other, as shown in FIG. 10, the bonding strength of the peripheral regions (edge exclusion portions) of the bonded substrates 31 and 32 is shown. Becomes smaller than the bonding strength of the reference region. For this reason, the bonding strength of the substrates 31 and 32 is insufficient, or impurities enter the bonded portion, causing deterioration of the characteristics of the semiconductor device.

  In the present invention, when the epitaxial layer is formed on the first substrate, the thickness of the epitaxial layer in the peripheral region is increased by an amount corresponding to the edge roll-off, whereby the first substrate and the second substrate are formed. Ensuring sufficient bonding strength when bonded to the substrate. Hereinafter, embodiments of the present invention will be described.

(First embodiment)
11 to 12 are schematic views showing a method for manufacturing a semiconductor substrate according to the first embodiment of the present invention.

  First, a Si crystal is grown in the <011> direction by the CZ method to form a single crystal ingot. Thereafter, the ingot is cut to obtain a first substrate 40 made of {011} silicon single crystal as shown in FIG. The diameter of the first substrate 40 is, for example, 300 mm, and the thickness is, for example, 775 μm.

Next, as shown in FIG. 11 (b), for example, monosilane (SiH ₄ ) is used as the source gas, the substrate temperature is set to 1100 ° C., for example, and the first is performed by a chemical vapor deposition (CVD) method. Silicon is epitaxially grown on the substrate 40. The thickness of the epitaxial layer at this time is constant except for the edge roll-off portion, and is typically 2 to 10 μm. The plane orientation of the surface of the epitaxial layer 41 is the same as the plane orientation of the first substrate 40, that is, {011} based on the principle of single crystal growth.

  In the present embodiment, when the epitaxial layer 41 is formed, the epitaxial layer is formed thicker by the thickness reduction of the substrate due to edge roll-off so that the surface of the epitaxial layer has the same height from the wafer center to the periphery. . FIG. 13 is a schematic diagram showing the structure of an epitaxial growth furnace. As shown in FIG. 13, the first substrate 40 is placed in a chamber 51 of an epitaxial growth furnace. Into the chamber 51, a raw material gas is supplied from a gas inlet 52a, and is discharged out of the furnace through an exhaust port 52b. The first substrate 40 placed in the chamber 51 is heated by a number of infrared lamps 53 arranged concentrically above and below. By controlling the power supplied to these infrared lamps 53, the temperature distribution on the surface of the first substrate 40 is adjusted, so that the thickness near the edge of the epitaxial layer corresponds to the edge roll-off rather than the thickness of the reference region. You can make it as thick as you want.

  In order to make the thickness in the vicinity of the edge of the epitaxial layer slightly thicker than the thickness of the reference region, for example, the growth temperature of the outermost peripheral portion of the substrate may be lowered by several degrees C. from the inner portion. The current epitaxial growth furnace can control the temperature concentrically with an accuracy of ± 0.5 ° C. and can sufficiently control the film thickness of 1 μm or less.

  When the epitaxial layer 41 is formed on the entire upper surface of the first substrate 40 with a uniform thickness, the epitaxial layer 41 is affected by the edge roll-off of the first substrate 40 as shown in the schematic diagram of FIG. The surface of 41 does not become flat. On the other hand, in the present embodiment, by adjusting the surface temperature distribution of the first substrate 40 during the formation of the epitaxial layer, as shown in the schematic diagram of FIG. Until almost flat.

  As described above, the edge roll-off varies depending on the substrate (see FIG. 9A), but the edge roll-off of the substrates in the same lot is considered to be substantially the same. Therefore, if the epitaxial growth conditions are first determined so as to cancel the edge roll-off by an experiment or the like, it is not necessary to change the temperature distribution for each substrate, and wafers in the same lot can be epitaxially grown under the same conditions. Further, as described above, since the edge roll-off of most wafers is 1 μm or less, the thickness of the epitaxial layer 41 at a position 1 mm from the edge end is, for example, 0.5 to 1 μm thicker than the thickness in the reference region. As such, the temperature distribution may be set.

After the epitaxial layer 41 having a shape in which the thickness in the vicinity of the edge is slightly larger than the thickness of the reference region is formed in this way, an ion implantation apparatus is used to form the epitaxial layer 41 from above the epitaxial layer 41 as shown in FIG. Hydrogen ions (H ⁺ ) are implanted. In this case, it is preferable to determine an acceleration voltage at the time of hydrogen ion implantation so that hydrogen ions have the highest concentration at the interface between the epitaxial layer 41 and the first substrate 40. The implantation amount (dose amount) of hydrogen ions is, for example, 1 × 10 ¹⁶ cm ⁻² to 1 × 10 ¹⁷ cm ⁻² . Here, the surface having the highest concentration of hydrogen ions is indicated by reference numeral 42.

  On the other hand, as shown in FIG. 11D, a second substrate 45 to be a base substrate (bonding substrate) is prepared. In the present embodiment, the diameter of the second substrate 45 is 300 mm, which is the same as that of the first substrate 40. The thickness of the second substrate 45 is, for example, 775 μm. The material of the second substrate 45 is not limited, but it is necessary that the second substrate 45 be formed of a material that can be bonded to a silicon crystal and does not become a contamination source in the device manufacturing process. As the second substrate 45, a general {001} silicon wafer is preferably used. The {001} silicon wafer is currently the most mass-produced technology, and it is easy to increase the diameter.

  Next, as shown in FIG. 12A, the surface of the first substrate 40 on the epitaxial layer 41 side is bonded onto the second substrate 45. This bonding is performed by bringing the first substrate 40 and the second substrate 45 into close contact with each other at room temperature, and no adhesive or the like is used. In the present embodiment, the thickness of the edge portion of the epitaxial layer 41 is increased by an amount corresponding to the edge roll-off of the first substrate 40, so that the gap between the first substrate 40 and the second substrate 45 is increased. In particular, the adhesion at the edge removal portion is significantly improved as compared with the prior art.

  After bonding the first substrate 40 and the second substrate 45 in this manner, for example, by heating to 500 ° C., stress is generated in the portion where hydrogen ions are introduced (surface indicated by reference numeral 42), As shown in FIG. 12B, the epitaxial layer 41 is cleaved. Hereinafter, the epitaxial layer 41 remaining on the second substrate 45 after cleavage is referred to as a silicon single crystal layer 41a. Thereafter, in order to increase the bonding strength between the second substrate 45 and the silicon single crystal layer 41a thereon, heat treatment is performed for 30 minutes at a temperature of 1100 ° C., for example, in a nitrogen atmosphere.

  Next, as shown in FIG. 12C, the surface of the silicon single crystal layer 41a is polished and flattened by a CMP method or the like. Thereby, the semiconductor substrate 46 provided with the {011} silicon single crystal layer 41a is completed.

  On the other hand, the surface (surface on the epitaxial layer forming side) of the first substrate 40 remaining in the step shown in FIG. Thereafter, a series of steps shown in FIGS. 11A to 11D and FIGS. 12A to 12C are performed using the first substrate 40, and further provided with a {011} silicon single crystal layer 41a. A semiconductor substrate 46 is manufactured. In this case, when the epitaxial layer 41 is formed on the first substrate 40 in consideration of the edge roll-off of the second substrate 45, the thickness of the epitaxial layer at the end portion is larger than the thickness of the epitaxial layer in the reference region. Conditions for epitaxial growth are set so as to be slightly thicker.

  In the present embodiment, since only the epitaxial layer 41 is transferred onto the second substrate 45, the first substrate 40 is hardly consumed and can be used many times. Therefore, even if an expensive {011} silicon single crystal substrate is used as the first substrate 45, the manufacturing cost per semiconductor substrate 46 can be reduced.

  In the present embodiment, since the epitaxial layer 41 grown on the first substrate 40 is transferred onto the second substrate 45, the first substrate 40 is reused by reusing the first substrate 40. Less susceptible to quality degradation. It is well known that a silicon single crystal produced by an epitaxial growth method is the highest quality crystal among several types of silicon crystals that can be produced at present.

  Furthermore, in this embodiment, since the epitaxial layer 41 is formed on the first substrate 40 so as to cancel the edge roll-off, the first substrate 40 (epitaxial layer 41) and the second substrate 45 The bonding strength is sufficient, and there is little risk of impurities entering the bonded portion. Thereby, a high-quality {011} semiconductor substrate is obtained.

(Second Embodiment)
15 and 16 are schematic views showing a method for manufacturing a semiconductor substrate according to the second embodiment of the present invention. 15 and 16, the same components as those in FIGS. 11 and 12 are denoted by the same reference numerals. This embodiment shows an example in which the present invention is applied to the manufacture of an SOI substrate.

  First, as shown in FIG. 15A, a first substrate 40 made of {011} silicon single crystal is obtained. Then, as shown in FIG. 15B, an epitaxial layer 41 is formed on the first substrate 40 by chemical vapor deposition. At this time, as in the first embodiment, the thickness of the edge portion of the epitaxial layer 41 needs to be thicker than the thickness of the reference region by an amount corresponding to the edge roll-off.

  Next, the first substrate 40 is heated in an oxidizing atmosphere to oxidize the surfaces of the first substrate 40 and the epitaxial layer 41 to form a silicon oxide film 43 as shown in FIG. The thickness of the silicon oxide film 43 is, for example, 200 nm. Thereafter, as shown in FIG. 15D, hydrogen ions are implanted into the epitaxial layer 41 using an ion implantation apparatus so that the interface between the epitaxial layer 41 and the first substrate 40 has the highest concentration. Again, the surface with the highest concentration of hydrogen ions is indicated by reference numeral 42.

  On the other hand, as shown in FIG. 16A, a second substrate 45 serving as a base substrate (bonding substrate) is prepared. Here, it is assumed that a {001} silicon wafer having the same size as that of the first substrate 40 is used as the second substrate 45.

  Next, as shown in FIG. 16B, the first substrate 40 is bonded onto the second substrate 45 so that the epitaxial layer 41 is on the lower side. The bonding is performed by bringing the first substrate 40 and the second substrate 45 into close contact with each other at room temperature, and no adhesive is used. Also in this embodiment, since the thickness of the edge portion of the epitaxial layer 41 is increased by an amount corresponding to the edge roll-off as in the first embodiment, the first substrate 40, the second substrate 45, The adhesion between the two is improved compared to the conventional case.

  Next, as shown in FIG. 16C, the stacked body of the substrates 40 and 45 is heated to, for example, 500 ° C., and stress is generated in a portion (surface indicated by reference numeral 42) into which hydrogen ions are introduced, thereby Cleave 41. Hereinafter, the epitaxial layer 41 remaining on the second substrate 45 is referred to as a silicon single crystal layer 41a. Thereafter, in order to increase the bonding strength between the second substrate 45 and the silicon single crystal layer 41a thereon, heat treatment is performed for 30 minutes at a temperature of 1100 ° C., for example, in a nitrogen atmosphere.

  Next, as shown in FIG. 16D, the surface of the silicon single crystal layer 41a is polished and flattened by a CMP method or the like. Thereby, the SOI semiconductor substrate 47 provided with the {011} silicon single crystal layer 41a is completed.

  On the other hand, after the surface (the surface on the epitaxial layer forming side) of the first substrate 40 remaining in the step shown in FIG. 16C is lightly polished, the silicon oxide film 43 is removed. Thereafter, a series of steps shown in FIGS. 15A to 15D and FIGS. 16A to 16D are performed using the first substrate 40, and further provided with a {011} silicon single crystal layer 41a. An SOI semiconductor substrate 47 is manufactured. In this case, when the epitaxial layer 41 is formed on the first substrate 40 in consideration of the edge roll-off of the second substrate 45, the thickness of the epitaxial layer at the end portion is larger than the thickness of the epitaxial layer in the reference region. Conditions for epitaxial growth are set so as to be slightly thicker. In this embodiment, the same effect as that of the first embodiment can be obtained.

In the present embodiment, the SOI substrate having the silicon oxide film 43 between the second substrate 45 and the {011} silicon single crystal layer 41a has been described, but calcium fluoride (CaF) is used instead of the silicon oxide film 43. ₂ ) A film or other insulating film may be formed. In this embodiment, hydrogen ions are implanted after the silicon oxide film 43 is formed. However, the silicon oxide film 43 may be formed after the hydrogen ions are implanted.

(Third embodiment)
FIG. 17 is a schematic cross-sectional view showing a semiconductor substrate according to the third embodiment of the present invention. The semiconductor substrate 63 of this embodiment is different from the semiconductor substrate of the first embodiment in that 99 of silicon atoms constituting the {011} silicon single crystal layer 62a stacked on the second substrate (base substrate) 45. % Or more is ²⁸ Si, that is, the isotope abundance ratio of ²⁸ Si in the {011} silicon single crystal layer 62a is 99% or more, and other configurations are basically the same as those in the first embodiment. Since it is the same, description of the overlapping part is omitted.

In the present embodiment, an epitaxial layer made of silicon having a ²⁸ Si isotope abundance ratio of 99.0% or more is formed on a first substrate made of {011} silicon. After that, the surface of the first substrate on the epitaxial layer side is bonded onto the second substrate (base substrate) 45, hydrogen ions are implanted into the interface between the first substrate and the epitaxial layer, and then a temperature is applied. Cleave the epitaxial layer. In this way, the semiconductor substrate 63 having the {011} silicon single crystal layer 62a made of silicon having a ²⁸ Si isotope abundance ratio of 99.0% or more is manufactured.

There are three kinds of stable isotopes ( ²⁸ Si, ²⁹ Si, ³⁰ Si) in silicon, and in the case of ordinary silicon crystals, the isotope abundance ratio of ²⁸ Si, ²⁹ Si and ³⁰ Si is ²⁸ Si: ²⁹ Si : ³⁰ Si = 92.23%: 4.67%: 3.1%. As a result of studies and examinations by the inventors of the present application, it has been found that when the abundance ratio of ²⁸ Si in the silicon crystal is 99.0% or more, the thermal conductivity is improved as compared with a normal silicon crystal. . Further, in Non-Patent Document 5, when a silicon crystal having an isotope abundance ratio of, for example, ²⁸ Si of 99.7% is manufactured by using an isotope separation method, the thermal conductivity is about 60% as compared with a normal silicon crystal. It is described that it improves.

In chemical vapor deposition of shown in the first embodiment {011} silicon single crystal, as the material gas for example ²⁸ SiH ₄ using (monosilane) of ²⁸ Si isotope abundance ratio is more than 99.0% epitaxial When the layer is formed, the ²⁸ Si isotope abundance ratio in the uppermost silicon single crystal layer 62 a of the semiconductor substrate 63 to be finally formed is 99.0% or more.

Since the semiconductor substrate 63 of the present embodiment has the silicon single crystal layer 62a having a ²⁸ Si isotope abundance ratio of 99.0% or more and a surface orientation of {011}, the thermal conductivity. Is expensive. By forming a transistor using the semiconductor substrate 63, heat generated during operation can be efficiently dissipated, and the reliability of the semiconductor device is improved.

Si isotopes can be separated and concentrated using a laser isotope separation method, a gas centrifugation method, or the like. In recent years, ²⁸ Si and generated in isotope separation ²⁸ SiH ₄ (monosilane) are commercially available.

In the present embodiment, the case where the silicon single crystal layer on the surface of the semiconductor substrate of the first embodiment is made of silicon having a ²⁸ Si isotope abundance ratio of 99.0% or more has been described. The SOI of the second embodiment In the semiconductor substrate 47, the silicon single crystal layer 41a may be formed of silicon having a ²⁸ Si isotope abundance ratio of 99.0% or more.

(Fourth embodiment)
FIG. 18 is a schematic cross-sectional view showing a semiconductor substrate according to the fourth embodiment of the present invention. The semiconductor substrate 65 of this embodiment is different from the semiconductor substrate of the first embodiment in that boron (B) is used as the second substrate (base substrate) 64 at a concentration of 5 × 10 ¹⁶ to 2 × 10 ¹⁷ cm ⁻³ . Since the other structure is basically the same as that of the first embodiment, description of overlapping parts is omitted.

  In recent years, semiconductor memory devices are required to have an extremely low allowable leakage current of several fA (femtoamperes). Further, it is known that leakage current increases when a metal element such as iron (Fe) or copper (Cu) is mixed in the silicon crystal. Therefore, when manufacturing a semiconductor device, particularly a semiconductor memory device, it is important that a metal element such as iron (Fe) and copper (Cu) is not mixed in the silicon single crystal layer in the manufacturing process.

In the semiconductor substrate 65 of this embodiment, boron (B) is added to the second substrate (base substrate) 64 at a concentration of 5 × 10 ¹⁶ to 2 × 10 ¹⁷ cm ⁻³ as described above. Boron added to the second substrate 64 acts as gettering, and bonds with metal elements such as iron (Fe) and copper (Cu). This avoids the diffusion of the metal element from the second substrate (base substrate) 64 to the silicon single crystal layer 41a in the heat treatment step or the like when manufacturing the semiconductor device, and as a result, it is possible to ensure good transistor characteristics. it can.

When the boron concentration in the second substrate 64 is less than 5 × 10 ¹⁶ cm ⁻³ , the gettering effect cannot be sufficiently obtained. On the other hand, when the boron concentration in the second substrate 64 exceeds 2 × 10 ¹⁷ cm ⁻³ , the boron in the second substrate 61 is converted into a silicon single crystal when heat treatment is performed at a temperature of 1100 ° C. for 1 hour or more. There is a possibility that the specific resistance is changed by diffusing into the layer 41a and the transistor characteristics are deteriorated.

In the present embodiment, since the silicon substrate to which boron is added at a concentration of 5 × 10 ¹⁶ to 2 × 10 ¹⁷ cm ⁻³ is used as the second substrate (base substrate) 64 as described above, the first embodiment is used. In addition to obtaining the same effect as the above, there is an effect that an increase in leakage current and deterioration of transistor characteristics due to metal elements such as iron (Fe) and copper (Cu) are avoided.

  Note that a silicon substrate to which boron is added at the above concentration may be used as the base substrate (second substrate) of the semiconductor substrate of the first, second, or third embodiment. Patent Document 6 describes that boron is added to a silicon substrate.

(Fifth embodiment)
FIG. 19 is a schematic cross-sectional view showing a semiconductor substrate according to the fifth embodiment of the present invention. The semiconductor substrate 67 of this embodiment is different from the semiconductor substrate of the first embodiment in that a silicon substrate doped with boron at a concentration of 5 × 10 ¹⁸ cm ⁻³ or more is used as the second substrate (base substrate) 66. Since the other configuration is basically the same as that of the first embodiment, the description of the overlapping portion is omitted.

It is known that mechanical strength is improved when boron is added to a silicon substrate at a concentration of 5 × 10 ¹⁸ cm ⁻³ or more (for example, Non-Patent Document 6). Further, by adding boron to the silicon substrate at a concentration of 5 × 10 ¹⁸ cm ⁻³ or more, the gettering ability is improved as compared with the fourth embodiment. However, as described above, when heat treatment is performed at a high temperature in the semiconductor device manufacturing process (for example, heat treatment for 1 hour or more at a temperature of 1100 ° C.), the silicon single crystal layer on the second substrate (base substrate) is formed thereon. There arises a problem that the specific resistance of the silicon single crystal layer changes due to diffusion of boron.

The semiconductor substrate 67 according to the present embodiment is basically preferably used for manufacturing a semiconductor device that does not include a heat treatment step at a high temperature (for example, 1100 ° C. or higher) and for a long time (for example, 1 hour or longer) during the manufacturing process. . Since the semiconductor substrate 67 of this embodiment uses a silicon substrate to which boron is added at a concentration of 5 × 10 ¹⁸ cm ⁻³ or more as the second substrate (base substrate) 66, the mechanical strength is improved. The effect that the board | substrate curvature at the time of heat processing is prevented can be show | played.

  Note that a silicon substrate to which boron is added at the above concentration may be used as the base substrate (second substrate) of the semiconductor substrate of the first, second, or third embodiment.

(Sixth embodiment)
FIG. 20 is a schematic cross-sectional view showing a semiconductor substrate according to the sixth embodiment of the present invention. The semiconductor substrate 70 of this embodiment is different from the semiconductor substrate of the fourth or fifth embodiment in that the second substrate (base substrate) 71 is doped with isotope-separated boron (B). The other configurations are basically the same as those in the fourth or fifth embodiment, and therefore, the description of the overlapping parts is omitted here.

  As described in the fourth and fifth embodiments, when boron is added to the silicon crystal, leakage current can be reduced due to the gettering effect of boron. However, generally, when boron is added to a silicon crystal, the thermal conductivity decreases.

The isotope abundance ratio of ¹¹ B and ¹⁰ B in normal boron (B) is ¹¹ B: ¹⁰ B = 80.2%: 19.8%. Patent Document 7 describes that the thermal conductivity is improved by several tens of percent compared to normal boron by setting the isotope abundance ratio of either ¹¹ B or ¹⁰ B to 85% or more. .

In the semiconductor substrate 70 according to the present embodiment, as the boron doped into the second substrate (base substrate) 71, one having an isotope abundance ratio of ¹¹ B or ¹⁰ B of 85% or more is used. This second substrate can be formed as follows. That is, when a silicon single crystal is produced by a chemical vapor deposition method, diborane ( ¹¹ B ₂ H ₆ or ¹⁰ B ₂ H ₆ ) containing boron isotope-separated with a source gas is flowed. The silicon single crystal thus formed is melted, and an ingot of single crystal silicon is formed by the CZ method. Thereafter, the ingot is cut to obtain a silicon substrate to be the second substrate 71.

In the present embodiment, boron having an isotope ratio of ¹¹ B or ¹⁰ B of 85% or more is used for the second substrate (base substrate) 71, so that the semiconductor substrate of the fourth or fifth embodiment As compared with the above, the thermal conductivity of the second substrate (base substrate) 71 is increased, and the heat generated in the transistor can be more efficiently removed.

  Boron isotopes can be separated by laser isotope separation, gas centrifugation, or the like. Boron isotopes can be obtained, for example, from Eagle Picher, USA.

(Seventh embodiment)
FIG. 21 is a schematic cross-sectional view showing a semiconductor substrate according to the seventh embodiment of the present invention. In the above-described third embodiment, the case where 99% or more of silicon atoms constituting the {011} silicon single crystal layer is ²⁸ Si has been described. However, in the semiconductor substrate 75 of this embodiment, the second substrate ( (Base substrate) 76 is made of silicon having a ²⁸ Si isotope abundance ratio of 99% or more.

FIGS. 22A to 22C are schematic views showing a method for producing polycrystalline silicon made of ²⁸ Si in the order of steps. A silicon core 81 is disposed in the reduction furnace 80. The silicon core 81 is connected to a power source 82 and generates heat by power supplied from the power source 82.

As shown in FIG. 22A, a gas in which ²⁸ SiHCl ₃ (trichlorosilane) and hydrogen (H ₂ ) are mixed is supplied into the reduction furnace 80, and the silicon core 81 is energized to a temperature of about 1000 ° C. And Then, ²⁸ SiHCl ₃ is reduced in the reduction furnace 80, and high-quality polycrystalline silicon ( ²⁸ Si) is deposited on the surface of the silicon core 81 as shown in FIG.

When the polycrystalline silicon is sufficiently deposited on the surface of the silicon core 81 as shown in FIG. 22 (c), the silicon core 81 is taken out from the reduction furnace 80. Polycrystalline silicon deposited on the surface of the silicon core 81 is melted, and a silicon single crystal is grown by the CZ method to form an ingot having a ²⁸ Si isotope abundance ratio of 99% or more. A second substrate (base substrate) 76 used in this embodiment is cut out from the ingot. Since other processes are the same as those in the first embodiment, the description thereof is omitted here.

In the present embodiment, 99 Si or more of the silicon constituting the second substrate (base substrate) 76 is ²⁸ Si, and the thermal conductivity of the second substrate 76 is high. Thereby, there is an effect that heat dissipation is better than that of the semiconductor substrate of the first embodiment.

In the semiconductor substrates of the first to sixth embodiments described above, a silicon substrate having a ²⁸ Si isotope abundance ratio of 99% or more may be used as the second substrate (base substrate).

(Semiconductor device)
23 and 24 are cross-sectional views showing a method of manufacturing a p-type transistor using a semiconductor substrate according to the present invention in the order of steps. Here, in order to simplify the description, a case where a p-type field effect transistor is formed using the semiconductor substrate 46 shown in the first embodiment will be described, but the semiconductor substrate described in the other embodiments is used. Also good. Here, for convenience of explanation, the second substrate 45 of the first embodiment is referred to as a base substrate 45.

First, as shown in FIG. 23A, a semiconductor substrate 46 composed of a base substrate 45 and a {011} silicon single crystal layer 41a thereon is prepared. Then, as shown in FIG. 23B, the silicon single crystal layer 41a is separated into a plurality of element regions by an element isolation film 91 formed by an STI (Shallow Trench Isolation) method. That is, a trench is formed at a predetermined position of the silicon single crystal layer 41a using photolithography, and an insulating material such as SiO ₂ is buried in the trench to form the element isolation film 91.

  After forming the element isolation film 91 in this way, an n-type impurity such as phosphorus (P) is implanted into the silicon single crystal layer 41a to form an n-well 92.

Next, as shown in FIG. 23C, for example, SiO ₂ is deposited on the silicon single crystal layer 41a to form a gate insulating film 93. Thereafter, a polycrystalline silicon film 94 is formed on the gate insulating film 93 by CVD.

  Next, after applying a photoresist on the polycrystalline silicon film 94, exposure and development are performed to form a photoresist film (not shown) having a predetermined pattern. Thereafter, the polysilicon film 94 is etched using the photoresist film as a mask to form a gate electrode 95 as shown in FIG. At this time, the gate insulating film 93 is simultaneously etched to leave the gate insulating film 93 only below the gate electrode 95. Next, using the gate electrode 95 as a mask, a p-type impurity such as boron (B) is shallowly implanted into the surface of the n-well 92 to form a low concentration p-type impurity region 96.

Next, an insulating film made of SiO ₂ or the like is formed on the entire upper surface of the silicon single crystal layer 41a, and the insulating film is etched back to form sidewalls on both sides of the gate electrode 95 as shown in FIG. 97 is formed. Thereafter, a p-type impurity such as boron (B) is deeply implanted into the n-well 92 using the gate electrode 95 and the sidewall 97 as a mask to form a high-concentration p-type impurity region 98. In this way, a p-type transistor having an LDD (Lightly Doped Drain) structure is formed.

  In the case of a {011} silicon single crystal, the hole mobility in the <011> direction is the highest (see FIG. 1). Therefore, it is preferable that the channel length direction is the <011> direction.

Next, as shown in FIG. 24C, an insulating film such as SiO ₂ is deposited on the entire upper surface of the silicon single crystal layer 41a to form an interlayer insulating film 99. Then, a contact hole reaching the high-concentration p-type impurity region 98 from the upper surface of the interlayer insulating film 99 is formed, and a conductive material such as tungsten (W) is buried in the contact hole to form the plug 100. Further, a conductor film made of a conductor such as aluminum (aluminum alloy) is formed on the interlayer insulating film 99, and this conductor film is patterned by photolithography to form the wiring 101. In this way, a semiconductor device having a p-type transistor is completed.

  In this embodiment, since the p-type transistor is formed in the {011} silicon single crystal layer 41a, the movement speed of holes is high, and high-speed operation is possible. In this embodiment, since the semiconductor substrate manufactured by the method described in the first embodiment, that is, a semiconductor substrate having a high bonding strength between the base substrate 45 and the silicon single crystal layer 41a is used. The reliability of semiconductor devices is high.

  In the present embodiment, a method for manufacturing a p-type transistor is described, but it is needless to say that an n-type transistor may be formed in the silicon single crystal layer 41a. When an n-type transistor is formed in a {011} silicon single crystal layer, the mobility of carriers (electrons) is lower than when an n-type transistor is formed in a {001} silicon single crystal layer. However, when the electronic circuit is composed of CMOS, the effect of increasing the speed of the p-type transistor is greater. Therefore, when the CMOS is formed on the {011} silicon single crystal layer, the CMOS is formed on the {001} silicon single crystal layer. In comparison, the operation speed of the electronic circuit is increased.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Additional remark 1) In the semiconductor substrate which has a base substrate and the silicon single crystal layer arrange | positioned above the said base substrate,
A semiconductor substrate, wherein a surface orientation of the surface of the silicon single crystal layer is {011}, and the silicon single crystal layer has a thickness distribution that cancels an edge roll-off of the base substrate.

  (Supplementary note 2) The semiconductor substrate according to supplementary note 1, wherein an insulating film is provided between the base substrate and the silicon single crystal layer.

(Additional remark 3) 99% or more of the silicon atoms which comprise the said silicon single crystal layer consist of ²⁸ Si, The semiconductor substrate of Additional remark 1 or 2 characterized by the above-mentioned.

  (Supplementary note 4) The semiconductor substrate according to Supplementary note 1 or 2, wherein the base substrate is a silicon substrate having a surface orientation of {001}.

  (Supplementary note 5) The semiconductor substrate according to supplementary note 4, wherein boron is added to the base substrate.

(Additional remark 6) Content of the said boron is 5 * 10 < ¹⁶ > thru | or 2 * 10 < ¹⁷ > cm < ^-3 >, The semiconductor substrate of Additional remark 5 characterized by the above-mentioned.

(Additional remark 7) Content of the said boron is 5 * 10 < ¹⁸ > cm < ^-3 > or more, The semiconductor substrate of Additional remark 5 characterized by the above-mentioned.

(Supplementary Note 8) The semiconductor substrate according to Note 5, wherein the more than 85% of the base substrate added boron is either a ¹¹ B or ¹⁰ B.

(Supplementary note 9) The semiconductor substrate according to supplementary note 1, wherein the base substrate is made of a silicon single crystal, and 99% or more thereof is made of ²⁸ Si.

(Appendix 10) A step of epitaxially growing a silicon single crystal layer directly on a first substrate made of a silicon single crystal having a surface orientation of {011},
Implanting hydrogen ions into the silicon single crystal layer;
Bonding a second substrate and the first substrate through the silicon single crystal layer;
Cleaving the silicon single crystal layer at a portion where the ion-implanted hydrogen concentration is high,
The method of manufacturing a semiconductor substrate, wherein the silicon single crystal layer is formed by adjusting an epitaxial growth condition so as to have a thickness distribution that cancels an edge roll-off of the first substrate or the second substrate. .

  (Supplementary note 11) The semiconductor substrate according to supplementary note 10, further comprising a step of covering surfaces of the first substrate and the silicon single crystal layer with an insulating film before the step of cleaving the silicon single crystal layer. Manufacturing method.

  (Supplementary note 12) The method for producing a semiconductor substrate according to supplementary note 10, wherein the cleavage-side surface of the first substrate after the cleavage is polished and used again for the production of a semiconductor substrate.

FIG. 1 is a diagram showing the relationship between carrier density and hole mobility in a (001) silicon wafer and a (011) silicon wafer. FIGS. 2A and 2B are schematic views showing dislocations introduced when the seed crystal comes into contact with the melt. FIGS. 3A to 3C are schematic views showing the removal of dislocations by necking. FIG. 4 is a schematic diagram showing an ingot formed after necking. FIG. 5A is a schematic diagram showing how dislocations are removed by growth in the <001> direction, and FIG. 5B is a schematic diagram showing how dislocations remain by growth in the <011> direction. FIG. 6 is a schematic diagram (No. 1) showing a method for manufacturing an SOI substrate by Smart Cut. FIG. 7 is a schematic diagram (part 2) illustrating a method for manufacturing an SOI substrate by Smart Cut. FIG. 8 is a schematic diagram for explaining edge roll-off. FIG. 9A is a diagram showing the measurement results of ROA performed on five wafers, and FIG. 9B is a diagram showing the profile, FQA, and W of the front surface of the fifth wafer together with ROA. It is. FIG. 10 is a schematic diagram showing a state where two substrates are bonded together. FIG. 11 is a schematic diagram (part 1) illustrating the method for manufacturing the semiconductor substrate according to the first embodiment of the present invention. FIG. 12 is a schematic diagram (part 2) illustrating the method for manufacturing the semiconductor substrate according to the first embodiment of the present invention. FIG. 13 is a schematic diagram showing the structure of an epitaxial growth furnace. FIG. 14A is a schematic view showing a state where the epitaxial layer is formed on the entire upper surface of the first substrate with a uniform thickness, and FIG. 14B shows the edge roll-off of the first substrate by the epitaxial layer. It is a schematic diagram which shows the state formed by thickness distribution which cancels. FIG. 15 is a schematic diagram (part 1) illustrating the method for manufacturing a semiconductor substrate according to the second embodiment of the present invention. FIG. 16 is a schematic diagram (part 2) illustrating the method for manufacturing a semiconductor substrate according to the second embodiment of the present invention. FIG. 17 is a schematic cross-sectional view showing a semiconductor substrate according to the third embodiment of the present invention. FIG. 18 is a schematic cross-sectional view showing a semiconductor substrate according to the fourth embodiment of the present invention. FIG. 19 is a schematic cross-sectional view showing a semiconductor substrate according to the fifth embodiment of the present invention. FIG. 20 is a schematic cross-sectional view showing a semiconductor substrate according to the sixth embodiment of the present invention. FIG. 21 is a schematic cross-sectional view showing a semiconductor substrate according to the seventh embodiment of the present invention. FIGS. 22A to 22C are schematic views showing a method for producing polycrystalline silicon made of ²⁸ Si in the order of steps. FIG. 23 is a cross-sectional view (No. 1) showing the method for manufacturing the p-type transistor using the semiconductor substrate according to the present invention. FIG. 24 is a sectional view (No. 2) showing the method for manufacturing the p-type transistor using the semiconductor substrate according to the present invention.

Explanation of symbols

10 ... melt,
11 ... Seed crystal,
13 ... Ingot,
20, 40 ... first substrate,
20a, 41a, 62a ... single crystal silicon layer,
21, 43 ... silicon oxide film,
22, 42 ... the surface where the hydrogen concentration is the highest,
25, 45, 64, 66, 71, 76 ... second substrate (base substrate)
26 ... SOI substrate,
41 ... epitaxial layer,
46, 47, 63, 65, 67, 70, 75 ... semiconductor substrate,
51 ... Chamber,
52a ... Gas inlet,
52b ... exhaust port,
53. Infrared lamp,
80 ... reduction furnace,
81 ... silicon core,
82 ... Power supply,
91 ... element isolation film,
92 ... n-well,
93. Gate insulating film,
94: polycrystalline silicon film,
95 ... Gate electrode,
96 ... low concentration p-type impurity region,
97 ... sidewall,
98 ... High concentration p-type impurity region,
99 ... interlayer insulating film,
100 ... plug,
101: Wiring.

Claims (5)

In a semiconductor substrate having a base substrate and a silicon single crystal layer disposed above the base substrate,
A semiconductor substrate, wherein a surface orientation of the surface of the silicon single crystal layer is {011}, and the silicon single crystal layer has a thickness distribution that cancels an edge roll-off of the base substrate.   The semiconductor substrate according to claim 1, wherein an insulating film is provided between the base substrate and the silicon single crystal layer. A step of epitaxially growing a silicon single crystal layer directly on a first substrate made of a silicon single crystal having a surface orientation of {011};
Implanting hydrogen into the silicon single crystal layer;
Bonding a second substrate and the first substrate through the silicon single crystal layer;
Cleaving the silicon single crystal layer at a portion where the ion-implanted hydrogen concentration is high,
The method of manufacturing a semiconductor substrate, wherein the silicon single crystal layer is formed by adjusting an epitaxial growth condition so as to have a thickness distribution that cancels an edge roll-off of the first substrate or the second substrate. .   4. The method of manufacturing a semiconductor substrate according to claim 3, further comprising a step of covering surfaces of the first substrate and the silicon single crystal layer with an insulating film before the step of cleaving the silicon single crystal layer. .   4. The method of manufacturing a semiconductor substrate according to claim 3, wherein the cleavage-side surface of the first substrate after the cleavage is polished and used again for manufacturing the semiconductor substrate.

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