JP2008270977A - High-frequency amplifying circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-frequency amplifying circuit which can improve linearity by suppressing a gain variation for a change of input electric power. <P>SOLUTION: In a high-frequency amplifying circuit, a high-frequency signal divided into two by a divider 12 is amplified by FETs 24-1 and 26-1 to be combined. A fixed bias voltage is applied to a gate terminal 24g of the FET 24-1. A bias circuit 36 applying a bias voltage to a gate terminal 26g of the FET 26-1 includes a coupler 42 decoupling a part of the high-frequency signal inputted to the FET 26-1, a monitoring FET 46 amplifying the high-frequency signal decoupled by the coupler 42, a fixed current bias circuit 44 adjusting a bias voltage applied to a gate terminal 46g of the monitoring FET 46 so that the bias current in a drain terminal 46d of the monitoring FET 46 converges to a fixed value, and a voltage conversion circuit 48 correcting the bias voltage in the gate terminal 46g of the monitoring FET 46 by a predetermined gain and an offset so that the corrected voltage applies to the gate terminal 26g of the FET 26-1. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a high-frequency amplifier circuit, and more particularly to a high-frequency amplifier circuit that achieves high-efficiency amplification.

  As one of means for realizing a highly efficient amplifier, a Doherty amplifier is known (for example, Patent Document 1 below). The Doherty amplifier operates when a distributor (such as a Wilkinson distributor) that distributes an input signal, a carrier amplifier that is biased to class AB and operates from low input power, and a bias that is biased to class C and input power is sufficiently large, for example. And a peak amplifier. The output circuit is a synthesis circuit without isolation, realizing a variable load and enabling high-efficiency operation.

JP 2006-197556 A

  In the Doherty amplifier, when the input power is small, the peak amplifier is off and its output impedance is open. Therefore, all the power distributed to the peak amplifier side by the distributor is reflected and is normally used for the distributor. It is consumed by the resistance of the Wilkinson distributor (reflected wave absorption resistance). As a result, a loss of about 3 dB occurs and the gain of the entire Doherty amplifier is reduced. Further, the gain fluctuation also increases in the region where the peak amplifier starts to operate. As a result, as shown in FIG. 9, the gain of the entire Doherty amplifier varies with changes in input power, and the linearity of the Doherty amplifier decreases.

  An object of the present invention is to provide a high-frequency amplifier circuit capable of suppressing gain fluctuations with respect to changes in input power and improving linearity.

  The high frequency amplifier circuit according to the present invention employs the following means in order to achieve the above object.

  A high-frequency amplifier circuit according to the present invention includes a distributor that distributes a high-frequency signal that accompanies amplitude variation into two, a first amplifier that amplifies one of the high-frequency signals that is distributed into two by the distributor, and a high-frequency that is distributed into two by the distributor A second amplifier that amplifies the other of the signals, a first bias circuit that applies a constant bias voltage to the input terminal of the first amplifier, and a second bias circuit that applies a bias voltage to the input terminal of the second amplifier. A high-frequency amplifier circuit that synthesizes and outputs the high-frequency signal amplified by the first amplifier and the high-frequency signal amplified by the second amplifier, wherein the second bias circuit is a high-frequency signal input to the second amplifier Branching means for branching a part of the signal, a monitoring amplifier for amplifying the high-frequency signal branched by the branching means, and a bias current for the change of the bias current at the output terminal of the monitoring amplifier. A constant current bias circuit for adjusting a bias voltage applied to the input terminal of the monitor amplifier so as to converge to a value, and a bias voltage applied to the input terminal of the second amplifier based on the bias voltage at the input terminal of the monitor amplifier And a bias adjustment circuit for adjustment.

  In one aspect of the present invention, it is preferable that the bias adjustment circuit includes a voltage gain adjustment circuit that corrects the bias voltage at the input terminal of the monitor amplifier with a predetermined gain and offset and applies the correction voltage to the input terminal of the second amplifier. is there.

  In one aspect of the present invention, it is preferable that the constant value is set based on a bias current value at the output terminal of the first amplifier when the input power to the first amplifier is zero.

  In one aspect of the present invention, the bias adjustment circuit includes a bias applied to the input terminal of the second amplifier so that the efficiency of the high frequency amplifier circuit becomes a predetermined value when the average power output from the high frequency amplifier circuit is maximum. It is preferable to adjust the voltage.

  According to the present invention, by adjusting the bias voltage applied to the input terminal of the second amplifier based on the bias voltage at the input terminal of the monitoring amplifier that operates with a constant current bias, the entire high-frequency amplifier circuit with respect to changes in input power Variation in gain can be suppressed, and the linearity of the high-frequency amplifier circuit can be improved.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.

  1 to 3 are diagrams showing an outline of the configuration of the high-frequency amplifier circuit 10 according to the embodiment of the present invention, FIG. 1 shows an outline of the overall configuration, FIG. 2 shows an overview of the configuration of the bias circuit 34, FIG. 3 schematically shows the configuration of the bias circuit 36. A high-frequency signal with amplitude fluctuation (envelope fluctuation) is input to the input terminal IN. The high-frequency signal here is a wideband modulation signal having a predetermined bandwidth, and for example, WCDMA or OFDM can be used as a modulation method. The distributor 12 distributes the high-frequency signal input to the input terminal IN into two. As the distributor 12, for example, a Wilkinson distributor can be used, and the distributor 12 equally distributes the high frequency signal. One of the high-frequency signals distributed by the distributor 12 is input to an amplifier (first amplifier) 24, and the other of the high-frequency signals distributed by the distributor 12 has a predetermined characteristic impedance (for example, 50Ω). A π / 2 phase difference is given by the / 4 wavelength line 28 and then inputted to the amplifier (second amplifier) 26. The amplifier 24 amplifies one of the high-frequency signals distributed by the distributor 12, and the amplifier 26 amplifies the other high-frequency signal distributed by the distributor 12. The high frequency signal amplified by the amplifier 24 is combined with the high frequency signal amplified by the amplifier 26 after passing through a quarter wavelength line 30 having a predetermined characteristic impedance (for example, Rout). The synthesized high frequency signal is output from the output terminal OUT and supplied to a load (not shown) having an impedance Rout / 2, for example.

  The bias circuit (first bias circuit) 34 applies a constant bias voltage to the input terminal of the amplifier 24. FIG. 2 shows an example of the bias circuit 34. In the example shown in FIG. 2, the FET 24-1 is used for the amplifier 24, the gate terminal 24 g of the FET 24-1 corresponds to the input terminal of the amplifier 24, and the drain terminal 24 d of the FET 24-1 is the output terminal of the amplifier 24. Equivalent to. The voltage of the gate bias power supply VGG1 is divided by the temperature-sensitive resistor RT, the variable resistor RV, and the resistor R1 connected in series with each other, and this divided voltage is fed to the gate terminal of the FET 24-1 via the bias choke coil L1. 24g applied. The gate terminal 24g of the FET 24-1 is also connected to the thermistor TH and the resistor R2 connected in series via the bias choke coil L1. A bias current (drain current) Idd1 is supplied from the drain bias power supply VDD1 to the drain terminal 24d of the FET 24-1 via the bias choke coil L2. Also, DC blocking capacitors C1 and C2 are provided on the gate terminal 24g side and the drain terminal 24d side of the FET 24-1, respectively. Here, the bias voltage applied to the input terminal of the amplifier 24 (the gate terminal 24g of the FET 24-1) is adjusted to a constant value so that the amplifier 24 is biased to class AB. Therefore, as shown in FIG. 4, a bias current (drain current) Idd1 flows from the output terminal of the amplifier 24 (drain terminal 24d of the FET 24-1) from when the input power Pin to the amplifier 24 (FET 24-1) is small, As the input power Pin to the amplifier 24 increases (changes), the bias current (drain current) Idd1 at the output terminal of the amplifier 24 increases (changes). In addition to the configuration example shown in FIG. 2, a known bias circuit can be applied to the configuration of the bias circuit 34.

  In the present embodiment, the configuration of the Doherty amplifier can be applied to the distributor 12, the amplifier 24, the quarter wavelength lines 28 and 30, and the bias circuit 34. However, the configuration of the bias circuit 36 of the amplifier 26 is different from that of the Doherty amplifier. Hereinafter, a configuration example of the bias circuit 36 will be described.

  The bias circuit (second bias circuit) 36 applies a bias voltage to the input terminal of the amplifier 26. FIG. 3 shows an example of the bias circuit 36. In the example shown in FIG. 3, the FET 26-1 is used for the amplifier 26, the gate terminal 26 g of the FET 26-1 corresponds to the input terminal of the amplifier 26, and the drain terminal 26 d of the FET 26-1 is the output terminal of the amplifier 26. Equivalent to.

  In the example shown in FIG. 3, a part of the high frequency signal inputted to the amplifier 26 (the gate terminal 26g of the FET 26-1) is branched out by the coupler 42 and taken out. The high-frequency signal branched by the coupler 42 is supplied to the gate terminal 46 g of the monitoring FET (monitoring amplifier) 46 and amplified by the monitoring FET 46. Here, the monitoring FET 46 is formed on the same chip as the FET 26-1 so that characteristics such as the pinch-off voltage Vth, the mutual conductance Gm, and the gate-source breakdown voltage are substantially equal to those of the FET 26-1. Manufacturing). The monitoring FET 46 may be a device scaled down with respect to the FET 26-1. When the size ratio of the FET 26-1 and the monitoring FET 46 is x: 1 (x> 1), The coupling degree of the coupler 42 is preferably set so that the ratio between the input power and the input power to the monitor FET 46 is x: 1.

  The constant current bias circuit 44 includes a gate terminal 46g (monitoring amplifier) of the monitoring FET 46 so that a bias current (drain current) at the drain terminal 46d (output terminal of the monitoring amplifier) of the monitoring FET 46 converges to a constant value Idd3. The bias voltage applied to the input terminal is adjusted. Therefore, the monitoring FET 46 operates with a constant current bias.

  A configuration example of the constant current bias circuit 44 here is shown in FIG. In the example shown in FIG. 5, the voltage of the gate bias power supply VGG2 is applied to the gate terminal 46g of the monitoring FET 46 via the time constant circuit 38 including the resistor R15 and the capacitor C13 and the bias choke coil L11. The drain bias power supply VDD2 is connected to the drain terminal 46d of the monitoring FET 46 via the resistor R12 and the bias choke coil L12. The drain bias power supply VDD2 is connected to the monitoring FET 46 via the resistor R12 and the bias choke coil L12. A bias current (drain current) is supplied to the drain terminal 46d. The voltage of the drain bias power supply VDD2 is divided by a resistor R11, a diode D1, and a resistor R13 connected in series with each other, and the divided voltage Vb is applied to the base terminal of the transistor Tr1. The emitter terminal of the transistor Tr1 is connected to the drain terminal 46d of the monitoring FET 46 via the bias choke coil L12, and the collector terminal of the transistor Tr1 is the gate terminal of the monitoring FET 46 via the resistor R14 and the bias choke coil L11. It is connected to 46g. Further, on the gate terminal 46g side and the drain terminal 46d side of the monitoring FET 46, capacitors C11 and C12 for cutting off direct current are provided.

In the constant current bias circuit 44 shown in FIG. 5, for example, when the drain current of the monitoring FET 46 decreases, the base-emitter voltage Vbe of the transistor Tr1 increases and the base current Ib of the transistor Tr1 also increases. As a result, the collector current Ic of the transistor Tr1 also increases, and the voltage drop of the resistor R15 of the time constant circuit 38 occurs, so that the bias voltage supplied to the gate terminal 46g of the monitoring FET 46 operates in a shallow direction. The drain current of the FET 46 for use is increased. On the other hand, when the drain current of the monitoring FET 46 increases, the bias voltage supplied to the gate terminal 46g of the monitoring FET 46 is adjusted so as to decrease the drain current. Therefore, assuming that the voltage value of the drain bias power supply VDD2 is VDD2, the base voltage value of the transistor Tr1 is Vb, the base-emitter voltage value of the transistor Tr1 is Vbe, and the resistance value of the resistor R12 is R12, the following equation (1) is established. A bias voltage applied to the gate terminal 46g of the monitoring FET 46 so that the drain current converges to a constant value Idd3 with respect to a change in the drain current of the monitoring FET 46 (bias current at the output terminal of the monitoring amplifier). Is adjusted. As a result, the bias voltage is adjusted so that the bias current (drain current) at the output terminal of the monitoring FET 46 converges to a constant value Idd3 with respect to the change in the input power to the monitoring FET 46. Note that the temperature characteristic of the base-emitter voltage Vbe of the transistor Tr1 is compensated by the temperature characteristic of the diode D1.
Idd3 = (VDD2-Vb-Vbe) / R12 (1)

  However, since the constant current bias circuit 44 shown in FIG. 5 is provided with the time constant circuit 38, the drain current is constant at the time constant τ of the time constant circuit 38 with respect to the change of the drain current of the monitoring FET 46. The bias voltage applied to the gate terminal 46g of the monitoring FET 46 is adjusted so as to converge to the value Idd3. Therefore, the drain current operates so as to converge to the constant value Idd3 with respect to the fluctuation of the drain current having a period sufficiently longer than the time constant τ of the time constant circuit 38. On the other hand, for the fluctuation of the drain current having a period sufficiently shorter than the time constant τ, the drain current does not operate so as to converge to the constant value Idd3, and the fluctuation of the drain current is allowed. In the present embodiment, the time constant τ of the time constant circuit 38 is set to a value sufficiently larger than the reciprocal of the bandwidth of the high-frequency signal (wideband modulation signal). Therefore, the drain current operates so as to converge to the constant value Idd3 with respect to the fluctuation of the input power Pin (the fluctuation of the average input power) having a period sufficiently longer than the time constant τ. On the other hand, the fluctuation of the drain current is allowed for a modulation component having a period sufficiently shorter than the time constant τ. For example, when WCDMA is used as a modulation method, a signal component having a bandwidth of 3.84 MHz is demodulated using a root Nyquist filter having the characteristics shown in FIG. It can be set to 0.6 ms (1 / τ ≦ 1666 Hz). The time constant τ of the time constant circuit 38 is expressed by (resistance value R15 of the resistor R15) × (capacitance C13 of the capacitor C13).

  A voltage conversion circuit 48 provided as a bias adjustment circuit applies a bias voltage to the gate terminal 26g (input terminal of the amplifier 26) of the FET 26-1 based on the bias voltage at the gate terminal (input terminal) 46g of the monitoring FET 46. Adjust. The aforementioned constant value Idd3 can be set based on the bias current value (Iddr1 in FIG. 4) at the drain terminal 24d of the FET 24-1 when the input power Pin to the amplifier 24 (FET 24-1) is zero. For example, when the bias voltage is adjusted to be the same between the gate terminal 26g of the FET 26-1 and the gate terminal 46g of the monitoring FET 46 when the input power Pin to the FET 24-1 is 0, Iddr1 / x is obtained. Can be set.

  A configuration example of the voltage conversion circuit 48 here is shown in FIG. In the example shown in FIG. 7, the voltage conversion circuit 48 includes a voltage gain adjustment amplifier including an operational amplifier (OP amplifier) OP1, resistors R21 and R22, a gain adjustment resistor R23, and an offset adjustment power source VSE. The voltage conversion circuit (voltage gain adjustment amplifier) 48 corrects the bias voltage Vin at the gate terminal 46g of the monitoring FET 46 with a predetermined voltage gain and offset, and applies the corrected voltage Vout to the gate terminal 26g of the FET 26-1. . The voltage gain here can be adjusted by the resistance value of the gain adjusting resistor R23, and the offset value can be adjusted by the voltage value of the offset adjusting power source VSE. As a result, as shown in FIG. 4, the characteristic between the input power Pin to the amplifier 26 and the bias current (drain current) Idd2 at the output terminal of the amplifier 26 has a predetermined slope, which increases the input power Pin. On the other hand, the bias voltage applied to the input terminal of the amplifier 26 is adjusted so that the bias current Idd2 gradually increases. The slope of the drain current Idd2 with respect to the input power Pin can be adjusted by adjusting the voltage gain of the voltage gain adjustment amplifier 48. For example, when the average power output from the high-frequency amplifier circuit 10 is the maximum (the input power Pin in that case is P0), the bias current Idd2 of the amplifier 26 is set to a predetermined value at which the efficiency of the high-frequency amplifier circuit 10 is high. The bias voltage applied to the input terminal of the amplifier 26 (the voltage gain of the voltage gain adjustment amplifier 48) can be adjusted so as to match the bias current value (Iddr2 in FIG. 4). That is, the voltage gain of the voltage gain adjustment amplifier 48 can be adjusted so that the slope of the drain current Idd2 with respect to the input power Pin matches (Iddr2-Iddr1) / P0. For the maximum value (maximum average power) of the average power output from the high-frequency amplifier circuit 10, the maximum instantaneous power that can be output from the high-frequency amplifier circuit 10 is determined by the ratio (Peak Average Ratio) between the peak power and the average power of the high-frequency signal. It can be expressed as a divided value. In FIG. 4, in addition to the bias current characteristics of the amplifiers 24 and 26, the bias current characteristics of the peak amplifier of the Doherty amplifier are also shown for comparison.

  In the Doherty amplifier described above, the bias current (drain current) at the output terminal of the carrier amplifier biased to class AB and the bias current (drain current) at the output terminal of the peak amplifier biased to class C are given by the input power Pin: The change changes as shown in FIG. When the input power Pin is small, the peak amplifier is in an off state and its output impedance is in an open state. Therefore, all the power distributed to the peak amplifier side by the distributor is reflected, and Wilkinson distribution normally used for the distributor is used. Is consumed by the resistance of the vessel (reflected wave absorption resistance). As a result, a loss of about 3 dB occurs and the gain of the entire Doherty amplifier is reduced. Further, as shown in FIG. 8, since the bias current (drain current) of the peak amplifier increases (changes) with respect to the increase (change) of the input power Pin, the gain of the entire Doherty amplifier fluctuates. Gain variation increases in the region where the amplifier begins to operate. As a result, as shown in FIG. 9, the gain Gain in the entire Doherty amplifier varies with respect to the change in the input power Pin, and the linearity of the Doherty amplifier is degraded. FIG. 9 also shows the gain characteristics of the balanced amplifier with respect to the input power Pin compared to the Doherty amplifier.

  On the other hand, in the present embodiment, the bias voltage at the input terminal of the monitoring FET 46 operating at a constant current bias is corrected by the voltage conversion circuit (voltage gain adjustment amplifier) 48 and applied to the input terminal of the amplifier 26. As a result, when the input power Pin is small, the amplifier 26 is apparently biased to operate in class AB, and the high-frequency amplifier circuit 10 according to the present embodiment functions as a class AB balanced amplifier. Therefore, reflection of power distributed to the amplifier 26 side by the distributor 12 can be suppressed, and power consumption at the distributor 12 (reflected wave absorption resistor of the Wilkinson distributor) can be suppressed. The decrease in gain can be suppressed. Further, when the input power Pin is small by setting the bias current Idd3 of the monitoring FET 46 so that the bias current Idd2 of the amplifier 26 matches the bias current Idd1 of the amplifier 24 when the input power Pin is 0. The reflection of the power distributed to the amplifier 26 side can be almost eliminated, and the gain reduction in the entire high-frequency amplifier circuit 10 can be almost eliminated. On the other hand, when the input power Pin is large, for example, when the average power output from the amplifier 26 is maximum, the amplifier 26 apparently is biased to operate in class C, and the high-frequency amplifier circuit 10 according to this embodiment is operated. Functions as a Doherty amplifier. That is, the amplifier 24 functions as a carrier amplifier, and the amplifier 26 functions as a peak amplifier. When the average power output from the high-frequency amplifier circuit 10 is maximum, the bias current (drain current) Idd2 of the amplifier 26 is set to a current value Iddr2 at which the efficiency of the high-frequency amplifier circuit 10 becomes a predetermined value with high efficiency. Therefore, high-efficiency amplification can be performed in the same manner as the Doherty amplifier. Thus, in this embodiment, as the input power Pin increases, the operation of the balanced amplifier gradually shifts to the operation of the Doherty amplifier. Therefore, as shown in FIG. The fluctuation of the gain Gain in the entire circuit 10 can be suppressed, and the linearity of the high-frequency amplifier circuit 10 can be improved.

  Further, in the Doherty amplifier, when the input power Pin is small, the bias current (drain current) of the peak amplifier is almost zero, so that it is difficult to adjust the bias for correcting variations in semiconductor elements such as FETs. In addition, since the output signal of the carrier amplifier and the output signal of the peak amplifier are synthesized by a synthesis circuit without isolation, load fluctuation due to temperature is large, resulting in characteristic deterioration, and mass productivity is reduced.

  In contrast, in this embodiment, since the bias current (drain current) Idd2 flows to the output terminal of the amplifier 26 (the drain terminal 24d of the FET 24-1) when the input power Pin is small, the bias adjustment of the amplifier 26 can be easily performed. It can be carried out. Furthermore, load fluctuation due to temperature can also be suppressed.

  In the present embodiment, the above-mentioned constant value Idd3 can be set based on Iddr2, for example, can be set to Iddr2 / x. Furthermore, the constant value Idd3 can be set to a value not less than Iddr1 / x and not more than Iddr2 / x. Also in these cases, by adjusting the voltage gain and offset of the voltage conversion circuit (voltage gain adjustment amplifier) 48, the bias current (drain current) Idd2 of the amplifier 26 is set to zero when the input power Pin is 0 as shown in FIG. It is sometimes possible to adjust to Iddr1 and when the input power Pin is P0, Iddr2.

  As mentioned above, although the form for implementing this invention was demonstrated, this invention is not limited to such embodiment at all, and it can implement with a various form in the range which does not deviate from the summary of this invention. Of course.

It is a figure which shows the outline of a structure of the high frequency amplifier circuit which concerns on embodiment of this invention. It is a figure which shows the outline of a structure of the high frequency amplifier circuit which concerns on embodiment of this invention. It is a figure which shows the outline of a structure of the high frequency amplifier circuit which concerns on embodiment of this invention. It is a figure which shows an example of the bias current characteristic of the high frequency amplifier circuit which concerns on embodiment of this invention. It is a figure which shows an example of a structure of the constant current bias circuit used for the high frequency amplifier circuit which concerns on embodiment of this invention. It is a figure which shows an example of a root Nyquist filter characteristic. It is a figure which shows an example of a structure of the voltage converter circuit used for the high frequency amplifier circuit which concerns on embodiment of this invention. It is a figure which shows an example of the bias current characteristic of a Doherty amplifier. It is a figure which shows an example of the gain characteristic of a Doherty amplifier and a balance type amplifier. It is a figure which shows an example of the gain characteristic of the high frequency amplifier circuit which concerns on embodiment of this invention.

Explanation of symbols

  10 high frequency amplifier circuit, 12 distributor, 24, 26 amplifier, 24-1, 26-1 FET, 28, 30 1/4 wavelength line, 34, 36 bias circuit, 38 time constant circuit, 42 coupler, 44 constant current bias Circuit, 46 Monitor FET, 48 Voltage conversion circuit.

Claims (4)

A distributor for distributing a high-frequency signal with amplitude variation into two;
A first amplifier that amplifies one of the high-frequency signals distributed in two by the distributor;
A second amplifier for amplifying the other of the high-frequency signals distributed in two by the distributor;
A first bias circuit for applying a constant bias voltage to the input terminal of the first amplifier;
A second bias circuit for applying a bias voltage to the input terminal of the second amplifier;
With
A high-frequency amplifier circuit that combines and outputs a high-frequency signal amplified by a first amplifier and a high-frequency signal amplified by a second amplifier,
The second bias circuit is
Branching means for branching a part of the high-frequency signal input to the second amplifier;
A monitoring amplifier for amplifying the high-frequency signal branched by the branching means;
A constant current bias circuit for adjusting a bias voltage applied to the input terminal of the monitor amplifier so that the bias current converges to a constant value in response to a change in the bias current at the output terminal of the monitor amplifier;
A bias adjustment circuit for adjusting a bias voltage applied to the input terminal of the second amplifier based on the bias voltage at the input terminal of the monitor amplifier;
A high-frequency amplifier circuit. The high-frequency amplifier circuit according to claim 1,
The bias adjustment circuit includes a voltage gain adjustment circuit that corrects the bias voltage at the input terminal of the monitor amplifier with a predetermined gain and offset and applies the correction voltage to the input terminal of the second amplifier. The high-frequency amplifier circuit according to claim 1 or 2,
The high-frequency amplifier circuit, wherein the constant value is set based on a bias current value at an output terminal of the first amplifier when input power to the first amplifier is zero. The high-frequency amplifier circuit according to claim 1,
The bias adjustment circuit adjusts the bias voltage applied to the input terminal of the second amplifier so that the efficiency of the high frequency amplifier circuit becomes a predetermined value when the average power output from the high frequency amplifier circuit is maximum. circuit.

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