JP2008270864A - Semiconductor integrated circuit and control method of equalizer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of adjusting the amount of equalization of a received data signal while suppressing an increasing circuit scale. <P>SOLUTION: The semiconductor integrated circuit 100 includes: an equalizer; a phase comparing circuit which detects a phase of the data signal equalized by the equalizer so as to compare the phase of the data signal and the phase of a restoration clock signal, outputs a first comparison signal when a bit width of the equalized data signal is smaller than a cycle of the restoration clock signal or outputs a second comparison signal when the bit width is larger than the cycle, outputs a third comparison signal when the phase of the restoration clock signal is forward the phase of the data signal or outputs a fourth comparison signal when the phase of the restoration clock signal is behind the phase of the data signal; a restoration clock generation circuit for generating the restoration clock signal based on the third and fourth comparison signals and a reference clock signal; and a control circuit for controlling the amount of peaking of the equalizer based on at least the first and second comparison signals. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit including an equalizer and a method for controlling the equalizer.

  In recent years, the frequency of SerDes (Serializer Desirizer) circuits has been increased. And the influence of deterioration of the Eye waveform by ISI (Inter-symbol-Interference) resulting from the low-pass filter (Low-Pass-Filter) characteristic of the transmission line is remarkable.

  When the ISI is large, it is necessary to automatically optimize the amount of receiver equalization according to the transmission line depending on the length of the transmission line to be connected.

  In the prior art, reception equalization is performed by extracting a low-frequency component and a high-frequency component of a received waveform with a digital filter capable of high-speed operation, and substantially matching the low-frequency component and the high-frequency component.

  In this prior art, in the comparator input / output, a high frequency component included in the input / output amplitude is extracted and rectified, and then an equalizer (Equalizer) is set so that the difference between these extracted high frequency components is minimized. ) Is optimized (for example, see Non-Patent Document 1).

However, the above-described prior art requires a filter, a rectifier, a capacitor for removing harmonic components after rectification, and the like, resulting in an increase in circuit scale.
JSChoi et, al 'A CMOS 3.5Gbps Continuous-time Adaptive Cable Equalizer with Joint Adaptive Method of Low-Frequency Gain and High- Frequency Boosting', 2003 Symposium on VLSI Circuits Digest of Technical Papers, 2003, p. 103-106

  An object of the present invention is to provide a semiconductor integrated circuit capable of adjusting an equalization amount of a received data signal while suppressing an increase in circuit scale.

A semiconductor integrated circuit according to an embodiment of one aspect of the present invention includes:
There is a semiconductor integrated circuit for adjusting the equalization amount of a received data signal,
An equalizer for equalizing the received data signal;
The recovered data signal is output based on the data signal and the recovered clock signal equalized by the equalizer, the phase of the data signal equalized by the equalizer is detected, and the phase of the data signal and the recovered clock signal When the bit width of the equalized data signal is smaller than the period of the recovered clock signal, the first comparison signal is output, while the bit width of the equalized data signal is Output a second comparison signal when the period of the recovered clock signal is larger than the period of the recovered clock signal, and output a third comparison signal when the phase of the recovered clock signal is ahead of the phase of the data signal, A phase comparison circuit that outputs a fourth comparison signal when the phase of the recovered clock signal is behind the phase of the data signal;
A recovered clock generation circuit for generating the recovered clock signal based on the third and fourth comparison signals and the reference clock signal;
And a control circuit that controls the peaking amount of the equalizer based on at least the first and second comparison signals.

An equalizer control method according to an embodiment of one aspect of the present invention includes:
There is an equalizer control method for adjusting the equalization amount of the received data signal,
The received data signal is equalized by an equalizer,
The phase of the data signal equalized by the equalizer is detected, and the phase of the data signal and the phase of the recovered clock signal are compared by a phase comparison circuit.
The phase comparison circuit outputs a first comparison signal when the bit width of the equalized data signal is smaller than the period of the recovered clock signal, while the bit width of the equalized data signal is If the period of the restored clock signal is greater than the second comparison signal is output,
The phase comparison circuit outputs a third comparison signal when the phase of the recovered clock signal is ahead of the phase of the data signal,
The phase comparison circuit outputs a fourth comparison signal when the phase of the recovered clock signal is delayed from the phase of the data signal,
Based on the third and fourth comparison signals and the reference clock signal, the restored clock generation circuit generates the restored clock signal,
The peaking amount of the equalizer is controlled based on at least the first and second comparison signals.

  According to the semiconductor integrated circuit of the present invention, the equalization amount of the received data signal can be adjusted while suppressing an increase in circuit scale.

  The semiconductor integrated circuit according to one embodiment of the present invention, for example, does not directly extract the frequency component information of the received signal from the input waveform, but uses information obtained in the phase comparison by the Bang-Bang type phase comparison circuit. This realizes optimal reception equalization with a small circuit configuration.

  For example, a signal for predicting the occurrence of ISI is extracted from the phase comparison information obtained in the Bang-Bang type phase comparison circuit and fed back to the threshold setting of the equalizer.

  Embodiments according to the present invention will be described below with reference to the drawings.

  FIG. 1 is a circuit diagram showing a configuration of a main part of a semiconductor integrated circuit 100 according to a first embodiment which is an aspect of the present invention.

  As shown in FIG. 1, a semiconductor integrated circuit (CDR (Clock Data Recovery) circuit) 100 that adjusts an equalization amount of a received data signal includes an equalizer 1, a phase comparison circuit 2, a deserializer 3, A counter 4, a second counter 5, a third counter 6, a control circuit 7, a digital filter 8, and a restored clock generation circuit 9 are provided.

  The equalizer 1 equalizes the data signal received via the input terminal 100a.

  The phase comparison circuit 2 is, for example, a Bang-Bang type phase comparison circuit. The phase comparison circuit 2 outputs a restored data signal Data based on the data signal equalized by the equalizer 1 and the restored clock signal.

  Further, the phase comparison circuit 2 detects the phase of the data signal equalized by the equalizer 1 and compares the phase of this data signal with the phase of the recovered clock signal. The phase comparison circuit 2 outputs the first comparison signal PS when the bit width of the equalized data signal is smaller than the period of the recovered clock signal, while the bit width of the equalized data signal is recovered. When the period is longer than the period of the clock signal, the second comparison signal PL is output. The phase comparison circuit 2 outputs the third comparison signal Early when the phase of the recovered clock signal is ahead of the phase of the data signal, while the phase of the recovered clock signal is higher than the phase of the data signal. If it is delayed, the fourth comparison signal Late is output.

  The deserializer 3 converts the output signal of the phase detection circuit 2 into parallel. The restored data signal converted in parallel by the deserializer 3 is output from the semiconductor integrated circuit 100 via the output terminal 100b.

  The first counter 4 counts, for example, the first comparison signal PS converted in parallel by the deserializer 3 for a predetermined period as the signal amount of the first comparison signal PS, and the counted first count value X Is output to the control circuit 7.

  The second counter 5 counts, for example, the second comparison signal PL converted in parallel by the deserializer 3 during the predetermined period as the signal amount of the second comparison signal PL, and the counted second count value Y is output to the control circuit 7.

  The third counter 6 counts the sum (output of the adder 6a) of the third comparison signal Early and the fourth comparison signal Late converted in parallel by the deserializer 3 during the predetermined period. 3 is output to the control circuit 7.

  The control circuit 7 controls the peaking amount of the equalizer based on at least the first and second comparison signals PS and PL. That is, the control circuit 7 compares the first count value X of the first comparison signal PS with the second count value Y of the second comparison signal PL. Then, when the first count value X is larger than the second count value Y by a predetermined value or more, the control circuit 7 controls the equalizer 1 so as to increase the peaking amount. On the other hand, when the second count value Y is larger than the first count value X by a predetermined value or more, the control circuit 7 controls the equalizer 1 so as to decrease the peaking amount.

  In particular, the control circuit 7 controls the peaking amount of the equalizer 1 as described above when the third count value Z for a predetermined period is smaller than the predetermined value.

  Further, the control circuit 7 takes in the restored data signal, and the data string of the restored data output from the deserializer 3 includes the patterns “... 00100...” And “. In this case (that is, when the data signal 100a contains a lot of high frequency components and contains a pattern that is easily affected by ISI), the peaking amount of the equalizer 1 may be controlled as described above. Accordingly, it is possible to reduce the possibility of capturing a case caused by random jitter.

  The recovered clock generation circuit 9 generates a recovered clock signal based on the third and fourth comparison signals Early and Late and the reference clock signal.

  Here, the relationship between the data signal input to the phase comparison circuit 2 and the output comparison signal will be described.

  2 to 5 show the waveform of the data signal input to the phase comparison circuit 2 of FIG. 1, the waveform of the recovered clock signal, and the truth value for the value captured by the recovered clock signal CLK and the output comparison signal. It is a figure which shows a relationship.

  First, a state in which the recovered clock signal CLK is ahead of the data signal will be described (FIG. 2). In this state, the value of the data signal Data equalized by the equalizer 1 is captured at the clock edges p, q, r of the recovered clock signal CLK and the inverted signal CLKB. If the captured values are P, Q, and R, respectively, the truth value of P xor Q = 1 & Q xor R = 0 is obtained. Therefore, when this truth value is obtained as a result of the phase comparison, the phase comparison circuit 2 outputs the third comparison signal Early because the recovered clock signal CLK is ahead of the data signal.

  Next, a state where the recovered clock signal CLK is delayed from the data signal will be described (FIG. 3). In this state, similarly, the value of the data signal Data equalized by the equalizer 1 is captured at the clock edges p, q, r of the recovered clock signal CLK and the inverted signal CLKB. If the captured values are P, Q, and R, respectively, the truth value of P xor Q = 0 & Q xor R = 1 is obtained. Accordingly, when the truth value is obtained as a result of the phase comparison, the phase comparison circuit 2 outputs the fourth comparison signal Late because the recovered clock signal CLK is delayed from the data signal.

  Next, a state where the bit width T ′ of the data signal is smaller than the period of the recovered clock signal CLK will be described (FIG. 4). In this state, similarly, the value of the data signal Data equalized by the equalizer 1 is captured at the clock edges p, q, r of the recovered clock signal CLK and the inverted signal CLKB. If the captured values are P, Q, and R, respectively, the truth value of P xor Q = 1 & Q xor R = 1 is obtained. Therefore, when this truth value is obtained as a result of the phase comparison, the phase comparison circuit 2 outputs the first comparison signal PS because the bit width T ′ of the data signal is smaller than the period T of the recovered clock signal CLK. .

  Next, a state where the bit width T ′ of the data signal is larger than the period of the restored clock signal CLK will be described (FIG. 5). In this state, the value of the data signal Data equalized by the equalizer 1 is captured at the clock edges p, q, r of the recovered clock signal CLK and the inverted signal CLKB as described above. If the captured values are P, Q, and R, respectively, the truth value of P xor Q = 0 & Q xor R = 0 is obtained. Therefore, when this truth value is obtained as a result of the phase comparison, the phase comparison circuit 2 outputs the second comparison signal PL because the bit width T ′ of the data signal is larger than the period T of the recovered clock signal CLK. .

  Here, for example, when a data signal having a high transition rate such as “101010...” Is input and the recovered clock signal CLK is located at the approximate center of the bit width T ′ of the data signal, the recovered clock signal CLK The value captured by the inverted signal CLKB can be unstable (meta-stable). In this case, there is a case where the phase comparison circuit 2 erroneously outputs the first and second comparison signals PS and PL.

  Therefore, when a large number of third and fourth comparison signals Early and Late are generated as in the pattern “101010...” (= When the value of the third count value Z is larger than the predetermined value K) ) Prevents the control circuit 7 from taking in the first and second comparison signals PS and PL. The predetermined value K is a parameter value that can be designated from the outside, and is set to a value that stabilizes the operation of the semiconductor integrated circuit (CDR circuit) 100.

  Thereby, it is possible to prevent the control circuit 7 from controlling the equalizer 1 based on the first and second comparison signals PS and PL that are erroneously output.

  Next, an example of the circuit configuration of the phase comparison circuit 2 that executes the truth table described above will be described.

  FIG. 6 is a circuit diagram illustrating an example of the circuit configuration of the phase comparison circuit 2 according to the first embodiment.

  As shown in FIG. 6, the phase comparison circuit 2 includes a first D flip-flop 2a to which the data signal equalized by the equalizer 1 and the recovered clock signal CLK are input, the data signal equalized by the equalizer 1, and And a second D flip-flop 2b to which an inverted clock signal CLKB obtained by inverting the restored clock signal is input.

  Further, the phase comparison circuit 2 includes a third D flip-flop 2c to which the output signal B ′ of the second D flip-flop 2b and the recovered clock signal CLK are input, and an output signal A of the first D flip-flop 2a and And a fourth D flip-flop 2d that receives the restored clock signal CLK and outputs the output signal C (the restored data signal).

  Further, the phase comparison circuit 2 includes a first exclusive OR operation circuit 2e to which the output signal A of the first D flip-flop 2a and the output signal B of the third D flip-flop 2c are input, A second exclusive OR operation circuit 2f to which the output signal C of the D flip-flop 2d and the output signal B of the third D flip-flop 2c are input.

  Further, the phase comparison circuit 2 includes a fifth D flip-flop 2g to which the output signal (A xor B) of the first exclusive OR operation circuit 2e and the restored clock signal CLK are input, and a second exclusive logic. And a sixth D flip-flop 2h to which the output signal (C xor B) of the sum operation circuit 2f and the recovered clock signal CLK are input.

  Further, the phase comparison circuit 2 receives the output signal (A xor B) of the first exclusive OR operation circuit 2e and the output signal (C xor B) of the second exclusive OR operation circuit 2f. The output signal (A xor B) of the first AND operation circuit 2i that receives the inverted input and outputs the third comparison signal Early and the first exclusive OR operation circuit 2e is inverted and input to the second AND circuit 2i. A second AND operation circuit 2j that receives the output signal (C xor B) of the exclusive OR operation circuit 2f and outputs the fourth comparison signal Late.

  Further, the phase comparison circuit 2 receives the output signal delay (A xor B) of the fifth D flip-flop 2g and the output signal (C xor B) of the second exclusive OR circuit 2f. The third AND operation circuit 2k that outputs the first comparison signal PS and the output signal delay (C xor B) of the sixth D flip-flop 2h are input and the first exclusive OR operation circuit And a fourth AND operation circuit 21 that receives the output signal (A xor B) of 2e and outputs the second comparison signal PL.

  Here, an example of a timing chart of the operation in which the phase comparison circuit 2 shown in FIG. 6 outputs each comparison signal is shown below.

  FIG. 7 is a timing chart showing waveforms of signals of the phase comparison circuit 2 having the configuration shown in FIG. 6 when the phase of the recovered clock signal is ahead of the phase of the equalized data signal.

  As shown in FIG. 7, when the phase of the recovered clock signal is ahead of the phase of the equalized data signal, the first comparison signal Early (“High”) is output as the output of the first AND operation circuit 2i. Is output.

  On the other hand, FIG. 8 is a timing chart showing the waveforms of the signals of the phase comparison circuit 2 having the configuration shown in FIG. 6 when the phase of the recovered clock signal is behind the phase of the equalized data signal. .

  As shown in FIG. 8, when the phase of the recovered clock signal is behind the phase of the equalized data signal, the second comparison signal Late (“High”) is output as the output of the second AND operation circuit 2j. Is output.

  Here, “the phase of the recovered clock signal is advanced” means that, for example, the up-edge phase of the recovered clock signal CLK is advanced with respect to the center (= 0.5T ′) of the bit width T ′ of the data signal. Is pointing to.

  FIG. 9 is a timing chart showing waveforms of signals of the phase comparison circuit 2 having the configuration shown in FIG. 6 when the bit width T ′ of the equalized data signal is larger than the period T of the recovered clock signal. It is.

  As shown in FIG. 9, when the bit width T ′ of the equalized data signal is larger than the period T of the recovered clock signal, the comparison signal PL (“High”) is output as the output of the fourth AND operation circuit 2l. Is output.

  On the other hand, FIG. 10 is a timing chart showing waveforms of respective signals of the phase comparison circuit 2 having the configuration shown in FIG. 6 when the bit width T ′ of the equalized data signal is smaller than the period T of the recovered clock signal. It is.

  As shown in FIG. 10, when the bit width T ′ of the equalized data signal is smaller than the period T of the recovered clock signal, the comparison signal PS (“High”) is output as the output of the third AND operation circuit 2k. Is output.

  The bit width T ′ of the data signal corresponds to a period in which the data signal is “High” in FIGS. Therefore, when the logic of the data signal is inverted, the bit width T ′ corresponds to a period during which the data signal is “Low”.

  Next, an example of an operation in which the semiconductor integrated circuit 100 having the above configuration / function adjusts the peaking amount of the equalizer will be described.

  FIG. 11 is a diagram illustrating the transition of the operation state for adjusting the peaking amount of the semiconductor integrated circuit 100 according to the first embodiment.

  First, the phase of the data signal equalized by the equalizer 1 is detected, and the phase of the data signal is compared with the phase of the recovered clock signal by the phase comparison circuit 2. When the bit width T ′ of the equalized data signal is smaller than the period T of the recovered clock signal CLK, the phase comparison circuit 2 outputs the first comparison signal PS. On the other hand, the phase comparison circuit 2 outputs a second comparison signal PL when the bit width T ′ of the equalized data signal is larger than the period T of the recovered clock signal.

  As shown in FIG. 11, for example, when the initial state is the first state State1, the control circuit 7 counts the first count value X obtained by counting the first comparison signal PS and the second comparison signal PL. Are compared with the second count value Y. When the first count value X is larger than the second count value Y by a predetermined value L (L is a natural number where L <K), the state transitions to the second state State2, and the control circuit 7 The equalizer 1 is controlled so as to increase the amount.

  On the other hand, when the second count value Y is larger than the first count value X by a predetermined value L or more, the state transitions to the third state 3 and the control circuit 7 controls the equalizer 1 so as to decrease the peaking amount. To do.

  As described above, the control circuit 7 may maintain the peaking amount when the value of the third count value Z is equal to or greater than the predetermined value K regardless of the first and second count values. Good. That is, the control circuit 7 controls the peaking amount of the equalizer 1 when the third count value Z obtained by counting the third and fourth comparison signals in the predetermined period is smaller than the predetermined value K. Good.

  Next, as shown in FIG. 11, after the transition from the first state State1 to the second state State2, the control circuit 7 acquires the first and second count values X and Y again. When the first count value X is greater than the second count value Y by a predetermined value L or more, the control circuit 7 controls the equalizer 1 again to increase the peaking amount.

  Note that when the value of the third count value Z acquired again becomes equal to or greater than the predetermined value K, the control circuit 7 may maintain the peaking amount and make a transition to the first state State1. Further, when the difference between the second count value Y and the first count value X is less than the predetermined value L, the transition to the first state State1 may be made.

  Also, as shown in FIG. 11, after the transition from the first state State1 to the third state State3, the control circuit 7 acquires the first and second count values X and Y again. When the second count value Y is larger than the first count value X by a predetermined value L or more, the control circuit 7 controls the equalizer 1 again to decrease the peaking amount.

  Note that when the value of the third count value Z acquired again becomes equal to or greater than the predetermined value K, the control circuit 7 may maintain the peaking amount and make a transition to the first state State1. Further, when the difference between the first count value X and the second count value Y is less than the predetermined value L, the transition to the first state State1 may be performed.

  Here, the phase comparison circuit 2 outputs the third comparison signal Early when the phase of the recovered clock signal is ahead of the phase of the data signal as a result of the phase comparison in each of the above states, and the recovered clock signal Is delayed from the phase of the data signal, the fourth comparison signal Late is output.

  By repeating the operation of the semiconductor integrated circuit 100 described above, the peaking amount of the data signal is adjusted, and the bit width T ′ of the data signal is brought close to the period T of the recovered clock signal CLK.

  Similarly, when the initial state is the second and third states State 2 and 3, the operation state of the semiconductor integrated circuit 100 is changed.

  As described above, according to the semiconductor integrated circuit of this embodiment, the equalization amount of the received data signal can be adjusted while suppressing an increase in circuit scale.

  As described in the above embodiments, not only when the data signal input to the phase comparison circuit is equal to the data rate of the data to the equalizer, but also the data rate of the data input to the phase comparison circuit and the recovery clock. The present invention is also applicable to the case where the clock frequency is 1 / n (n: natural number) of the data rate of data input to the equalizer.

1 is a circuit diagram illustrating a configuration of a main part of a semiconductor integrated circuit 100 according to a first embodiment which is an aspect of the present invention. FIG. FIG. 2 is a diagram illustrating a waveform of a data signal input to a phase comparison circuit 2 in FIG. 1, a waveform of a recovered clock signal, and a relationship between a truth value for a value captured by the recovered clock signal CLK and an output comparison signal. . FIG. 2 is a diagram illustrating a waveform of a data signal input to a phase comparison circuit 2 in FIG. 1, a waveform of a recovered clock signal, and a relationship between a truth value for a value captured by the recovered clock signal CLK and an output comparison signal. . FIG. 2 is a diagram illustrating a waveform of a data signal input to a phase comparison circuit 2 in FIG. 1, a waveform of a recovered clock signal, and a relationship between a truth value for a value captured by the recovered clock signal CLK and an output comparison signal. . FIG. 2 is a diagram illustrating a waveform of a data signal input to a phase comparison circuit 2 in FIG. 1, a waveform of a recovered clock signal, and a relationship between a truth value for a value captured by the recovered clock signal CLK and an output comparison signal. . FIG. 3 is a circuit diagram illustrating an example of a circuit configuration of a phase comparison circuit 2 according to the first embodiment. FIG. 7 is a timing chart showing waveforms of signals of the phase comparison circuit 2 having the configuration shown in FIG. 6 when the phase of the recovered clock signal is ahead of the phase of the equalized data signal. 7 is a timing chart showing waveforms of respective signals of the phase comparison circuit 2 having the configuration shown in FIG. 6 when the phase of the recovered clock signal is delayed from the phase of the equalized data signal. 7 is a timing chart showing waveforms of respective signals of the phase comparison circuit 2 having the configuration shown in FIG. 6 when the bit width T ′ of the equalized data signal is larger than the period T of the recovered clock signal. 7 is a timing chart showing waveforms of signals of the phase comparison circuit 2 having the configuration shown in FIG. 6 when the bit width T ′ of the equalized data signal is smaller than the period T of the recovered clock signal. FIG. 6 is a diagram illustrating transition of an operation state for adjusting the peaking amount of the semiconductor integrated circuit 100 according to the first embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Equalizer 2 Phase comparison circuit 2a 1st D flip-flop 2b 2nd D flip-flop 2c 3rd D flip-flop 2d 4th D flip-flop 2e 1st exclusive OR operation circuit 2f 2nd exclusive OR operation circuit 2g 5th D flip-flop 2h 6th D flip-flop 2i 1st AND operation circuit 2j 2nd AND operation circuit 2k 3rd AND operation circuit 2l 4th AND operation circuit 3 Deserializer 4 First Counter 5 Second Counter 6 Third Counter 6a Adder 7 Control Circuit 8 Digital Filter 9 Restored Clock Generation Circuit 100 Semiconductor Integrated Circuit 100a Output Terminal 100b Input Terminal

Claims (5)

There is a semiconductor integrated circuit for adjusting the equalization amount of a received data signal,
An equalizer for equalizing the received data signal;
The recovered data signal is output based on the data signal and the recovered clock signal equalized by the equalizer, the phase of the data signal equalized by the equalizer is detected, and the phase of the data signal and the recovered clock signal When the bit width of the equalized data signal is smaller than the period of the recovered clock signal, the first comparison signal is output, while the bit width of the equalized data signal is Output a second comparison signal when the period of the recovered clock signal is larger than the period of the recovered clock signal, and output a third comparison signal when the phase of the recovered clock signal is ahead of the phase of the data signal, A phase comparison circuit that outputs a fourth comparison signal when the phase of the recovered clock signal is behind the phase of the data signal;
A recovered clock generation circuit for generating the recovered clock signal based on the third and fourth comparison signals and the reference clock signal;
And a control circuit that controls the peaking amount of the equalizer based on at least the first and second comparison signals. The control circuit includes:
Comparing the signal amount of the first comparison signal and the signal amount of the second comparison signal;
When the signal amount of the first comparison signal is larger than the signal amount of the second comparison signal by a predetermined value or more, the equalizer is controlled to increase the peaking amount,
The equalizer is controlled so as to reduce the peaking amount when the signal amount of the second comparison signal is larger than the signal amount of the first comparison signal by a predetermined value or more. Semiconductor integrated circuit. A deserializer for converting the output signal of the phase detection circuit in parallel;
A first counter for counting the first comparison signal converted in parallel by the deserializer;
A second counter that counts the second comparison signal converted in parallel by the deserializer,
The control circuit includes:
Comparing a first count value obtained by counting the first comparison signal with a second count value obtained by counting the second comparison signal;
When the first count value is larger than the second count value by a predetermined value or more, the equalizer is controlled to increase the peaking amount,
2. The semiconductor integrated circuit according to claim 1, wherein when the second count value is larger than the first count value by a predetermined value or more, the equalizer is controlled so as to reduce a peaking amount. A third counter for counting the third comparison signal and the fourth comparison signal converted in parallel by the deserializer;
The control circuit controls the peaking amount of the equalizer when a third count value obtained by counting the third comparison signal and the fourth comparison signal for a predetermined period is smaller than a predetermined value. The semiconductor integrated circuit according to claim 1. There is an equalizer control method for adjusting the equalization amount of the received data signal,
The received data signal is equalized by an equalizer,
The phase of the data signal equalized by the equalizer is detected, and the phase of the data signal and the phase of the recovered clock signal are compared by a phase comparison circuit.
The phase comparison circuit outputs a first comparison signal when the bit width of the equalized data signal is smaller than the period of the recovered clock signal, while the bit width of the equalized data signal is If the period of the restored clock signal is greater than the second comparison signal is output,
The phase comparison circuit outputs a third comparison signal when the phase of the recovered clock signal is ahead of the phase of the data signal,
The phase comparison circuit outputs a fourth comparison signal when the phase of the recovered clock signal is delayed from the phase of the data signal,
Based on the third and fourth comparison signals and the reference clock signal, the restored clock generation circuit generates the restored clock signal,
An equalizer control method, comprising: controlling an amount of peaking of the equalizer based on at least the first and second comparison signals.

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