JP2008270641A - Field-effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an insulated gate type field-effect transistor preventing gate insulation breakdown resulted from a gate insulating film and characteristic degradation by hot carrier. <P>SOLUTION: In a field-effect transistor whose gate electrode is insulated from a semiconductor substrate surface, gate air gap is provided at least between a gate electrode surface and the semiconductor substrate surface which is opposite to the gate electrode surface, and the gate air gap is filled with a gas. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a field effect transistor constituting an integrated circuit, and more particularly to a field effect transistor resistant to breakdown and hot carriers.

  Especially since the 1970s, most integrated circuits are composed of MOS (Metal-Oxide-Semiconductor) FET (Field Effect Transistor) using a silicon substrate. Also, CMOS (complementary) FETs combining n-channel and p-channel are used in most integrated circuits. In this FET, a gate for inputting a signal is insulated from the silicon substrate through an insulating film, and the gate and the substrate are electrically short-circuited with a certain resistance value when the insulation is broken. , The FET does not operate normally. Since the capacitance of the gate of the FET is small, even a slight charge generates a high voltage and breaks the insulation. This is why MOSFETs are said to be vulnerable to electrostatic breakdown.

A carrier having an energy of 2 to 3 eV or more generated in the substrate due to the drain current flowing is called a hot carrier because of its high energy, and the hot carrier penetrates into the insulating film by entering the insulating film. A fixed charge is generated, and the threshold voltage V _{TH of the} FET is changed. As a result, the operation of the integrated circuit gradually becomes unstable and does not operate at the end.

Japanese Patent Application Laid-Open No. H10-260260 discloses that transistor characteristics are prevented from being deteriorated due to hot electrons by filling a part or the whole between a gate electrode and a channel with a gas having a predetermined pressure.
JP 61-183969 A

  As described above, MOSFETs have major problems of gate dielectric breakdown due to the gate insulating film and FET characteristic deterioration due to hot carriers.

  The present invention has been made in order to solve the above-described problems of the prior art, and an insulated gate field effect transistor which prevents gate dielectric breakdown due to the gate insulating film and deterioration of characteristics due to hot carriers is provided. The purpose is to provide.

  This is because the permanent dielectric breakdown and the accumulation of hot carriers, which are conventional problems, are due to the presence of a solid as an insulating film. In the present invention, all or part of the conventional gate insulating film is replaced with gas or liquid so that the above-described problem phenomenon does not occur.

  Specifically, in a field effect transistor in which a gate electrode is insulated from the surface of a semiconductor substrate, a gate gap exists at least between the surface of the semiconductor substrate facing the gate electrode surface, and the gate gap is filled with gas. The structure.

  In this case, the gate gap may be filled with gas and liquid. Further, the length of the leakage current path in the insulating region existing between the gate electrode and the semiconductor substrate surface may be twice or more the thickness of the gate gap.

  According to the present invention, a structure of a field effect transistor that is resistant to dielectric breakdown and hot carriers can be provided, so that a highly reliable field effect transistor that can avoid characteristic deterioration can be provided. In addition, since the phenomenon that the insulating film is deteriorated by radiation does not occur, it can be used in outer space or a place where radiation damage is remarkable.

  The gist of the present invention is to form a void under the gate by removing the sacrificial film under the gate once formed. When the end of the gap is closed with an insulating film or the like, a part of the atmosphere enters the gap at a high temperature. As a result, the gap is filled with gas. If the insulating film is deposited in a vacuum, the amount of invading gas can be reduced. However, since a so-called complete vacuum cannot be realized by a practical technique, it is also called a gas in this case.

  Hereinafter, the best mode for carrying out the present invention will be described with reference to FIGS.

  FIG. 1 is a sectional view of a gas insulated gate field effect transistor (abbreviated as MGSFET (Metal-Gas-Semiconductor Field-Effect Transistor)) of the present invention. The basic structure is the same as an oxide-insulated gate field effect transistor (abbreviated MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor)) used in products. The different part is the gate gap 12.

  FIG. 2 is a plan view of the transistor of the present invention. In FIG. 2, a cross section AA ′ in the channel length direction and a cross section BB ′ in the channel width direction are shown in FIGS. 1 and 3 to 7 (a) and (b), respectively.

Of particular importance, the portions of the leakage current paths A, B and C (shown by 20, 21 and 22 respectively) shown in FIG. 1 must be sufficiently thicker than the thickness T _GAP of the gate gap 12. If it is thin, pressure breakdown will be induced at that portion, and the desired high breakdown voltage cannot be achieved. In the present invention, the desired high withstand voltage can be achieved by setting the length of each current path (20, 21, 22) to at least twice the thickness T _GAP of the gate gap 12.

  Next, a manufacturing method for obtaining the structure of FIG. 1 will be described with reference to FIGS.

As shown in FIG. 3, an element isolation region 4 is formed using a p-type silicon substrate 1 by using a well-known local oxidation method (LOCOS). First, thermal oxidation is performed using the selectively formed silicon nitride film 3 as an oxidation resistant film to form a field oxide film 4. The thermal oxidation conditions are 1000 ° C. and 120 minutes by wet oxidation, and the SiO ₂ film 4 having a thickness of about 500 nm can be formed. Since a strong tensile stress is generated in the silicon nitride film (Si ₃ N ₄ ) 3, a pad oxide film 2 is generally laid under the silicon nitride film 3 in order to prevent damage to the silicon substrate. Here, the thickness was set to 30 nm. Since all pattern formation including this figure is performed by well-known photolithography and etching, the description is omitted in each drawing.

Thereafter, as shown in FIG. 4, the silicon nitride film 3 is removed by treatment with hot phosphoric acid at 180 ° C. for 45 minutes, the pad oxide film 2 is removed, and a 10 nm thick SiO ₂ film is formed (10 nm thick). The SiO ₂ film is not shown in this figure), and a 40 nm thick field oxide film end protective film 5 is deposited by LPCVD, and the field oxide film end protective film 5 is processed by photoetching. Further, after that, a sacrificial film 6 to be removed by etching is formed to form a void later. Here, a 50 nm thick SiO ₂ film 6 was used. The thickness can be arbitrarily set to obtain desired transistor characteristics. In this figure, the sacrificial film 6 is shown as being processed by photoetching.

Thereafter, as shown in FIG. 5, a polycrystalline silicon gate electrode 8 having a thickness of 200 nm in which phosphorus is added at 10 ²⁰ / cm ³ or more to a desired portion is selectively formed, and arsenic is formed using the gate electrode 8 as a mask. 5 × 10 ¹⁵ / cm ^{2 is} implanted at an energy of 30 keV, and instantaneous annealing is performed at 900 ° C. for 10 seconds to obtain the source / drain 10. Thereafter, an etching protective film 9 made of a silicon nitride film having a thickness of 80 nm is deposited by LPCVD (Low Pressure Chemical Vapor Deposition).

After that, as shown in FIG. 6, when the etching hole 11 is selectively opened and the sacrificial film 6 made of SiO ₂ is etched with buffered hydrofluoric acid (NH ₄ F + HF) through this hole, the gate gap 12 is formed. The etching time is set so that the sacrificial film 6 just under the gate is removed. What is important at this time is that the field oxide film end protective film 5 of the silicon nitride film (Si ₃ N ₄ ) is not etched by buffered hydrofluoric acid, so that this becomes a protective film and the SiO ₂ field oxide film as shown in FIG. 4 is not etched. In reality, there are cases where etching does not cause a problem, but in that case, it is necessary to set the pattern arrangement with a sufficient margin.

Thereafter, as shown in FIG. 7, in order to close the etching hole 11, an interlayer insulating film 13 of 300 nm thick SiO ₂ film is applied at 400 ° C. by APCVD (Atmospheric-Pressure Chemical Vapor Deposition) for about 1 minute. And accumulate. The reason for using APCVD that is poor in uniformity without using LPCVD that can deposit a film with a uniform thickness along the underlying layer is to prevent the deposited SiO ₂ from penetrating under the gate electrode 8. is there. If it penetrates directly under the gate electrode 8, the breakdown voltage of the gate electrode 8 is determined in this portion, and the object of the present invention cannot be achieved.

Further, the atmosphere for depositing APCVD may remain in the gate gap 12 as it is, which is an important factor. In the case of this measure, the SiO ₂ film was deposited by the following reaction.

SiH ₄ + 2O ₂ → SiO ₂ + 2H ₂ O (Formula 1)
However, since the surface of the silicon substrate 1 and the gate electrode 8 of polycrystalline silicon are exposed to water vapor oxidation at a deposition temperature of 400 ° C. for 1 minute, a very thin film may be formed. From the estimation of the oxidation rate in consideration of the atmosphere, it is estimated to be 1-2 nm or less. The flow rate of SiH ₄ and O ₂ is 1,000 ml / min or less, but N ₂ for diluting them is flowing at a flow rate of approximately 50,000 ml / min, so that only a small amount of gas remains in the gate gap 12. It is estimated to be nitrogen containing water vapor. That is, it can be estimated that there are no p-type or n-type impurities harmful to the transistor.

  Thereafter, PSG (Phospho-Silicate Glass) containing 300% of phosphorus, which is extremely effective for gettering alkali ions, is deposited by 300 nm to form a stable and reliable transistor. In the description of the present invention, the interlayer insulating film 13 is representative, but there are various options for the material used and its deposition method.

  After that, as already shown in FIG. 1, if the contact hole 14 to the source / drain is selectively formed and the electrode 15 made of Al (aluminum) is selectively formed, the gap insulated gate electric field of the present invention can be obtained. An effect transistor can be realized.

  FIG. 8 shows an example of characteristics realized in accordance with the manufacturing process described above. The characteristics (a) of the transistor (MGS transistor) when the gate gap is provided as described above and the characteristics (b) of a normal transistor (MOS transistor) without the gate gap are shown. The structures of the fabricated transistors are almost the same, and the channel length LCH is 1 μm and the channel width WCH is 5 μm. The characteristic (a) is that the gate gap is 50 nm, and the characteristic (b) is that the gate oxide film thickness is 50 nm. Each figure shows the current-voltage characteristics when the gate voltage is initially applied to a high voltage and the current-voltage characteristics when the gate voltage is applied to a high voltage again after applying the gate voltage to about 50V. Yes.

  In the case of the transistor (b) having a normal gate insulating film, a current starts to gradually flow around 20V when an initial gate voltage is applied, and a rapid current flows due to gate dielectric breakdown when the gate voltage is around 35V. Thereafter, up to 50 V, a current flowing through the gate dielectric breakdown path is observed. When the gate voltage is applied again, a large amount of current flows even at a low gate voltage due to the current flowing through the gate-broken path. As described above, in the conventional transistor, when a dielectric breakdown is caused by applying a high voltage to the gate and then measured again, a resistive leak current path is formed and it can no longer be said to be an insulating film.

  On the other hand, in the case of the transistor (a) having a gate gap, a sudden large current due to dielectric breakdown flows near 20 V when the initial gate voltage is applied, but the current remains small even when the gate voltage is increased to near 50 V. is doing. That is, it is understood that a sufficiently high withstand voltage characteristic can be obtained by once causing dielectric breakdown and flowing a large current.

The drain current when the same applied voltage is applied is 50 nm, which is the same as the dielectric constant of SiO ₂ , that is, about 3.9 times larger than that of a transistor having a gate gap of about 3.9 times. Flowing.

  The reason why the initial breakdown voltage of the transistor having the gate gap is relatively low is estimated to be that creeping leakage current is generated in the weaker one of the leakage current paths shown in FIG. The Considering the length of the distance, it is estimated that the leakage current path 20 is the main cause, but no evidence has been found. It is estimated that once the dielectric breakdown occurs, this creeping leakage current path disappears, and as a result, a transistor having a high gate breakdown voltage is formed.

  In this way, the breakdown voltage of the gate insulating film can be ignored, so that the transistor can be protected from the breakdown of the gate insulating film part caused by cosmic rays and radiation. An insulated gate field effect transistor having excellent characteristics can be realized.

Further, as described above, when a solid such as a gate insulating film is used as a gas, dielectric breakdown that occurs in the solid does not occur. Further, since the common gate insulating film thickness T _OXIDE of MOSFET is 10 μm or less, if the gap is 10 μm or less, no harmful discharge phenomenon peculiar to gas occurs. The discharge requires a distance with sufficient energy for the accelerated electrons to ionize the gas, and sufficient energy cannot be obtained at a distance on the order of 10 μm.

  Since there is no solid to store charges, even if hot carriers enter, the carriers are absorbed by the source and drain, and the threshold voltage change phenomenon due to so-called hot carriers is slight. Since this depends on the state of the silicon substrate surface, the control of the surface is an important factor.

  As described above, according to the present invention, it is possible to provide a structure of a field effect transistor that is strong against breakdown and hot carriers, and thus it is possible to provide a highly reliable field effect transistor that can avoid characteristic deterioration.

  In the description of the present invention, a source / drain having a single shape as shown in FIG. 1 is used. Usually, a fine transistor is close to the gate electrode 8 in order to increase the breakdown voltage of the drain. A shallow junction is formed in the portion, and a deep junction is formed in the portion in contact with the electrode 15, and this structure can be used as it is in the present invention. This structure is called an LDD (Lightly Doped Drain) or extension structure, and the present invention can be applied to both.

In the description of the element isolation region, the field oxide film 4 by the LOCOS method is used. However, a groove is formed in the silicon substrate 1 and element isolation is performed with a SiO ₂ -based film embedded in the groove. The present invention can be similarly applied to the deep groove separation.

  In the description of the present invention, a transistor in which the gate gap 12 is filled with a gas is used. However, as another embodiment of the present invention, this portion can be filled with an insulating liquid. The term “liquid” as used herein is broadly defined to include a gel-like or sol-like substance.

  In that case, a drain current that is double the relative dielectric constant of the liquid can be obtained, and the transistor characteristics are excellent. For example, an insulating liquid is widely used for insulation of a large-sized power transformer, and the excellent dielectric strength characteristics of the insulating liquid are widely known. In the case of liquid, corona discharge such as gas and plasma discharge are less likely to occur, and the insulation is excellent.

  In the case of a liquid, it is necessary to obtain an optimal solution for the material of the interlayer insulating film 13 and the deposition method. For example, it is difficult to deposit the interlayer insulating film 13 at a temperature equal to or higher than the boiling point of the liquid, and it may be scattered by the vapor pressure of the liquid in a high vacuum. It is necessary to choose.

  Specifically, an insulating liquid mainly composed of alkylbenzene, polybutene, alkylnaphthalene, methylpolyallylmethane, alkyldiphenylethane, or the like that is widely used as an insulating liquid for power equipment can be used. In the case of using a liquid, the temperature of the process for closing the etching hole 11 needs to be lower than the boiling point of the insulating film to be used, and a sputtering method that can deposit the insulating film at a low temperature is suitable.

  The field effect transistor according to the present invention has a structure that does not in principle cause permanent gate dielectric breakdown caused by the gate insulating film and deterioration of transistor characteristics due to hot carriers by filling the gap under the gate electrode with gas or liquid. realizable.

It is a figure which shows the cross section of the field effect transistor of the Example of this invention, (a) shows a channel length direction, (b) shows sectional drawing of a channel width direction. It is a figure which shows the top view of the field effect transistor of the Example of this invention, AA 'shows the cross-sectional line of a channel length direction, and BB' shows the cross-sectional line of a channel width direction. It is a figure explaining the manufacturing process of the field effect transistor of the Example of this invention. It is a figure explaining the manufacturing process of the field effect transistor of the Example of this invention. It is a figure explaining the manufacturing process of the field effect transistor of the Example of this invention. It is a figure explaining the manufacturing process of the field effect transistor of the Example of this invention. It is a figure explaining the manufacturing process of the field effect transistor of the Example of this invention. It is a figure explaining operation | movement of the field effect transistor of the Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Pad oxide film 3 Silicon nitride film 4 Field oxide film 5 Field oxide film edge protective film 6 Sacrificial film 8 Gate electrode 9 Etching protective film 10 Source / drain 11 Etching hole 12 Gate gap 13 Interlayer insulating film 14 Contact hole 15 Electrode 20 Leakage current path A
21 Leakage current path B
22 Leakage current path C

Claims (3)

In a field effect transistor in which the gate electrode is insulated from the surface of the semiconductor substrate,
An insulated gate field effect transistor characterized in that a gate gap exists at least between a gate electrode surface and a semiconductor substrate surface facing the gate electrode surface, and the gate gap is filled with a gas. In a field effect transistor in which the gate electrode is insulated from the surface of the semiconductor substrate,
An insulated gate field effect transistor characterized in that a gate gap exists between at least a gate electrode surface and a semiconductor substrate surface facing the gate electrode surface, and the gate gap is filled with a gas and a liquid. The insulated gate field effect transistor according to claim 1 or 2,
An insulated gate field effect transistor characterized in that the length of the leakage current path of the insulating region existing between the gate electrode and the semiconductor substrate surface is at least twice the thickness of the gate gap.

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