JP2008270610A - Semiconductor package - Google Patents

Semiconductor package Download PDF

Info

Publication number
JP2008270610A
JP2008270610A JP2007113240A JP2007113240A JP2008270610A JP 2008270610 A JP2008270610 A JP 2008270610A JP 2007113240 A JP2007113240 A JP 2007113240A JP 2007113240 A JP2007113240 A JP 2007113240A JP 2008270610 A JP2008270610 A JP 2008270610A
Authority
JP
Japan
Prior art keywords
satin
semiconductor package
surface roughness
characters
pear
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007113240A
Other languages
Japanese (ja)
Inventor
Osamu Fujii
治 藤井
Toshihiro Ikegami
敏宏 池上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Priority to JP2007113240A priority Critical patent/JP2008270610A/en
Publication of JP2008270610A publication Critical patent/JP2008270610A/en
Pending legal-status Critical Current

Links

Images

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a semiconductor package with which a forged article can be easily identified. <P>SOLUTION: A semiconductor package of the present invention seals a semiconductor chip with a resin, one surface of the semiconductor package is formed from aventurine 1 with first surface coarseness, characters 12 of a product number or the like formed from aventurine 2 having second surface coarseness are provided on the aventurine 1, and the aventurine 1 and the aventurine 2 have the same reference plane. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、金型成形による樹脂封止型の半導体パッケージに関する。   The present invention relates to a resin-sealed semiconductor package formed by mold molding.

従来、半導体パッケージにおける製品番号等の表示は、梨地や鏡面仕上げのパッケージ表面にレーザーマーカーで刻印を施したり、インクで捺印(例えば、「特許文献1」を参照。)を行なっていた。   Conventionally, the display of product numbers and the like in semiconductor packages has been performed by marking the surface of a package with a satin finish or a mirror finish with a laser marker or stamping with ink (see, for example, “Patent Document 1”).

しかしながら、このような従来の方法では、模写が容易で、半導体装置の偽造品に容易に利用されるという問題があった。
特許第2951220号公報
However, such a conventional method has a problem that copying is easy and it can be easily used for a counterfeit product of a semiconductor device.
Japanese Patent No. 2951220

本発明は、偽造品を容易に識別することができる半導体パッケージを提供する。   The present invention provides a semiconductor package capable of easily identifying a counterfeit product.

本発明の一態様によれば、半導体チップを樹脂封止した半導体パッケージであって、前記半導体パッケージの一表面が第1の表面粗さを有する第1の梨地で形成され、前記第1の梨地上に第2の表面粗さを有する第2の梨地で形成された製品番号等の文字を備え、前記第1の梨地および前記第2の梨地が同じ基準面を有することを特徴とする半導体パッケージが提供される。   According to an aspect of the present invention, there is provided a semiconductor package in which a semiconductor chip is sealed with resin, wherein one surface of the semiconductor package is formed of a first satin having a first surface roughness, and the first pear is formed. A semiconductor package comprising characters such as a product number formed of a second satin having a second surface roughness on the ground, wherein the first satin and the second satin have the same reference surface Is provided.

また、本発明の別の一態様によれば、半導体チップを樹脂封止した半導体パッケージであって、前記半導体パッケージの一表面が第1の表面粗さを有する第1の梨地で形成され、前記第1の梨地上に第2の表面粗さを有する第2の梨地で形成された文字領域と、前記文字領域に前記第1の梨地で形成された製品番号等の文字を備え、前記第1の梨地および前記第2の梨地が同じ基準面を有することを特徴とする半導体パッケージが提供される。   According to another aspect of the present invention, there is provided a semiconductor package in which a semiconductor chip is resin-sealed, wherein one surface of the semiconductor package is formed of a first satin having a first surface roughness, A character region formed of a second satin having a second surface roughness on the first pear surface; and a character such as a product number formed of the first pear texture in the character region, the first There is provided a semiconductor package characterized in that the satin and the second satin have the same reference surface.

さらに、本発明の別の一態様によれば、半導体チップを樹脂封止した半導体パッケージであって、前記半導体パッケージの一表面が鏡面仕上げで形成され、前記鏡面上に所定の表面粗さを有する梨地で形成された製品番号等の文字を備え、前記鏡面および前記梨地が同じ基準面を有することを特徴とする半導体パッケージが提供される。   Further, according to another aspect of the present invention, there is provided a semiconductor package in which a semiconductor chip is sealed with a resin, wherein one surface of the semiconductor package is formed with a mirror finish and has a predetermined surface roughness on the mirror surface. There is provided a semiconductor package comprising characters such as a product number formed in satin, wherein the mirror surface and the satin have the same reference surface.

さらに、本発明の別の一態様によれば、半導体チップを樹脂封止した半導体パッケージであって、前記半導体パッケージの一表面が所定の表面粗さを有する梨地で形成され、前記梨地上に鏡面仕上げで形成された製品番号等の文字を備え、前記梨地および前記鏡面が同じ基準面を有することを特徴とする半導体パッケージが提供される。   Furthermore, according to another aspect of the present invention, there is provided a semiconductor package in which a semiconductor chip is sealed with resin, wherein one surface of the semiconductor package is formed with a satin surface having a predetermined surface roughness, and is mirror-finished on the pear surface. There is provided a semiconductor package having characters such as a product number formed by finishing, wherein the satin finish and the mirror surface have the same reference surface.

本発明によれば、製品番号等の文字が下地と同じ基準面に周囲と異なる表面粗さで形成されているので、偽造品を容易に識別することができる。   According to the present invention, since the characters such as the product number are formed on the same reference surface as the base with a surface roughness different from the surroundings, a forged product can be easily identified.

以下、図面を参照しながら、本発明の実施例を説明する。   Embodiments of the present invention will be described below with reference to the drawings.

図1は、本発明の実施例1に係わる半導体パッケージを示す図である。ここでは、一例として、32ピンDIP(Dual In-line Package)の表面に製品番号(ABC012−3)が形成された図面を示した。   FIG. 1 is a view showing a semiconductor package according to Embodiment 1 of the present invention. Here, as an example, a drawing in which a product number (ABC012-3) is formed on the surface of a 32-pin DIP (Dual In-line Package) is shown.

本発明の実施例1に係わる半導体パッケージは、第1の表面粗さを有する梨地1のパッケージ上面11(以下、「下地11」という。)に第2の表面粗さを有する梨地2で形成された文字12を備えている。   The semiconductor package according to the first embodiment of the present invention is formed of the satin 2 having the second surface roughness on the package upper surface 11 (hereinafter referred to as “base 11”) of the satin 1 having the first surface roughness. The character 12 is provided.

梨地1および梨地2は、放電加工やダイヤモンドなどの吹きつけで形成された金型により一体成形される。具体的には、放電加工やダイヤモンドなどの吹きつけで金型表面に所望の傷を付け、その後、化学的にエッチング処理を行なって微視的には滑らかで、表面粗さの異なる2種類の梨地1および梨地2が形成される。   The satin 1 and the satin 2 are integrally formed by a die formed by electrical discharge machining or spraying with diamond or the like. Specifically, desired scratches are made on the surface of the mold by electric discharge machining or spraying with diamond, etc., and then chemically etched to make microscopically smooth and different in surface roughness. A satin 1 and a satin 2 are formed.

吹きつけで金型表面を加工する際には、製品番号などの文字12の部分をマスクすることで梨地1と梨地2の表面粗さを制御している。   When the mold surface is processed by spraying, the surface roughness of the satin 1 and the satin 2 is controlled by masking the character 12 portion such as the product number.

このように、まずパッケージ金型を形成し、その表面を加工して梨地1と梨地2を一体成形するので、梨地1および梨地2の基準面(加工前の表面)は同じ面であり、パッケージ表面に文字12を形成したことによる凹凸はほとんど生じない。   Thus, the package mold is first formed, and the surface is processed to integrally form the satin 1 and the satin 2, so that the reference surface (surface before processing) of the satin 1 and the satin 2 is the same surface, and the package The unevenness due to the formation of the character 12 on the surface hardly occurs.

図2は、本発明の実施例1に係わる半導体パッケージの表面付近の断面を示す模式図である。
図2に示したように、文字12の部分は表面粗さ2の梨地2で形成され、下地11の部分は表面粗さ1の梨地1で形成されている。表面粗さの違いは、基準面13上に存在する深さ5〜20μm程度の小さな凹部の平均ピッチの違いに起因している。
FIG. 2 is a schematic view showing a cross section near the surface of the semiconductor package according to the first embodiment of the present invention.
As shown in FIG. 2, the character 12 portion is formed of a satin 2 having a surface roughness of 2, and the base 11 portion is formed of a satin 1 having a surface roughness of 1. The difference in surface roughness is attributed to the difference in the average pitch of small recesses having a depth of about 5 to 20 μm existing on the reference surface 13.

すなわち、梨地1では凹部が平均ピッチ40〜50μmで2次元的に不均一に散在し、梨地2では凹部が平均ピッチ80〜100μmで2次元的に不均一に散在する。   That is, in the satin 1, the recesses are scattered two-dimensionally and unevenly at an average pitch of 40 to 50 μm, and in the satin 2, the recesses are scattered two-dimensionally and unevenly at an average pitch of 80 to 100 μm.

このように、同一の基準面13上に凹部の平均ピッチが異なる領域を作ることで文字12が形成されている。   Thus, the character 12 is formed by making the area | region from which the average pitch of a recessed part differs on the same reference surface 13. FIG.

上記実施例1によれば、製品番号等の文字12が下地11と同じ基準面13に周囲と異なる表面粗さで形成されているので、文字12が印刷やレーザー加工等で形成された偽造品を容易に識別することができる。   According to the first embodiment, since the characters 12 such as product numbers are formed on the same reference surface 13 as the base 11 with a surface roughness different from the surroundings, the forged product in which the characters 12 are formed by printing, laser processing, or the like. Can be easily identified.

上述の実施例1では、下地11および文字12が表面粗さの異なる梨地で形成されるとしたが、本発明はこれに限られるものではなく、例えば、梨地1または梨地2のいずれかを鏡面仕上げ(梨地加工なし)とすることもできる。   In the first embodiment described above, the base 11 and the characters 12 are formed of satin having different surface roughnesses. However, the present invention is not limited to this. For example, either the satin 1 or the satin 2 is mirrored. It can also be finished (without satin finish).

図3は、本発明の実施例2に係わる半導体パッケージを示す平面図である。ここでは、一例として、実施例1と同様の32ピンDIPの平面図を示した。   FIG. 3 is a plan view showing a semiconductor package according to Embodiment 2 of the present invention. Here, as an example, a plan view of a 32-pin DIP similar to that of the first embodiment is shown.

本発明の実施例2に係わる半導体パッケージは、第1の表面粗さを有する梨地1のパッケージ上面21(以下、「下地21」という。)に第2の表面粗さを有する梨地2で形成された文字領域23を備え、文字領域23の中に梨地1の文字22が形成されている。   The semiconductor package according to the second embodiment of the present invention is formed of the satin 2 having the second surface roughness on the package upper surface 21 (hereinafter referred to as “base 21”) of the satin 1 having the first surface roughness. The character region 23 is provided, and the satin 1 character 22 is formed in the character region 23.

梨地1および梨地2は、実施例1と同様に、放電加工やダイヤモンドなどの吹きつけで形成された金型により一体成形される。したがって、下地21、文字22、および文字領域23の基準面、つまり、梨地1および梨地2の基準面は同じ面であり、パッケージ表面に文字22および文字領域23を形成したことによる凹凸はほとんど生じない。   Similarly to Example 1, the satin 1 and the satin 2 are integrally formed by a die formed by electric discharge machining or spraying with diamond or the like. Therefore, the reference planes of the base 21, the character 22 and the character area 23, that is, the reference planes of the satin 1 and the satin 2 are the same surface, and the unevenness due to the formation of the character 22 and the character area 23 on the package surface almost occurs. Absent.

梨地1および梨地2の断面構造は、実施例1と同様であるので、詳しい説明は省略する。   Since the cross-sectional structures of the satin 1 and the satin 2 are the same as those in the first embodiment, detailed description thereof is omitted.

上記実施例2によれば、製品番号等の文字22が文字領域23と同じ基準面13に周囲と異なる表面粗さで形成されているので、文字22が印刷やレーザー加工等で形成された偽造品を容易に識別することができる。   According to the second embodiment, the character 22 such as the product number is formed on the same reference surface 13 as the character region 23 with a surface roughness different from that of the surrounding area. Therefore, the forgery in which the character 22 is formed by printing, laser processing, or the like. The product can be easily identified.

上述の実施例2では、下地21および文字22と文字領域23が表面粗さの異なる梨地で形成されるとしたが、本発明はこれに限られるものではなく、例えば、梨地1または梨地2のいずれかを鏡面仕上げ(梨地加工なし)とすることもできる。   In the above-described second embodiment, the base 21 and the characters 22 and the character regions 23 are formed of satin having different surface roughnesses. However, the present invention is not limited to this. For example, the satin 1 or the satin 2 Either of them can be mirror finished (no matte finish).

また、上述の実施例2では、下地21および文字22は同じ梨地1で形成されるとしたが、本発明はこれに限られるものではなく、例えば、下地21、文字22、および文字領域23がすべて異なる表面粗さを有する梨地とすることもできるし、さらには、これらのうちいずれかを鏡面仕上げとしても良い。   In the second embodiment, the base 21 and the character 22 are formed of the same satin 1, but the present invention is not limited to this. For example, the base 21, the character 22, and the character region 23 are provided. All of them can be satin having different surface roughnesses, or any one of them can be mirror-finished.

さらに、上述の実施例1および2の説明では、パッケージ形状は32ピンDIPであるとしたが、本発明はこれに限られるものではなく、樹脂モールドで一体成形する樹脂封止型パッケージであれば、形状、ピン数に関わりなく適用することができる。   Furthermore, in the above description of the first and second embodiments, the package shape is the 32-pin DIP. However, the present invention is not limited to this, and any resin-sealed package that is integrally molded with a resin mold may be used. It can be applied regardless of the shape and the number of pins.

さらに、上述の実施例1および2の説明では、製品番号等の文字12または22はパッケージ上面に形成されるとしたが、本発明はこれに限られるものではなく、例えば、パッケージ下面など他のパッケージ表面に形成しても良い。   Furthermore, in the above description of the first and second embodiments, the characters 12 or 22 such as the product number are formed on the upper surface of the package, but the present invention is not limited to this. It may be formed on the package surface.

本発明の実施例1に係わる半導体パッケージを示す図。The figure which shows the semiconductor package concerning Example 1 of this invention. 本発明の実施例1に係わる半導体パッケージの表面付近の断面を示す模式図。The schematic diagram which shows the cross section of the surface vicinity of the semiconductor package concerning Example 1 of this invention. 本発明の実施例2に係わる半導体パッケージを示す平面図。The top view which shows the semiconductor package concerning Example 2 of this invention.

符号の説明Explanation of symbols

11、21 下地(梨地1)
12 文字(梨地2)
13 基準面
22 文字(梨地1)
23 文字領域(梨地2)
11, 21 Ground (Pearl 1)
12 characters (nashiji 2)
13 Reference plane 22 characters (Nashiji 1)
23 character area (nashiji 2)

Claims (5)

半導体チップを樹脂封止した半導体パッケージであって、
前記半導体パッケージの一表面が第1の表面粗さを有する第1の梨地で形成され、
前記第1の梨地上に第2の表面粗さを有する第2の梨地で形成された製品番号等の文字を備え、
前記第1の梨地および前記第2の梨地が同じ基準面を有することを特徴とする半導体パッケージ。
A semiconductor package in which a semiconductor chip is sealed with resin,
One surface of the semiconductor package is formed of a first satin having a first surface roughness;
Provided with characters such as a product number formed with a second pear surface having a second surface roughness on the first pear surface,
The semiconductor package, wherein the first satin and the second satin have the same reference plane.
半導体チップを樹脂封止した半導体パッケージであって、
前記半導体パッケージの一表面が第1の表面粗さを有する第1の梨地で形成され、
前記第1の梨地上に第2の表面粗さを有する第2の梨地で形成された文字領域と、
前記文字領域に前記第1の梨地で形成された製品番号等の文字を備え、
前記第1の梨地および前記第2の梨地が同じ基準面を有することを特徴とする半導体パッケージ。
A semiconductor package in which a semiconductor chip is sealed with resin,
One surface of the semiconductor package is formed of a first satin having a first surface roughness;
A character region formed of a second pear surface having a second surface roughness on the first pear surface;
Provided with characters such as a product number formed in the first satin in the character region,
The semiconductor package, wherein the first satin and the second satin have the same reference plane.
前記第1の梨地は平均ピッチが40〜50μmの表面粗さであり、前記第2の梨地は平均ピッチが80〜100μmの表面粗さであることを特徴とする請求項1または請求項2に記載の半導体パッケージ。   3. The first pear texture has a surface roughness with an average pitch of 40 to 50 [mu] m, and the second pear texture has a surface roughness with an average pitch of 80 to 100 [mu] m. The semiconductor package described. 半導体チップを樹脂封止した半導体パッケージであって、
前記半導体パッケージの一表面が鏡面仕上げで形成され、
前記鏡面上に所定の表面粗さを有する梨地で形成された製品番号等の文字を備え、
前記鏡面および前記梨地が同じ基準面を有することを特徴とする半導体パッケージ。
A semiconductor package in which a semiconductor chip is sealed with resin,
One surface of the semiconductor package is formed with a mirror finish,
Provided with characters such as product numbers formed of satin having a predetermined surface roughness on the mirror surface,
The semiconductor package, wherein the mirror surface and the matte surface have the same reference surface.
半導体チップを樹脂封止した半導体パッケージであって、
前記半導体パッケージの一表面が所定の表面粗さを有する梨地で形成され、
前記梨地上に鏡面仕上げで形成された製品番号等の文字を備え、
前記梨地および前記鏡面が同じ基準面を有することを特徴とする半導体パッケージ。
A semiconductor package in which a semiconductor chip is sealed with resin,
One surface of the semiconductor package is formed of satin having a predetermined surface roughness,
With characters such as product numbers formed with a mirror finish on the pear ground,
The semiconductor package, wherein the matte surface and the mirror surface have the same reference surface.
JP2007113240A 2007-04-23 2007-04-23 Semiconductor package Pending JP2008270610A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007113240A JP2008270610A (en) 2007-04-23 2007-04-23 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007113240A JP2008270610A (en) 2007-04-23 2007-04-23 Semiconductor package

Publications (1)

Publication Number Publication Date
JP2008270610A true JP2008270610A (en) 2008-11-06

Family

ID=40049699

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007113240A Pending JP2008270610A (en) 2007-04-23 2007-04-23 Semiconductor package

Country Status (1)

Country Link
JP (1) JP2008270610A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012529771A (en) * 2009-06-16 2012-11-22 インテル コーポレイション Integrated circuit package having security mechanism and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012529771A (en) * 2009-06-16 2012-11-22 インテル コーポレイション Integrated circuit package having security mechanism and manufacturing method thereof

Similar Documents

Publication Publication Date Title
JP6798568B2 (en) Cards, card manufacturing methods
CN105459713B (en) The manufacturing method of decorative panel and decorative panel
US20140131208A1 (en) Metallic shell and method for etching pattern
EP1432032A3 (en) Semiconductor chip stack and method for manufacturing the same
JP2008270610A (en) Semiconductor package
EP1160853A3 (en) Method of producing a semiconductor device
US10347551B2 (en) Semiconductor package
JP2010021251A (en) Semiconductor device and its manufacturing method
JP2010040618A (en) Lead frame, semiconductor device, and manufacturing method thereof
US7508083B2 (en) Electronic component comprising a semiconductor chip and a plastic housing, and method for producing the same
EP4249249A3 (en) Decorative material and method for producing same
JP2010087173A (en) Method of manufacturing semiconductor device, and semiconductor device
US20130248906A1 (en) Light emitting diode package structure and method for fabricating the same
CN108960006B (en) Fingerprint identification module and manufacturing method thereof
JP2002110716A (en) Manufacturing method of semiconductor device
US20060099728A1 (en) Method of manufacturing a substrate structure for increasing cutting precision and strength thereof
JP6345957B2 (en) Metal-ceramic circuit board and manufacturing method thereof
US7803663B2 (en) Method for manufacturing a molded MMC multi media card package obtained with laser cutting
US20170358538A1 (en) Semiconductor device and method for manufacturing the same
JP2013139091A (en) Resin molding, mold for molding resin and method for molding resin
CN109962145B (en) Lead frame manufacturing method and molded body
CN107170713B (en) Substrate and multi-substrate including a plurality of the substrates and method for manufacturing the same
KR200392031Y1 (en) Mold for manufacturing fin type heat sink
JP6566586B2 (en) Metal-ceramic circuit board and manufacturing method thereof
JP6411227B2 (en) IC card

Legal Events

Date Code Title Description
A711 Notification of change in applicant

Effective date: 20081226

Free format text: JAPANESE INTERMEDIATE CODE: A712

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090210