JP2008270328A - Laminated varistor and manufacturing method therefor - Google Patents

Laminated varistor and manufacturing method therefor Download PDF

Info

Publication number
JP2008270328A
JP2008270328A JP2007107946A JP2007107946A JP2008270328A JP 2008270328 A JP2008270328 A JP 2008270328A JP 2007107946 A JP2007107946 A JP 2007107946A JP 2007107946 A JP2007107946 A JP 2007107946A JP 2008270328 A JP2008270328 A JP 2008270328A
Authority
JP
Japan
Prior art keywords
external electrode
varistor
electrode
laminated
external
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007107946A
Other languages
Japanese (ja)
Other versions
JP5034640B2 (en
Inventor
Naoki Muto
直樹 武藤
雅幸 ▲高▼橋
Masayuki Takahashi
Masafumi Goto
雅史 後藤
Yoshiharu Kataoka
義晴 片岡
Hiroshi Ishibashi
啓 石橋
Masashi Senba
正志 船場
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2007107946A priority Critical patent/JP5034640B2/en
Publication of JP2008270328A publication Critical patent/JP2008270328A/en
Application granted granted Critical
Publication of JP5034640B2 publication Critical patent/JP5034640B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01CRESISTORS
    • H01C7/00Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/10Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material voltage responsive, i.e. varistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Thermistors And Varistors (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminated varistor that has high reliability that can withstand under a severe usage environment, such as an electronic device for vehicle, and to provide its manufacturing method. <P>SOLUTION: The laminated varistor is provided with a sintere 11 that is formed, by alternatively laminating a varistor layer 12 and an internal electrode 13 and sintering the laminated body and a pair of external electrodes, wherein the internal electrode 13 is alternatively connected with at least both end faces of the sintere 11. The pair of external electrodes is formed of two layers, having different quantities of glass, and the glass content of an inside first external electrode 14 connected to the internal electrode is 5 wt.% or lower (includes zero). The glass content of a second external electrode 15, formed outside on the first external electrode 14, is 10 wt.% to 30 wt.%, thereby preventing infiltration of water content from the outside and obtaining a high-reliability laminated varistor. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、各種電子機器や車載用電子デバイスを異常電圧やノイズによる誤動作から保護するのに用いられる積層バリスタとその製造方法に関する。   The present invention relates to a multilayer varistor used for protecting various electronic devices and in-vehicle electronic devices from malfunction caused by abnormal voltage or noise, and a method for manufacturing the same.

近年、各種電子機器や車載用電子デバイスを雷サージ電圧や静電気などによる異常電圧から保護したり、電子機器や電子デバイスが回路に発生するノイズにより誤動作するのを防ぐためなどの目的で酸化亜鉛を主成分とした積層バリスタが多く用いられるようになってきている。   In recent years, zinc oxide has been used for the purpose of protecting various electronic devices and in-vehicle electronic devices from abnormal voltage due to lightning surge voltage, static electricity, etc., and preventing electronic devices and electronic devices from malfunctioning due to noise generated in the circuit. Many laminated varistors having a main component have been used.

図2は、一般的な積層バリスタ21の一部切欠斜視図であり、バリスタ材料よりなるセラミック層22と内部電極23とが交互に積層され焼結されて焼結体を構成し、内部電極23はその端面が焼結体の対向する両端面に交互に露出するよう積層されており、焼結体の両端面に形成された一対の外部電極24に交互に接続されている。   FIG. 2 is a partially cutaway perspective view of a general laminated varistor 21, in which ceramic layers 22 and internal electrodes 23 made of a varistor material are alternately laminated and sintered to form a sintered body. Are laminated so that their end faces are alternately exposed at opposite end faces of the sintered body, and are alternately connected to a pair of external electrodes 24 formed at both end faces of the sintered body.

なお、本願の発明に関連する先行技術文献情報としては、例えば、特許文献1が知られている。
特開2000−277306号公報
As prior art document information related to the invention of the present application, for example, Patent Document 1 is known.
JP 2000-277306 A

上記のような酸化亜鉛を主成分とする積層バリスタ21を構成するセラミック層22は絶縁体ではなく半導体セラミックであるため、水分や酸性、アルカリ性の液体が焼結体内部に浸入した場合、特性が劣化しやすい。   The ceramic layer 22 constituting the laminated varistor 21 mainly composed of zinc oxide is not an insulator but a semiconductor ceramic. Therefore, when moisture, acid, or alkaline liquid infiltrates into the sintered body, the characteristics are as follows. Easy to deteriorate.

このため、水分などが焼結体内部に浸入するのを防止することが重要である。   For this reason, it is important to prevent moisture and the like from entering the sintered body.

特に車載用の電子デバイスに用いられる電子部品では、より厳しい使用環境に耐えられることが求められ、更にこのような水分や酸性、アルカリ性の液体などが焼結体内部へ浸入することを防止し、高い信頼性を確保する必要がある。   In particular, electronic components used in in-vehicle electronic devices are required to withstand more severe usage environments, and further prevent such moisture, acid, and alkaline liquids from entering the sintered body. It is necessary to ensure high reliability.

そこで、本発明は例えば車載用電子デバイスなどの厳しい使用環境に耐えられる、信頼性の高い積層バリスタとその製造方法を提供することを目的とする。   Accordingly, an object of the present invention is to provide a highly reliable multilayer varistor that can withstand harsh usage environments such as in-vehicle electronic devices and a method for manufacturing the same.

そしてこの目的を達成するために、本発明の積層バリスタは、バリスタ層と内部電極を交互に積層した積層体を焼結した焼結体と、この焼結体の少なくとも両端面において前記内部電極が交互に接続された状態で設けられた一対の外部電極とを備え、前記一対の外部電極はガラス量の異なる2層よりなり、この2層の外部電極のうち、内部電極に接続される内側の第1の外部電極のガラス含有量が5重量%以下(0を含む)であり、かつ第1の外部電極の上で外側に形成される第2の外部電極のガラス含有量が10重量%以上で30重量%以下とした積層バリスタとその製造方法である。   In order to achieve this object, the laminated varistor of the present invention comprises a sintered body obtained by sintering a laminated body in which varistor layers and internal electrodes are alternately laminated, and the internal electrodes are provided on at least both end faces of the sintered body. A pair of external electrodes provided in an alternately connected state, and the pair of external electrodes is composed of two layers having different glass amounts. Of the two layers of external electrodes, the inner electrodes connected to the internal electrodes The glass content of the first external electrode is 5% by weight or less (including 0), and the glass content of the second external electrode formed outside on the first external electrode is 10% by weight or more. And a manufacturing method thereof.

本発明によれば、内部電極に接する内側の第1の外部電極のガラス含有量を5重量%以下と少なくして第1の外部電極を緻密に形成し、外部からの水分等の浸入を防止するとともに、この第1の外部電極の外側に形成した第2の外部電極のガラス含有量を10重量%〜30重量%と多くして、第2の外部電極のガラスと、第1の外部電極の終端部付近の焼結体成分のZnとが反応して、外部電極の終端部に対向する焼結体内部の表面付近にガラス層を形成し、このガラス層により外部電極終端部付近から水分が焼結体内部に浸入することを防止して信頼性の高い積層バリスタを得ることができる。   According to the present invention, the glass content of the inner first external electrode in contact with the internal electrode is reduced to 5% by weight or less so that the first external electrode is densely formed to prevent the intrusion of moisture and the like from the outside. In addition, the glass content of the second external electrode and the first external electrode are increased by increasing the glass content of the second external electrode formed outside the first external electrode to 10 wt% to 30 wt%. The Zn component of the sintered body in the vicinity of the terminal portion of the metal reacts to form a glass layer near the surface inside the sintered body facing the terminal portion of the external electrode. Is prevented from entering the sintered body, and a highly reliable laminated varistor can be obtained.

以下、本発明の積層バリスタとその製造方法について一実施の形態および図面を用いて説明する。   Hereinafter, a laminated varistor of the present invention and a manufacturing method thereof will be described with reference to an embodiment and drawings.

(実施の形態1)
図1は実施の形態1の積層バリスタの断面図であり、バリスタ層12と内部電極13は交互に積層されたのち焼結されて焼結体11を構成し、前記内部電極13は交互に一対の第1の外部電極14に接続されている。
(Embodiment 1)
FIG. 1 is a cross-sectional view of the multilayer varistor according to the first embodiment. The varistor layers 12 and the internal electrodes 13 are alternately laminated and then sintered to form a sintered body 11, and the internal electrodes 13 are alternately paired. The first external electrode 14 is connected.

そしてこの第1の外部電極14の上には、第1の外部電極14よりもガラス含有量が多い第2の外部電極15が設けられている。   A second external electrode 15 having a glass content higher than that of the first external electrode 14 is provided on the first external electrode 14.

ここで、第1の外部電極14は内部電極13に直接接合されるため、緻密であることが必要である。   Here, since the first external electrode 14 is directly bonded to the internal electrode 13, it is necessary to be dense.

もし第1の外部電極14が多孔性の電極であれば、外部からの水分が浸入した時に内部電極13とバリスタ層12の界面等を伝わって焼結体11内部に水分が浸入し、積層バリスタの特性低下につながる。   If the first external electrode 14 is a porous electrode, when moisture from the outside enters, the moisture penetrates into the sintered body 11 through the interface between the internal electrode 13 and the varistor layer 12, and the laminated varistor. This leads to deterioration of the characteristics.

第1の外部電極14を緻密にするためには、金属成分以外のガラスフリットやセラミック粉末を含まないか、含んでも少量とすることが望ましい。   In order to make the first external electrode 14 dense, it is desirable that the glass frit or ceramic powder other than the metal component is not contained or is contained in a small amount.

従って、第1の外部電極14は出来るだけ純金属に近い組成で構成されるのが好ましく、金属量に対するガラスの含有量は5重量%以下に抑えることが好ましい。   Therefore, it is preferable that the first external electrode 14 has a composition as close to pure metal as possible, and the glass content with respect to the metal amount is preferably suppressed to 5% by weight or less.

ガラスの含有量が5重量%を越えた場合、金属とガラスが完全に相溶できないため、気孔発生の原因となり、第1の外部電極14を通して内部電極13に水分が浸入する可能性が高くなる。   When the glass content exceeds 5% by weight, the metal and the glass cannot be completely compatible with each other, which may cause pores and increase the possibility of moisture entering the internal electrode 13 through the first external electrode 14. .

また、第1の外部電極14はバリスタ層12の端面に直接接触しているため、ガラス含有量が5重量%を越えて多くなると、ガラスのバリスタ層12中に拡散し、バリスタ電圧の低下などの特性低下につながるため好ましくない。   Further, since the first external electrode 14 is in direct contact with the end face of the varistor layer 12, if the glass content increases beyond 5% by weight, the glass diffuses into the varistor layer 12 and the varistor voltage decreases. This is not preferable because it leads to a decrease in characteristics.

第1の外部電極14の上に形成される第2の外部電極15は、バリスタ層12の端面や内部電極13と直接接触することがないため、緻密性はそれほど要求されない。   The second external electrode 15 formed on the first external electrode 14 does not come into direct contact with the end face of the varistor layer 12 or the internal electrode 13, so that the denseness is not so required.

むしろ、この第2の外部電極15のガラス含有量を第1の外部電極14のガラス含有量よりも多くすることにより、第2の外部電極15に含まれるガラスが、緻密な第1の外部電極14上を移動し、第1の外部電極14の終端部16でバリスタ層12と反応してこの終端部16に対向する焼結体内部の表面付近にガラスと焼結体の成分であるZnよりなるガラス層17を形成し、このガラス層によって外部電極終端部からの水分等の浸入を防止できることが確認できている。   Rather, by making the glass content of the second external electrode 15 larger than the glass content of the first external electrode 14, the glass contained in the second external electrode 15 becomes a dense first external electrode. 14, and reacts with the varistor layer 12 at the terminal portion 16 of the first external electrode 14, so that Zn near the surface of the inside of the sintered body facing this terminal portion 16 is formed from Zn which is a component of glass and the sintered body. The glass layer 17 is formed, and it has been confirmed that this glass layer can prevent intrusion of moisture and the like from the terminal portion of the external electrode.

セラミックのバリスタ層12に密着性の高いガラスが少ない第1の外部電極14では、その終端部16で焼結体11との密着性が低下しやすく、水分がこの終端部16を経由して焼結体11内部の内部電極13界面に浸入する可能性が生じる。   In the first external electrode 14 in which the ceramic varistor layer 12 is low in glass having high adhesion, the adhesion to the sintered body 11 tends to decrease at the terminal end 16, and moisture is baked through the terminal end 16. There is a possibility of entering the interface of the internal electrode 13 inside the bonded body 11.

この終端部16は、図1では上下2箇所で示したが、第1の外部電極14の端部が焼結体と接する部分すべてを指す。   The end portion 16 is shown in two places in the upper and lower portions in FIG. 1, but refers to all portions where the end portion of the first external electrode 14 is in contact with the sintered body.

以上のように、本実施の形態の積層バリスタでは、内部電極13と直接接合する第1の外部電極14を緻密にして水分浸入を防止し、さらにその終端部16からの水分浸入についても、終端部16近辺にガラス層17を形成することにより防止するものである。   As described above, in the multilayer varistor of the present embodiment, the first external electrode 14 that is directly bonded to the internal electrode 13 is made dense to prevent water intrusion, and the water intrusion from the terminal portion 16 is also terminated. This is prevented by forming the glass layer 17 in the vicinity of the portion 16.

そしてこの構成により信頼性の高い積層バリスタを得ることができるものである。   With this configuration, a highly reliable laminated varistor can be obtained.

次に本発明の実施の形態に係る積層バリスタの製造方法について説明する。   Next, the manufacturing method of the laminated varistor according to the embodiment of the present invention will be described.

まず、ZnOを主成分とし、BiやSbの酸化物などの添加物よりなるバリスタ粉末と、有機材料としてポリビニルブチラール樹脂と、溶剤、可塑剤、分散剤等を混合してセラミックスラリーを作製し、ドクターブレート法などの方法を用いて焼成によりセラミック層12となるグリーンシートを作製する。   First, a ceramic slurry is prepared by mixing a varistor powder mainly composed of ZnO and made of additives such as oxides of Bi and Sb, a polyvinyl butyral resin as an organic material, a solvent, a plasticizer, a dispersant, and the like. A green sheet to be the ceramic layer 12 is produced by firing using a doctor blade method or the like.

一方、Agよりなる金属粉末と、有機材料として溶剤、樹脂、可塑剤等よりなるビヒクルとを混合して電極ペーストを作製し、この電極ペーストをスクリーン印刷法によりグリーンシート上に塗布して内部電極13となる導電体層を形成する。   On the other hand, an electrode paste is prepared by mixing a metal powder made of Ag and a vehicle made of a solvent, a resin, a plasticizer, or the like as an organic material, and this electrode paste is applied on a green sheet by a screen printing method to form an internal electrode. A conductor layer to be 13 is formed.

次いで、この導電体層を形成したグリーンシートを17枚積層した後、その上段と下段に電極ペーストを塗布していないグリーンシートを1枚または複数枚積層して上下の保護層を形成し、積層体グリーンブロック(図示せず)を作製した。   Next, after stacking 17 green sheets on which the conductor layer is formed, one or more green sheets not coated with electrode paste are stacked on the upper and lower layers to form upper and lower protective layers. A body green block (not shown) was prepared.

次いで、この積層体グリーンブロックを長さ6.6mm、幅5.8mm、厚み3.3mmの寸法に切断して、焼成により焼結体11となる略直方体形状の積層体(図示せず)を作製した。このとき積層体の両端面は導電体層の一方の端部がグリーンシートを挟んで一層おきに交互に、対向する端面に露出した構造とした。   Next, this laminate green block is cut into dimensions of 6.6 mm in length, 5.8 mm in width, and 3.3 mm in thickness, and a substantially rectangular parallelepiped laminate (not shown) that becomes a sintered body 11 by firing. Produced. At this time, the both end surfaces of the laminate were structured such that one end of the conductor layer was alternately exposed every other layer across the green sheet.

この積層体を脱バインダー後、800℃〜950℃の温度で焼成し、長さ5.7mm、幅5.0mm、厚み2.7mmの焼結体11を得た。   After debinding the laminate, the laminate was fired at a temperature of 800 ° C. to 950 ° C. to obtain a sintered body 11 having a length of 5.7 mm, a width of 5.0 mm, and a thickness of 2.7 mm.

この焼結体11をバレル研磨して角部の面取りを行い、一対の両端面にホウケイ酸系のガラスを金属成分に対して5重量%以下の量で含む電極ペーストを用いて導電体層を形成して焼付を行い、第1の外部電極14を形成した。   The sintered body 11 is barrel-polished to chamfer corners, and a conductor layer is formed using an electrode paste containing borosilicate glass in an amount of 5% by weight or less with respect to a metal component on a pair of both end faces. Formed and baked to form the first external electrode 14.

その後、第1の外部電極14に用いた電極ペーストよりもガラス量が多く、5〜20重量%のホウケイ酸系ガラスを含む電極ペーストを用いて、第1の外部電極14の上に導電体層を形成し、焼付を行って第2の外部電極15を形成することにより、試料番号2〜6の試料を作製した。   Thereafter, a conductive layer is formed on the first external electrode 14 by using an electrode paste containing 5 to 20% by weight of borosilicate glass and having a larger amount of glass than the electrode paste used for the first external electrode 14. Were formed and baked to form the second external electrode 15, thereby preparing samples Nos. 2 to 6.

また比較例として、第2の外部電極15を形成せず、ガラスを含まない電極ペーストを用いて第1の外部電極14を形成した試料(試料番号1)と、ガラス含有量が本実施の形態の範囲外の試料(試料番号2)を作製し、各々を本実施の形態と同様に積層、焼成して比較例の積層バリスタを作製した。   In addition, as a comparative example, the second external electrode 15 is not formed and the first external electrode 14 is formed using an electrode paste not containing glass (sample number 1), and the glass content is the present embodiment. Samples outside the range (sample number 2) were produced, and each was laminated and fired in the same manner as in this embodiment to produce a laminated varistor of a comparative example.

試料番号2〜7の断面のEPMA(電子線マイクロアナリシス)分析により、Si、Znを主成分とするガラス層が形成されていることが確認された。   By the EPMA (electron beam microanalysis) analysis of the cross sections of sample numbers 2 to 7, it was confirmed that a glass layer mainly composed of Si and Zn was formed.

この実施の形態1による積層バリスタと、比較例の積層バリスタ各々に対して、85℃、85%の高温高湿中で定格電圧(16V)を印加して信頼性試験を行った。   A reliability test was performed by applying a rated voltage (16 V) to the multilayer varistor according to the first embodiment and the multilayer varistor of the comparative example in high temperature and high humidity of 85 ° C. and 85%.

試験後の試料のバリスタ電圧V1mAを測定し、試験前のバリスタ電圧と比較して変化率が10%以上となったものを不良個数としてカウントして(表1)に示す。 The varistor voltage V 1 mA of the sample after the test is measured, and the change rate of 10% or more compared with the varistor voltage before the test is counted as the number of defects (Table 1).

Figure 2008270328
Figure 2008270328

(表1)で試料番号に※印を付したものは、本実施の形態の範囲外であることを示す。   In Table 1, the sample number with an asterisk (*) indicates that it is out of the scope of the present embodiment.

(表1)に示すように、第2の外部電極15を設けていない試料番号1では外部電極の終端部近辺から水分が浸入し、30個中17個の不良発生が見られた。   As shown in (Table 1), in Sample No. 1 in which the second external electrode 15 was not provided, moisture entered from the vicinity of the terminal portion of the external electrode, and 17 out of 30 defects were observed.

また第2の外部電極15を形成したが、そのガラス含有量が本実施の形態の範囲外である試料番号2でも同様に30個中6個の不良発生が見られた。   In addition, although the second external electrode 15 was formed, in the sample number 2 whose glass content is outside the range of the present embodiment, 6 out of 30 defects were similarly observed.

第2の外部電極15のガラス含有量が本実施の形態の範囲外の35重量%である試料番号7では、信頼性試験においてバリスタ電圧の変化率は10%を超えなかったが、第2の外部電極15表面にガラスが浮いた状態となり、バリスタ電圧測定のための外部端子との電気的接触不良が発生した。   In the sample number 7 in which the glass content of the second external electrode 15 is 35% by weight outside the range of the present embodiment, the change rate of the varistor voltage did not exceed 10% in the reliability test. The glass floated on the surface of the external electrode 15, resulting in poor electrical contact with the external terminal for varistor voltage measurement.

このため、外部端子との電気的接触が確保できるように、第2の外部電極表面のガラスを削除してバリスタ電圧を測定したが、はんだ付け性は著しく損なわれていた。   For this reason, the varistor voltage was measured by removing the glass on the surface of the second external electrode so as to ensure electrical contact with the external terminal, but the solderability was significantly impaired.

以上の結果から明らかなように、本実施の形態により2層よりなる外部電極のうち、内部電極に接続される内側の第1の外部電極14のガラス含有量が5重量%以下とし、かつ前記第1の外部電極14の上で外側に形成される第2の外部電極15のガラス含有量が10重量%〜30重量%とすることにより、外部からの水分浸入による特性の低下を防ぎ、信頼性の高い積層バリスタが得られることが解る。   As is apparent from the above results, the glass content of the inner first external electrode 14 connected to the internal electrode out of the two layers of external electrodes according to the present embodiment is 5% by weight or less, and The glass content of the second external electrode 15 formed outside on the first external electrode 14 is 10% by weight to 30% by weight, thereby preventing deterioration of characteristics due to moisture intrusion from the outside. It can be seen that a highly functional laminated varistor can be obtained.

本発明の積層バリスタは、内部電極と直接接合される第1の外部電極のガラス含有量を少なくして緻密な外部電極とし、さらに第1の外部電極の上に形成したガラス量を多く含む第2の外部電極により、外部電極の回り込み終端部付近の焼結体内部に水分浸入を防ぐためのガラス層を形成したものであり、高温高湿中でも高い信頼性を保持することができるため、車載用電子デバイスや各種電子機器に用いられる積層バリスタなどに有用である。   The multilayer varistor of the present invention is a dense external electrode in which the glass content of the first external electrode directly bonded to the internal electrode is reduced, and further includes a large amount of glass formed on the first external electrode. The glass layer for preventing moisture intrusion is formed inside the sintered body near the wraparound terminal portion of the external electrode by the external electrode 2 and can maintain high reliability even in high temperature and high humidity. This is useful for laminated varistors used in electronic devices for electronic devices and various electronic devices.

本発明の実施の形態1における積層バリスタの断面図Sectional drawing of the laminated varistor in Embodiment 1 of this invention 一般的な積層バリスタの一部切欠斜視図Partial cutaway perspective view of a typical laminated varistor

符号の説明Explanation of symbols

11 焼結体
12 バリスタ層
13 内部電極
14 第1の外部電極
15 第2の外部電極
16 終端部
17 ガラス層
21 積層バリスタ
22 セラミック層
23 内部電極
24 外部電極
DESCRIPTION OF SYMBOLS 11 Sintered body 12 Varistor layer 13 Internal electrode 14 1st external electrode 15 2nd external electrode 16 Termination part 17 Glass layer 21 Multilayer varistor 22 Ceramic layer 23 Internal electrode 24 External electrode

Claims (2)

バリスタ層と内部電極を交互に積層した積層体を焼結した焼結体と、この焼結体の少なくとも両端面において前記内部電極が交互に接続された状態で設けられた一対の外部電極とを備え、前記一対の外部電極はガラス量の異なる2層よりなり、前記2層よりなる外部電極のうち、内部電極に接続される内側の第1の外部電極のガラス含有量が5重量%以下(0を含む)であり、かつ前記第1の外部電極の上で外側に形成される第2の外部電極のガラス含有量が10重量%〜30重量%であることを特徴とする積層バリスタ。 A sintered body obtained by sintering a laminate in which varistor layers and internal electrodes are alternately laminated, and a pair of external electrodes provided in a state in which the internal electrodes are alternately connected at least at both end faces of the sintered body. And the pair of external electrodes is composed of two layers having different glass amounts, and the glass content of the inner first external electrode connected to the internal electrode among the external electrodes composed of the two layers is 5% by weight or less ( And a glass content of the second external electrode formed outside on the first external electrode is 10% by weight to 30% by weight. バリスタ層と内部電極を交互に積層して積層体を得る積層工程と、前記積層体を焼成して焼結体を得る焼成工程と、前記焼結体の両端面に外部電極を形成する外部電極形成工程を含む積層バリスタの製造方法であって、前記電極形成工程は焼結体の両端面にガラス含有量が5重量%以下(0を含む)の第1の外部電極を形成した後、この第1の外部電極の上にガラス含有量が10重量%〜30重量%の第2の外部電極を形成することを特徴とする積層バリスタの製造方法。 Laminating step for alternately laminating varistor layers and internal electrodes to obtain a laminated body, firing step for firing the laminated body to obtain a sintered body, and external electrodes for forming external electrodes on both end faces of the sintered body A method of manufacturing a laminated varistor including a forming step, wherein the electrode forming step forms a first external electrode having a glass content of 5% by weight or less (including 0) on both end faces of the sintered body, A method for producing a laminated varistor, comprising forming a second external electrode having a glass content of 10 wt% to 30 wt% on a first external electrode.
JP2007107946A 2007-04-17 2007-04-17 Multilayer varistor and manufacturing method thereof Active JP5034640B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007107946A JP5034640B2 (en) 2007-04-17 2007-04-17 Multilayer varistor and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007107946A JP5034640B2 (en) 2007-04-17 2007-04-17 Multilayer varistor and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2008270328A true JP2008270328A (en) 2008-11-06
JP5034640B2 JP5034640B2 (en) 2012-09-26

Family

ID=40049482

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007107946A Active JP5034640B2 (en) 2007-04-17 2007-04-17 Multilayer varistor and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP5034640B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11908599B2 (en) 2021-08-31 2024-02-20 Panasonic Intellectual Property Management Co., Ltd. Varistor and method for manufacturing the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04273417A (en) * 1991-02-28 1992-09-29 Mitsubishi Materials Corp Laminated ceramic capacitor
JPH053131A (en) * 1991-04-17 1993-01-08 Matsushita Electric Ind Co Ltd Multilayer ceramic capacitor and manufacture thereof
JPH0536503A (en) * 1991-07-25 1993-02-12 Murata Mfg Co Ltd Laminated varistor
JPH0636970A (en) * 1992-07-14 1994-02-10 Mitsubishi Materials Corp External electrode of chip type electronic component
JPH0927405A (en) * 1995-07-11 1997-01-28 Marcon Electron Co Ltd Multilayer chip varistor
JP2000164406A (en) * 1998-11-25 2000-06-16 Murata Mfg Co Ltd Chip type electronic part and manufacture thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04273417A (en) * 1991-02-28 1992-09-29 Mitsubishi Materials Corp Laminated ceramic capacitor
JPH053131A (en) * 1991-04-17 1993-01-08 Matsushita Electric Ind Co Ltd Multilayer ceramic capacitor and manufacture thereof
JPH0536503A (en) * 1991-07-25 1993-02-12 Murata Mfg Co Ltd Laminated varistor
JPH0636970A (en) * 1992-07-14 1994-02-10 Mitsubishi Materials Corp External electrode of chip type electronic component
JPH0927405A (en) * 1995-07-11 1997-01-28 Marcon Electron Co Ltd Multilayer chip varistor
JP2000164406A (en) * 1998-11-25 2000-06-16 Murata Mfg Co Ltd Chip type electronic part and manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11908599B2 (en) 2021-08-31 2024-02-20 Panasonic Intellectual Property Management Co., Ltd. Varistor and method for manufacturing the same

Also Published As

Publication number Publication date
JP5034640B2 (en) 2012-09-26

Similar Documents

Publication Publication Date Title
KR101411519B1 (en) Voltage non-linear resistance ceramic composition and voltage non-linear resistance element
WO2015045625A1 (en) Laminated ceramic electronic component
KR20040023757A (en) Chip electronic component
KR102107032B1 (en) Glass composition, paste for external electrode including the same and multi-layer ceramic electronic part
WO2022113822A1 (en) Multilayer varistor and method for manufacturing same
JPWO2015045722A1 (en) Multilayer ceramic electronic components
JP5527404B2 (en) Multilayer ceramic electronic components
JP4654690B2 (en) Multilayer varistor
JP5034640B2 (en) Multilayer varistor and manufacturing method thereof
JP2015035362A (en) Electrostatic protection component
JP5301852B2 (en) Multilayer chip varistor
JPH11307391A (en) Electrode for electronic component and the electronic component
JP5527405B2 (en) Multilayer ceramic electronic components
JP4442135B2 (en) Manufacturing method of ceramic electronic component
JP5527400B2 (en) Multilayer ceramic electronic components
JP5527403B2 (en) Multilayer ceramic electronic components
JP5527401B2 (en) Multilayer ceramic electronic components
JP2007005500A (en) Zinc oxide laminated varistor and its manufacturing method
JP2000036220A (en) Conductive paste and ceramic electronic part using same
JP2005183593A (en) Joined type voltage dependent resistor and manufacturing method thereof
JP7322793B2 (en) Chip varistor manufacturing method and chip varistor
JP5760894B2 (en) ESD protection element
JP2023142120A (en) Method for manufacturing laminated ceramic component and laminated ceramic component
JPH07201637A (en) Multilayer ceramic electronic device
JP2007184335A (en) Method for manufacturing laminated chip varistor

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20100329

RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7421

Effective date: 20100413

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110909

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110913

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111101

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120605

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120618

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150713

Year of fee payment: 3

R151 Written notification of patent or utility model registration

Ref document number: 5034640

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150713

Year of fee payment: 3